[deliverable/linux.git] / arch / blackfin / kernel / kgdb.c

/*
 * arch/blackfin/kernel/kgdb.c - Blackfin kgdb pieces
 *
 * Copyright 2005-2008 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#include <linux/ptrace.h>		/* for linux pt_regs struct */
#include <linux/kgdb.h>
#include <linux/uaccess.h>
#include <asm/irq_regs.h>

void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
{
	gdb_regs[BFIN_R0] = regs->r0;
	gdb_regs[BFIN_R1] = regs->r1;
	gdb_regs[BFIN_R2] = regs->r2;
	gdb_regs[BFIN_R3] = regs->r3;
	gdb_regs[BFIN_R4] = regs->r4;
	gdb_regs[BFIN_R5] = regs->r5;
	gdb_regs[BFIN_R6] = regs->r6;
	gdb_regs[BFIN_R7] = regs->r7;
	gdb_regs[BFIN_P0] = regs->p0;
	gdb_regs[BFIN_P1] = regs->p1;
	gdb_regs[BFIN_P2] = regs->p2;
	gdb_regs[BFIN_P3] = regs->p3;
	gdb_regs[BFIN_P4] = regs->p4;
	gdb_regs[BFIN_P5] = regs->p5;
	gdb_regs[BFIN_SP] = regs->reserved;
	gdb_regs[BFIN_FP] = regs->fp;
	gdb_regs[BFIN_I0] = regs->i0;
	gdb_regs[BFIN_I1] = regs->i1;
	gdb_regs[BFIN_I2] = regs->i2;
	gdb_regs[BFIN_I3] = regs->i3;
	gdb_regs[BFIN_M0] = regs->m0;
	gdb_regs[BFIN_M1] = regs->m1;
	gdb_regs[BFIN_M2] = regs->m2;
	gdb_regs[BFIN_M3] = regs->m3;
	gdb_regs[BFIN_B0] = regs->b0;
	gdb_regs[BFIN_B1] = regs->b1;
	gdb_regs[BFIN_B2] = regs->b2;
	gdb_regs[BFIN_B3] = regs->b3;
	gdb_regs[BFIN_L0] = regs->l0;
	gdb_regs[BFIN_L1] = regs->l1;
	gdb_regs[BFIN_L2] = regs->l2;
	gdb_regs[BFIN_L3] = regs->l3;
	gdb_regs[BFIN_A0_DOT_X] = regs->a0x;
	gdb_regs[BFIN_A0_DOT_W] = regs->a0w;
	gdb_regs[BFIN_A1_DOT_X] = regs->a1x;
	gdb_regs[BFIN_A1_DOT_W] = regs->a1w;
	gdb_regs[BFIN_ASTAT] = regs->astat;
	gdb_regs[BFIN_RETS] = regs->rets;
	gdb_regs[BFIN_LC0] = regs->lc0;
	gdb_regs[BFIN_LT0] = regs->lt0;
	gdb_regs[BFIN_LB0] = regs->lb0;
	gdb_regs[BFIN_LC1] = regs->lc1;
	gdb_regs[BFIN_LT1] = regs->lt1;
	gdb_regs[BFIN_LB1] = regs->lb1;
	gdb_regs[BFIN_CYCLES] = 0;
	gdb_regs[BFIN_CYCLES2] = 0;
	gdb_regs[BFIN_USP] = regs->usp;
	gdb_regs[BFIN_SEQSTAT] = regs->seqstat;
	gdb_regs[BFIN_SYSCFG] = regs->syscfg;
	gdb_regs[BFIN_RETI] = regs->pc;
	gdb_regs[BFIN_RETX] = regs->retx;
	gdb_regs[BFIN_RETN] = regs->retn;
	gdb_regs[BFIN_RETE] = regs->rete;
	gdb_regs[BFIN_PC] = regs->pc;
	gdb_regs[BFIN_CC] = (regs->astat >> 5) & 1;
	gdb_regs[BFIN_EXTRA1] = 0;
	gdb_regs[BFIN_EXTRA2] = 0;
	gdb_regs[BFIN_EXTRA3] = 0;
	gdb_regs[BFIN_IPEND] = regs->ipend;
}

/*
 * Extracts ebp, esp and eip values understandable by gdb from the values
 * saved by switch_to.
 * thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp
 * prior to entering switch_to is 8 greater than the value that is saved.
 * If switch_to changes, change following code appropriately.
 */
void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
{
	gdb_regs[BFIN_SP] = p->thread.ksp;
	gdb_regs[BFIN_PC] = p->thread.pc;
	gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat;
}

void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
{
	regs->r0 = gdb_regs[BFIN_R0];
	regs->r1 = gdb_regs[BFIN_R1];
	regs->r2 = gdb_regs[BFIN_R2];
	regs->r3 = gdb_regs[BFIN_R3];
	regs->r4 = gdb_regs[BFIN_R4];
	regs->r5 = gdb_regs[BFIN_R5];
	regs->r6 = gdb_regs[BFIN_R6];
	regs->r7 = gdb_regs[BFIN_R7];
	regs->p0 = gdb_regs[BFIN_P0];
	regs->p1 = gdb_regs[BFIN_P1];
	regs->p2 = gdb_regs[BFIN_P2];
	regs->p3 = gdb_regs[BFIN_P3];
	regs->p4 = gdb_regs[BFIN_P4];
	regs->p5 = gdb_regs[BFIN_P5];
	regs->fp = gdb_regs[BFIN_FP];
	regs->i0 = gdb_regs[BFIN_I0];
	regs->i1 = gdb_regs[BFIN_I1];
	regs->i2 = gdb_regs[BFIN_I2];
	regs->i3 = gdb_regs[BFIN_I3];
	regs->m0 = gdb_regs[BFIN_M0];
	regs->m1 = gdb_regs[BFIN_M1];
	regs->m2 = gdb_regs[BFIN_M2];
	regs->m3 = gdb_regs[BFIN_M3];
	regs->b0 = gdb_regs[BFIN_B0];
	regs->b1 = gdb_regs[BFIN_B1];
	regs->b2 = gdb_regs[BFIN_B2];
	regs->b3 = gdb_regs[BFIN_B3];
	regs->l0 = gdb_regs[BFIN_L0];
	regs->l1 = gdb_regs[BFIN_L1];
	regs->l2 = gdb_regs[BFIN_L2];
	regs->l3 = gdb_regs[BFIN_L3];
	regs->a0x = gdb_regs[BFIN_A0_DOT_X];
	regs->a0w = gdb_regs[BFIN_A0_DOT_W];
	regs->a1x = gdb_regs[BFIN_A1_DOT_X];
	regs->a1w = gdb_regs[BFIN_A1_DOT_W];
	regs->rets = gdb_regs[BFIN_RETS];
	regs->lc0 = gdb_regs[BFIN_LC0];
	regs->lt0 = gdb_regs[BFIN_LT0];
	regs->lb0 = gdb_regs[BFIN_LB0];
	regs->lc1 = gdb_regs[BFIN_LC1];
	regs->lt1 = gdb_regs[BFIN_LT1];
	regs->lb1 = gdb_regs[BFIN_LB1];
	regs->usp = gdb_regs[BFIN_USP];
	regs->syscfg = gdb_regs[BFIN_SYSCFG];
	regs->retx = gdb_regs[BFIN_RETX];
	regs->retn = gdb_regs[BFIN_RETN];
	regs->rete = gdb_regs[BFIN_RETE];
	regs->pc = gdb_regs[BFIN_PC];

#if 0				/* can't change these */
	regs->astat = gdb_regs[BFIN_ASTAT];
	regs->seqstat = gdb_regs[BFIN_SEQSTAT];
	regs->ipend = gdb_regs[BFIN_IPEND];
#endif
}

static struct hw_breakpoint {
	unsigned int occupied:1;
	unsigned int skip:1;
	unsigned int enabled:1;
	unsigned int type:1;
	unsigned int dataacc:2;
	unsigned short count;
	unsigned int addr;
} breakinfo[HW_WATCHPOINT_NUM];

static int bfin_set_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
{
	int breakno;
	int bfin_type;
	int dataacc = 0;

	switch (type) {
	case BP_HARDWARE_BREAKPOINT:
		bfin_type = TYPE_INST_WATCHPOINT;
		break;
	case BP_WRITE_WATCHPOINT:
		dataacc = 1;
		bfin_type = TYPE_DATA_WATCHPOINT;
		break;
	case BP_READ_WATCHPOINT:
		dataacc = 2;
		bfin_type = TYPE_DATA_WATCHPOINT;
		break;
	case BP_ACCESS_WATCHPOINT:
		dataacc = 3;
		bfin_type = TYPE_DATA_WATCHPOINT;
		break;
	default:
		return -ENOSPC;
	}

	/* Because hardware data watchpoint impelemented in current
	 * Blackfin can not trigger an exception event as the hardware
	 * instrction watchpoint does, we ignaore all data watch point here.
	 * They can be turned on easily after future blackfin design
	 * supports this feature.
	 */
	for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
		if (bfin_type == breakinfo[breakno].type
			&& !breakinfo[breakno].occupied) {
			breakinfo[breakno].occupied = 1;
			breakinfo[breakno].skip = 0;
			breakinfo[breakno].enabled = 1;
			breakinfo[breakno].addr = addr;
			breakinfo[breakno].dataacc = dataacc;
			breakinfo[breakno].count = 0;
			return 0;
		}

	return -ENOSPC;
}

static int bfin_remove_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
{
	int breakno;
	int bfin_type;

	switch (type) {
	case BP_HARDWARE_BREAKPOINT:
		bfin_type = TYPE_INST_WATCHPOINT;
		break;
	case BP_WRITE_WATCHPOINT:
	case BP_READ_WATCHPOINT:
	case BP_ACCESS_WATCHPOINT:
		bfin_type = TYPE_DATA_WATCHPOINT;
		break;
	default:
		return 0;
	}
	for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
		if (bfin_type == breakinfo[breakno].type
			&& breakinfo[breakno].occupied
			&& breakinfo[breakno].addr == addr) {
			breakinfo[breakno].occupied = 0;
			breakinfo[breakno].enabled = 0;
		}

	return 0;
}

static void bfin_remove_all_hw_break(void)
{
	int breakno;

	memset(breakinfo, 0, sizeof(struct hw_breakpoint)*HW_WATCHPOINT_NUM);

	for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
		breakinfo[breakno].type = TYPE_INST_WATCHPOINT;
	for (; breakno < HW_WATCHPOINT_NUM; breakno++)
		breakinfo[breakno].type = TYPE_DATA_WATCHPOINT;
}

static void bfin_correct_hw_break(void)
{
	int breakno;
	unsigned int wpiactl = 0;
	unsigned int wpdactl = 0;
	int enable_wp = 0;

	for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
		if (breakinfo[breakno].enabled) {
			enable_wp = 1;

			switch (breakno) {
			case 0:
				wpiactl |= WPIAEN0|WPICNTEN0;
				bfin_write_WPIA0(breakinfo[breakno].addr);
				bfin_write_WPIACNT0(breakinfo[breakno].count
					+ breakinfo->skip);
				break;
			case 1:
				wpiactl |= WPIAEN1|WPICNTEN1;
				bfin_write_WPIA1(breakinfo[breakno].addr);
				bfin_write_WPIACNT1(breakinfo[breakno].count
					+ breakinfo->skip);
				break;
			case 2:
				wpiactl |= WPIAEN2|WPICNTEN2;
				bfin_write_WPIA2(breakinfo[breakno].addr);
				bfin_write_WPIACNT2(breakinfo[breakno].count
					+ breakinfo->skip);
				break;
			case 3:
				wpiactl |= WPIAEN3|WPICNTEN3;
				bfin_write_WPIA3(breakinfo[breakno].addr);
				bfin_write_WPIACNT3(breakinfo[breakno].count
					+ breakinfo->skip);
				break;
			case 4:
				wpiactl |= WPIAEN4|WPICNTEN4;
				bfin_write_WPIA4(breakinfo[breakno].addr);
				bfin_write_WPIACNT4(breakinfo[breakno].count
					+ breakinfo->skip);
				break;
			case 5:
				wpiactl |= WPIAEN5|WPICNTEN5;
				bfin_write_WPIA5(breakinfo[breakno].addr);
				bfin_write_WPIACNT5(breakinfo[breakno].count
					+ breakinfo->skip);
				break;
			case 6:
				wpdactl |= WPDAEN0|WPDCNTEN0|WPDSRC0;
				wpdactl |= breakinfo[breakno].dataacc
					<< WPDACC0_OFFSET;
				bfin_write_WPDA0(breakinfo[breakno].addr);
				bfin_write_WPDACNT0(breakinfo[breakno].count
					+ breakinfo->skip);
				break;
			case 7:
				wpdactl |= WPDAEN1|WPDCNTEN1|WPDSRC1;
				wpdactl |= breakinfo[breakno].dataacc
					<< WPDACC1_OFFSET;
				bfin_write_WPDA1(breakinfo[breakno].addr);
				bfin_write_WPDACNT1(breakinfo[breakno].count
					+ breakinfo->skip);
				break;
			}
		}

	/* Should enable WPPWR bit first before set any other
	 * WPIACTL and WPDACTL bits */
	if (enable_wp) {
		bfin_write_WPIACTL(WPPWR);
		CSYNC();
		bfin_write_WPIACTL(wpiactl|WPPWR);
		bfin_write_WPDACTL(wpdactl);
		CSYNC();
	}
}

static void bfin_disable_hw_debug(struct pt_regs *regs)
{
	/* Disable hardware debugging while we are in kgdb */
	bfin_write_WPIACTL(0);
	bfin_write_WPDACTL(0);
	CSYNC();
}

#ifdef CONFIG_SMP
void kgdb_passive_cpu_callback(void *info)
{
	kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs());
}

void kgdb_roundup_cpus(unsigned long flags)
{
	unsigned int cpu;

	for (cpu = cpumask_first(cpu_online_mask); cpu < nr_cpu_ids;
		cpu = cpumask_next(cpu, cpu_online_mask))
		smp_call_function_single(cpu, kgdb_passive_cpu_callback,
					 NULL, 0);
}

void kgdb_roundup_cpu(int cpu, unsigned long flags)
{
	smp_call_function_single(cpu, kgdb_passive_cpu_callback, NULL, 0);
}
#endif

#ifdef CONFIG_IPIPE
static unsigned long kgdb_arch_imask;
#endif

int kgdb_arch_handle_exception(int vector, int signo,
			       int err_code, char *remcom_in_buffer,
			       char *remcom_out_buffer,
			       struct pt_regs *regs)
{
	long addr;
	char *ptr;
	int newPC;
	int i;

	switch (remcom_in_buffer[0]) {
	case 'c':
	case 's':
		if (kgdb_contthread && kgdb_contthread != current) {
			strcpy(remcom_out_buffer, "E00");
			break;
		}

		kgdb_contthread = NULL;

		/* try to read optional parameter, pc unchanged if no parm */
		ptr = &remcom_in_buffer[1];
		if (kgdb_hex2long(&ptr, &addr)) {
			regs->retx = addr;
		}
		newPC = regs->retx;

		/* clear the trace bit */
		regs->syscfg &= 0xfffffffe;

		/* set the trace bit if we're stepping */
		if (remcom_in_buffer[0] == 's') {
			regs->syscfg |= 0x1;
			kgdb_single_step = regs->ipend;
			kgdb_single_step >>= 6;
			for (i = 10; i > 0; i--, kgdb_single_step >>= 1)
				if (kgdb_single_step & 1)
					break;
			/* i indicate event priority of current stopped instruction
			 * user space instruction is 0, IVG15 is 1, IVTMR is 10.
			 * kgdb_single_step > 0 means in single step mode
			 */
			kgdb_single_step = i + 1;

			preempt_disable();
#ifdef CONFIG_IPIPE
			kgdb_arch_imask = cpu_pda[raw_smp_processor_id()].ex_imask;
			cpu_pda[raw_smp_processor_id()].ex_imask = 0;
#endif
		}

		bfin_correct_hw_break();

		return 0;
	}			/* switch */
	return -1;		/* this means that we do not want to exit from the handler */
}

struct kgdb_arch arch_kgdb_ops = {
	.gdb_bpt_instr = {0xa1},
	.flags = KGDB_HW_BREAKPOINT,
	.set_hw_breakpoint = bfin_set_hw_break,
	.remove_hw_breakpoint = bfin_remove_hw_break,
	.disable_hw_break = bfin_disable_hw_debug,
	.remove_all_hw_break = bfin_remove_all_hw_break,
	.correct_hw_break = bfin_correct_hw_break,
};

#define IN_MEM(addr, size, l1_addr, l1_size) \
({ \
	unsigned long __addr = (unsigned long)(addr); \
	(l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \
})
#define ASYNC_BANK_SIZE \
	(ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
	 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE)

int kgdb_validate_break_address(unsigned long addr)
{
	int cpu = raw_smp_processor_id();

	if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end)
		return 0;
	if (IN_MEM(addr, BREAK_INSTR_SIZE, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE))
		return 0;
	if (cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH))
		return 0;
#ifdef CONFIG_SMP
	else if (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH))
		return 0;
#endif
	if (IN_MEM(addr, BREAK_INSTR_SIZE, L2_START, L2_LENGTH))
		return 0;

	return -EFAULT;
}

void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long ip)
{
	regs->retx = ip;
}

int kgdb_arch_init(void)
{
	kgdb_single_step = 0;
#ifdef CONFIG_IPIPE
	kgdb_arch_imask = 0;
#endif

	bfin_remove_all_hw_break();
	return 0;
}

void kgdb_arch_exit(void)
{
}
Commit	Line	Data
474f1a66	1	/*
a5ac0129	2	* arch/blackfin/kernel/kgdb.c - Blackfin kgdb pieces
474f1a66	3	*
a5ac0129	4	* Copyright 2005-2008 Analog Devices Inc.
474f1a66	5	*
a5ac0129	6	* Licensed under the GPL-2 or later.
474f1a66 SZ	7	*/
474f1a66 SZ	8
474f1a66 SZ	9	#include <linux/ptrace.h> /* for linux pt_regs struct */
474f1a66 SZ	10	#include <linux/kgdb.h>
a5ac0129	11	#include <linux/uaccess.h>
259c9b17	12	#include <asm/irq_regs.h>
474f1a66	13
a5ac0129	14	void pt_regs_to_gdb_regs(unsigned long gdb_regs, struct pt_regs regs)
474f1a66 SZ	15	{
	16	gdb_regs[BFIN_R0] = regs->r0;
	17	gdb_regs[BFIN_R1] = regs->r1;
	18	gdb_regs[BFIN_R2] = regs->r2;
	19	gdb_regs[BFIN_R3] = regs->r3;
	20	gdb_regs[BFIN_R4] = regs->r4;
	21	gdb_regs[BFIN_R5] = regs->r5;
	22	gdb_regs[BFIN_R6] = regs->r6;
	23	gdb_regs[BFIN_R7] = regs->r7;
	24	gdb_regs[BFIN_P0] = regs->p0;
	25	gdb_regs[BFIN_P1] = regs->p1;
	26	gdb_regs[BFIN_P2] = regs->p2;
	27	gdb_regs[BFIN_P3] = regs->p3;
	28	gdb_regs[BFIN_P4] = regs->p4;
	29	gdb_regs[BFIN_P5] = regs->p5;
	30	gdb_regs[BFIN_SP] = regs->reserved;
	31	gdb_regs[BFIN_FP] = regs->fp;
	32	gdb_regs[BFIN_I0] = regs->i0;
	33	gdb_regs[BFIN_I1] = regs->i1;
	34	gdb_regs[BFIN_I2] = regs->i2;
	35	gdb_regs[BFIN_I3] = regs->i3;
	36	gdb_regs[BFIN_M0] = regs->m0;
	37	gdb_regs[BFIN_M1] = regs->m1;
	38	gdb_regs[BFIN_M2] = regs->m2;
	39	gdb_regs[BFIN_M3] = regs->m3;
	40	gdb_regs[BFIN_B0] = regs->b0;
	41	gdb_regs[BFIN_B1] = regs->b1;
	42	gdb_regs[BFIN_B2] = regs->b2;
	43	gdb_regs[BFIN_B3] = regs->b3;
	44	gdb_regs[BFIN_L0] = regs->l0;
	45	gdb_regs[BFIN_L1] = regs->l1;
	46	gdb_regs[BFIN_L2] = regs->l2;
	47	gdb_regs[BFIN_L3] = regs->l3;
	48	gdb_regs[BFIN_A0_DOT_X] = regs->a0x;
	49	gdb_regs[BFIN_A0_DOT_W] = regs->a0w;
	50	gdb_regs[BFIN_A1_DOT_X] = regs->a1x;
	51	gdb_regs[BFIN_A1_DOT_W] = regs->a1w;
	52	gdb_regs[BFIN_ASTAT] = regs->astat;
	53	gdb_regs[BFIN_RETS] = regs->rets;
	54	gdb_regs[BFIN_LC0] = regs->lc0;
	55	gdb_regs[BFIN_LT0] = regs->lt0;
	56	gdb_regs[BFIN_LB0] = regs->lb0;
	57	gdb_regs[BFIN_LC1] = regs->lc1;
	58	gdb_regs[BFIN_LT1] = regs->lt1;
	59	gdb_regs[BFIN_LB1] = regs->lb1;
	60	gdb_regs[BFIN_CYCLES] = 0;
	61	gdb_regs[BFIN_CYCLES2] = 0;
	62	gdb_regs[BFIN_USP] = regs->usp;
	63	gdb_regs[BFIN_SEQSTAT] = regs->seqstat;
	64	gdb_regs[BFIN_SYSCFG] = regs->syscfg;
	65	gdb_regs[BFIN_RETI] = regs->pc;
	66	gdb_regs[BFIN_RETX] = regs->retx;
	67	gdb_regs[BFIN_RETN] = regs->retn;
	68	gdb_regs[BFIN_RETE] = regs->rete;
	69	gdb_regs[BFIN_PC] = regs->pc;
d2db97bf	70	gdb_regs[BFIN_CC] = (regs->astat >> 5) & 1;
474f1a66 SZ	71	gdb_regs[BFIN_EXTRA1] = 0;
	72	gdb_regs[BFIN_EXTRA2] = 0;
	73	gdb_regs[BFIN_EXTRA3] = 0;
	74	gdb_regs[BFIN_IPEND] = regs->ipend;
	75	}
	76
	77	/*
	78	* Extracts ebp, esp and eip values understandable by gdb from the values
	79	* saved by switch_to.
	80	* thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp
025dfdaf	81	* prior to entering switch_to is 8 greater than the value that is saved.
474f1a66 SZ	82	* If switch_to changes, change following code appropriately.
	83	*/
	84	void sleeping_thread_to_gdb_regs(unsigned long gdb_regs, struct task_struct p)
	85	{
	86	gdb_regs[BFIN_SP] = p->thread.ksp;
	87	gdb_regs[BFIN_PC] = p->thread.pc;
	88	gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat;
	89	}
	90
a5ac0129	91	void gdb_regs_to_pt_regs(unsigned long gdb_regs, struct pt_regs regs)
474f1a66 SZ	92	{
	93	regs->r0 = gdb_regs[BFIN_R0];
	94	regs->r1 = gdb_regs[BFIN_R1];
	95	regs->r2 = gdb_regs[BFIN_R2];
	96	regs->r3 = gdb_regs[BFIN_R3];
	97	regs->r4 = gdb_regs[BFIN_R4];
	98	regs->r5 = gdb_regs[BFIN_R5];
	99	regs->r6 = gdb_regs[BFIN_R6];
	100	regs->r7 = gdb_regs[BFIN_R7];
	101	regs->p0 = gdb_regs[BFIN_P0];
	102	regs->p1 = gdb_regs[BFIN_P1];
	103	regs->p2 = gdb_regs[BFIN_P2];
	104	regs->p3 = gdb_regs[BFIN_P3];
	105	regs->p4 = gdb_regs[BFIN_P4];
	106	regs->p5 = gdb_regs[BFIN_P5];
	107	regs->fp = gdb_regs[BFIN_FP];
	108	regs->i0 = gdb_regs[BFIN_I0];
	109	regs->i1 = gdb_regs[BFIN_I1];
	110	regs->i2 = gdb_regs[BFIN_I2];
	111	regs->i3 = gdb_regs[BFIN_I3];
	112	regs->m0 = gdb_regs[BFIN_M0];
	113	regs->m1 = gdb_regs[BFIN_M1];
	114	regs->m2 = gdb_regs[BFIN_M2];
	115	regs->m3 = gdb_regs[BFIN_M3];
	116	regs->b0 = gdb_regs[BFIN_B0];
	117	regs->b1 = gdb_regs[BFIN_B1];
	118	regs->b2 = gdb_regs[BFIN_B2];
	119	regs->b3 = gdb_regs[BFIN_B3];
	120	regs->l0 = gdb_regs[BFIN_L0];
	121	regs->l1 = gdb_regs[BFIN_L1];
	122	regs->l2 = gdb_regs[BFIN_L2];
	123	regs->l3 = gdb_regs[BFIN_L3];
	124	regs->a0x = gdb_regs[BFIN_A0_DOT_X];
	125	regs->a0w = gdb_regs[BFIN_A0_DOT_W];
	126	regs->a1x = gdb_regs[BFIN_A1_DOT_X];
	127	regs->a1w = gdb_regs[BFIN_A1_DOT_W];
	128	regs->rets = gdb_regs[BFIN_RETS];
	129	regs->lc0 = gdb_regs[BFIN_LC0];
	130	regs->lt0 = gdb_regs[BFIN_LT0];
	131	regs->lb0 = gdb_regs[BFIN_LB0];
	132	regs->lc1 = gdb_regs[BFIN_LC1];
	133	regs->lt1 = gdb_regs[BFIN_LT1];
	134	regs->lb1 = gdb_regs[BFIN_LB1];
	135	regs->usp = gdb_regs[BFIN_USP];
	136	regs->syscfg = gdb_regs[BFIN_SYSCFG];
7fe1a912	137	regs->retx = gdb_regs[BFIN_RETX];
474f1a66 SZ	138	regs->retn = gdb_regs[BFIN_RETN];
	139	regs->rete = gdb_regs[BFIN_RETE];
	140	regs->pc = gdb_regs[BFIN_PC];
	141
	142	#if 0 /* can't change these */
	143	regs->astat = gdb_regs[BFIN_ASTAT];
	144	regs->seqstat = gdb_regs[BFIN_SEQSTAT];
	145	regs->ipend = gdb_regs[BFIN_IPEND];
	146	#endif
	147	}
	148
8d0177db	149	static struct hw_breakpoint {
474f1a66 SZ	150	unsigned int occupied:1;
	151	unsigned int skip:1;
	152	unsigned int enabled:1;
	153	unsigned int type:1;
	154	unsigned int dataacc:2;
	155	unsigned short count;
	156	unsigned int addr;
a5ac0129	157	} breakinfo[HW_WATCHPOINT_NUM];
474f1a66	158
8d0177db	159	static int bfin_set_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
474f1a66 SZ	160	{
474f1a66 SZ	161	int breakno;
a5ac0129 SZ	162	int bfin_type;
	163	int dataacc = 0;
	164
	165	switch (type) {
	166	case BP_HARDWARE_BREAKPOINT:
	167	bfin_type = TYPE_INST_WATCHPOINT;
	168	break;
	169	case BP_WRITE_WATCHPOINT:
	170	dataacc = 1;
	171	bfin_type = TYPE_DATA_WATCHPOINT;
	172	break;
	173	case BP_READ_WATCHPOINT:
	174	dataacc = 2;
	175	bfin_type = TYPE_DATA_WATCHPOINT;
	176	break;
	177	case BP_ACCESS_WATCHPOINT:
	178	dataacc = 3;
	179	bfin_type = TYPE_DATA_WATCHPOINT;
	180	break;
	181	default:
	182	return -ENOSPC;
	183	}
	184
25985edc	185	/* Because hardware data watchpoint impelemented in current
a5ac0129 SZ	186	* Blackfin can not trigger an exception event as the hardware
	187	* instrction watchpoint does, we ignaore all data watch point here.
	188	* They can be turned on easily after future blackfin design
	189	* supports this feature.
	190	*/
	191	for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
	192	if (bfin_type == breakinfo[breakno].type
	193	&& !breakinfo[breakno].occupied) {
474f1a66	194	breakinfo[breakno].occupied = 1;
8a0e9acf	195	breakinfo[breakno].skip = 0;
474f1a66	196	breakinfo[breakno].enabled = 1;
474f1a66	197	breakinfo[breakno].addr = addr;
a5ac0129 SZ	198	breakinfo[breakno].dataacc = dataacc;
a5ac0129 SZ	199	breakinfo[breakno].count = 0;
474f1a66 SZ	200	return 0;
	201	}
	202
	203	return -ENOSPC;
	204	}
	205
8d0177db	206	static int bfin_remove_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
474f1a66 SZ	207	{
474f1a66 SZ	208	int breakno;
a5ac0129 SZ	209	int bfin_type;
	210
	211	switch (type) {
	212	case BP_HARDWARE_BREAKPOINT:
	213	bfin_type = TYPE_INST_WATCHPOINT;
	214	break;
	215	case BP_WRITE_WATCHPOINT:
	216	case BP_READ_WATCHPOINT:
	217	case BP_ACCESS_WATCHPOINT:
	218	bfin_type = TYPE_DATA_WATCHPOINT;
	219	break;
	220	default:
	221	return 0;
	222	}
	223	for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
	224	if (bfin_type == breakinfo[breakno].type
	225	&& breakinfo[breakno].occupied
	226	&& breakinfo[breakno].addr == addr) {
	227	breakinfo[breakno].occupied = 0;
	228	breakinfo[breakno].enabled = 0;
	229	}
474f1a66 SZ	230
	231	return 0;
	232	}
	233
8d0177db	234	static void bfin_remove_all_hw_break(void)
474f1a66	235	{
a5ac0129	236	int breakno;
474f1a66	237
a5ac0129 SZ	238	memset(breakinfo, 0, sizeof(struct hw_breakpoint)*HW_WATCHPOINT_NUM);
	239
	240	for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
	241	breakinfo[breakno].type = TYPE_INST_WATCHPOINT;
	242	for (; breakno < HW_WATCHPOINT_NUM; breakno++)
	243	breakinfo[breakno].type = TYPE_DATA_WATCHPOINT;
474f1a66	244	}
474f1a66	245
8d0177db	246	static void bfin_correct_hw_break(void)
474f1a66 SZ	247	{
474f1a66 SZ	248	int breakno;
a5ac0129 SZ	249	unsigned int wpiactl = 0;
	250	unsigned int wpdactl = 0;
	251	int enable_wp = 0;
	252
	253	for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
	254	if (breakinfo[breakno].enabled) {
	255	enable_wp = 1;
474f1a66	256
474f1a66 SZ	257	switch (breakno) {
474f1a66 SZ	258	case 0:
a5ac0129 SZ	259	wpiactl \|= WPIAEN0\|WPICNTEN0;
	260	bfin_write_WPIA0(breakinfo[breakno].addr);
	261	bfin_write_WPIACNT0(breakinfo[breakno].count
	262	+ breakinfo->skip);
474f1a66	263	break;
474f1a66	264	case 1:
a5ac0129 SZ	265	wpiactl \|= WPIAEN1\|WPICNTEN1;
	266	bfin_write_WPIA1(breakinfo[breakno].addr);
	267	bfin_write_WPIACNT1(breakinfo[breakno].count
	268	+ breakinfo->skip);
474f1a66	269	break;
474f1a66	270	case 2:
a5ac0129 SZ	271	wpiactl \|= WPIAEN2\|WPICNTEN2;
	272	bfin_write_WPIA2(breakinfo[breakno].addr);
	273	bfin_write_WPIACNT2(breakinfo[breakno].count
	274	+ breakinfo->skip);
474f1a66	275	break;
474f1a66	276	case 3:
a5ac0129 SZ	277	wpiactl \|= WPIAEN3\|WPICNTEN3;
	278	bfin_write_WPIA3(breakinfo[breakno].addr);
	279	bfin_write_WPIACNT3(breakinfo[breakno].count
	280	+ breakinfo->skip);
474f1a66 SZ	281	break;
474f1a66 SZ	282	case 4:
a5ac0129 SZ	283	wpiactl \|= WPIAEN4\|WPICNTEN4;
	284	bfin_write_WPIA4(breakinfo[breakno].addr);
	285	bfin_write_WPIACNT4(breakinfo[breakno].count
	286	+ breakinfo->skip);
474f1a66 SZ	287	break;
474f1a66 SZ	288	case 5:
a5ac0129 SZ	289	wpiactl \|= WPIAEN5\|WPICNTEN5;
	290	bfin_write_WPIA5(breakinfo[breakno].addr);
	291	bfin_write_WPIACNT5(breakinfo[breakno].count
	292	+ breakinfo->skip);
	293	break;
	294	case 6:
	295	wpdactl \|= WPDAEN0\|WPDCNTEN0\|WPDSRC0;
	296	wpdactl \|= breakinfo[breakno].dataacc
	297	<< WPDACC0_OFFSET;
	298	bfin_write_WPDA0(breakinfo[breakno].addr);
	299	bfin_write_WPDACNT0(breakinfo[breakno].count
	300	+ breakinfo->skip);
	301	break;
	302	case 7:
	303	wpdactl \|= WPDAEN1\|WPDCNTEN1\|WPDSRC1;
	304	wpdactl \|= breakinfo[breakno].dataacc
	305	<< WPDACC1_OFFSET;
	306	bfin_write_WPDA1(breakinfo[breakno].addr);
	307	bfin_write_WPDACNT1(breakinfo[breakno].count
	308	+ breakinfo->skip);
474f1a66 SZ	309	break;
	310	}
	311	}
a5ac0129 SZ	312
	313	/* Should enable WPPWR bit first before set any other
	314	* WPIACTL and WPDACTL bits */
	315	if (enable_wp) {
	316	bfin_write_WPIACTL(WPPWR);
	317	CSYNC();
	318	bfin_write_WPIACTL(wpiactl\|WPPWR);
474f1a66 SZ	319	bfin_write_WPDACTL(wpdactl);
474f1a66 SZ	320	CSYNC();
474f1a66 SZ	321	}
	322	}
	323
d7ba979d	324	static void bfin_disable_hw_debug(struct pt_regs *regs)
474f1a66 SZ	325	{
474f1a66 SZ	326	/* Disable hardware debugging while we are in kgdb */
a5ac0129 SZ	327	bfin_write_WPIACTL(0);
a5ac0129 SZ	328	bfin_write_WPDACTL(0);
474f1a66 SZ	329	CSYNC();
	330	}
	331
a5ac0129 SZ	332	#ifdef CONFIG_SMP
	333	void kgdb_passive_cpu_callback(void *info)
	334	{
	335	kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs());
	336	}
	337
	338	void kgdb_roundup_cpus(unsigned long flags)
	339	{
1439d030 SZ	340	unsigned int cpu;
	341
	342	for (cpu = cpumask_first(cpu_online_mask); cpu < nr_cpu_ids;
a0f4207d SZ	343	cpu = cpumask_next(cpu, cpu_online_mask))
	344	smp_call_function_single(cpu, kgdb_passive_cpu_callback,
	345	NULL, 0);
a5ac0129 SZ	346	}
	347
	348	void kgdb_roundup_cpu(int cpu, unsigned long flags)
	349	{
a0f4207d	350	smp_call_function_single(cpu, kgdb_passive_cpu_callback, NULL, 0);
a5ac0129 SZ	351	}
	352	#endif
	353
900de051 SZ	354	#ifdef CONFIG_IPIPE
900de051 SZ	355	static unsigned long kgdb_arch_imask;
b68233e7	356	#endif
900de051	357
a5ac0129	358	int kgdb_arch_handle_exception(int vector, int signo,
474f1a66 SZ	359	int err_code, char *remcom_in_buffer,
474f1a66 SZ	360	char *remcom_out_buffer,
a5ac0129	361	struct pt_regs *regs)
474f1a66 SZ	362	{
474f1a66 SZ	363	long addr;
474f1a66 SZ	364	char *ptr;
474f1a66 SZ	365	int newPC;
0d1cdd7a	366	int i;
474f1a66 SZ	367
	368	switch (remcom_in_buffer[0]) {
	369	case 'c':
	370	case 's':
	371	if (kgdb_contthread && kgdb_contthread != current) {
	372	strcpy(remcom_out_buffer, "E00");
	373	break;
	374	}
	375
	376	kgdb_contthread = NULL;
	377
	378	/* try to read optional parameter, pc unchanged if no parm */
	379	ptr = &remcom_in_buffer[1];
	380	if (kgdb_hex2long(&ptr, &addr)) {
a5ac0129	381	regs->retx = addr;
474f1a66	382	}
a5ac0129	383	newPC = regs->retx;
474f1a66 SZ	384
474f1a66 SZ	385	/* clear the trace bit */
a5ac0129	386	regs->syscfg &= 0xfffffffe;
474f1a66 SZ	387
	388	/* set the trace bit if we're stepping */
	389	if (remcom_in_buffer[0] == 's') {
a5ac0129 SZ	390	regs->syscfg \|= 0x1;
	391	kgdb_single_step = regs->ipend;
	392	kgdb_single_step >>= 6;
	393	for (i = 10; i > 0; i--, kgdb_single_step >>= 1)
	394	if (kgdb_single_step & 1)
0d1cdd7a SZ	395	break;
	396	/* i indicate event priority of current stopped instruction
	397	* user space instruction is 0, IVG15 is 1, IVTMR is 10.
a5ac0129	398	* kgdb_single_step > 0 means in single step mode
0d1cdd7a	399	*/
a5ac0129	400	kgdb_single_step = i + 1;
900de051	401
b68233e7	402	preempt_disable();
900de051 SZ	403	#ifdef CONFIG_IPIPE
	404	kgdb_arch_imask = cpu_pda[raw_smp_processor_id()].ex_imask;
	405	cpu_pda[raw_smp_processor_id()].ex_imask = 0;
	406	#endif
474f1a66 SZ	407	}
474f1a66 SZ	408
a5ac0129	409	bfin_correct_hw_break();
474f1a66 SZ	410
	411	return 0;
	412	} /* switch */
	413	return -1; /* this means that we do not want to exit from the handler */
	414	}
	415
	416	struct kgdb_arch arch_kgdb_ops = {
	417	.gdb_bpt_instr = {0xa1},
	418	.flags = KGDB_HW_BREAKPOINT,
a5ac0129 SZ	419	.set_hw_breakpoint = bfin_set_hw_break,
a5ac0129 SZ	420	.remove_hw_breakpoint = bfin_remove_hw_break,
d7ba979d	421	.disable_hw_break = bfin_disable_hw_debug,
a5ac0129 SZ	422	.remove_all_hw_break = bfin_remove_all_hw_break,
a5ac0129 SZ	423	.correct_hw_break = bfin_correct_hw_break,
474f1a66	424	};
a5ac0129	425
e56e03b0 MF	426	#define IN_MEM(addr, size, l1_addr, l1_size) \
	427	({ \
	428	unsigned long __addr = (unsigned long)(addr); \
	429	(l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \
	430	})
	431	#define ASYNC_BANK_SIZE \
	432	(ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
	433	ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE)
	434
a5ac0129 SZ	435	int kgdb_validate_break_address(unsigned long addr)
	436	{
	437	int cpu = raw_smp_processor_id();
	438
	439	if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end)
	440	return 0;
31fba6e7	441	if (IN_MEM(addr, BREAK_INSTR_SIZE, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE))
a5ac0129	442	return 0;
31fba6e7	443	if (cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH))
a5ac0129	444	return 0;
31fba6e7 MF	445	#ifdef CONFIG_SMP
31fba6e7 MF	446	else if (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH))
a5ac0129	447	return 0;
a5ac0129	448	#endif
31fba6e7	449	if (IN_MEM(addr, BREAK_INSTR_SIZE, L2_START, L2_LENGTH))
a5ac0129	450	return 0;
a5ac0129	451
11aca0e7	452	return -EFAULT;
a5ac0129 SZ	453	}
a5ac0129 SZ	454
e8861129 JW	455	void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long ip)
	456	{
	457	regs->retx = ip;
	458	}
	459
a5ac0129 SZ	460	int kgdb_arch_init(void)
	461	{
	462	kgdb_single_step = 0;
900de051 SZ	463	#ifdef CONFIG_IPIPE
	464	kgdb_arch_imask = 0;
	465	#endif
a5ac0129 SZ	466
	467	bfin_remove_all_hw_break();
	468	return 0;
	469	}
	470
	471	void kgdb_arch_exit(void)
	472	{
	473	}