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| Commit | Line | Data |
|---|---|---|
| 2f6f4bcd BW |
1 | /* |
| 2 | * File: include/asm-blackfin/mach-bf518/mem_init.h | |
| 3 | * Based on: | |
| 4 | * Author: | |
| 5 | * | |
| 6 | * Created: | |
| 7 | * Description: | |
| 8 | * | |
| 9 | * Rev: | |
| 10 | * | |
| 11 | * Modified: | |
| 12 | * Copyright 2004-2007 Analog Devices Inc. | |
| 13 | * | |
| 14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
| 15 | * | |
| 16 | * This program is free software; you can redistribute it and/or modify | |
| 17 | * it under the terms of the GNU General Public License as published by | |
| 18 | * the Free Software Foundation; either version 2, or (at your option) | |
| 19 | * any later version. | |
| 20 | * | |
| 21 | * This program is distributed in the hope that it will be useful, | |
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 24 | * GNU General Public License for more details. | |
| 25 | * | |
| 26 | * You should have received a copy of the GNU General Public License | |
| 27 | * along with this program; see the file COPYING. | |
| 28 | * If not, write to the Free Software Foundation, | |
| 29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
| 30 | */ | |
| 31 | ||
| 32 | #if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75 || CONFIG_MEM_MT48LC32M16A2TG_75) | |
| 33 | #if (CONFIG_SCLK_HZ > 119402985) | |
| 34 | #define SDRAM_tRP TRP_2 | |
| 35 | #define SDRAM_tRP_num 2 | |
| 36 | #define SDRAM_tRAS TRAS_7 | |
| 37 | #define SDRAM_tRAS_num 7 | |
| 38 | #define SDRAM_tRCD TRCD_2 | |
| 39 | #define SDRAM_tWR TWR_2 | |
| 40 | #endif | |
| 41 | #if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985) | |
| 42 | #define SDRAM_tRP TRP_2 | |
| 43 | #define SDRAM_tRP_num 2 | |
| 44 | #define SDRAM_tRAS TRAS_6 | |
| 45 | #define SDRAM_tRAS_num 6 | |
| 46 | #define SDRAM_tRCD TRCD_2 | |
| 47 | #define SDRAM_tWR TWR_2 | |
| 48 | #endif | |
| 49 | #if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612) | |
| 50 | #define SDRAM_tRP TRP_2 | |
| 51 | #define SDRAM_tRP_num 2 | |
| 52 | #define SDRAM_tRAS TRAS_5 | |
| 53 | #define SDRAM_tRAS_num 5 | |
| 54 | #define SDRAM_tRCD TRCD_2 | |
| 55 | #define SDRAM_tWR TWR_2 | |
| 56 | #endif | |
| 57 | #if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239) | |
| 58 | #define SDRAM_tRP TRP_2 | |
| 59 | #define SDRAM_tRP_num 2 | |
| 60 | #define SDRAM_tRAS TRAS_4 | |
| 61 | #define SDRAM_tRAS_num 4 | |
| 62 | #define SDRAM_tRCD TRCD_2 | |
| 63 | #define SDRAM_tWR TWR_2 | |
| 64 | #endif | |
| 65 | #if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866) | |
| 66 | #define SDRAM_tRP TRP_2 | |
| 67 | #define SDRAM_tRP_num 2 | |
| 68 | #define SDRAM_tRAS TRAS_3 | |
| 69 | #define SDRAM_tRAS_num 3 | |
| 70 | #define SDRAM_tRCD TRCD_2 | |
| 71 | #define SDRAM_tWR TWR_2 | |
| 72 | #endif | |
| 73 | #if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667) | |
| 74 | #define SDRAM_tRP TRP_1 | |
| 75 | #define SDRAM_tRP_num 1 | |
| 76 | #define SDRAM_tRAS TRAS_4 | |
| 77 | #define SDRAM_tRAS_num 3 | |
| 78 | #define SDRAM_tRCD TRCD_1 | |
| 79 | #define SDRAM_tWR TWR_2 | |
| 80 | #endif | |
| 81 | #if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493) | |
| 82 | #define SDRAM_tRP TRP_1 | |
| 83 | #define SDRAM_tRP_num 1 | |
| 84 | #define SDRAM_tRAS TRAS_3 | |
| 85 | #define SDRAM_tRAS_num 3 | |
| 86 | #define SDRAM_tRCD TRCD_1 | |
| 87 | #define SDRAM_tWR TWR_2 | |
| 88 | #endif | |
| 89 | #if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119) | |
| 90 | #define SDRAM_tRP TRP_1 | |
| 91 | #define SDRAM_tRP_num 1 | |
| 92 | #define SDRAM_tRAS TRAS_2 | |
| 93 | #define SDRAM_tRAS_num 2 | |
| 94 | #define SDRAM_tRCD TRCD_1 | |
| 95 | #define SDRAM_tWR TWR_2 | |
| 96 | #endif | |
| 97 | #if (CONFIG_SCLK_HZ <= 29850746) | |
| 98 | #define SDRAM_tRP TRP_1 | |
| 99 | #define SDRAM_tRP_num 1 | |
| 100 | #define SDRAM_tRAS TRAS_1 | |
| 101 | #define SDRAM_tRAS_num 1 | |
| 102 | #define SDRAM_tRCD TRCD_1 | |
| 103 | #define SDRAM_tWR TWR_2 | |
| 104 | #endif | |
| 105 | #endif | |
| 106 | ||
| 107 | #if (CONFIG_MEM_MT48LC16M16A2TG_75) | |
| 108 | /*SDRAM INFORMATION: */ | |
| 109 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | |
| 110 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | |
| 111 | #define SDRAM_CL CL_3 | |
| 112 | #endif | |
| 113 | ||
| 114 | #if (CONFIG_MEM_MT48LC16M8A2TG_75) | |
| 115 | /*SDRAM INFORMATION: */ | |
| 116 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | |
| 117 | #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ | |
| 118 | #define SDRAM_CL CL_3 | |
| 119 | #endif | |
| 120 | ||
| 121 | #if (CONFIG_MEM_MT48LC32M8A2_75) | |
| 122 | /*SDRAM INFORMATION: */ | |
| 123 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | |
| 124 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | |
| 125 | #define SDRAM_CL CL_3 | |
| 126 | #endif | |
| 127 | ||
| 128 | #if (CONFIG_MEM_MT48LC64M4A2FB_7E) | |
| 129 | /*SDRAM INFORMATION: */ | |
| 130 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | |
| 131 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | |
| 132 | #define SDRAM_CL CL_3 | |
| 133 | #endif | |
| 134 | ||
| 135 | #if (CONFIG_MEM_GENERIC_BOARD) | |
| 136 | /*SDRAM INFORMATION: Modify this for your board */ | |
| 137 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | |
| 138 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | |
| 139 | #define SDRAM_CL CL_3 | |
| 140 | #endif | |
| 141 | ||
| 142 | #if (CONFIG_MEM_MT48LC32M16A2TG_75) | |
| 143 | /*SDRAM INFORMATION: */ | |
| 144 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | |
| 145 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | |
| 146 | #define SDRAM_CL CL_3 | |
| 147 | #endif | |
| 148 | ||
| 149 | /* Equation from section 17 (p17-46) of BF533 HRM */ | |
| 150 | #define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) | |
| 151 | ||
| 152 | /* Enable SCLK Out */ | |
| 153 | #define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS) | |
| 154 | ||
| 155 | #if defined CONFIG_CLKIN_HALF | |
| 156 | #define CLKIN_HALF 1 | |
| 157 | #else | |
| 158 | #define CLKIN_HALF 0 | |
| 159 | #endif | |
| 160 | ||
| 161 | #if defined CONFIG_PLL_BYPASS | |
| 162 | #define PLL_BYPASS 1 | |
| 163 | #else | |
| 164 | #define PLL_BYPASS 0 | |
| 165 | #endif | |
| 166 | ||
| 167 | /***************************************Currently Not Being Used *********************************/ | |
| 168 | #define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | |
| 169 | #define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | |
| 170 | #define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)) | |
| 171 | #define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | |
| 172 | #define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | |
| 173 | ||
| 174 | #if (flash_EBIU_AMBCTL_TT > 3) | |
| 175 | #define flash_EBIU_AMBCTL0_TT B0TT_4 | |
| 176 | #endif | |
| 177 | #if (flash_EBIU_AMBCTL_TT == 3) | |
| 178 | #define flash_EBIU_AMBCTL0_TT B0TT_3 | |
| 179 | #endif | |
| 180 | #if (flash_EBIU_AMBCTL_TT == 2) | |
| 181 | #define flash_EBIU_AMBCTL0_TT B0TT_2 | |
| 182 | #endif | |
| 183 | #if (flash_EBIU_AMBCTL_TT < 2) | |
| 184 | #define flash_EBIU_AMBCTL0_TT B0TT_1 | |
| 185 | #endif | |
| 186 | ||
| 187 | #if (flash_EBIU_AMBCTL_ST > 3) | |
| 188 | #define flash_EBIU_AMBCTL0_ST B0ST_4 | |
| 189 | #endif | |
| 190 | #if (flash_EBIU_AMBCTL_ST == 3) | |
| 191 | #define flash_EBIU_AMBCTL0_ST B0ST_3 | |
| 192 | #endif | |
| 193 | #if (flash_EBIU_AMBCTL_ST == 2) | |
| 194 | #define flash_EBIU_AMBCTL0_ST B0ST_2 | |
| 195 | #endif | |
| 196 | #if (flash_EBIU_AMBCTL_ST < 2) | |
| 197 | #define flash_EBIU_AMBCTL0_ST B0ST_1 | |
| 198 | #endif | |
| 199 | ||
| 200 | #if (flash_EBIU_AMBCTL_HT > 2) | |
| 201 | #define flash_EBIU_AMBCTL0_HT B0HT_3 | |
| 202 | #endif | |
| 203 | #if (flash_EBIU_AMBCTL_HT == 2) | |
| 204 | #define flash_EBIU_AMBCTL0_HT B0HT_2 | |
| 205 | #endif | |
| 206 | #if (flash_EBIU_AMBCTL_HT == 1) | |
| 207 | #define flash_EBIU_AMBCTL0_HT B0HT_1 | |
| 208 | #endif | |
| 209 | #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0) | |
| 210 | #define flash_EBIU_AMBCTL0_HT B0HT_0 | |
| 211 | #endif | |
| 212 | #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0) | |
| 213 | #define flash_EBIU_AMBCTL0_HT B0HT_1 | |
| 214 | #endif | |
| 215 | ||
| 216 | #if (flash_EBIU_AMBCTL_WAT > 14) | |
| 217 | #define flash_EBIU_AMBCTL0_WAT B0WAT_15 | |
| 218 | #endif | |
| 219 | #if (flash_EBIU_AMBCTL_WAT == 14) | |
| 220 | #define flash_EBIU_AMBCTL0_WAT B0WAT_14 | |
| 221 | #endif | |
| 222 | #if (flash_EBIU_AMBCTL_WAT == 13) | |
| 223 | #define flash_EBIU_AMBCTL0_WAT B0WAT_13 | |
| 224 | #endif | |
| 225 | #if (flash_EBIU_AMBCTL_WAT == 12) | |
| 226 | #define flash_EBIU_AMBCTL0_WAT B0WAT_12 | |
| 227 | #endif | |
| 228 | #if (flash_EBIU_AMBCTL_WAT == 11) | |
| 229 | #define flash_EBIU_AMBCTL0_WAT B0WAT_11 | |
| 230 | #endif | |
| 231 | #if (flash_EBIU_AMBCTL_WAT == 10) | |
| 232 | #define flash_EBIU_AMBCTL0_WAT B0WAT_10 | |
| 233 | #endif | |
| 234 | #if (flash_EBIU_AMBCTL_WAT == 9) | |
| 235 | #define flash_EBIU_AMBCTL0_WAT B0WAT_9 | |
| 236 | #endif | |
| 237 | #if (flash_EBIU_AMBCTL_WAT == 8) | |
| 238 | #define flash_EBIU_AMBCTL0_WAT B0WAT_8 | |
| 239 | #endif | |
| 240 | #if (flash_EBIU_AMBCTL_WAT == 7) | |
| 241 | #define flash_EBIU_AMBCTL0_WAT B0WAT_7 | |
| 242 | #endif | |
| 243 | #if (flash_EBIU_AMBCTL_WAT == 6) | |
| 244 | #define flash_EBIU_AMBCTL0_WAT B0WAT_6 | |
| 245 | #endif | |
| 246 | #if (flash_EBIU_AMBCTL_WAT == 5) | |
| 247 | #define flash_EBIU_AMBCTL0_WAT B0WAT_5 | |
| 248 | #endif | |
| 249 | #if (flash_EBIU_AMBCTL_WAT == 4) | |
| 250 | #define flash_EBIU_AMBCTL0_WAT B0WAT_4 | |
| 251 | #endif | |
| 252 | #if (flash_EBIU_AMBCTL_WAT == 3) | |
| 253 | #define flash_EBIU_AMBCTL0_WAT B0WAT_3 | |
| 254 | #endif | |
| 255 | #if (flash_EBIU_AMBCTL_WAT == 2) | |
| 256 | #define flash_EBIU_AMBCTL0_WAT B0WAT_2 | |
| 257 | #endif | |
| 258 | #if (flash_EBIU_AMBCTL_WAT == 1) | |
| 259 | #define flash_EBIU_AMBCTL0_WAT B0WAT_1 | |
| 260 | #endif | |
| 261 | ||
| 262 | #if (flash_EBIU_AMBCTL_RAT > 14) | |
| 263 | #define flash_EBIU_AMBCTL0_RAT B0RAT_15 | |
| 264 | #endif | |
| 265 | #if (flash_EBIU_AMBCTL_RAT == 14) | |
| 266 | #define flash_EBIU_AMBCTL0_RAT B0RAT_14 | |
| 267 | #endif | |
| 268 | #if (flash_EBIU_AMBCTL_RAT == 13) | |
| 269 | #define flash_EBIU_AMBCTL0_RAT B0RAT_13 | |
| 270 | #endif | |
| 271 | #if (flash_EBIU_AMBCTL_RAT == 12) | |
| 272 | #define flash_EBIU_AMBCTL0_RAT B0RAT_12 | |
| 273 | #endif | |
| 274 | #if (flash_EBIU_AMBCTL_RAT == 11) | |
| 275 | #define flash_EBIU_AMBCTL0_RAT B0RAT_11 | |
| 276 | #endif | |
| 277 | #if (flash_EBIU_AMBCTL_RAT == 10) | |
| 278 | #define flash_EBIU_AMBCTL0_RAT B0RAT_10 | |
| 279 | #endif | |
| 280 | #if (flash_EBIU_AMBCTL_RAT == 9) | |
| 281 | #define flash_EBIU_AMBCTL0_RAT B0RAT_9 | |
| 282 | #endif | |
| 283 | #if (flash_EBIU_AMBCTL_RAT == 8) | |
| 284 | #define flash_EBIU_AMBCTL0_RAT B0RAT_8 | |
| 285 | #endif | |
| 286 | #if (flash_EBIU_AMBCTL_RAT == 7) | |
| 287 | #define flash_EBIU_AMBCTL0_RAT B0RAT_7 | |
| 288 | #endif | |
| 289 | #if (flash_EBIU_AMBCTL_RAT == 6) | |
| 290 | #define flash_EBIU_AMBCTL0_RAT B0RAT_6 | |
| 291 | #endif | |
| 292 | #if (flash_EBIU_AMBCTL_RAT == 5) | |
| 293 | #define flash_EBIU_AMBCTL0_RAT B0RAT_5 | |
| 294 | #endif | |
| 295 | #if (flash_EBIU_AMBCTL_RAT == 4) | |
| 296 | #define flash_EBIU_AMBCTL0_RAT B0RAT_4 | |
| 297 | #endif | |
| 298 | #if (flash_EBIU_AMBCTL_RAT == 3) | |
| 299 | #define flash_EBIU_AMBCTL0_RAT B0RAT_3 | |
| 300 | #endif | |
| 301 | #if (flash_EBIU_AMBCTL_RAT == 2) | |
| 302 | #define flash_EBIU_AMBCTL0_RAT B0RAT_2 | |
| 303 | #endif | |
| 304 | #if (flash_EBIU_AMBCTL_RAT == 1) | |
| 305 | #define flash_EBIU_AMBCTL0_RAT B0RAT_1 | |
| 306 | #endif | |
| 307 | ||
| 308 | #define flash_EBIU_AMBCTL0 \ | |
| 309 | (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \ | |
| 310 | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN) |