[deliverable/linux.git] / arch / blackfin / mach-bf533 / head.S

/*
 * File:         arch/blackfin/mach-bf533/head.S
 * Based on:
 * Author:       Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
 *
 * Created:      1998
 * Description:  bf533 startup file
 *
 * Modified:
 *               Copyright 2004-2006 Analog Devices Inc.
 *
 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see the file COPYING, or write
 * to the Free Software Foundation, Inc.,
 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/blackfin.h>
#include <asm/trace.h>
#if CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach-common/clocks.h>
#include <asm/mach/mem_init.h>
#endif
#if CONFIG_DEBUG_KERNEL_START
#include <asm/mach-common/def_LPBlackfin.h>
#endif

.global __rambase
.global __ramstart
.global __ramend
.extern ___bss_stop
.extern ___bss_start
.extern _bf53x_relocate_l1_mem

#define INITIAL_STACK	0xFFB01000

__INIT

ENTRY(__start)
	/* R0: argument of command line string, passed from uboot, save it */
	R7 = R0;
	/* Set the SYSCFG register:
	 * Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
	 */
	R0 = 0x36;
	SYSCFG = R0;
	R0 = 0;

	/* Clear Out All the data and pointer Registers */
	R1 = R0;
	R2 = R0;
	R3 = R0;
	R4 = R0;
	R5 = R0;
	R6 = R0;

	P0 = R0;
	P1 = R0;
	P2 = R0;
	P3 = R0;
	P4 = R0;
	P5 = R0;

	LC0 = r0;
	LC1 = r0;
	L0 = r0;
	L1 = r0;
	L2 = r0;
	L3 = r0;

	/* Clear Out All the DAG Registers */
	B0 = r0;
	B1 = r0;
	B2 = r0;
	B3 = r0;

	I0 = r0;
	I1 = r0;
	I2 = r0;
	I3 = r0;

	M0 = r0;
	M1 = r0;
	M2 = r0;
	M3 = r0;

	trace_buffer_start(p0,r0);
	P0 = R1;
	R0 = R1;

#if CONFIG_DEBUG_KERNEL_START

/*
 * Set up a temporary Event Vector Table, so if something bad happens before
 * the kernel is fully started, it doesn't vector off into the bootloaders
 * table
 */
	P0.l = lo(EVT2);
	P0.h = hi(EVT2);
	P1.l = lo(EVT15);
	P1.h = hi(EVT15);
	P2.l = debug_kernel_start_trap;
	P2.h = debug_kernel_start_trap;

	RTS = P2;
	RTI = P2;
	RTX = P2;
	RTN = P2;
	RTE = P2;

.Lfill_temp_vector_table:
	[P0++] = P2;	/* Core Event Vector Table */
	CC = P0 == P1;
	if !CC JUMP .Lfill_temp_vector_table
	P0 = r0;
	P1 = r0;
	P2 = r0;

#endif

	p0.h = hi(FIO_MASKA_C);
	p0.l = lo(FIO_MASKA_C);
	r0 = 0xFFFF(Z);
	w[p0] = r0.L;	/* Disable all interrupts */
	ssync;

	p0.h = hi(FIO_MASKB_C);
	p0.l = lo(FIO_MASKB_C);
	r0 = 0xFFFF(Z);
	w[p0] = r0.L;	/* Disable all interrupts */
	ssync;

	/* Turn off the icache */
	p0.l = LO(IMEM_CONTROL);
	p0.h = HI(IMEM_CONTROL);
	R1 = [p0];
	R0 = ~ENICPLB;
	R0 = R0 & R1;

	/* Anomaly 05000125 */
#if ANOMALY_05000125
	CLI R2;
	SSYNC;
#endif
	[p0] = R0;
	SSYNC;
#if ANOMALY_05000125
	STI R2;
#endif

	/* Turn off the dcache */
	p0.l = LO(DMEM_CONTROL);
	p0.h = HI(DMEM_CONTROL);
	R1 = [p0];
	R0 = ~ENDCPLB;
	R0 = R0 & R1;

	/* Anomaly 05000125 */
#if ANOMALY_05000125
	CLI R2;
	SSYNC;
#endif
	[p0] = R0;
	SSYNC;
#if ANOMALY_05000125
	STI R2;
#endif

	/* Initialise UART - when booting from u-boot, the UART is not disabled
	 * so if we dont initalize here, our serial console gets hosed */
	p0.h = hi(UART_LCR);
	p0.l = lo(UART_LCR);
	r0 = 0x0(Z);
	w[p0] = r0.L;	/* To enable DLL writes */
	ssync;

	p0.h = hi(UART_DLL);
	p0.l = lo(UART_DLL);
	r0 = 0x0(Z);
	w[p0] = r0.L;
	ssync;

	p0.h = hi(UART_DLH);
	p0.l = lo(UART_DLH);
	r0 = 0x00(Z);
	w[p0] = r0.L;
	ssync;

	p0.h = hi(UART_GCTL);
	p0.l = lo(UART_GCTL);
	r0 = 0x0(Z);
	w[p0] = r0.L;	/* To enable UART clock */
	ssync;

	/* Initialize stack pointer */
	sp.l = lo(INITIAL_STACK);
	sp.h = hi(INITIAL_STACK);
	fp = sp;
	usp = sp;

	/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
	call _bf53x_relocate_l1_mem;
#if CONFIG_BFIN_KERNEL_CLOCK
	call _start_dma_code;
#endif

	/* Code for initializing Async memory banks */

	p2.h = hi(EBIU_AMBCTL1);
	p2.l = lo(EBIU_AMBCTL1);
	r0.h = hi(AMBCTL1VAL);
	r0.l = lo(AMBCTL1VAL);
	[p2] = r0;
	ssync;

	p2.h = hi(EBIU_AMBCTL0);
	p2.l = lo(EBIU_AMBCTL0);
	r0.h = hi(AMBCTL0VAL);
	r0.l = lo(AMBCTL0VAL);
	[p2] = r0;
	ssync;

	p2.h = hi(EBIU_AMGCTL);
	p2.l = lo(EBIU_AMGCTL);
	r0 = AMGCTLVAL;
	w[p2] = r0;
	ssync;

	/* This section keeps the processor in supervisor mode
	 * during kernel boot.  Switches to user mode at end of boot.
	 * See page 3-9 of Hardware Reference manual for documentation.
	 */

	/* EVT15 = _real_start */

	p0.l = lo(EVT15);
	p0.h = hi(EVT15);
	p1.l = _real_start;
	p1.h = _real_start;
	[p0] = p1;
	csync;

	p0.l = lo(IMASK);
	p0.h = hi(IMASK);
	p1.l = IMASK_IVG15;
	p1.h = 0x0;
	[p0] = p1;
	csync;

	raise 15;
	p0.l = .LWAIT_HERE;
	p0.h = .LWAIT_HERE;
	reti = p0;
#if ANOMALY_05000281
	nop; nop; nop;
#endif
	rti;

.LWAIT_HERE:
	jump .LWAIT_HERE;
ENDPROC(__start)

ENTRY(_real_start)
	[ -- sp ] = reti;
	p0.l = lo(WDOG_CTL);
	p0.h = hi(WDOG_CTL);
	r0 = 0xAD6(z);
	w[p0] = r0;	/* watchdog off for now */
	ssync;

	/* Code update for BSS size == 0
	 * Zero out the bss region.
	 */

	p1.l = ___bss_start;
	p1.h = ___bss_start;
	p2.l = ___bss_stop;
	p2.h = ___bss_stop;
	r0 = 0;
	p2 -= p1;
	lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
.L_clear_bss:
	B[p1++] = r0;

	/* In case there is a NULL pointer reference
	 * Zero out region before stext
	 */

	p1.l = 0x0;
	p1.h = 0x0;
	r0.l = __stext;
	r0.h = __stext;
	r0 = r0 >> 1;
	p2 = r0;
	r0 = 0;
	lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
.L_clear_zero:
	W[p1++] = r0;

	/* pass the uboot arguments to the global value command line */
	R0 = R7;
	call _cmdline_init;

	p1.l = __rambase;
	p1.h = __rambase;
	r0.l = __sdata;
	r0.h = __sdata;
	[p1] = r0;

	p1.l = __ramstart;
	p1.h = __ramstart;
	p3.l = ___bss_stop;
	p3.h = ___bss_stop;

	r1 = p3;
	[p1] = r1;

	/*
	 * load the current thread pointer and stack
	 */
	r1.l = _init_thread_union;
	r1.h = _init_thread_union;

	r2.l = 0x2000;
	r2.h = 0x0000;
	r1 = r1 + r2;
	sp = r1;
	usp = sp;
	fp = sp;
	jump.l _start_kernel;
ENDPROC(_real_start)

__FINIT

.section .l1.text
#if CONFIG_BFIN_KERNEL_CLOCK
ENTRY(_start_dma_code)
	p0.h = hi(SIC_IWR);
	p0.l = lo(SIC_IWR);
	r0.l = 0x1;
	r0.h = 0x0;
	[p0] = r0;
	SSYNC;

	/*
	 *  Set PLL_CTL
	 *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
	 *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
	 *   - [7]     = output delay (add 200ps of delay to mem signals)
	 *   - [6]     = input delay (add 200ps of input delay to mem signals)
	 *   - [5]     = PDWN      : 1=All Clocks off
	 *   - [3]     = STOPCK    : 1=Core Clock off
	 *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
	 *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
	 *   all other bits set to zero
	 */

	p0.h = hi(PLL_LOCKCNT);
	p0.l = lo(PLL_LOCKCNT);
	r0 = 0x300(Z);
	w[p0] = r0.l;
	ssync;

	P2.H = hi(EBIU_SDGCTL);
	P2.L = lo(EBIU_SDGCTL);
	R0 = [P2];
	BITSET (R0, 24);
	[P2] = R0;
	SSYNC;

	r0 = CONFIG_VCO_MULT & 63;       /* Load the VCO multiplier         */
	r0 = r0 << 9;                    /* Shift it over,                  */
	r1 = CLKIN_HALF;                 /* Do we need to divide CLKIN by 2?*/
	r0 = r1 | r0;
	r1 = PLL_BYPASS;                 /* Bypass the PLL?                 */
	r1 = r1 << 8;                    /* Shift it over                   */
	r0 = r1 | r0;                    /* add them all together           */

	p0.h = hi(PLL_CTL);
	p0.l = lo(PLL_CTL);              /* Load the address                */
	cli r2;                          /* Disable interrupts              */
	ssync;
	w[p0] = r0.l;                    /* Set the value                   */
	idle;                            /* Wait for the PLL to stablize    */
	sti r2;                          /* Enable interrupts               */

.Lcheck_again:
	p0.h = hi(PLL_STAT);
	p0.l = lo(PLL_STAT);
	R0 = W[P0](Z);
	CC = BITTST(R0,5);
	if ! CC jump .Lcheck_again;

	/* Configure SCLK & CCLK Dividers */
	r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
	p0.h = hi(PLL_DIV);
	p0.l = lo(PLL_DIV);
	w[p0] = r0.l;
	ssync;

	p0.l = lo(EBIU_SDRRC);
	p0.h = hi(EBIU_SDRRC);
	r0 = mem_SDRRC;
	w[p0] = r0.l;
	ssync;

	p0.l = LO(EBIU_SDBCTL);
	p0.h = HI(EBIU_SDBCTL);     /* SDRAM Memory Bank Control Register */
	r0 = mem_SDBCTL;
	w[p0] = r0.l;
	ssync;

	P2.H = hi(EBIU_SDGCTL);
	P2.L = lo(EBIU_SDGCTL);
	R0 = [P2];
	BITCLR (R0, 24);
	p0.h = hi(EBIU_SDSTAT);
	p0.l = lo(EBIU_SDSTAT);
	r2.l = w[p0];
	cc = bittst(r2,3);
	if !cc jump .Lskip;
	NOP;
	BITSET (R0, 23);
.Lskip:
	[P2] = R0;
	SSYNC;

	R0.L = lo(mem_SDGCTL);
	R0.H = hi(mem_SDGCTL);
	R1 = [p2];
	R1 = R1 | R0;
	[P2] = R1;
	SSYNC;

	p0.h = hi(SIC_IWR);
	p0.l = lo(SIC_IWR);
	r0.l = lo(IWR_ENABLE_ALL);
	r0.h = hi(IWR_ENABLE_ALL);
	[p0] = r0;
	SSYNC;

	RTS;
ENDPROC(_start_dma_code)
#endif /* CONFIG_BFIN_KERNEL_CLOCK */

ENTRY(_bfin_reset)
	/* No more interrupts to be handled*/
	CLI R6;
	SSYNC;

#if defined(CONFIG_BFIN_SHARED_FLASH_ENET)
	p0.h = hi(FIO_INEN);
	p0.l = lo(FIO_INEN);
	r0.l = ~(1 << CONFIG_ENET_FLASH_PIN);
	w[p0] = r0.l;

	p0.h = hi(FIO_DIR);
	p0.l = lo(FIO_DIR);
	r0.l = (1 << CONFIG_ENET_FLASH_PIN);
	w[p0] = r0.l;

	p0.h = hi(FIO_FLAG_C);
	p0.l = lo(FIO_FLAG_C);
	r0.l = (1 << CONFIG_ENET_FLASH_PIN);
	w[p0] = r0.l;
#endif

	/* Clear the IMASK register */
	p0.h = hi(IMASK);
	p0.l = lo(IMASK);
	r0 = 0x0;
	[p0] = r0;

	/* Clear the ILAT register */
	p0.h = hi(ILAT);
	p0.l = lo(ILAT);
	r0 = [p0];
	[p0] = r0;
	SSYNC;

	/* make sure SYSCR is set to use BMODE */
	P0.h = hi(SYSCR);
	P0.l = lo(SYSCR);
	R0.l = 0x0;
	W[P0] = R0.l;
	SSYNC;

	/* issue a system soft reset */
	P1.h = hi(SWRST);
	P1.l = lo(SWRST);
	R1.l = 0x0007;
	W[P1] = R1;
	SSYNC;

	/* clear system soft reset */
	R0.l = 0x0000;
	W[P0] = R0;
	SSYNC;

	/* issue core reset */
	raise 1;

	RTS;
ENDPROC(_bfin_reset)

#if CONFIG_DEBUG_KERNEL_START
debug_kernel_start_trap:
	/* Set up a temp stack in L1 - SDRAM might not be working  */
	P0.L = lo(L1_DATA_A_START + 0x100);
	P0.H = hi(L1_DATA_A_START + 0x100);
	SP = P0;

	/* Make sure the Clocks are the way I think they should be */
	r0 = CONFIG_VCO_MULT & 63;       /* Load the VCO multiplier         */
	r0 = r0 << 9;                    /* Shift it over,                  */
	r1 = CLKIN_HALF;                 /* Do we need to divide CLKIN by 2?*/
	r0 = r1 | r0;
	r1 = PLL_BYPASS;                 /* Bypass the PLL?                 */
	r1 = r1 << 8;                    /* Shift it over                   */
	r0 = r1 | r0;                    /* add them all together           */

	p0.h = hi(PLL_CTL);
	p0.l = lo(PLL_CTL);              /* Load the address                */
	cli r2;                          /* Disable interrupts              */
	ssync;
	w[p0] = r0.l;                    /* Set the value                   */
	idle;                            /* Wait for the PLL to stablize    */
	sti r2;                          /* Enable interrupts               */

.Lcheck_again1:
	p0.h = hi(PLL_STAT);
	p0.l = lo(PLL_STAT);
	R0 = W[P0](Z);
	CC = BITTST(R0,5);
	if ! CC jump .Lcheck_again1;

	/* Configure SCLK & CCLK Dividers */
	r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
	p0.h = hi(PLL_DIV);
	p0.l = lo(PLL_DIV);
	w[p0] = r0.l;
	ssync;

	/* Make sure UART is enabled - you can never be sure */

/*
 * Setup for console. Argument comes from the menuconfig
 */

#ifdef CONFIG_BAUD_9600
#define CONSOLE_BAUD_RATE       9600
#elif CONFIG_BAUD_19200
#define CONSOLE_BAUD_RATE       19200
#elif CONFIG_BAUD_38400
#define CONSOLE_BAUD_RATE       38400
#elif CONFIG_BAUD_57600
#define CONSOLE_BAUD_RATE       57600
#elif CONFIG_BAUD_115200
#define CONSOLE_BAUD_RATE       115200
#endif

	p0.h = hi(UART_GCTL);
	p0.l = lo(UART_GCTL);
	r0 = 0x00(Z);
	w[p0] = r0.L;   /* To Turn off UART clocks */
	ssync;

	p0.h = hi(UART_LCR);
	p0.l = lo(UART_LCR);
	r0 = 0x83(Z);
	w[p0] = r0.L;   /* To enable DLL writes */
	ssync;

	R1 = (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_SCLK_DIV) / (CONSOLE_BAUD_RATE * 16));

	p0.h = hi(UART_DLL);
	p0.l = lo(UART_DLL);
	r0 = 0xFF(Z);
	r0 = R1 & R0;
	w[p0] = r0.L;
	ssync;

	p0.h = hi(UART_DLH);
	p0.l = lo(UART_DLH);
	r1 >>= 8 ;
	w[p0] = r1.L;
	ssync;

	p0.h = hi(UART_GCTL);
	p0.l = lo(UART_GCTL);
	r0 = 0x0(Z);
	w[p0] = r0.L;   /* To enable UART clock */
	ssync;

	p0.h = hi(UART_LCR);
	p0.l = lo(UART_LCR);
	r0 = 0x03(Z);
	w[p0] = r0.L;   /* To Turn on UART */
	ssync;

	p0.h = hi(UART_GCTL);
	p0.l = lo(UART_GCTL);
	r0 = 0x01(Z);
	w[p0] = r0.L;   /* To Turn on UART Clocks */
	ssync;

	P0.h = hi(UART_THR);
	P0.l = lo(UART_THR);
	P1.h = hi(UART_LSR);
	P1.l = lo(UART_LSR);

	R0.L = 'K';
	call .Lwait_char;
	R0.L='e';
	call .Lwait_char;
	R0.L='r';
	call .Lwait_char;
	R0.L='n'
	call .Lwait_char;
	R0.L='e'
	call .Lwait_char;
	R0.L='l';
	call .Lwait_char;
	R0.L=' ';
	call .Lwait_char;
	R0.L='c';
	call .Lwait_char;
	R0.L='r';
	call .Lwait_char;
	R0.L='a';
	call .Lwait_char;
	R0.L='s';
	call .Lwait_char;
	R0.L='h';
	call .Lwait_char;
	R0.L='\r';
	call .Lwait_char;
	R0.L='\n';
	call .Lwait_char;

	R0.L='S';
	call .Lwait_char;
	R0.L='E';
	call .Lwait_char;
	R0.L='Q'
	call .Lwait_char;
	R0.L='S'
	call .Lwait_char;
	R0.L='T';
	call .Lwait_char;
	R0.L='A';
	call .Lwait_char;
	R0.L='T';
	call .Lwait_char;
	R0.L='=';
	call .Lwait_char;
	R2 = SEQSTAT;
	call .Ldump_reg;

	R0.L=' ';
	call .Lwait_char;
	R0.L='R';
	call .Lwait_char;
	R0.L='E'
	call .Lwait_char;
	R0.L='T'
	call .Lwait_char;
	R0.L='X';
	call .Lwait_char;
	R0.L='=';
	call .Lwait_char;
	R2 = RETX;
	call .Ldump_reg;

	R0.L='\r';
	call .Lwait_char;
	R0.L='\n';
	call .Lwait_char;

.Ldebug_kernel_start_trap_done:
	JUMP    .Ldebug_kernel_start_trap_done;
.Ldump_reg:
	R3 = 32;
	R4 = 0x0F;
	R5 = ':';  /* one past 9 */

.Ldump_reg2:
	R0 = R2;
	R3 += -4;
	R0 >>>= R3;
	R0 = R0 & R4;
	R0 += 0x30;
	CC = R0 <= R5;
	if CC JUMP .Ldump_reg1;
	R0 += 7;

.Ldump_reg1:
	R1.l = W[P1];
	CC = BITTST(R1, 5);
	if !CC JUMP .Ldump_reg1;
	W[P0] = r0;

	CC = R3 == 0;
	if !CC JUMP .Ldump_reg2
	RTS;

.Lwait_char:
	R1.l = W[P1];
	CC = BITTST(R1, 5);
	if !CC JUMP .Lwait_char;
	W[P0] = r0;
	RTS;

#endif  /* CONFIG_DEBUG_KERNEL_START  */

.data

/*
 * Set up the usable of RAM stuff. Size of RAM is determined then
 * an initial stack set up at the end.
 */

.align 4
__rambase:
.long   0
__ramstart:
.long   0
__ramend:
.long   0
Commit	Line	Data
1394f032 BW	1	/*
	2	* File: arch/blackfin/mach-bf533/head.S
	3	* Based on:
	4	* Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
	5	*
	6	* Created: 1998
	7	* Description: bf533 startup file
	8	*
	9	* Modified:
	10	* Copyright 2004-2006 Analog Devices Inc.
	11	*
	12	* Bugs: Enter bugs at http://blackfin.uclinux.org/
	13	*
	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License as published by
	16	* the Free Software Foundation; either version 2 of the License, or
	17	* (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, see the file COPYING, or write
	26	* to the Free Software Foundation, Inc.,
	27	* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	28	*/
	29
	30	#include <linux/linkage.h>
52a07812	31	#include <linux/init.h>
1394f032	32	#include <asm/blackfin.h>
669b792c	33	#include <asm/trace.h>
1394f032	34	#if CONFIG_BFIN_KERNEL_CLOCK
f16295e7	35	#include <asm/mach-common/clocks.h>
1394f032 BW	36	#include <asm/mach/mem_init.h>
	37	#endif
	38	#if CONFIG_DEBUG_KERNEL_START
	39	#include <asm/mach-common/def_LPBlackfin.h>
	40	#endif
	41
	42	.global __rambase
	43	.global __ramstart
	44	.global __ramend
	45	.extern ___bss_stop
	46	.extern ___bss_start
	47	.extern _bf53x_relocate_l1_mem
	48
	49	#define INITIAL_STACK 0xFFB01000
	50
52a07812	51	__INIT
1394f032 BW	52
1394f032 BW	53	ENTRY(__start)
1394f032 BW	54	/* R0: argument of command line string, passed from uboot, save it */
1394f032 BW	55	R7 = R0;
83a5c3e3 MF	56	/* Set the SYSCFG register:
	57	* Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
	58	*/
1394f032	59	R0 = 0x36;
1394f032 BW	60	SYSCFG = R0;
	61	R0 = 0;
	62
83a5c3e3	63	/* Clear Out All the data and pointer Registers */
1394f032 BW	64	R1 = R0;
	65	R2 = R0;
	66	R3 = R0;
	67	R4 = R0;
	68	R5 = R0;
	69	R6 = R0;
	70
	71	P0 = R0;
	72	P1 = R0;
	73	P2 = R0;
	74	P3 = R0;
	75	P4 = R0;
	76	P5 = R0;
	77
	78	LC0 = r0;
	79	LC1 = r0;
	80	L0 = r0;
	81	L1 = r0;
	82	L2 = r0;
	83	L3 = r0;
	84
83a5c3e3	85	/* Clear Out All the DAG Registers */
1394f032 BW	86	B0 = r0;
	87	B1 = r0;
	88	B2 = r0;
	89	B3 = r0;
	90
	91	I0 = r0;
	92	I1 = r0;
	93	I2 = r0;
	94	I3 = r0;
	95
	96	M0 = r0;
	97	M1 = r0;
	98	M2 = r0;
	99	M3 = r0;
	100
669b792c RG	101	trace_buffer_start(p0,r0);
	102	P0 = R1;
	103	R0 = R1;
	104
1394f032 BW	105	#if CONFIG_DEBUG_KERNEL_START
	106
	107	/*
	108	* Set up a temporary Event Vector Table, so if something bad happens before
	109	* the kernel is fully started, it doesn't vector off into the bootloaders
	110	* table
	111	*/
	112	P0.l = lo(EVT2);
	113	P0.h = hi(EVT2);
	114	P1.l = lo(EVT15);
	115	P1.h = hi(EVT15);
	116	P2.l = debug_kernel_start_trap;
	117	P2.h = debug_kernel_start_trap;
	118
	119	RTS = P2;
	120	RTI = P2;
	121	RTX = P2;
	122	RTN = P2;
	123	RTE = P2;
	124
	125	.Lfill_temp_vector_table:
	126	[P0++] = P2; /* Core Event Vector Table */
	127	CC = P0 == P1;
	128	if !CC JUMP .Lfill_temp_vector_table
	129	P0 = r0;
	130	P1 = r0;
	131	P2 = r0;
	132
	133	#endif
	134
	135	p0.h = hi(FIO_MASKA_C);
	136	p0.l = lo(FIO_MASKA_C);
	137	r0 = 0xFFFF(Z);
	138	w[p0] = r0.L; /* Disable all interrupts */
	139	ssync;
	140
	141	p0.h = hi(FIO_MASKB_C);
	142	p0.l = lo(FIO_MASKB_C);
	143	r0 = 0xFFFF(Z);
	144	w[p0] = r0.L; /* Disable all interrupts */
	145	ssync;
	146
	147	/* Turn off the icache */
e208f83a MF	148	p0.l = LO(IMEM_CONTROL);
e208f83a MF	149	p0.h = HI(IMEM_CONTROL);
1394f032 BW	150	R1 = [p0];
	151	R0 = ~ENICPLB;
	152	R0 = R0 & R1;
	153
	154	/* Anomaly 05000125 */
1aafd909	155	#if ANOMALY_05000125
1394f032 BW	156	CLI R2;
	157	SSYNC;
	158	#endif
	159	[p0] = R0;
	160	SSYNC;
1aafd909	161	#if ANOMALY_05000125
1394f032 BW	162	STI R2;
	163	#endif
	164
	165	/* Turn off the dcache */
e208f83a MF	166	p0.l = LO(DMEM_CONTROL);
e208f83a MF	167	p0.h = HI(DMEM_CONTROL);
1394f032 BW	168	R1 = [p0];
	169	R0 = ~ENDCPLB;
	170	R0 = R0 & R1;
	171
	172	/* Anomaly 05000125 */
1aafd909	173	#if ANOMALY_05000125
1394f032 BW	174	CLI R2;
	175	SSYNC;
	176	#endif
	177	[p0] = R0;
	178	SSYNC;
1aafd909	179	#if ANOMALY_05000125
1394f032 BW	180	STI R2;
	181	#endif
	182
5079df99 MF	183	/* Initialise UART - when booting from u-boot, the UART is not disabled
5079df99 MF	184	* so if we dont initalize here, our serial console gets hosed */
1394f032 BW	185	p0.h = hi(UART_LCR);
	186	p0.l = lo(UART_LCR);
	187	r0 = 0x0(Z);
	188	w[p0] = r0.L; /* To enable DLL writes */
	189	ssync;
	190
	191	p0.h = hi(UART_DLL);
	192	p0.l = lo(UART_DLL);
	193	r0 = 0x0(Z);
	194	w[p0] = r0.L;
	195	ssync;
	196
	197	p0.h = hi(UART_DLH);
	198	p0.l = lo(UART_DLH);
	199	r0 = 0x00(Z);
	200	w[p0] = r0.L;
	201	ssync;
	202
	203	p0.h = hi(UART_GCTL);
	204	p0.l = lo(UART_GCTL);
	205	r0 = 0x0(Z);
	206	w[p0] = r0.L; /* To enable UART clock */
	207	ssync;
	208
	209	/* Initialize stack pointer */
	210	sp.l = lo(INITIAL_STACK);
	211	sp.h = hi(INITIAL_STACK);
	212	fp = sp;
	213	usp = sp;
	214
	215	/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
	216	call _bf53x_relocate_l1_mem;
	217	#if CONFIG_BFIN_KERNEL_CLOCK
	218	call _start_dma_code;
	219	#endif
	220
	221	/* Code for initializing Async memory banks */
	222
	223	p2.h = hi(EBIU_AMBCTL1);
	224	p2.l = lo(EBIU_AMBCTL1);
	225	r0.h = hi(AMBCTL1VAL);
	226	r0.l = lo(AMBCTL1VAL);
	227	[p2] = r0;
	228	ssync;
	229
	230	p2.h = hi(EBIU_AMBCTL0);
	231	p2.l = lo(EBIU_AMBCTL0);
	232	r0.h = hi(AMBCTL0VAL);
	233	r0.l = lo(AMBCTL0VAL);
	234	[p2] = r0;
	235	ssync;
	236
	237	p2.h = hi(EBIU_AMGCTL);
	238	p2.l = lo(EBIU_AMGCTL);
	239	r0 = AMGCTLVAL;
	240	w[p2] = r0;
	241	ssync;
	242
	243	/* This section keeps the processor in supervisor mode
	244	* during kernel boot. Switches to user mode at end of boot.
	245	* See page 3-9 of Hardware Reference manual for documentation.
	246	*/
	247
	248	/* EVT15 = _real_start */
249
250	p0.l = lo(EVT15);
251	p0.h = hi(EVT15);
252	p1.l = _real_start;
253	p1.h = _real_start;
254	[p0] = p1;
255	csync;
256
257	p0.l = lo(IMASK);
258	p0.h = hi(IMASK);
259	p1.l = IMASK_IVG15;
260	p1.h = 0x0;
261	[p0] = p1;
262	csync;
263
264	raise 15;
265	p0.l = .LWAIT_HERE;
266	p0.h = .LWAIT_HERE;
267	reti = p0;
1aafd909	268	#if ANOMALY_05000281
1394f032 BW	269	nop; nop; nop;
	270	#endif
	271	rti;
	272
	273	.LWAIT_HERE:
	274	jump .LWAIT_HERE;
52a07812	275	ENDPROC(__start)
1394f032 BW	276
	277	ENTRY(_real_start)
	278	[ -- sp ] = reti;
	279	p0.l = lo(WDOG_CTL);
	280	p0.h = hi(WDOG_CTL);
	281	r0 = 0xAD6(z);
	282	w[p0] = r0; /* watchdog off for now */
	283	ssync;
	284
	285	/* Code update for BSS size == 0
	286	* Zero out the bss region.
	287	*/
	288
	289	p1.l = ___bss_start;
	290	p1.h = ___bss_start;
	291	p2.l = ___bss_stop;
	292	p2.h = ___bss_stop;
	293	r0 = 0;
	294	p2 -= p1;
	295	lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
	296	.L_clear_bss:
	297	B[p1++] = r0;
	298
	299	/* In case there is a NULL pointer reference
	300	* Zero out region before stext
	301	*/
	302
	303	p1.l = 0x0;
	304	p1.h = 0x0;
	305	r0.l = __stext;
	306	r0.h = __stext;
	307	r0 = r0 >> 1;
	308	p2 = r0;
	309	r0 = 0;
	310	lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
	311	.L_clear_zero:
	312	W[p1++] = r0;
	313
83a5c3e3	314	/* pass the uboot arguments to the global value command line */
1394f032 BW	315	R0 = R7;
	316	call _cmdline_init;
	317
	318	p1.l = __rambase;
	319	p1.h = __rambase;
	320	r0.l = __sdata;
	321	r0.h = __sdata;
	322	[p1] = r0;
	323
	324	p1.l = __ramstart;
	325	p1.h = __ramstart;
	326	p3.l = ___bss_stop;
	327	p3.h = ___bss_stop;
	328
	329	r1 = p3;
	330	[p1] = r1;
	331
	332	/*
83a5c3e3	333	* load the current thread pointer and stack
1394f032 BW	334	*/
	335	r1.l = _init_thread_union;
	336	r1.h = _init_thread_union;
	337
	338	r2.l = 0x2000;
	339	r2.h = 0x0000;
	340	r1 = r1 + r2;
	341	sp = r1;
	342	usp = sp;
	343	fp = sp;
52a07812 MF	344	jump.l _start_kernel;
	345	ENDPROC(_real_start)
	346
	347	__FINIT
1394f032 BW	348
	349	.section .l1.text
	350	#if CONFIG_BFIN_KERNEL_CLOCK
	351	ENTRY(_start_dma_code)
	352	p0.h = hi(SIC_IWR);
	353	p0.l = lo(SIC_IWR);
	354	r0.l = 0x1;
	355	r0.h = 0x0;
	356	[p0] = r0;
	357	SSYNC;
	358
	359	/*
	360	* Set PLL_CTL
	361	* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
	362	* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
	363	* - [7] = output delay (add 200ps of delay to mem signals)
	364	* - [6] = input delay (add 200ps of input delay to mem signals)
	365	* - [5] = PDWN : 1=All Clocks off
	366	* - [3] = STOPCK : 1=Core Clock off
	367	* - [1] = PLL_OFF : 1=Disable Power to PLL
	368	* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
	369	* all other bits set to zero
	370	*/
	371
	372	p0.h = hi(PLL_LOCKCNT);
	373	p0.l = lo(PLL_LOCKCNT);
	374	r0 = 0x300(Z);
	375	w[p0] = r0.l;
	376	ssync;
	377
	378	P2.H = hi(EBIU_SDGCTL);
	379	P2.L = lo(EBIU_SDGCTL);
	380	R0 = [P2];
	381	BITSET (R0, 24);
	382	[P2] = R0;
	383	SSYNC;
	384
	385	r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
	386	r0 = r0 << 9; /* Shift it over, */
	387	r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
	388	r0 = r1 \| r0;
	389	r1 = PLL_BYPASS; /* Bypass the PLL? */
	390	r1 = r1 << 8; /* Shift it over */
	391	r0 = r1 \| r0; /* add them all together */
	392
	393	p0.h = hi(PLL_CTL);
	394	p0.l = lo(PLL_CTL); /* Load the address */
	395	cli r2; /* Disable interrupts */
	396	ssync;
	397	w[p0] = r0.l; /* Set the value */
	398	idle; /* Wait for the PLL to stablize */
	399	sti r2; /* Enable interrupts */
	400
	401	.Lcheck_again:
	402	p0.h = hi(PLL_STAT);
	403	p0.l = lo(PLL_STAT);
	404	R0 = W[P0](Z);
	405	CC = BITTST(R0,5);
	406	if ! CC jump .Lcheck_again;
	407
	408	/* Configure SCLK & CCLK Dividers */
	409	r0 = (CONFIG_CCLK_ACT_DIV \| CONFIG_SCLK_DIV);
	410	p0.h = hi(PLL_DIV);
	411	p0.l = lo(PLL_DIV);
412	w[p0] = r0.l;
413	ssync;
414
415	p0.l = lo(EBIU_SDRRC);
416	p0.h = hi(EBIU_SDRRC);
417	r0 = mem_SDRRC;
418	w[p0] = r0.l;
419	ssync;
420
e208f83a MF	421	p0.l = LO(EBIU_SDBCTL);
e208f83a MF	422	p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
1394f032 BW	423	r0 = mem_SDBCTL;
	424	w[p0] = r0.l;
	425	ssync;
	426
	427	P2.H = hi(EBIU_SDGCTL);
	428	P2.L = lo(EBIU_SDGCTL);
	429	R0 = [P2];
	430	BITCLR (R0, 24);
	431	p0.h = hi(EBIU_SDSTAT);
	432	p0.l = lo(EBIU_SDSTAT);
	433	r2.l = w[p0];
	434	cc = bittst(r2,3);
	435	if !cc jump .Lskip;
	436	NOP;
	437	BITSET (R0, 23);
	438	.Lskip:
	439	[P2] = R0;
	440	SSYNC;
	441
	442	R0.L = lo(mem_SDGCTL);
	443	R0.H = hi(mem_SDGCTL);
	444	R1 = [p2];
	445	R1 = R1 \| R0;
	446	[P2] = R1;
	447	SSYNC;
	448
	449	p0.h = hi(SIC_IWR);
	450	p0.l = lo(SIC_IWR);
83a5c3e3 MF	451	r0.l = lo(IWR_ENABLE_ALL);
83a5c3e3 MF	452	r0.h = hi(IWR_ENABLE_ALL);
1394f032 BW	453	[p0] = r0;
	454	SSYNC;
	455
	456	RTS;
52a07812	457	ENDPROC(_start_dma_code)
1394f032 BW	458	#endif /* CONFIG_BFIN_KERNEL_CLOCK */
	459
	460	ENTRY(_bfin_reset)
	461	/* No more interrupts to be handled*/
	462	CLI R6;
	463	SSYNC;
	464
	465	#if defined(CONFIG_BFIN_SHARED_FLASH_ENET)
	466	p0.h = hi(FIO_INEN);
	467	p0.l = lo(FIO_INEN);
	468	r0.l = ~(1 << CONFIG_ENET_FLASH_PIN);
	469	w[p0] = r0.l;
	470
	471	p0.h = hi(FIO_DIR);
	472	p0.l = lo(FIO_DIR);
	473	r0.l = (1 << CONFIG_ENET_FLASH_PIN);
	474	w[p0] = r0.l;
	475
	476	p0.h = hi(FIO_FLAG_C);
	477	p0.l = lo(FIO_FLAG_C);
	478	r0.l = (1 << CONFIG_ENET_FLASH_PIN);
	479	w[p0] = r0.l;
	480	#endif
	481
1394f032 BW	482	/* Clear the IMASK register */
	483	p0.h = hi(IMASK);
	484	p0.l = lo(IMASK);
	485	r0 = 0x0;
	486	[p0] = r0;
	487
	488	/* Clear the ILAT register */
	489	p0.h = hi(ILAT);
	490	p0.l = lo(ILAT);
	491	r0 = [p0];
	492	[p0] = r0;
	493	SSYNC;
	494
ef9256d2 MF	495	/* make sure SYSCR is set to use BMODE */
	496	P0.h = hi(SYSCR);
	497	P0.l = lo(SYSCR);
	498	R0.l = 0x0;
	499	W[P0] = R0.l;
1394f032 BW	500	SSYNC;
1394f032 BW	501
ef9256d2 MF	502	/* issue a system soft reset */
	503	P1.h = hi(SWRST);
	504	P1.l = lo(SWRST);
	505	R1.l = 0x0007;
	506	W[P1] = R1;
1394f032 BW	507	SSYNC;
1394f032 BW	508
ef9256d2 MF	509	/* clear system soft reset */
	510	R0.l = 0x0000;
	511	W[P0] = R0;
1394f032 BW	512	SSYNC;
1394f032 BW	513
ef9256d2 MF	514	/* issue core reset */
ef9256d2 MF	515	raise 1;
1394f032 BW	516
1394f032 BW	517	RTS;
ef9256d2	518	ENDPROC(_bfin_reset)
1394f032 BW	519
	520	#if CONFIG_DEBUG_KERNEL_START
	521	debug_kernel_start_trap:
	522	/* Set up a temp stack in L1 - SDRAM might not be working */
	523	P0.L = lo(L1_DATA_A_START + 0x100);
	524	P0.H = hi(L1_DATA_A_START + 0x100);
	525	SP = P0;
	526
	527	/* Make sure the Clocks are the way I think they should be */
	528	r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
	529	r0 = r0 << 9; /* Shift it over, */
	530	r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
	531	r0 = r1 \| r0;
	532	r1 = PLL_BYPASS; /* Bypass the PLL? */
	533	r1 = r1 << 8; /* Shift it over */
	534	r0 = r1 \| r0; /* add them all together */
	535
	536	p0.h = hi(PLL_CTL);
	537	p0.l = lo(PLL_CTL); /* Load the address */
	538	cli r2; /* Disable interrupts */
	539	ssync;
	540	w[p0] = r0.l; /* Set the value */
	541	idle; /* Wait for the PLL to stablize */
	542	sti r2; /* Enable interrupts */
	543
	544	.Lcheck_again1:
	545	p0.h = hi(PLL_STAT);
	546	p0.l = lo(PLL_STAT);
	547	R0 = W[P0](Z);
	548	CC = BITTST(R0,5);
	549	if ! CC jump .Lcheck_again1;
	550
	551	/* Configure SCLK & CCLK Dividers */
	552	r0 = (CONFIG_CCLK_ACT_DIV \| CONFIG_SCLK_DIV);
	553	p0.h = hi(PLL_DIV);
	554	p0.l = lo(PLL_DIV);
	555	w[p0] = r0.l;
	556	ssync;
	557
	558	/* Make sure UART is enabled - you can never be sure */
	559
	560	/*
	561	* Setup for console. Argument comes from the menuconfig
	562	*/
	563
	564	#ifdef CONFIG_BAUD_9600
	565	#define CONSOLE_BAUD_RATE 9600
	566	#elif CONFIG_BAUD_19200
	567	#define CONSOLE_BAUD_RATE 19200
	568	#elif CONFIG_BAUD_38400
	569	#define CONSOLE_BAUD_RATE 38400
	570	#elif CONFIG_BAUD_57600
	571	#define CONSOLE_BAUD_RATE 57600
	572	#elif CONFIG_BAUD_115200
	573	#define CONSOLE_BAUD_RATE 115200
	574	#endif
	575
	576	p0.h = hi(UART_GCTL);
	577	p0.l = lo(UART_GCTL);
	578	r0 = 0x00(Z);
	579	w[p0] = r0.L; /* To Turn off UART clocks */
	580	ssync;
	581
	582	p0.h = hi(UART_LCR);
583	p0.l = lo(UART_LCR);
584	r0 = 0x83(Z);
585	w[p0] = r0.L; /* To enable DLL writes */
586	ssync;
587
588	R1 = (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_SCLK_DIV) / (CONSOLE_BAUD_RATE * 16));
589
590	p0.h = hi(UART_DLL);
591	p0.l = lo(UART_DLL);
592	r0 = 0xFF(Z);
593	r0 = R1 & R0;
594	w[p0] = r0.L;
595	ssync;
596
597	p0.h = hi(UART_DLH);
598	p0.l = lo(UART_DLH);
599	r1 >>= 8 ;
600	w[p0] = r1.L;
601	ssync;
602
603	p0.h = hi(UART_GCTL);
604	p0.l = lo(UART_GCTL);
605	r0 = 0x0(Z);
606	w[p0] = r0.L; /* To enable UART clock */
607	ssync;
608
609	p0.h = hi(UART_LCR);
610	p0.l = lo(UART_LCR);
611	r0 = 0x03(Z);
612	w[p0] = r0.L; /* To Turn on UART */
613	ssync;
614
615	p0.h = hi(UART_GCTL);
616	p0.l = lo(UART_GCTL);
617	r0 = 0x01(Z);
618	w[p0] = r0.L; /* To Turn on UART Clocks */
619	ssync;
620
621	P0.h = hi(UART_THR);
622	P0.l = lo(UART_THR);
623	P1.h = hi(UART_LSR);
624	P1.l = lo(UART_LSR);
625
626	R0.L = 'K';
627	call .Lwait_char;
628	R0.L='e';
629	call .Lwait_char;
630	R0.L='r';
631	call .Lwait_char;
632	R0.L='n'
633	call .Lwait_char;
634	R0.L='e'
635	call .Lwait_char;
636	R0.L='l';
637	call .Lwait_char;
638	R0.L=' ';
639	call .Lwait_char;
640	R0.L='c';
641	call .Lwait_char;
642	R0.L='r';
643	call .Lwait_char;
644	R0.L='a';
645	call .Lwait_char;
646	R0.L='s';
647	call .Lwait_char;
648	R0.L='h';
649	call .Lwait_char;
650	R0.L='\r';
651	call .Lwait_char;
652	R0.L='\n';
653	call .Lwait_char;
654
655	R0.L='S';
656	call .Lwait_char;
657	R0.L='E';
658	call .Lwait_char;
659	R0.L='Q'
660	call .Lwait_char;
661	R0.L='S'
662	call .Lwait_char;
663	R0.L='T';
664	call .Lwait_char;
665	R0.L='A';
666	call .Lwait_char;
667	R0.L='T';
668	call .Lwait_char;
669	R0.L='=';
670	call .Lwait_char;
671	R2 = SEQSTAT;
672	call .Ldump_reg;
673
674	R0.L=' ';
675	call .Lwait_char;
676	R0.L='R';
677	call .Lwait_char;
678	R0.L='E'
679	call .Lwait_char;
680	R0.L='T'
681	call .Lwait_char;
682	R0.L='X';
683	call .Lwait_char;
684	R0.L='=';
685	call .Lwait_char;
686	R2 = RETX;
687	call .Ldump_reg;
688
689	R0.L='\r';
690	call .Lwait_char;
691	R0.L='\n';
692	call .Lwait_char;
693
694	.Ldebug_kernel_start_trap_done:
695	JUMP .Ldebug_kernel_start_trap_done;
696	.Ldump_reg:
697	R3 = 32;
698	R4 = 0x0F;
699	R5 = ':'; /* one past 9 */
700
701	.Ldump_reg2:
702	R0 = R2;
703	R3 += -4;
704	R0 >>>= R3;
705	R0 = R0 & R4;
706	R0 += 0x30;
707	CC = R0 <= R5;
708	if CC JUMP .Ldump_reg1;
709	R0 += 7;
710
711	.Ldump_reg1:
712	R1.l = W[P1];
713	CC = BITTST(R1, 5);
714	if !CC JUMP .Ldump_reg1;
715	W[P0] = r0;
716
717	CC = R3 == 0;
718	if !CC JUMP .Ldump_reg2
719	RTS;
720
721	.Lwait_char:
722	R1.l = W[P1];
723	CC = BITTST(R1, 5);
724	if !CC JUMP .Lwait_char;
725	W[P0] = r0;
726	RTS;
727
728	#endif /* CONFIG_DEBUG_KERNEL_START */
729
730	.data
731
732	/*
733	* Set up the usable of RAM stuff. Size of RAM is determined then
734	* an initial stack set up at the end.
735	*/
736
737	.align 4
738	__rambase:
739	.long 0
740	__ramstart:
741	.long 0
742	__ramend:
743	.long 0