Commit | Line | Data |
---|---|---|
d3afa58c MS |
1 | /* |
2 | * Contains common pci routines for ALL ppc platform | |
3 | * (based on pci_32.c and pci_64.c) | |
4 | * | |
5 | * Port for PPC64 David Engebretsen, IBM Corp. | |
6 | * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. | |
7 | * | |
8 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * Rework, based on alpha PCI code. | |
10 | * | |
11 | * Common pmac/prep/chrp pci routines. -- Cort | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License | |
15 | * as published by the Free Software Foundation; either version | |
16 | * 2 of the License, or (at your option) any later version. | |
17 | */ | |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/string.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/bootmem.h> | |
24 | #include <linux/mm.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/syscalls.h> | |
27 | #include <linux/irq.h> | |
28 | #include <linux/vmalloc.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
f1ca09b2 GL |
30 | #include <linux/of.h> |
31 | #include <linux/of_address.h> | |
04bea68b | 32 | #include <linux/of_pci.h> |
66421a64 | 33 | #include <linux/export.h> |
d3afa58c MS |
34 | |
35 | #include <asm/processor.h> | |
6bd55f0b | 36 | #include <linux/io.h> |
d3afa58c MS |
37 | #include <asm/pci-bridge.h> |
38 | #include <asm/byteorder.h> | |
39 | ||
40 | static DEFINE_SPINLOCK(hose_spinlock); | |
41 | LIST_HEAD(hose_list); | |
42 | ||
43 | /* XXX kill that some day ... */ | |
44 | static int global_phb_number; /* Global phb counter */ | |
45 | ||
46 | /* ISA Memory physical address */ | |
47 | resource_size_t isa_mem_base; | |
48 | ||
d3afa58c MS |
49 | static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; |
50 | ||
bf13a6fa BH |
51 | unsigned long isa_io_base; |
52 | unsigned long pci_dram_offset; | |
53 | static int pci_bus_count; | |
54 | ||
55 | ||
d3afa58c MS |
56 | void set_pci_dma_ops(struct dma_map_ops *dma_ops) |
57 | { | |
58 | pci_dma_ops = dma_ops; | |
59 | } | |
60 | ||
61 | struct dma_map_ops *get_pci_dma_ops(void) | |
62 | { | |
63 | return pci_dma_ops; | |
64 | } | |
65 | EXPORT_SYMBOL(get_pci_dma_ops); | |
66 | ||
d3afa58c MS |
67 | struct pci_controller *pcibios_alloc_controller(struct device_node *dev) |
68 | { | |
69 | struct pci_controller *phb; | |
70 | ||
71 | phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); | |
72 | if (!phb) | |
73 | return NULL; | |
74 | spin_lock(&hose_spinlock); | |
75 | phb->global_number = global_phb_number++; | |
76 | list_add_tail(&phb->list_node, &hose_list); | |
77 | spin_unlock(&hose_spinlock); | |
78 | phb->dn = dev; | |
79 | phb->is_dynamic = mem_init_done; | |
80 | return phb; | |
81 | } | |
82 | ||
83 | void pcibios_free_controller(struct pci_controller *phb) | |
84 | { | |
85 | spin_lock(&hose_spinlock); | |
86 | list_del(&phb->list_node); | |
87 | spin_unlock(&hose_spinlock); | |
88 | ||
89 | if (phb->is_dynamic) | |
90 | kfree(phb); | |
91 | } | |
92 | ||
93 | static resource_size_t pcibios_io_size(const struct pci_controller *hose) | |
94 | { | |
28f65c11 | 95 | return resource_size(&hose->io_resource); |
d3afa58c MS |
96 | } |
97 | ||
98 | int pcibios_vaddr_is_ioport(void __iomem *address) | |
99 | { | |
100 | int ret = 0; | |
101 | struct pci_controller *hose; | |
102 | resource_size_t size; | |
103 | ||
104 | spin_lock(&hose_spinlock); | |
105 | list_for_each_entry(hose, &hose_list, list_node) { | |
106 | size = pcibios_io_size(hose); | |
107 | if (address >= hose->io_base_virt && | |
108 | address < (hose->io_base_virt + size)) { | |
109 | ret = 1; | |
110 | break; | |
111 | } | |
112 | } | |
113 | spin_unlock(&hose_spinlock); | |
114 | return ret; | |
115 | } | |
116 | ||
117 | unsigned long pci_address_to_pio(phys_addr_t address) | |
118 | { | |
119 | struct pci_controller *hose; | |
120 | resource_size_t size; | |
121 | unsigned long ret = ~0; | |
122 | ||
123 | spin_lock(&hose_spinlock); | |
124 | list_for_each_entry(hose, &hose_list, list_node) { | |
125 | size = pcibios_io_size(hose); | |
126 | if (address >= hose->io_base_phys && | |
127 | address < (hose->io_base_phys + size)) { | |
128 | unsigned long base = | |
129 | (unsigned long)hose->io_base_virt - _IO_BASE; | |
130 | ret = base + (address - hose->io_base_phys); | |
131 | break; | |
132 | } | |
133 | } | |
134 | spin_unlock(&hose_spinlock); | |
135 | ||
136 | return ret; | |
137 | } | |
138 | EXPORT_SYMBOL_GPL(pci_address_to_pio); | |
139 | ||
140 | /* | |
141 | * Return the domain number for this bus. | |
142 | */ | |
143 | int pci_domain_nr(struct pci_bus *bus) | |
144 | { | |
145 | struct pci_controller *hose = pci_bus_to_host(bus); | |
146 | ||
147 | return hose->global_number; | |
148 | } | |
149 | EXPORT_SYMBOL(pci_domain_nr); | |
150 | ||
151 | /* This routine is meant to be used early during boot, when the | |
152 | * PCI bus numbers have not yet been assigned, and you need to | |
153 | * issue PCI config cycles to an OF device. | |
154 | * It could also be used to "fix" RTAS config cycles if you want | |
155 | * to set pci_assign_all_buses to 1 and still use RTAS for PCI | |
156 | * config cycles. | |
157 | */ | |
158 | struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node) | |
159 | { | |
160 | while (node) { | |
161 | struct pci_controller *hose, *tmp; | |
162 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
163 | if (hose->dn == node) | |
164 | return hose; | |
165 | node = node->parent; | |
166 | } | |
167 | return NULL; | |
168 | } | |
169 | ||
170 | static ssize_t pci_show_devspec(struct device *dev, | |
171 | struct device_attribute *attr, char *buf) | |
172 | { | |
173 | struct pci_dev *pdev; | |
174 | struct device_node *np; | |
175 | ||
176 | pdev = to_pci_dev(dev); | |
177 | np = pci_device_to_OF_node(pdev); | |
178 | if (np == NULL || np->full_name == NULL) | |
179 | return 0; | |
180 | return sprintf(buf, "%s", np->full_name); | |
181 | } | |
182 | static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); | |
183 | ||
184 | /* Add sysfs properties */ | |
185 | int pcibios_add_platform_entries(struct pci_dev *pdev) | |
186 | { | |
187 | return device_create_file(&pdev->dev, &dev_attr_devspec); | |
188 | } | |
189 | ||
b51d4a3e MS |
190 | void pcibios_set_master(struct pci_dev *dev) |
191 | { | |
192 | /* No special bus mastering setup handling */ | |
193 | } | |
194 | ||
d3afa58c MS |
195 | /* |
196 | * Reads the interrupt pin to determine if interrupt is use by card. | |
197 | * If the interrupt is used, then gets the interrupt line from the | |
198 | * openfirmware and sets it in the pci_dev and pci_config line. | |
199 | */ | |
200 | int pci_read_irq_line(struct pci_dev *pci_dev) | |
201 | { | |
202 | struct of_irq oirq; | |
203 | unsigned int virq; | |
204 | ||
205 | /* The current device-tree that iSeries generates from the HV | |
206 | * PCI informations doesn't contain proper interrupt routing, | |
207 | * and all the fallback would do is print out crap, so we | |
208 | * don't attempt to resolve the interrupts here at all, some | |
209 | * iSeries specific fixup does it. | |
210 | * | |
211 | * In the long run, we will hopefully fix the generated device-tree | |
212 | * instead. | |
213 | */ | |
214 | pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); | |
215 | ||
216 | #ifdef DEBUG | |
217 | memset(&oirq, 0xff, sizeof(oirq)); | |
218 | #endif | |
219 | /* Try to get a mapping from the device-tree */ | |
0c02c800 | 220 | if (of_irq_parse_pci(pci_dev, &oirq)) { |
d3afa58c MS |
221 | u8 line, pin; |
222 | ||
223 | /* If that fails, lets fallback to what is in the config | |
224 | * space and map that through the default controller. We | |
225 | * also set the type to level low since that's what PCI | |
226 | * interrupts are. If your platform does differently, then | |
227 | * either provide a proper interrupt tree or don't use this | |
228 | * function. | |
229 | */ | |
230 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) | |
231 | return -1; | |
232 | if (pin == 0) | |
233 | return -1; | |
234 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || | |
235 | line == 0xff || line == 0) { | |
236 | return -1; | |
237 | } | |
238 | pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", | |
239 | line, pin); | |
240 | ||
241 | virq = irq_create_mapping(NULL, line); | |
18e3b107 | 242 | if (virq) |
4adc192e | 243 | irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); |
d3afa58c MS |
244 | } else { |
245 | pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", | |
246 | oirq.size, oirq.specifier[0], oirq.specifier[1], | |
74a7f084 | 247 | of_node_full_name(oirq.controller)); |
d3afa58c MS |
248 | |
249 | virq = irq_create_of_mapping(oirq.controller, oirq.specifier, | |
250 | oirq.size); | |
251 | } | |
18e3b107 | 252 | if (!virq) { |
d3afa58c MS |
253 | pr_debug(" Failed to map !\n"); |
254 | return -1; | |
255 | } | |
256 | ||
257 | pr_debug(" Mapped to linux irq %d\n", virq); | |
258 | ||
259 | pci_dev->irq = virq; | |
260 | ||
261 | return 0; | |
262 | } | |
263 | EXPORT_SYMBOL(pci_read_irq_line); | |
264 | ||
265 | /* | |
266 | * Platform support for /proc/bus/pci/X/Y mmap()s, | |
267 | * modelled on the sparc64 implementation by Dave Miller. | |
268 | * -- paulus. | |
269 | */ | |
270 | ||
271 | /* | |
272 | * Adjust vm_pgoff of VMA such that it is the physical page offset | |
273 | * corresponding to the 32-bit pci bus offset for DEV requested by the user. | |
274 | * | |
275 | * Basically, the user finds the base address for his device which he wishes | |
276 | * to mmap. They read the 32-bit value from the config space base register, | |
277 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
278 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
279 | * | |
280 | * Returns negative error code on failure, zero on success. | |
281 | */ | |
282 | static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, | |
283 | resource_size_t *offset, | |
284 | enum pci_mmap_state mmap_state) | |
285 | { | |
286 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
287 | unsigned long io_offset = 0; | |
288 | int i, res_bit; | |
289 | ||
f7eaacc1 | 290 | if (!hose) |
d3afa58c MS |
291 | return NULL; /* should never happen */ |
292 | ||
293 | /* If memory, add on the PCI bridge address offset */ | |
294 | if (mmap_state == pci_mmap_mem) { | |
295 | #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ | |
296 | *offset += hose->pci_mem_offset; | |
297 | #endif | |
298 | res_bit = IORESOURCE_MEM; | |
299 | } else { | |
300 | io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
301 | *offset += io_offset; | |
302 | res_bit = IORESOURCE_IO; | |
303 | } | |
304 | ||
305 | /* | |
306 | * Check that the offset requested corresponds to one of the | |
307 | * resources of the device. | |
308 | */ | |
309 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
310 | struct resource *rp = &dev->resource[i]; | |
311 | int flags = rp->flags; | |
312 | ||
313 | /* treat ROM as memory (should be already) */ | |
314 | if (i == PCI_ROM_RESOURCE) | |
315 | flags |= IORESOURCE_MEM; | |
316 | ||
317 | /* Active and same type? */ | |
318 | if ((flags & res_bit) == 0) | |
319 | continue; | |
320 | ||
321 | /* In the range of this resource? */ | |
322 | if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) | |
323 | continue; | |
324 | ||
325 | /* found it! construct the final physical address */ | |
326 | if (mmap_state == pci_mmap_io) | |
327 | *offset += hose->io_base_phys - io_offset; | |
328 | return rp; | |
329 | } | |
330 | ||
331 | return NULL; | |
332 | } | |
333 | ||
334 | /* | |
335 | * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
336 | * device mapping. | |
337 | */ | |
338 | static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, | |
339 | pgprot_t protection, | |
340 | enum pci_mmap_state mmap_state, | |
341 | int write_combine) | |
342 | { | |
343 | pgprot_t prot = protection; | |
344 | ||
345 | /* Write combine is always 0 on non-memory space mappings. On | |
346 | * memory space, if the user didn't pass 1, we check for a | |
347 | * "prefetchable" resource. This is a bit hackish, but we use | |
348 | * this to workaround the inability of /sysfs to provide a write | |
349 | * combine bit | |
350 | */ | |
351 | if (mmap_state != pci_mmap_mem) | |
352 | write_combine = 0; | |
353 | else if (write_combine == 0) { | |
354 | if (rp->flags & IORESOURCE_PREFETCH) | |
355 | write_combine = 1; | |
356 | } | |
357 | ||
358 | return pgprot_noncached(prot); | |
359 | } | |
360 | ||
361 | /* | |
362 | * This one is used by /dev/mem and fbdev who have no clue about the | |
363 | * PCI device, it tries to find the PCI device first and calls the | |
364 | * above routine | |
365 | */ | |
366 | pgprot_t pci_phys_mem_access_prot(struct file *file, | |
367 | unsigned long pfn, | |
368 | unsigned long size, | |
369 | pgprot_t prot) | |
370 | { | |
371 | struct pci_dev *pdev = NULL; | |
372 | struct resource *found = NULL; | |
373 | resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; | |
374 | int i; | |
375 | ||
376 | if (page_is_ram(pfn)) | |
377 | return prot; | |
378 | ||
379 | prot = pgprot_noncached(prot); | |
380 | for_each_pci_dev(pdev) { | |
381 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
382 | struct resource *rp = &pdev->resource[i]; | |
383 | int flags = rp->flags; | |
384 | ||
385 | /* Active and same type? */ | |
386 | if ((flags & IORESOURCE_MEM) == 0) | |
387 | continue; | |
388 | /* In the range of this resource? */ | |
389 | if (offset < (rp->start & PAGE_MASK) || | |
390 | offset > rp->end) | |
391 | continue; | |
392 | found = rp; | |
393 | break; | |
394 | } | |
395 | if (found) | |
396 | break; | |
397 | } | |
398 | if (found) { | |
399 | if (found->flags & IORESOURCE_PREFETCH) | |
400 | prot = pgprot_noncached_wc(prot); | |
401 | pci_dev_put(pdev); | |
402 | } | |
403 | ||
404 | pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", | |
405 | (unsigned long long)offset, pgprot_val(prot)); | |
406 | ||
407 | return prot; | |
408 | } | |
409 | ||
410 | /* | |
411 | * Perform the actual remap of the pages for a PCI device mapping, as | |
412 | * appropriate for this architecture. The region in the process to map | |
413 | * is described by vm_start and vm_end members of VMA, the base physical | |
414 | * address is found in vm_pgoff. | |
415 | * The pci device structure is provided so that architectures may make mapping | |
416 | * decisions on a per-device or per-bus basis. | |
417 | * | |
418 | * Returns a negative error code on failure, zero on success. | |
419 | */ | |
420 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
421 | enum pci_mmap_state mmap_state, int write_combine) | |
422 | { | |
423 | resource_size_t offset = | |
424 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
425 | struct resource *rp; | |
426 | int ret; | |
427 | ||
428 | rp = __pci_mmap_make_offset(dev, &offset, mmap_state); | |
429 | if (rp == NULL) | |
430 | return -EINVAL; | |
431 | ||
432 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
433 | vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, | |
434 | vma->vm_page_prot, | |
435 | mmap_state, write_combine); | |
436 | ||
437 | ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
438 | vma->vm_end - vma->vm_start, vma->vm_page_prot); | |
439 | ||
440 | return ret; | |
441 | } | |
442 | ||
443 | /* This provides legacy IO read access on a bus */ | |
444 | int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) | |
445 | { | |
446 | unsigned long offset; | |
447 | struct pci_controller *hose = pci_bus_to_host(bus); | |
448 | struct resource *rp = &hose->io_resource; | |
449 | void __iomem *addr; | |
450 | ||
451 | /* Check if port can be supported by that bus. We only check | |
452 | * the ranges of the PHB though, not the bus itself as the rules | |
453 | * for forwarding legacy cycles down bridges are not our problem | |
454 | * here. So if the host bridge supports it, we do it. | |
455 | */ | |
456 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
457 | offset += port; | |
458 | ||
459 | if (!(rp->flags & IORESOURCE_IO)) | |
460 | return -ENXIO; | |
461 | if (offset < rp->start || (offset + size) > rp->end) | |
462 | return -ENXIO; | |
463 | addr = hose->io_base_virt + port; | |
464 | ||
465 | switch (size) { | |
466 | case 1: | |
467 | *((u8 *)val) = in_8(addr); | |
468 | return 1; | |
469 | case 2: | |
470 | if (port & 1) | |
471 | return -EINVAL; | |
472 | *((u16 *)val) = in_le16(addr); | |
473 | return 2; | |
474 | case 4: | |
475 | if (port & 3) | |
476 | return -EINVAL; | |
477 | *((u32 *)val) = in_le32(addr); | |
478 | return 4; | |
479 | } | |
480 | return -EINVAL; | |
481 | } | |
482 | ||
483 | /* This provides legacy IO write access on a bus */ | |
484 | int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) | |
485 | { | |
486 | unsigned long offset; | |
487 | struct pci_controller *hose = pci_bus_to_host(bus); | |
488 | struct resource *rp = &hose->io_resource; | |
489 | void __iomem *addr; | |
490 | ||
491 | /* Check if port can be supported by that bus. We only check | |
492 | * the ranges of the PHB though, not the bus itself as the rules | |
493 | * for forwarding legacy cycles down bridges are not our problem | |
494 | * here. So if the host bridge supports it, we do it. | |
495 | */ | |
496 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
497 | offset += port; | |
498 | ||
499 | if (!(rp->flags & IORESOURCE_IO)) | |
500 | return -ENXIO; | |
501 | if (offset < rp->start || (offset + size) > rp->end) | |
502 | return -ENXIO; | |
503 | addr = hose->io_base_virt + port; | |
504 | ||
505 | /* WARNING: The generic code is idiotic. It gets passed a pointer | |
506 | * to what can be a 1, 2 or 4 byte quantity and always reads that | |
507 | * as a u32, which means that we have to correct the location of | |
508 | * the data read within those 32 bits for size 1 and 2 | |
509 | */ | |
510 | switch (size) { | |
511 | case 1: | |
512 | out_8(addr, val >> 24); | |
513 | return 1; | |
514 | case 2: | |
515 | if (port & 1) | |
516 | return -EINVAL; | |
517 | out_le16(addr, val >> 16); | |
518 | return 2; | |
519 | case 4: | |
520 | if (port & 3) | |
521 | return -EINVAL; | |
522 | out_le32(addr, val); | |
523 | return 4; | |
524 | } | |
525 | return -EINVAL; | |
526 | } | |
527 | ||
528 | /* This provides legacy IO or memory mmap access on a bus */ | |
529 | int pci_mmap_legacy_page_range(struct pci_bus *bus, | |
530 | struct vm_area_struct *vma, | |
531 | enum pci_mmap_state mmap_state) | |
532 | { | |
533 | struct pci_controller *hose = pci_bus_to_host(bus); | |
534 | resource_size_t offset = | |
535 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
536 | resource_size_t size = vma->vm_end - vma->vm_start; | |
537 | struct resource *rp; | |
538 | ||
539 | pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", | |
540 | pci_domain_nr(bus), bus->number, | |
541 | mmap_state == pci_mmap_mem ? "MEM" : "IO", | |
542 | (unsigned long long)offset, | |
543 | (unsigned long long)(offset + size - 1)); | |
544 | ||
545 | if (mmap_state == pci_mmap_mem) { | |
546 | /* Hack alert ! | |
547 | * | |
548 | * Because X is lame and can fail starting if it gets an error | |
549 | * trying to mmap legacy_mem (instead of just moving on without | |
550 | * legacy memory access) we fake it here by giving it anonymous | |
551 | * memory, effectively behaving just like /dev/zero | |
552 | */ | |
553 | if ((offset + size) > hose->isa_mem_size) { | |
79bf3a13 | 554 | #ifdef CONFIG_MMU |
6bd55f0b MS |
555 | pr_debug("Process %s (pid:%d) mapped non-existing PCI", |
556 | current->comm, current->pid); | |
557 | pr_debug("legacy memory for 0%04x:%02x\n", | |
558 | pci_domain_nr(bus), bus->number); | |
79bf3a13 | 559 | #endif |
d3afa58c MS |
560 | if (vma->vm_flags & VM_SHARED) |
561 | return shmem_zero_setup(vma); | |
562 | return 0; | |
563 | } | |
564 | offset += hose->isa_mem_phys; | |
565 | } else { | |
6bd55f0b | 566 | unsigned long io_offset = (unsigned long)hose->io_base_virt - |
d3afa58c MS |
567 | _IO_BASE; |
568 | unsigned long roffset = offset + io_offset; | |
569 | rp = &hose->io_resource; | |
570 | if (!(rp->flags & IORESOURCE_IO)) | |
571 | return -ENXIO; | |
572 | if (roffset < rp->start || (roffset + size) > rp->end) | |
573 | return -ENXIO; | |
574 | offset += hose->io_base_phys; | |
575 | } | |
576 | pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); | |
577 | ||
578 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
579 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
580 | return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
581 | vma->vm_end - vma->vm_start, | |
582 | vma->vm_page_prot); | |
583 | } | |
584 | ||
585 | void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
586 | const struct resource *rsrc, | |
587 | resource_size_t *start, resource_size_t *end) | |
588 | { | |
589 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
590 | resource_size_t offset = 0; | |
591 | ||
592 | if (hose == NULL) | |
593 | return; | |
594 | ||
595 | if (rsrc->flags & IORESOURCE_IO) | |
596 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
597 | ||
598 | /* We pass a fully fixed up address to userland for MMIO instead of | |
599 | * a BAR value because X is lame and expects to be able to use that | |
600 | * to pass to /dev/mem ! | |
601 | * | |
602 | * That means that we'll have potentially 64 bits values where some | |
603 | * userland apps only expect 32 (like X itself since it thinks only | |
604 | * Sparc has 64 bits MMIO) but if we don't do that, we break it on | |
605 | * 32 bits CHRPs :-( | |
606 | * | |
607 | * Hopefully, the sysfs insterface is immune to that gunk. Once X | |
608 | * has been fixed (and the fix spread enough), we can re-enable the | |
609 | * 2 lines below and pass down a BAR value to userland. In that case | |
610 | * we'll also have to re-enable the matching code in | |
611 | * __pci_mmap_make_offset(). | |
612 | * | |
613 | * BenH. | |
614 | */ | |
615 | #if 0 | |
616 | else if (rsrc->flags & IORESOURCE_MEM) | |
617 | offset = hose->pci_mem_offset; | |
618 | #endif | |
619 | ||
620 | *start = rsrc->start - offset; | |
621 | *end = rsrc->end - offset; | |
622 | } | |
623 | ||
624 | /** | |
625 | * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree | |
626 | * @hose: newly allocated pci_controller to be setup | |
627 | * @dev: device node of the host bridge | |
628 | * @primary: set if primary bus (32 bits only, soon to be deprecated) | |
629 | * | |
630 | * This function will parse the "ranges" property of a PCI host bridge device | |
631 | * node and setup the resource mapping of a pci controller based on its | |
632 | * content. | |
633 | * | |
634 | * Life would be boring if it wasn't for a few issues that we have to deal | |
635 | * with here: | |
636 | * | |
637 | * - We can only cope with one IO space range and up to 3 Memory space | |
638 | * ranges. However, some machines (thanks Apple !) tend to split their | |
639 | * space into lots of small contiguous ranges. So we have to coalesce. | |
640 | * | |
641 | * - We can only cope with all memory ranges having the same offset | |
642 | * between CPU addresses and PCI addresses. Unfortunately, some bridges | |
643 | * are setup for a large 1:1 mapping along with a small "window" which | |
644 | * maps PCI address 0 to some arbitrary high address of the CPU space in | |
645 | * order to give access to the ISA memory hole. | |
646 | * The way out of here that I've chosen for now is to always set the | |
647 | * offset based on the first resource found, then override it if we | |
648 | * have a different offset and the previous was set by an ISA hole. | |
649 | * | |
650 | * - Some busses have IO space not starting at 0, which causes trouble with | |
651 | * the way we do our IO resource renumbering. The code somewhat deals with | |
652 | * it for 64 bits but I would expect problems on 32 bits. | |
653 | * | |
654 | * - Some 32 bits platforms such as 4xx can have physical space larger than | |
655 | * 32 bits so we need to use 64 bits values for the parsing | |
656 | */ | |
b881bc46 GKH |
657 | void pci_process_bridge_OF_ranges(struct pci_controller *hose, |
658 | struct device_node *dev, int primary) | |
d3afa58c | 659 | { |
d3afa58c | 660 | int memno = 0, isa_hole = -1; |
d3afa58c MS |
661 | unsigned long long isa_mb = 0; |
662 | struct resource *res; | |
4f7b6de4 AM |
663 | struct of_pci_range range; |
664 | struct of_pci_range_parser parser; | |
d3afa58c | 665 | |
6bd55f0b | 666 | pr_info("PCI host bridge %s %s ranges:\n", |
d3afa58c MS |
667 | dev->full_name, primary ? "(primary)" : ""); |
668 | ||
4f7b6de4 AM |
669 | /* Check for ranges property */ |
670 | if (of_pci_range_parser_init(&parser, dev)) | |
d3afa58c MS |
671 | return; |
672 | ||
d3afa58c | 673 | pr_debug("Parsing ranges property...\n"); |
4f7b6de4 | 674 | for_each_of_pci_range(&parser, &range) { |
d3afa58c | 675 | /* Read next ranges element */ |
6bd55f0b | 676 | pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ", |
4f7b6de4 | 677 | range.pci_space, range.pci_addr); |
6bd55f0b | 678 | pr_debug("cpu_addr:0x%016llx size:0x%016llx\n", |
4f7b6de4 | 679 | range.cpu_addr, range.size); |
d3afa58c MS |
680 | |
681 | /* If we failed translation or got a zero-sized region | |
682 | * (some FW try to feed us with non sensical zero sized regions | |
683 | * such as power3 which look like some kind of attempt | |
684 | * at exposing the VGA memory hole) | |
685 | */ | |
4f7b6de4 | 686 | if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) |
d3afa58c MS |
687 | continue; |
688 | ||
d3afa58c MS |
689 | /* Act based on address space type */ |
690 | res = NULL; | |
4f7b6de4 AM |
691 | switch (range.flags & IORESOURCE_TYPE_BITS) { |
692 | case IORESOURCE_IO: | |
6bd55f0b | 693 | pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n", |
4f7b6de4 AM |
694 | range.cpu_addr, range.cpu_addr + range.size - 1, |
695 | range.pci_addr); | |
d3afa58c MS |
696 | |
697 | /* We support only one IO range */ | |
698 | if (hose->pci_io_size) { | |
6bd55f0b | 699 | pr_info(" \\--> Skipped (too many) !\n"); |
d3afa58c MS |
700 | continue; |
701 | } | |
702 | /* On 32 bits, limit I/O space to 16MB */ | |
4f7b6de4 AM |
703 | if (range.size > 0x01000000) |
704 | range.size = 0x01000000; | |
d3afa58c MS |
705 | |
706 | /* 32 bits needs to map IOs here */ | |
4f7b6de4 AM |
707 | hose->io_base_virt = ioremap(range.cpu_addr, |
708 | range.size); | |
d3afa58c MS |
709 | |
710 | /* Expect trouble if pci_addr is not 0 */ | |
711 | if (primary) | |
712 | isa_io_base = | |
713 | (unsigned long)hose->io_base_virt; | |
714 | /* pci_io_size and io_base_phys always represent IO | |
715 | * space starting at 0 so we factor in pci_addr | |
716 | */ | |
4f7b6de4 AM |
717 | hose->pci_io_size = range.pci_addr + range.size; |
718 | hose->io_base_phys = range.cpu_addr - range.pci_addr; | |
d3afa58c MS |
719 | |
720 | /* Build resource */ | |
721 | res = &hose->io_resource; | |
4f7b6de4 AM |
722 | range.cpu_addr = range.pci_addr; |
723 | ||
d3afa58c | 724 | break; |
4f7b6de4 | 725 | case IORESOURCE_MEM: |
6bd55f0b | 726 | pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", |
4f7b6de4 AM |
727 | range.cpu_addr, range.cpu_addr + range.size - 1, |
728 | range.pci_addr, | |
729 | (range.pci_space & 0x40000000) ? | |
730 | "Prefetch" : ""); | |
d3afa58c MS |
731 | |
732 | /* We support only 3 memory ranges */ | |
733 | if (memno >= 3) { | |
6bd55f0b | 734 | pr_info(" \\--> Skipped (too many) !\n"); |
d3afa58c MS |
735 | continue; |
736 | } | |
737 | /* Handles ISA memory hole space here */ | |
4f7b6de4 AM |
738 | if (range.pci_addr == 0) { |
739 | isa_mb = range.cpu_addr; | |
d3afa58c MS |
740 | isa_hole = memno; |
741 | if (primary || isa_mem_base == 0) | |
4f7b6de4 AM |
742 | isa_mem_base = range.cpu_addr; |
743 | hose->isa_mem_phys = range.cpu_addr; | |
744 | hose->isa_mem_size = range.size; | |
d3afa58c MS |
745 | } |
746 | ||
747 | /* We get the PCI/Mem offset from the first range or | |
748 | * the, current one if the offset came from an ISA | |
749 | * hole. If they don't match, bugger. | |
750 | */ | |
751 | if (memno == 0 || | |
4f7b6de4 | 752 | (isa_hole >= 0 && range.pci_addr != 0 && |
d3afa58c | 753 | hose->pci_mem_offset == isa_mb)) |
4f7b6de4 AM |
754 | hose->pci_mem_offset = range.cpu_addr - |
755 | range.pci_addr; | |
756 | else if (range.pci_addr != 0 && | |
757 | hose->pci_mem_offset != range.cpu_addr - | |
758 | range.pci_addr) { | |
6bd55f0b | 759 | pr_info(" \\--> Skipped (offset mismatch) !\n"); |
d3afa58c MS |
760 | continue; |
761 | } | |
762 | ||
763 | /* Build resource */ | |
764 | res = &hose->mem_resources[memno++]; | |
d3afa58c MS |
765 | break; |
766 | } | |
4f7b6de4 AM |
767 | if (res != NULL) |
768 | of_pci_range_to_resource(&range, dev, res); | |
d3afa58c MS |
769 | } |
770 | ||
771 | /* If there's an ISA hole and the pci_mem_offset is -not- matching | |
772 | * the ISA hole offset, then we need to remove the ISA hole from | |
773 | * the resource list for that brige | |
774 | */ | |
775 | if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) { | |
776 | unsigned int next = isa_hole + 1; | |
6bd55f0b | 777 | pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb); |
d3afa58c MS |
778 | if (next < memno) |
779 | memmove(&hose->mem_resources[isa_hole], | |
780 | &hose->mem_resources[next], | |
781 | sizeof(struct resource) * (memno - next)); | |
782 | hose->mem_resources[--memno].flags = 0; | |
783 | } | |
784 | } | |
785 | ||
786 | /* Decide whether to display the domain number in /proc */ | |
787 | int pci_proc_domain(struct pci_bus *bus) | |
788 | { | |
e5b36841 | 789 | return 0; |
d3afa58c MS |
790 | } |
791 | ||
d3afa58c MS |
792 | /* This header fixup will do the resource fixup for all devices as they are |
793 | * probed, but not for bridge ranges | |
794 | */ | |
b881bc46 | 795 | static void pcibios_fixup_resources(struct pci_dev *dev) |
d3afa58c MS |
796 | { |
797 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
798 | int i; | |
799 | ||
800 | if (!hose) { | |
6bd55f0b | 801 | pr_err("No host bridge for PCI dev %s !\n", |
d3afa58c MS |
802 | pci_name(dev)); |
803 | return; | |
804 | } | |
805 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
806 | struct resource *res = dev->resource + i; | |
807 | if (!res->flags) | |
808 | continue; | |
e5b36841 | 809 | if (res->start == 0) { |
6bd55f0b | 810 | pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]", |
d3afa58c MS |
811 | pci_name(dev), i, |
812 | (unsigned long long)res->start, | |
813 | (unsigned long long)res->end, | |
814 | (unsigned int)res->flags); | |
6bd55f0b | 815 | pr_debug("is unassigned\n"); |
d3afa58c MS |
816 | res->end -= res->start; |
817 | res->start = 0; | |
818 | res->flags |= IORESOURCE_UNSET; | |
819 | continue; | |
820 | } | |
821 | ||
aa23bdc0 | 822 | pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n", |
d3afa58c | 823 | pci_name(dev), i, |
6bd55f0b | 824 | (unsigned long long)res->start, |
d3afa58c MS |
825 | (unsigned long long)res->end, |
826 | (unsigned int)res->flags); | |
d3afa58c MS |
827 | } |
828 | } | |
829 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); | |
830 | ||
831 | /* This function tries to figure out if a bridge resource has been initialized | |
832 | * by the firmware or not. It doesn't have to be absolutely bullet proof, but | |
833 | * things go more smoothly when it gets it right. It should covers cases such | |
834 | * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges | |
835 | */ | |
b881bc46 GKH |
836 | static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, |
837 | struct resource *res) | |
d3afa58c MS |
838 | { |
839 | struct pci_controller *hose = pci_bus_to_host(bus); | |
840 | struct pci_dev *dev = bus->self; | |
841 | resource_size_t offset; | |
842 | u16 command; | |
843 | int i; | |
844 | ||
d3afa58c MS |
845 | /* Job is a bit different between memory and IO */ |
846 | if (res->flags & IORESOURCE_MEM) { | |
847 | /* If the BAR is non-0 (res != pci_mem_offset) then it's | |
848 | * probably been initialized by somebody | |
849 | */ | |
850 | if (res->start != hose->pci_mem_offset) | |
851 | return 0; | |
852 | ||
853 | /* The BAR is 0, let's check if memory decoding is enabled on | |
854 | * the bridge. If not, we consider it unassigned | |
855 | */ | |
856 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
857 | if ((command & PCI_COMMAND_MEMORY) == 0) | |
858 | return 1; | |
859 | ||
860 | /* Memory decoding is enabled and the BAR is 0. If any of | |
861 | * the bridge resources covers that starting address (0 then | |
862 | * it's good enough for us for memory | |
863 | */ | |
864 | for (i = 0; i < 3; i++) { | |
865 | if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && | |
866 | hose->mem_resources[i].start == hose->pci_mem_offset) | |
867 | return 0; | |
868 | } | |
869 | ||
870 | /* Well, it starts at 0 and we know it will collide so we may as | |
871 | * well consider it as unassigned. That covers the Apple case. | |
872 | */ | |
873 | return 1; | |
874 | } else { | |
875 | /* If the BAR is non-0, then we consider it assigned */ | |
876 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
877 | if (((res->start - offset) & 0xfffffffful) != 0) | |
878 | return 0; | |
879 | ||
880 | /* Here, we are a bit different than memory as typically IO | |
881 | * space starting at low addresses -is- valid. What we do | |
882 | * instead if that we consider as unassigned anything that | |
883 | * doesn't have IO enabled in the PCI command register, | |
884 | * and that's it. | |
885 | */ | |
886 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
887 | if (command & PCI_COMMAND_IO) | |
888 | return 0; | |
889 | ||
890 | /* It's starting at 0 and IO is disabled in the bridge, consider | |
891 | * it unassigned | |
892 | */ | |
893 | return 1; | |
894 | } | |
895 | } | |
896 | ||
897 | /* Fixup resources of a PCI<->PCI bridge */ | |
b881bc46 | 898 | static void pcibios_fixup_bridge(struct pci_bus *bus) |
d3afa58c MS |
899 | { |
900 | struct resource *res; | |
901 | int i; | |
902 | ||
903 | struct pci_dev *dev = bus->self; | |
904 | ||
8a66da71 | 905 | pci_bus_for_each_resource(bus, res, i) { |
d3afa58c MS |
906 | if (!res) |
907 | continue; | |
908 | if (!res->flags) | |
909 | continue; | |
910 | if (i >= 3 && bus->self->transparent) | |
911 | continue; | |
912 | ||
913 | pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n", | |
914 | pci_name(dev), i, | |
6bd55f0b | 915 | (unsigned long long)res->start, |
d3afa58c MS |
916 | (unsigned long long)res->end, |
917 | (unsigned int)res->flags); | |
918 | ||
d3afa58c MS |
919 | /* Try to detect uninitialized P2P bridge resources, |
920 | * and clear them out so they get re-assigned later | |
921 | */ | |
922 | if (pcibios_uninitialized_bridge_resource(bus, res)) { | |
923 | res->flags = 0; | |
924 | pr_debug("PCI:%s (unassigned)\n", | |
925 | pci_name(dev)); | |
926 | } else { | |
927 | pr_debug("PCI:%s %016llx-%016llx\n", | |
928 | pci_name(dev), | |
929 | (unsigned long long)res->start, | |
930 | (unsigned long long)res->end); | |
931 | } | |
932 | } | |
933 | } | |
934 | ||
b881bc46 | 935 | void pcibios_setup_bus_self(struct pci_bus *bus) |
d3afa58c MS |
936 | { |
937 | /* Fix up the bus resources for P2P bridges */ | |
938 | if (bus->self != NULL) | |
939 | pcibios_fixup_bridge(bus); | |
940 | } | |
941 | ||
b881bc46 | 942 | void pcibios_setup_bus_devices(struct pci_bus *bus) |
d3afa58c MS |
943 | { |
944 | struct pci_dev *dev; | |
945 | ||
946 | pr_debug("PCI: Fixup bus devices %d (%s)\n", | |
947 | bus->number, bus->self ? pci_name(bus->self) : "PHB"); | |
948 | ||
949 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
d3afa58c | 950 | /* Setup OF node pointer in archdata */ |
088ab302 | 951 | dev->dev.of_node = pci_device_to_OF_node(dev); |
d3afa58c MS |
952 | |
953 | /* Fixup NUMA node as it may not be setup yet by the generic | |
954 | * code and is needed by the DMA init | |
955 | */ | |
956 | set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); | |
957 | ||
958 | /* Hook up default DMA ops */ | |
6c3bbdd6 NA |
959 | set_dma_ops(&dev->dev, pci_dma_ops); |
960 | dev->dev.archdata.dma_data = (void *)PCI_DRAM_OFFSET; | |
d3afa58c MS |
961 | |
962 | /* Read default IRQs and fixup if necessary */ | |
963 | pci_read_irq_line(dev); | |
964 | } | |
965 | } | |
966 | ||
b881bc46 | 967 | void pcibios_fixup_bus(struct pci_bus *bus) |
d3afa58c MS |
968 | { |
969 | /* When called from the generic PCI probe, read PCI<->PCI bridge | |
970 | * bases. This is -not- called when generating the PCI tree from | |
971 | * the OF device-tree. | |
972 | */ | |
973 | if (bus->self != NULL) | |
974 | pci_read_bridge_bases(bus); | |
975 | ||
976 | /* Now fixup the bus bus */ | |
977 | pcibios_setup_bus_self(bus); | |
978 | ||
979 | /* Now fixup devices on that bus */ | |
980 | pcibios_setup_bus_devices(bus); | |
981 | } | |
982 | EXPORT_SYMBOL(pcibios_fixup_bus); | |
983 | ||
984 | static int skip_isa_ioresource_align(struct pci_dev *dev) | |
985 | { | |
d3afa58c MS |
986 | return 0; |
987 | } | |
988 | ||
989 | /* | |
990 | * We need to avoid collisions with `mirrored' VGA ports | |
991 | * and other strange ISA hardware, so we always want the | |
992 | * addresses to be allocated in the 0x000-0x0ff region | |
993 | * modulo 0x400. | |
994 | * | |
995 | * Why? Because some silly external IO cards only decode | |
996 | * the low 10 bits of the IO address. The 0x00-0xff region | |
997 | * is reserved for motherboard devices that decode all 16 | |
998 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
999 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
1000 | * which might have be mirrored at 0x0100-0x03ff.. | |
1001 | */ | |
c86fac43 | 1002 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, |
d3afa58c MS |
1003 | resource_size_t size, resource_size_t align) |
1004 | { | |
1005 | struct pci_dev *dev = data; | |
c86fac43 | 1006 | resource_size_t start = res->start; |
d3afa58c MS |
1007 | |
1008 | if (res->flags & IORESOURCE_IO) { | |
d3afa58c | 1009 | if (skip_isa_ioresource_align(dev)) |
c86fac43 MS |
1010 | return start; |
1011 | if (start & 0x300) | |
d3afa58c | 1012 | start = (start + 0x3ff) & ~0x3ff; |
d3afa58c | 1013 | } |
c86fac43 MS |
1014 | |
1015 | return start; | |
d3afa58c MS |
1016 | } |
1017 | EXPORT_SYMBOL(pcibios_align_resource); | |
1018 | ||
1019 | /* | |
1020 | * Reparent resource children of pr that conflict with res | |
1021 | * under res, and make res replace those children. | |
1022 | */ | |
1023 | static int __init reparent_resources(struct resource *parent, | |
1024 | struct resource *res) | |
1025 | { | |
1026 | struct resource *p, **pp; | |
1027 | struct resource **firstpp = NULL; | |
1028 | ||
1029 | for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { | |
1030 | if (p->end < res->start) | |
1031 | continue; | |
1032 | if (res->end < p->start) | |
1033 | break; | |
1034 | if (p->start < res->start || p->end > res->end) | |
1035 | return -1; /* not completely contained */ | |
1036 | if (firstpp == NULL) | |
1037 | firstpp = pp; | |
1038 | } | |
1039 | if (firstpp == NULL) | |
1040 | return -1; /* didn't find any conflicting entries? */ | |
1041 | res->parent = parent; | |
1042 | res->child = *firstpp; | |
1043 | res->sibling = *pp; | |
1044 | *firstpp = res; | |
1045 | *pp = NULL; | |
1046 | for (p = res->child; p != NULL; p = p->sibling) { | |
1047 | p->parent = res; | |
1048 | pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", | |
1049 | p->name, | |
1050 | (unsigned long long)p->start, | |
1051 | (unsigned long long)p->end, res->name); | |
1052 | } | |
1053 | return 0; | |
1054 | } | |
1055 | ||
1056 | /* | |
1057 | * Handle resources of PCI devices. If the world were perfect, we could | |
1058 | * just allocate all the resource regions and do nothing more. It isn't. | |
1059 | * On the other hand, we cannot just re-allocate all devices, as it would | |
1060 | * require us to know lots of host bridge internals. So we attempt to | |
1061 | * keep as much of the original configuration as possible, but tweak it | |
1062 | * when it's found to be wrong. | |
1063 | * | |
1064 | * Known BIOS problems we have to work around: | |
1065 | * - I/O or memory regions not configured | |
1066 | * - regions configured, but not enabled in the command register | |
1067 | * - bogus I/O addresses above 64K used | |
1068 | * - expansion ROMs left enabled (this may sound harmless, but given | |
1069 | * the fact the PCI specs explicitly allow address decoders to be | |
1070 | * shared between expansion ROMs and other resource regions, it's | |
1071 | * at least dangerous) | |
1072 | * | |
1073 | * Our solution: | |
1074 | * (1) Allocate resources for all buses behind PCI-to-PCI bridges. | |
1075 | * This gives us fixed barriers on where we can allocate. | |
1076 | * (2) Allocate resources for all enabled devices. If there is | |
1077 | * a collision, just mark the resource as unallocated. Also | |
1078 | * disable expansion ROMs during this step. | |
1079 | * (3) Try to allocate resources for disabled devices. If the | |
1080 | * resources were assigned correctly, everything goes well, | |
1081 | * if they weren't, they won't disturb allocation of other | |
1082 | * resources. | |
1083 | * (4) Assign new addresses to resources which were either | |
1084 | * not configured at all or misconfigured. If explicitly | |
1085 | * requested by the user, configure expansion ROM address | |
1086 | * as well. | |
1087 | */ | |
1088 | ||
f7eaacc1 | 1089 | static void pcibios_allocate_bus_resources(struct pci_bus *bus) |
d3afa58c MS |
1090 | { |
1091 | struct pci_bus *b; | |
1092 | int i; | |
1093 | struct resource *res, *pr; | |
1094 | ||
1095 | pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", | |
1096 | pci_domain_nr(bus), bus->number); | |
1097 | ||
8a66da71 | 1098 | pci_bus_for_each_resource(bus, res, i) { |
d3afa58c MS |
1099 | if (!res || !res->flags |
1100 | || res->start > res->end || res->parent) | |
1101 | continue; | |
1102 | if (bus->parent == NULL) | |
1103 | pr = (res->flags & IORESOURCE_IO) ? | |
1104 | &ioport_resource : &iomem_resource; | |
1105 | else { | |
1106 | /* Don't bother with non-root busses when | |
1107 | * re-assigning all resources. We clear the | |
1108 | * resource flags as if they were colliding | |
1109 | * and as such ensure proper re-allocation | |
1110 | * later. | |
1111 | */ | |
d3afa58c MS |
1112 | pr = pci_find_parent_resource(bus->self, res); |
1113 | if (pr == res) { | |
1114 | /* this happens when the generic PCI | |
1115 | * code (wrongly) decides that this | |
1116 | * bridge is transparent -- paulus | |
1117 | */ | |
1118 | continue; | |
1119 | } | |
1120 | } | |
1121 | ||
6bd55f0b | 1122 | pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ", |
d3afa58c MS |
1123 | bus->self ? pci_name(bus->self) : "PHB", |
1124 | bus->number, i, | |
1125 | (unsigned long long)res->start, | |
6bd55f0b MS |
1126 | (unsigned long long)res->end); |
1127 | pr_debug("[0x%x], parent %p (%s)\n", | |
d3afa58c MS |
1128 | (unsigned int)res->flags, |
1129 | pr, (pr && pr->name) ? pr->name : "nil"); | |
1130 | ||
1131 | if (pr && !(pr->flags & IORESOURCE_UNSET)) { | |
1132 | if (request_resource(pr, res) == 0) | |
1133 | continue; | |
1134 | /* | |
1135 | * Must be a conflict with an existing entry. | |
1136 | * Move that entry (or entries) under the | |
1137 | * bridge resource and try again. | |
1138 | */ | |
1139 | if (reparent_resources(pr, res) == 0) | |
1140 | continue; | |
1141 | } | |
6bd55f0b MS |
1142 | pr_warn("PCI: Cannot allocate resource region "); |
1143 | pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number); | |
837c4ef1 | 1144 | res->start = res->end = 0; |
d3afa58c MS |
1145 | res->flags = 0; |
1146 | } | |
1147 | ||
1148 | list_for_each_entry(b, &bus->children, node) | |
1149 | pcibios_allocate_bus_resources(b); | |
1150 | } | |
1151 | ||
b881bc46 | 1152 | static inline void alloc_resource(struct pci_dev *dev, int idx) |
d3afa58c MS |
1153 | { |
1154 | struct resource *pr, *r = &dev->resource[idx]; | |
1155 | ||
1156 | pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", | |
1157 | pci_name(dev), idx, | |
1158 | (unsigned long long)r->start, | |
1159 | (unsigned long long)r->end, | |
1160 | (unsigned int)r->flags); | |
1161 | ||
1162 | pr = pci_find_parent_resource(dev, r); | |
1163 | if (!pr || (pr->flags & IORESOURCE_UNSET) || | |
1164 | request_resource(pr, r) < 0) { | |
6bd55f0b MS |
1165 | pr_warn("PCI: Cannot allocate resource region %d ", idx); |
1166 | pr_cont("of device %s, will remap\n", pci_name(dev)); | |
d3afa58c MS |
1167 | if (pr) |
1168 | pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", | |
1169 | pr, | |
1170 | (unsigned long long)pr->start, | |
1171 | (unsigned long long)pr->end, | |
1172 | (unsigned int)pr->flags); | |
1173 | /* We'll assign a new address later */ | |
1174 | r->flags |= IORESOURCE_UNSET; | |
1175 | r->end -= r->start; | |
1176 | r->start = 0; | |
1177 | } | |
1178 | } | |
1179 | ||
1180 | static void __init pcibios_allocate_resources(int pass) | |
1181 | { | |
1182 | struct pci_dev *dev = NULL; | |
1183 | int idx, disabled; | |
1184 | u16 command; | |
1185 | struct resource *r; | |
1186 | ||
1187 | for_each_pci_dev(dev) { | |
1188 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
1189 | for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { | |
1190 | r = &dev->resource[idx]; | |
1191 | if (r->parent) /* Already allocated */ | |
1192 | continue; | |
1193 | if (!r->flags || (r->flags & IORESOURCE_UNSET)) | |
1194 | continue; /* Not assigned at all */ | |
1195 | /* We only allocate ROMs on pass 1 just in case they | |
1196 | * have been screwed up by firmware | |
1197 | */ | |
1198 | if (idx == PCI_ROM_RESOURCE) | |
1199 | disabled = 1; | |
1200 | if (r->flags & IORESOURCE_IO) | |
1201 | disabled = !(command & PCI_COMMAND_IO); | |
1202 | else | |
1203 | disabled = !(command & PCI_COMMAND_MEMORY); | |
1204 | if (pass == disabled) | |
1205 | alloc_resource(dev, idx); | |
1206 | } | |
1207 | if (pass) | |
1208 | continue; | |
1209 | r = &dev->resource[PCI_ROM_RESOURCE]; | |
1210 | if (r->flags) { | |
1211 | /* Turn the ROM off, leave the resource region, | |
1212 | * but keep it unregistered. | |
1213 | */ | |
1214 | u32 reg; | |
1215 | pci_read_config_dword(dev, dev->rom_base_reg, ®); | |
1216 | if (reg & PCI_ROM_ADDRESS_ENABLE) { | |
1217 | pr_debug("PCI: Switching off ROM of %s\n", | |
1218 | pci_name(dev)); | |
1219 | r->flags &= ~IORESOURCE_ROM_ENABLE; | |
1220 | pci_write_config_dword(dev, dev->rom_base_reg, | |
1221 | reg & ~PCI_ROM_ADDRESS_ENABLE); | |
1222 | } | |
1223 | } | |
1224 | } | |
1225 | } | |
1226 | ||
1227 | static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) | |
1228 | { | |
1229 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1230 | resource_size_t offset; | |
1231 | struct resource *res, *pres; | |
1232 | int i; | |
1233 | ||
1234 | pr_debug("Reserving legacy ranges for domain %04x\n", | |
1235 | pci_domain_nr(bus)); | |
1236 | ||
1237 | /* Check for IO */ | |
1238 | if (!(hose->io_resource.flags & IORESOURCE_IO)) | |
1239 | goto no_io; | |
1240 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
1241 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
1242 | BUG_ON(res == NULL); | |
1243 | res->name = "Legacy IO"; | |
1244 | res->flags = IORESOURCE_IO; | |
1245 | res->start = offset; | |
1246 | res->end = (offset + 0xfff) & 0xfffffffful; | |
1247 | pr_debug("Candidate legacy IO: %pR\n", res); | |
1248 | if (request_resource(&hose->io_resource, res)) { | |
6bd55f0b | 1249 | pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n", |
d3afa58c MS |
1250 | pci_domain_nr(bus), bus->number, res); |
1251 | kfree(res); | |
1252 | } | |
1253 | ||
1254 | no_io: | |
1255 | /* Check for memory */ | |
1256 | offset = hose->pci_mem_offset; | |
1257 | pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset); | |
1258 | for (i = 0; i < 3; i++) { | |
1259 | pres = &hose->mem_resources[i]; | |
1260 | if (!(pres->flags & IORESOURCE_MEM)) | |
1261 | continue; | |
1262 | pr_debug("hose mem res: %pR\n", pres); | |
1263 | if ((pres->start - offset) <= 0xa0000 && | |
1264 | (pres->end - offset) >= 0xbffff) | |
1265 | break; | |
1266 | } | |
1267 | if (i >= 3) | |
1268 | return; | |
1269 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
1270 | BUG_ON(res == NULL); | |
1271 | res->name = "Legacy VGA memory"; | |
1272 | res->flags = IORESOURCE_MEM; | |
1273 | res->start = 0xa0000 + offset; | |
1274 | res->end = 0xbffff + offset; | |
1275 | pr_debug("Candidate VGA memory: %pR\n", res); | |
1276 | if (request_resource(pres, res)) { | |
6bd55f0b | 1277 | pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n", |
d3afa58c MS |
1278 | pci_domain_nr(bus), bus->number, res); |
1279 | kfree(res); | |
1280 | } | |
1281 | } | |
1282 | ||
1283 | void __init pcibios_resource_survey(void) | |
1284 | { | |
1285 | struct pci_bus *b; | |
1286 | ||
1287 | /* Allocate and assign resources. If we re-assign everything, then | |
1288 | * we skip the allocate phase | |
1289 | */ | |
1290 | list_for_each_entry(b, &pci_root_buses, node) | |
1291 | pcibios_allocate_bus_resources(b); | |
1292 | ||
e5b36841 BH |
1293 | pcibios_allocate_resources(0); |
1294 | pcibios_allocate_resources(1); | |
d3afa58c MS |
1295 | |
1296 | /* Before we start assigning unassigned resource, we try to reserve | |
1297 | * the low IO area and the VGA memory area if they intersect the | |
1298 | * bus available resources to avoid allocating things on top of them | |
1299 | */ | |
e5b36841 BH |
1300 | list_for_each_entry(b, &pci_root_buses, node) |
1301 | pcibios_reserve_legacy_regions(b); | |
d3afa58c | 1302 | |
e5b36841 BH |
1303 | /* Now proceed to assigning things that were left unassigned */ |
1304 | pr_debug("PCI: Assigning unassigned resources...\n"); | |
1305 | pci_assign_unassigned_resources(); | |
d3afa58c MS |
1306 | } |
1307 | ||
d3afa58c MS |
1308 | /* This is used by the PCI hotplug driver to allocate resource |
1309 | * of newly plugged busses. We can try to consolidate with the | |
1310 | * rest of the code later, for now, keep it as-is as our main | |
1311 | * resource allocation function doesn't deal with sub-trees yet. | |
1312 | */ | |
b881bc46 | 1313 | void pcibios_claim_one_bus(struct pci_bus *bus) |
d3afa58c MS |
1314 | { |
1315 | struct pci_dev *dev; | |
1316 | struct pci_bus *child_bus; | |
1317 | ||
1318 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1319 | int i; | |
1320 | ||
1321 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1322 | struct resource *r = &dev->resource[i]; | |
1323 | ||
1324 | if (r->parent || !r->start || !r->flags) | |
1325 | continue; | |
1326 | ||
6bd55f0b MS |
1327 | pr_debug("PCI: Claiming %s: ", pci_name(dev)); |
1328 | pr_debug("Resource %d: %016llx..%016llx [%x]\n", | |
1329 | i, (unsigned long long)r->start, | |
d3afa58c MS |
1330 | (unsigned long long)r->end, |
1331 | (unsigned int)r->flags); | |
1332 | ||
1333 | pci_claim_resource(dev, i); | |
1334 | } | |
1335 | } | |
1336 | ||
1337 | list_for_each_entry(child_bus, &bus->children, node) | |
1338 | pcibios_claim_one_bus(child_bus); | |
1339 | } | |
1340 | EXPORT_SYMBOL_GPL(pcibios_claim_one_bus); | |
1341 | ||
1342 | ||
1343 | /* pcibios_finish_adding_to_bus | |
1344 | * | |
1345 | * This is to be called by the hotplug code after devices have been | |
1346 | * added to a bus, this include calling it for a PHB that is just | |
1347 | * being added | |
1348 | */ | |
1349 | void pcibios_finish_adding_to_bus(struct pci_bus *bus) | |
1350 | { | |
1351 | pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", | |
1352 | pci_domain_nr(bus), bus->number); | |
1353 | ||
1354 | /* Allocate bus and devices resources */ | |
1355 | pcibios_allocate_bus_resources(bus); | |
1356 | pcibios_claim_one_bus(bus); | |
1357 | ||
1358 | /* Add new devices to global lists. Register in proc, sysfs. */ | |
1359 | pci_bus_add_devices(bus); | |
1360 | ||
1361 | /* Fixup EEH */ | |
1ce2470a | 1362 | /* eeh_add_device_tree_late(bus); */ |
d3afa58c MS |
1363 | } |
1364 | EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); | |
1365 | ||
d3afa58c MS |
1366 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
1367 | { | |
1368 | return pci_enable_resources(dev, mask); | |
1369 | } | |
1370 | ||
b881bc46 GKH |
1371 | static void pcibios_setup_phb_resources(struct pci_controller *hose, |
1372 | struct list_head *resources) | |
d3afa58c | 1373 | { |
5420e46d | 1374 | unsigned long io_offset; |
d3afa58c MS |
1375 | struct resource *res; |
1376 | int i; | |
1377 | ||
1378 | /* Hookup PHB IO resource */ | |
58de74b8 BH |
1379 | res = &hose->io_resource; |
1380 | ||
1381 | /* Fixup IO space offset */ | |
1382 | io_offset = (unsigned long)hose->io_base_virt - isa_io_base; | |
1383 | res->start = (res->start + io_offset) & 0xffffffffu; | |
1384 | res->end = (res->end + io_offset) & 0xffffffffu; | |
d3afa58c MS |
1385 | |
1386 | if (!res->flags) { | |
6bd55f0b MS |
1387 | pr_warn("PCI: I/O resource not set for host "); |
1388 | pr_cont("bridge %s (domain %d)\n", | |
1389 | hose->dn->full_name, hose->global_number); | |
d3afa58c MS |
1390 | /* Workaround for lack of IO resource only on 32-bit */ |
1391 | res->start = (unsigned long)hose->io_base_virt - isa_io_base; | |
1392 | res->end = res->start + IO_SPACE_LIMIT; | |
1393 | res->flags = IORESOURCE_IO; | |
1394 | } | |
f7eaacc1 MS |
1395 | pci_add_resource_offset(resources, res, |
1396 | (__force resource_size_t)(hose->io_base_virt - _IO_BASE)); | |
d3afa58c MS |
1397 | |
1398 | pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n", | |
1399 | (unsigned long long)res->start, | |
1400 | (unsigned long long)res->end, | |
1401 | (unsigned long)res->flags); | |
1402 | ||
1403 | /* Hookup PHB Memory resources */ | |
1404 | for (i = 0; i < 3; ++i) { | |
1405 | res = &hose->mem_resources[i]; | |
1406 | if (!res->flags) { | |
1407 | if (i > 0) | |
1408 | continue; | |
6bd55f0b MS |
1409 | pr_err("PCI: Memory resource 0 not set for "); |
1410 | pr_cont("host bridge %s (domain %d)\n", | |
1411 | hose->dn->full_name, hose->global_number); | |
d3afa58c MS |
1412 | |
1413 | /* Workaround for lack of MEM resource only on 32-bit */ | |
1414 | res->start = hose->pci_mem_offset; | |
1415 | res->end = (resource_size_t)-1LL; | |
1416 | res->flags = IORESOURCE_MEM; | |
1417 | ||
1418 | } | |
aa23bdc0 | 1419 | pci_add_resource_offset(resources, res, hose->pci_mem_offset); |
d3afa58c MS |
1420 | |
1421 | pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", | |
1422 | i, (unsigned long long)res->start, | |
1423 | (unsigned long long)res->end, | |
1424 | (unsigned long)res->flags); | |
1425 | } | |
1426 | ||
1427 | pr_debug("PCI: PHB MEM offset = %016llx\n", | |
1428 | (unsigned long long)hose->pci_mem_offset); | |
1429 | pr_debug("PCI: PHB IO offset = %08lx\n", | |
1430 | (unsigned long)hose->io_base_virt - _IO_BASE); | |
1431 | } | |
1432 | ||
bf13a6fa BH |
1433 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) |
1434 | { | |
1435 | struct pci_controller *hose = bus->sysdata; | |
1436 | ||
1437 | return of_node_get(hose->dn); | |
1438 | } | |
1439 | ||
b881bc46 | 1440 | static void pcibios_scan_phb(struct pci_controller *hose) |
bf13a6fa | 1441 | { |
58de74b8 | 1442 | LIST_HEAD(resources); |
bf13a6fa BH |
1443 | struct pci_bus *bus; |
1444 | struct device_node *node = hose->dn; | |
bf13a6fa | 1445 | |
74a7f084 | 1446 | pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node)); |
bf13a6fa | 1447 | |
58de74b8 BH |
1448 | pcibios_setup_phb_resources(hose, &resources); |
1449 | ||
4723b984 BH |
1450 | bus = pci_scan_root_bus(hose->parent, hose->first_busno, |
1451 | hose->ops, hose, &resources); | |
bf13a6fa | 1452 | if (bus == NULL) { |
6bd55f0b | 1453 | pr_err("Failed to create bus for PCI domain %04x\n", |
bf13a6fa | 1454 | hose->global_number); |
58de74b8 | 1455 | pci_free_resource_list(&resources); |
bf13a6fa BH |
1456 | return; |
1457 | } | |
b918c62e | 1458 | bus->busn_res.start = hose->first_busno; |
bf13a6fa BH |
1459 | hose->bus = bus; |
1460 | ||
b918c62e | 1461 | hose->last_busno = bus->busn_res.end; |
bf13a6fa BH |
1462 | } |
1463 | ||
1464 | static int __init pcibios_init(void) | |
1465 | { | |
1466 | struct pci_controller *hose, *tmp; | |
1467 | int next_busno = 0; | |
1468 | ||
6bd55f0b | 1469 | pr_info("PCI: Probing PCI hardware\n"); |
bf13a6fa BH |
1470 | |
1471 | /* Scan all of the recorded PCI controllers. */ | |
1472 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
1473 | hose->last_busno = 0xff; | |
1474 | pcibios_scan_phb(hose); | |
bf13a6fa BH |
1475 | if (next_busno <= hose->last_busno) |
1476 | next_busno = hose->last_busno + 1; | |
1477 | } | |
1478 | pci_bus_count = next_busno; | |
1479 | ||
1480 | /* Call common code to handle resource allocation */ | |
1481 | pcibios_resource_survey(); | |
1482 | ||
1483 | return 0; | |
1484 | } | |
1485 | ||
1486 | subsys_initcall(pcibios_init); | |
1487 | ||
1488 | static struct pci_controller *pci_bus_to_hose(int bus) | |
1489 | { | |
1490 | struct pci_controller *hose, *tmp; | |
1491 | ||
1492 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
1493 | if (bus >= hose->first_busno && bus <= hose->last_busno) | |
1494 | return hose; | |
1495 | return NULL; | |
1496 | } | |
1497 | ||
1498 | /* Provide information on locations of various I/O regions in physical | |
1499 | * memory. Do this on a per-card basis so that we choose the right | |
1500 | * root bridge. | |
1501 | * Note that the returned IO or memory base is a physical address | |
1502 | */ | |
1503 | ||
1504 | long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn) | |
1505 | { | |
1506 | struct pci_controller *hose; | |
1507 | long result = -EOPNOTSUPP; | |
1508 | ||
1509 | hose = pci_bus_to_hose(bus); | |
1510 | if (!hose) | |
1511 | return -ENODEV; | |
1512 | ||
1513 | switch (which) { | |
1514 | case IOBASE_BRIDGE_NUMBER: | |
1515 | return (long)hose->first_busno; | |
1516 | case IOBASE_MEMORY: | |
1517 | return (long)hose->pci_mem_offset; | |
1518 | case IOBASE_IO: | |
1519 | return (long)hose->io_base_phys; | |
1520 | case IOBASE_ISA_IO: | |
1521 | return (long)isa_io_base; | |
1522 | case IOBASE_ISA_MEM: | |
1523 | return (long)isa_mem_base; | |
1524 | } | |
1525 | ||
1526 | return result; | |
1527 | } | |
1528 | ||
d3afa58c MS |
1529 | /* |
1530 | * Null PCI config access functions, for the case when we can't | |
1531 | * find a hose. | |
1532 | */ | |
1533 | #define NULL_PCI_OP(rw, size, type) \ | |
1534 | static int \ | |
1535 | null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ | |
1536 | { \ | |
1537 | return PCIBIOS_DEVICE_NOT_FOUND; \ | |
1538 | } | |
1539 | ||
1540 | static int | |
1541 | null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
1542 | int len, u32 *val) | |
1543 | { | |
1544 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1545 | } | |
1546 | ||
1547 | static int | |
1548 | null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
1549 | int len, u32 val) | |
1550 | { | |
1551 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1552 | } | |
1553 | ||
1554 | static struct pci_ops null_pci_ops = { | |
1555 | .read = null_read_config, | |
1556 | .write = null_write_config, | |
1557 | }; | |
1558 | ||
1559 | /* | |
1560 | * These functions are used early on before PCI scanning is done | |
1561 | * and all of the pci_dev and pci_bus structures have been created. | |
1562 | */ | |
1563 | static struct pci_bus * | |
1564 | fake_pci_bus(struct pci_controller *hose, int busnr) | |
1565 | { | |
1566 | static struct pci_bus bus; | |
1567 | ||
1568 | if (!hose) | |
6bd55f0b | 1569 | pr_err("Can't find hose for PCI bus %d!\n", busnr); |
d3afa58c MS |
1570 | |
1571 | bus.number = busnr; | |
1572 | bus.sysdata = hose; | |
1573 | bus.ops = hose ? hose->ops : &null_pci_ops; | |
1574 | return &bus; | |
1575 | } | |
1576 | ||
1577 | #define EARLY_PCI_OP(rw, size, type) \ | |
1578 | int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ | |
1579 | int devfn, int offset, type value) \ | |
1580 | { \ | |
1581 | return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ | |
1582 | devfn, offset, value); \ | |
1583 | } | |
1584 | ||
1585 | EARLY_PCI_OP(read, byte, u8 *) | |
1586 | EARLY_PCI_OP(read, word, u16 *) | |
1587 | EARLY_PCI_OP(read, dword, u32 *) | |
1588 | EARLY_PCI_OP(write, byte, u8) | |
1589 | EARLY_PCI_OP(write, word, u16) | |
1590 | EARLY_PCI_OP(write, dword, u32) | |
1591 | ||
1592 | int early_find_capability(struct pci_controller *hose, int bus, int devfn, | |
1593 | int cap) | |
1594 | { | |
1595 | return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); | |
1596 | } | |
bf13a6fa | 1597 |