projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 2654d638 AF |
1 | /* |
| 2 | * MPC8541 CDS Device Tree Source | |
| 3 | * | |
| 32f960e9 | 4 | * Copyright 2006, 2008 Freescale Semiconductor Inc. |
| 2654d638 AF |
5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it | |
| 7 | * under the terms of the GNU General Public License as published by the | |
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 9 | * option) any later version. | |
| 10 | */ | |
| 11 | ||
| 32f960e9 | 12 | /dts-v1/; |
| 2654d638 AF |
13 | |
| 14 | / { | |
| 15 | model = "MPC8541CDS"; | |
| 52094879 | 16 | compatible = "MPC8541CDS", "MPC85xxCDS"; |
| 2654d638 AF |
17 | #address-cells = <1>; |
| 18 | #size-cells = <1>; | |
| 2654d638 | 19 | |
| ea082fa9 KG |
20 | aliases { |
| 21 | ethernet0 = &enet0; | |
| 22 | ethernet1 = &enet1; | |
| 23 | serial0 = &serial0; | |
| 24 | serial1 = &serial1; | |
| 25 | pci0 = &pci0; | |
| 26 | pci1 = &pci1; | |
| 27 | }; | |
| 28 | ||
| 2654d638 | 29 | cpus { |
| 2654d638 AF |
30 | #address-cells = <1>; |
| 31 | #size-cells = <0>; | |
| 2654d638 AF |
32 | |
| 33 | PowerPC,8541@0 { | |
| 34 | device_type = "cpu"; | |
| 32f960e9 KG |
35 | reg = <0x0>; |
| 36 | d-cache-line-size = <32>; // 32 bytes | |
| 37 | i-cache-line-size = <32>; // 32 bytes | |
| 38 | d-cache-size = <0x8000>; // L1, 32K | |
| 39 | i-cache-size = <0x8000>; // L1, 32K | |
| 2654d638 AF |
40 | timebase-frequency = <0>; // 33 MHz, from uboot |
| 41 | bus-frequency = <0>; // 166 MHz | |
| 42 | clock-frequency = <0>; // 825 MHz, from uboot | |
| c054065b | 43 | next-level-cache = <&L2>; |
| 2654d638 AF |
44 | }; |
| 45 | }; | |
| 46 | ||
| 47 | memory { | |
| 48 | device_type = "memory"; | |
| 32f960e9 | 49 | reg = <0x0 0x8000000>; // 128M at 0x0 |
| 2654d638 AF |
50 | }; |
| 51 | ||
| 52 | soc8541@e0000000 { | |
| 53 | #address-cells = <1>; | |
| 54 | #size-cells = <1>; | |
| 2654d638 | 55 | device_type = "soc"; |
| cf0d19fb | 56 | compatible = "simple-bus"; |
| 32f960e9 KG |
57 | ranges = <0x0 0xe0000000 0x100000>; |
| 58 | reg = <0xe0000000 0x1000>; // CCSRBAR 1M | |
| 2654d638 AF |
59 | bus-frequency = <0>; |
| 60 | ||
| 4da421d6 KG |
61 | memory-controller@2000 { |
| 62 | compatible = "fsl,8541-memory-controller"; | |
| 32f960e9 | 63 | reg = <0x2000 0x1000>; |
| 4da421d6 | 64 | interrupt-parent = <&mpic>; |
| 32f960e9 | 65 | interrupts = <18 2>; |
| 4da421d6 KG |
66 | }; |
| 67 | ||
| c054065b | 68 | L2: l2-cache-controller@20000 { |
| 4da421d6 | 69 | compatible = "fsl,8541-l2-cache-controller"; |
| 32f960e9 KG |
70 | reg = <0x20000 0x1000>; |
| 71 | cache-line-size = <32>; // 32 bytes | |
| 72 | cache-size = <0x40000>; // L2, 256K | |
| 4da421d6 | 73 | interrupt-parent = <&mpic>; |
| 32f960e9 | 74 | interrupts = <16 2>; |
| 4da421d6 KG |
75 | }; |
| 76 | ||
| 2654d638 | 77 | i2c@3000 { |
| ec9686c4 KG |
78 | #address-cells = <1>; |
| 79 | #size-cells = <0>; | |
| 80 | cell-index = <0>; | |
| 2654d638 | 81 | compatible = "fsl-i2c"; |
| 32f960e9 KG |
82 | reg = <0x3000 0x100>; |
| 83 | interrupts = <43 2>; | |
| 52094879 | 84 | interrupt-parent = <&mpic>; |
| 2654d638 AF |
85 | dfsrr; |
| 86 | }; | |
| 87 | ||
| dee80553 KG |
88 | dma@21300 { |
| 89 | #address-cells = <1>; | |
| 90 | #size-cells = <1>; | |
| 91 | compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma"; | |
| 92 | reg = <0x21300 0x4>; | |
| 93 | ranges = <0x0 0x21100 0x200>; | |
| 94 | cell-index = <0>; | |
| 95 | dma-channel@0 { | |
| 96 | compatible = "fsl,mpc8541-dma-channel", | |
| 97 | "fsl,eloplus-dma-channel"; | |
| 98 | reg = <0x0 0x80>; | |
| 99 | cell-index = <0>; | |
| 100 | interrupt-parent = <&mpic>; | |
| 101 | interrupts = <20 2>; | |
| 102 | }; | |
| 103 | dma-channel@80 { | |
| 104 | compatible = "fsl,mpc8541-dma-channel", | |
| 105 | "fsl,eloplus-dma-channel"; | |
| 106 | reg = <0x80 0x80>; | |
| 107 | cell-index = <1>; | |
| 108 | interrupt-parent = <&mpic>; | |
| 109 | interrupts = <21 2>; | |
| 110 | }; | |
| 111 | dma-channel@100 { | |
| 112 | compatible = "fsl,mpc8541-dma-channel", | |
| 113 | "fsl,eloplus-dma-channel"; | |
| 114 | reg = <0x100 0x80>; | |
| 115 | cell-index = <2>; | |
| 116 | interrupt-parent = <&mpic>; | |
| 117 | interrupts = <22 2>; | |
| 118 | }; | |
| 119 | dma-channel@180 { | |
| 120 | compatible = "fsl,mpc8541-dma-channel", | |
| 121 | "fsl,eloplus-dma-channel"; | |
| 122 | reg = <0x180 0x80>; | |
| 123 | cell-index = <3>; | |
| 124 | interrupt-parent = <&mpic>; | |
| 125 | interrupts = <23 2>; | |
| 126 | }; | |
| 127 | }; | |
| 128 | ||
| 2654d638 AF |
129 | mdio@24520 { |
| 130 | #address-cells = <1>; | |
| 131 | #size-cells = <0>; | |
| e77b28eb | 132 | compatible = "fsl,gianfar-mdio"; |
| 32f960e9 | 133 | reg = <0x24520 0x20>; |
| e77b28eb | 134 | |
| 52094879 KG |
135 | phy0: ethernet-phy@0 { |
| 136 | interrupt-parent = <&mpic>; | |
| 58fe255f | 137 | interrupts = <5 1>; |
| 32f960e9 | 138 | reg = <0x0>; |
| 2654d638 AF |
139 | device_type = "ethernet-phy"; |
| 140 | }; | |
| 52094879 KG |
141 | phy1: ethernet-phy@1 { |
| 142 | interrupt-parent = <&mpic>; | |
| 58fe255f | 143 | interrupts = <5 1>; |
| 32f960e9 | 144 | reg = <0x1>; |
| 2654d638 AF |
145 | device_type = "ethernet-phy"; |
| 146 | }; | |
| b31a1d8b AF |
147 | tbi0: tbi-phy@11 { |
| 148 | reg = <0x11>; | |
| 149 | device_type = "tbi-phy"; | |
| 150 | }; | |
| 151 | }; | |
| 152 | ||
| 153 | mdio@25520 { | |
| 154 | #address-cells = <1>; | |
| 155 | #size-cells = <0>; | |
| 156 | compatible = "fsl,gianfar-tbi"; | |
| 157 | reg = <0x25520 0x20>; | |
| 158 | ||
| 159 | tbi1: tbi-phy@11 { | |
| 160 | reg = <0x11>; | |
| 161 | device_type = "tbi-phy"; | |
| 162 | }; | |
| 2654d638 AF |
163 | }; |
| 164 | ||
| e77b28eb KG |
165 | enet0: ethernet@24000 { |
| 166 | cell-index = <0>; | |
| 2654d638 AF |
167 | device_type = "network"; |
| 168 | model = "TSEC"; | |
| 169 | compatible = "gianfar"; | |
| 32f960e9 | 170 | reg = <0x24000 0x1000>; |
| eae98266 | 171 | local-mac-address = [ 00 00 00 00 00 00 ]; |
| 32f960e9 | 172 | interrupts = <29 2 30 2 34 2>; |
| 52094879 | 173 | interrupt-parent = <&mpic>; |
| b31a1d8b | 174 | tbi-handle = <&tbi0>; |
| 52094879 | 175 | phy-handle = <&phy0>; |
| 2654d638 AF |
176 | }; |
| 177 | ||
| e77b28eb KG |
178 | enet1: ethernet@25000 { |
| 179 | cell-index = <1>; | |
| 2654d638 AF |
180 | device_type = "network"; |
| 181 | model = "TSEC"; | |
| 182 | compatible = "gianfar"; | |
| 32f960e9 | 183 | reg = <0x25000 0x1000>; |
| eae98266 | 184 | local-mac-address = [ 00 00 00 00 00 00 ]; |
| 32f960e9 | 185 | interrupts = <35 2 36 2 40 2>; |
| 52094879 | 186 | interrupt-parent = <&mpic>; |
| b31a1d8b | 187 | tbi-handle = <&tbi1>; |
| 52094879 | 188 | phy-handle = <&phy1>; |
| 2654d638 AF |
189 | }; |
| 190 | ||
| ea082fa9 KG |
191 | serial0: serial@4500 { |
| 192 | cell-index = <0>; | |
| 2654d638 AF |
193 | device_type = "serial"; |
| 194 | compatible = "ns16550"; | |
| 32f960e9 | 195 | reg = <0x4500 0x100>; // reg base, size |
| 2654d638 | 196 | clock-frequency = <0>; // should we fill in in uboot? |
| 32f960e9 | 197 | interrupts = <42 2>; |
| 52094879 | 198 | interrupt-parent = <&mpic>; |
| 2654d638 AF |
199 | }; |
| 200 | ||
| ea082fa9 KG |
201 | serial1: serial@4600 { |
| 202 | cell-index = <1>; | |
| 2654d638 AF |
203 | device_type = "serial"; |
| 204 | compatible = "ns16550"; | |
| 32f960e9 | 205 | reg = <0x4600 0x100>; // reg base, size |
| 2654d638 | 206 | clock-frequency = <0>; // should we fill in in uboot? |
| 32f960e9 | 207 | interrupts = <42 2>; |
| 52094879 | 208 | interrupt-parent = <&mpic>; |
| 2654d638 AF |
209 | }; |
| 210 | ||
| 3fd44736 KP |
211 | crypto@30000 { |
| 212 | compatible = "fsl,sec2.0"; | |
| 213 | reg = <0x30000 0x10000>; | |
| 214 | interrupts = <45 2>; | |
| 215 | interrupt-parent = <&mpic>; | |
| 216 | fsl,num-channels = <4>; | |
| 217 | fsl,channel-fifo-len = <24>; | |
| 218 | fsl,exec-units-mask = <0x7e>; | |
| 219 | fsl,descriptor-types-mask = <0x01010ebf>; | |
| 220 | }; | |
| 221 | ||
| 52094879 | 222 | mpic: pic@40000 { |
| 2654d638 AF |
223 | interrupt-controller; |
| 224 | #address-cells = <0>; | |
| 225 | #interrupt-cells = <2>; | |
| 32f960e9 | 226 | reg = <0x40000 0x40000>; |
| 2654d638 AF |
227 | compatible = "chrp,open-pic"; |
| 228 | device_type = "open-pic"; | |
| 2654d638 | 229 | }; |
| ab9683ca SW |
230 | |
| 231 | cpm@919c0 { | |
| 232 | #address-cells = <1>; | |
| 233 | #size-cells = <1>; | |
| 234 | compatible = "fsl,mpc8541-cpm", "fsl,cpm2"; | |
| 32f960e9 | 235 | reg = <0x919c0 0x30>; |
| ab9683ca SW |
236 | ranges; |
| 237 | ||
| 238 | muram@80000 { | |
| 239 | #address-cells = <1>; | |
| 240 | #size-cells = <1>; | |
| 32f960e9 | 241 | ranges = <0x0 0x80000 0x10000>; |
| ab9683ca SW |
242 | |
| 243 | data@0 { | |
| 244 | compatible = "fsl,cpm-muram-data"; | |
| 32f960e9 | 245 | reg = <0x0 0x2000 0x9000 0x1000>; |
| ab9683ca SW |
246 | }; |
| 247 | }; | |
| 248 | ||
| 249 | brg@919f0 { | |
| 250 | compatible = "fsl,mpc8541-brg", | |
| 251 | "fsl,cpm2-brg", | |
| 252 | "fsl,cpm-brg"; | |
| 32f960e9 | 253 | reg = <0x919f0 0x10 0x915f0 0x10>; |
| ab9683ca SW |
254 | }; |
| 255 | ||
| 256 | cpmpic: pic@90c00 { | |
| 257 | interrupt-controller; | |
| 258 | #address-cells = <0>; | |
| 259 | #interrupt-cells = <2>; | |
| 32f960e9 | 260 | interrupts = <46 2>; |
| ab9683ca | 261 | interrupt-parent = <&mpic>; |
| 32f960e9 | 262 | reg = <0x90c00 0x80>; |
| ab9683ca SW |
263 | compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic"; |
| 264 | }; | |
| 265 | }; | |
| 2654d638 | 266 | }; |
| 1b3c5cda | 267 | |
| ea082fa9 KG |
268 | pci0: pci@e0008000 { |
| 269 | cell-index = <0>; | |
| 32f960e9 | 270 | interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; |
| 1b3c5cda KG |
271 | interrupt-map = < |
| 272 | ||
| 273 | /* IDSEL 0x10 */ | |
| 32f960e9 KG |
274 | 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1 |
| 275 | 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1 | |
| 276 | 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1 | |
| 277 | 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1 | |
| 1b3c5cda KG |
278 | |
| 279 | /* IDSEL 0x11 */ | |
| 32f960e9 KG |
280 | 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1 |
| 281 | 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1 | |
| 282 | 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1 | |
| 283 | 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1 | |
| 1b3c5cda KG |
284 | |
| 285 | /* IDSEL 0x12 (Slot 1) */ | |
| 32f960e9 KG |
286 | 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1 |
| 287 | 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1 | |
| 288 | 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 | |
| 289 | 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1 | |
| 1b3c5cda KG |
290 | |
| 291 | /* IDSEL 0x13 (Slot 2) */ | |
| 32f960e9 KG |
292 | 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1 |
| 293 | 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1 | |
| 294 | 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1 | |
| 295 | 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1 | |
| 1b3c5cda KG |
296 | |
| 297 | /* IDSEL 0x14 (Slot 3) */ | |
| 32f960e9 KG |
298 | 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1 |
| 299 | 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1 | |
| 300 | 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1 | |
| 301 | 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1 | |
| 1b3c5cda KG |
302 | |
| 303 | /* IDSEL 0x15 (Slot 4) */ | |
| 32f960e9 KG |
304 | 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1 |
| 305 | 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1 | |
| 306 | 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1 | |
| 307 | 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1 | |
| 1b3c5cda KG |
308 | |
| 309 | /* Bus 1 (Tundra Bridge) */ | |
| 310 | /* IDSEL 0x12 (ISA bridge) */ | |
| 32f960e9 KG |
311 | 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1 |
| 312 | 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1 | |
| 313 | 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1 | |
| 314 | 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>; | |
| 1b3c5cda | 315 | interrupt-parent = <&mpic>; |
| 32f960e9 | 316 | interrupts = <24 2>; |
| 1b3c5cda | 317 | bus-range = <0 0>; |
| 32f960e9 KG |
318 | ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 |
| 319 | 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>; | |
| 320 | clock-frequency = <66666666>; | |
| 1b3c5cda KG |
321 | #interrupt-cells = <1>; |
| 322 | #size-cells = <2>; | |
| 323 | #address-cells = <3>; | |
| 32f960e9 | 324 | reg = <0xe0008000 0x1000>; |
| 1b3c5cda KG |
325 | compatible = "fsl,mpc8540-pci"; |
| 326 | device_type = "pci"; | |
| 327 | ||
| 328 | i8259@19000 { | |
| 329 | interrupt-controller; | |
| 330 | device_type = "interrupt-controller"; | |
| 32f960e9 | 331 | reg = <0x19000 0x0 0x0 0x0 0x1>; |
| 1b3c5cda KG |
332 | #address-cells = <0>; |
| 333 | #interrupt-cells = <2>; | |
| 334 | compatible = "chrp,iic"; | |
| 335 | interrupts = <1>; | |
| ea082fa9 | 336 | interrupt-parent = <&pci0>; |
| 1b3c5cda KG |
337 | }; |
| 338 | }; | |
| 339 | ||
| ea082fa9 KG |
340 | pci1: pci@e0009000 { |
| 341 | cell-index = <1>; | |
| 32f960e9 | 342 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 1b3c5cda KG |
343 | interrupt-map = < |
| 344 | ||
| 345 | /* IDSEL 0x15 */ | |
| 32f960e9 KG |
346 | 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 |
| 347 | 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1 | |
| 348 | 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1 | |
| 349 | 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>; | |
| 1b3c5cda | 350 | interrupt-parent = <&mpic>; |
| 32f960e9 | 351 | interrupts = <25 2>; |
| 1b3c5cda | 352 | bus-range = <0 0>; |
| 32f960e9 KG |
353 | ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 |
| 354 | 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>; | |
| 355 | clock-frequency = <66666666>; | |
| 1b3c5cda KG |
356 | #interrupt-cells = <1>; |
| 357 | #size-cells = <2>; | |
| 358 | #address-cells = <3>; | |
| 32f960e9 | 359 | reg = <0xe0009000 0x1000>; |
| 1b3c5cda KG |
360 | compatible = "fsl,mpc8540-pci"; |
| 361 | device_type = "pci"; | |
| 362 | }; | |
| 2654d638 | 363 | }; |