[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8544ds.dts

/*
 * MPC8544 DS Device Tree Source
 *
 * Copyright 2007, 2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;
/ {
	model = "MPC8544DS";
	compatible = "MPC8544DS", "MPC85xxDS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
		pci3 = &pci3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8544@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x0>;	// Filled by U-Boot
	};

	soc8544@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";

		ranges = <0x0 0xe0000000 0x100000>;
		reg = <0xe0000000 0x1000>;	// CCSRBAR 1M
		bus-frequency = <0>;		// Filled out by uboot.

		memory-controller@2000 {
			compatible = "fsl,8544-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,8544-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x40000>;	// L2, 256K
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-mdio";
			reg = <0x24520 0x20>;

			phy0: ethernet-phy@0 {
				interrupt-parent = <&mpic>;
				interrupts = <10 1>;
				reg = <0x0>;
				device_type = "ethernet-phy";
			};
			phy1: ethernet-phy@1 {
				interrupt-parent = <&mpic>;
				interrupts = <10 1>;
				reg = <0x1>;
				device_type = "ethernet-phy";
			};

			tbi0: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};

		mdio@26520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-tbi";
			reg = <0x26520 0x20>;

			tbi1: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};


		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8544-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8544-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8544-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8544-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		enet0: ethernet@24000 {
			cell-index = <0>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30 2 34 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy0>;
			tbi-handle = <&tbi0>;
			phy-connection-type = "rgmii-id";
		};

		enet1: ethernet@26000 {
			cell-index = <1>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x26000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <31 2 32 2 33 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy1>;
			tbi-handle = <&tbi1>;
			phy-connection-type = "rgmii-id";
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		global-utilities@e0000 {	//global utilities block
			compatible = "fsl,mpc8548-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

		crypto@30000 {
			compatible = "fsl,sec2.1", "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <45 2>;
			interrupt-parent = <&mpic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0xfe>;
			fsl,descriptor-types-mask = <0x12b0ebf>;
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};

		msi@41600 {
			compatible = "fsl,mpc8544-msi", "fsl,mpic-msi";
			reg = <0x41600 0x80>;
			msi-available-ranges = <0 0x100>;
			interrupts = <
				0xe0 0
				0xe1 0
				0xe2 0
				0xe3 0
				0xe4 0
				0xe5 0
				0xe6 0
				0xe7 0>;
			interrupt-parent = <&mpic>;
		};
	};

	pci0: pci@e0008000 {
		cell-index = <0>;
		compatible = "fsl,mpc8540-pci";
		device_type = "pci";
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x11 J17 Slot 1 */
			0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8800 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x12 J16 Slot 2 */

			0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
	};

	pci1: pcie@e0009000 {
		cell-index = <1>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0009000 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <26 2>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0x0 0x0 0x1 &mpic 0x4 0x1
			0000 0x0 0x0 0x2 &mpic 0x5 0x1
			0000 0x0 0x0 0x3 &mpic 0x6 0x1
			0000 0x0 0x0 0x4 &mpic 0x7 0x1
			>;
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0x80000000
				  0x2000000 0x0 0x80000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x10000>;
		};
	};

	pci2: pcie@e000a000 {
		cell-index = <2>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe000a000 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
			  0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <25 2>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0x0 0x0 0x1 &mpic 0x0 0x1
			0000 0x0 0x0 0x2 &mpic 0x1 0x1
			0000 0x0 0x0 0x3 &mpic 0x2 0x1
			0000 0x0 0x0 0x4 &mpic 0x3 0x1
			>;
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0xa0000000
				  0x2000000 0x0 0xa0000000
				  0x0 0x10000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x10000>;
		};
	};

	pci3: pcie@e000b000 {
		cell-index = <3>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe000b000 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
			  0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <27 2>;
		interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
		interrupt-map = <
			// IDSEL 0x1c  USB
			0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
			0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
			0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
			0xe300 0x0 0x0 0x4 &i8259 0xb 0x2

			// IDSEL 0x1d  Audio
			0xe800 0x0 0x0 0x1 &i8259 0x6 0x2

			// IDSEL 0x1e Legacy
			0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
			0xf100 0x0 0x0 0x1 &i8259 0x7 0x2

			// IDSEL 0x1f IDE/SATA
			0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
			0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
		>;

		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0xb0000000
				  0x2000000 0x0 0xb0000000
				  0x0 0x100000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;

			uli1575@0 {
				reg = <0x0 0x0 0x0 0x0 0x0>;
				#size-cells = <2>;
				#address-cells = <3>;
				ranges = <0x2000000 0x0 0xb0000000
					  0x2000000 0x0 0xb0000000
					  0x0 0x100000

					  0x1000000 0x0 0x0
					  0x1000000 0x0 0x0
					  0x0 0x100000>;
				isa@1e {
					device_type = "isa";
					#interrupt-cells = <2>;
					#size-cells = <1>;
					#address-cells = <2>;
					reg = <0xf000 0x0 0x0 0x0 0x0>;
					ranges = <0x1 0x0
						  0x1000000 0x0 0x0
						  0x1000>;
					interrupt-parent = <&i8259>;

					i8259: interrupt-controller@20 {
						reg = <0x1 0x20 0x2
						       0x1 0xa0 0x2
						       0x1 0x4d0 0x2>;
						interrupt-controller;
						device_type = "interrupt-controller";
						#address-cells = <0>;
						#interrupt-cells = <2>;
						compatible = "chrp,iic";
						interrupts = <9 2>;
						interrupt-parent = <&mpic>;
					};

					i8042@60 {
						#size-cells = <0>;
						#address-cells = <1>;
						reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
						interrupts = <1 3 12 3>;
						interrupt-parent = <&i8259>;

						keyboard@0 {
							reg = <0x0>;
							compatible = "pnpPNP,303";
						};

						mouse@1 {
							reg = <0x1>;
							compatible = "pnpPNP,f03";
						};
					};

					rtc@70 {
						compatible = "pnpPNP,b00";
						reg = <0x1 0x70 0x2>;
					};

					gpio@400 {
						reg = <0x1 0x400 0x80>;
					};
				};
			};
		};
	};
};
Commit	Line	Data
d93daf84 JL	1	/*
	2	* MPC8544 DS Device Tree Source
	3	*
32f960e9	4	* Copyright 2007, 2008 Freescale Semiconductor Inc.
d93daf84 JL	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
32f960e9	12	/dts-v1/;
d93daf84 JL	13	/ {
	14	model = "MPC8544DS";
	15	compatible = "MPC8544DS", "MPC85xxDS";
	16	#address-cells = <1>;
	17	#size-cells = <1>;
	18
ea082fa9 KG	19	aliases {
	20	ethernet0 = &enet0;
	21	ethernet1 = &enet1;
	22	serial0 = &serial0;
	23	serial1 = &serial1;
	24	pci0 = &pci0;
	25	pci1 = &pci1;
	26	pci2 = &pci2;
	27	pci3 = &pci3;
	28	};
	29
d93daf84	30	cpus {
d93daf84 JL	31	#address-cells = <1>;
	32	#size-cells = <0>;
	33
	34	PowerPC,8544@0 {
	35	device_type = "cpu";
32f960e9 KG	36	reg = <0x0>;
	37	d-cache-line-size = <32>; // 32 bytes
	38	i-cache-line-size = <32>; // 32 bytes
	39	d-cache-size = <0x8000>; // L1, 32K
	40	i-cache-size = <0x8000>; // L1, 32K
d93daf84 JL	41	timebase-frequency = <0>;
	42	bus-frequency = <0>;
	43	clock-frequency = <0>;
c054065b	44	next-level-cache = <&L2>;
d93daf84 JL	45	};
	46	};
	47
	48	memory {
	49	device_type = "memory";
32f960e9	50	reg = <0x0 0x0>; // Filled by U-Boot
d93daf84 JL	51	};
	52
	53	soc8544@e0000000 {
	54	#address-cells = <1>;
	55	#size-cells = <1>;
d93daf84	56	device_type = "soc";
cf0d19fb	57	compatible = "simple-bus";
b66510cb	58
32f960e9 KG	59	ranges = <0x0 0xe0000000 0x100000>;
32f960e9 KG	60	reg = <0xe0000000 0x1000>; // CCSRBAR 1M
d93daf84 JL	61	bus-frequency = <0>; // Filled out by uboot.
d93daf84 JL	62
4da421d6 KG	63	memory-controller@2000 {
4da421d6 KG	64	compatible = "fsl,8544-memory-controller";
32f960e9	65	reg = <0x2000 0x1000>;
4da421d6	66	interrupt-parent = <&mpic>;
32f960e9	67	interrupts = <18 2>;
4da421d6 KG	68	};
4da421d6 KG	69
c054065b	70	L2: l2-cache-controller@20000 {
4da421d6	71	compatible = "fsl,8544-l2-cache-controller";
32f960e9 KG	72	reg = <0x20000 0x1000>;
	73	cache-line-size = <32>; // 32 bytes
	74	cache-size = <0x40000>; // L2, 256K
4da421d6	75	interrupt-parent = <&mpic>;
32f960e9	76	interrupts = <16 2>;
4da421d6 KG	77	};
4da421d6 KG	78
d93daf84	79	i2c@3000 {
ec9686c4 KG	80	#address-cells = <1>;
	81	#size-cells = <0>;
	82	cell-index = <0>;
d93daf84	83	compatible = "fsl-i2c";
32f960e9 KG	84	reg = <0x3000 0x100>;
32f960e9 KG	85	interrupts = <43 2>;
d93daf84 JL	86	interrupt-parent = <&mpic>;
	87	dfsrr;
	88	};
	89
ec9686c4 KG	90	i2c@3100 {
	91	#address-cells = <1>;
	92	#size-cells = <0>;
	93	cell-index = <1>;
	94	compatible = "fsl-i2c";
32f960e9 KG	95	reg = <0x3100 0x100>;
32f960e9 KG	96	interrupts = <43 2>;
ec9686c4 KG	97	interrupt-parent = <&mpic>;
	98	dfsrr;
	99	};
	100
d93daf84 JL	101	mdio@24520 {
	102	#address-cells = <1>;
	103	#size-cells = <0>;
e77b28eb	104	compatible = "fsl,gianfar-mdio";
32f960e9	105	reg = <0x24520 0x20>;
e77b28eb	106
d93daf84 JL	107	phy0: ethernet-phy@0 {
d93daf84 JL	108	interrupt-parent = <&mpic>;
32f960e9 KG	109	interrupts = <10 1>;
32f960e9 KG	110	reg = <0x0>;
d93daf84 JL	111	device_type = "ethernet-phy";
	112	};
	113	phy1: ethernet-phy@1 {
	114	interrupt-parent = <&mpic>;
32f960e9 KG	115	interrupts = <10 1>;
32f960e9 KG	116	reg = <0x1>;
d93daf84 JL	117	device_type = "ethernet-phy";
d93daf84 JL	118	};
b31a1d8b AF	119
	120	tbi0: tbi-phy@11 {
	121	reg = <0x11>;
	122	device_type = "tbi-phy";
	123	};
d93daf84 JL	124	};
d93daf84 JL	125
b31a1d8b AF	126	mdio@26520 {
	127	#address-cells = <1>;
	128	#size-cells = <0>;
	129	compatible = "fsl,gianfar-tbi";
	130	reg = <0x26520 0x20>;
	131
	132	tbi1: tbi-phy@11 {
	133	reg = <0x11>;
	134	device_type = "tbi-phy";
	135	};
	136	};
	137
	138
1028d4f1 SS	139	dma@21300 {
	140	#address-cells = <1>;
	141	#size-cells = <1>;
	142	compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
32f960e9 KG	143	reg = <0x21300 0x4>;
32f960e9 KG	144	ranges = <0x0 0x21100 0x200>;
1028d4f1 SS	145	cell-index = <0>;
	146	dma-channel@0 {
	147	compatible = "fsl,mpc8544-dma-channel",
	148	"fsl,eloplus-dma-channel";
32f960e9	149	reg = <0x0 0x80>;
1028d4f1 SS	150	cell-index = <0>;
1028d4f1 SS	151	interrupt-parent = <&mpic>;
32f960e9	152	interrupts = <20 2>;
1028d4f1 SS	153	};
	154	dma-channel@80 {
	155	compatible = "fsl,mpc8544-dma-channel",
	156	"fsl,eloplus-dma-channel";
32f960e9	157	reg = <0x80 0x80>;
1028d4f1 SS	158	cell-index = <1>;
1028d4f1 SS	159	interrupt-parent = <&mpic>;
32f960e9	160	interrupts = <21 2>;
1028d4f1 SS	161	};
	162	dma-channel@100 {
	163	compatible = "fsl,mpc8544-dma-channel",
	164	"fsl,eloplus-dma-channel";
32f960e9	165	reg = <0x100 0x80>;
1028d4f1 SS	166	cell-index = <2>;
1028d4f1 SS	167	interrupt-parent = <&mpic>;
32f960e9	168	interrupts = <22 2>;
1028d4f1 SS	169	};
	170	dma-channel@180 {
	171	compatible = "fsl,mpc8544-dma-channel",
	172	"fsl,eloplus-dma-channel";
32f960e9	173	reg = <0x180 0x80>;
1028d4f1 SS	174	cell-index = <3>;
1028d4f1 SS	175	interrupt-parent = <&mpic>;
32f960e9	176	interrupts = <23 2>;
1028d4f1 SS	177	};
	178	};
	179
e77b28eb KG	180	enet0: ethernet@24000 {
e77b28eb KG	181	cell-index = <0>;
d93daf84 JL	182	device_type = "network";
	183	model = "TSEC";
	184	compatible = "gianfar";
32f960e9	185	reg = <0x24000 0x1000>;
d93daf84	186	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	187	interrupts = <29 2 30 2 34 2>;
d93daf84 JL	188	interrupt-parent = <&mpic>;
d93daf84 JL	189	phy-handle = <&phy0>;
b31a1d8b	190	tbi-handle = <&tbi0>;
9a9bcf4e	191	phy-connection-type = "rgmii-id";
d93daf84 JL	192	};
d93daf84 JL	193
e77b28eb KG	194	enet1: ethernet@26000 {
e77b28eb KG	195	cell-index = <1>;
d93daf84 JL	196	device_type = "network";
	197	model = "TSEC";
	198	compatible = "gianfar";
32f960e9	199	reg = <0x26000 0x1000>;
d93daf84	200	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	201	interrupts = <31 2 32 2 33 2>;
d93daf84 JL	202	interrupt-parent = <&mpic>;
d93daf84 JL	203	phy-handle = <&phy1>;
b31a1d8b	204	tbi-handle = <&tbi1>;
9a9bcf4e	205	phy-connection-type = "rgmii-id";
d93daf84 JL	206	};
d93daf84 JL	207
ea082fa9 KG	208	serial0: serial@4500 {
ea082fa9 KG	209	cell-index = <0>;
d93daf84 JL	210	device_type = "serial";
d93daf84 JL	211	compatible = "ns16550";
32f960e9	212	reg = <0x4500 0x100>;
d93daf84	213	clock-frequency = <0>;
32f960e9	214	interrupts = <42 2>;
d93daf84 JL	215	interrupt-parent = <&mpic>;
	216	};
	217
ea082fa9 KG	218	serial1: serial@4600 {
ea082fa9 KG	219	cell-index = <1>;
d93daf84 JL	220	device_type = "serial";
d93daf84 JL	221	compatible = "ns16550";
32f960e9	222	reg = <0x4600 0x100>;
d93daf84	223	clock-frequency = <0>;
32f960e9	224	interrupts = <42 2>;
d93daf84 JL	225	interrupt-parent = <&mpic>;
	226	};
	227
1b3c5cda KG	228	global-utilities@e0000 { //global utilities block
1b3c5cda KG	229	compatible = "fsl,mpc8548-guts";
32f960e9	230	reg = <0xe0000 0x1000>;
1b3c5cda KG	231	fsl,has-rstcr;
1b3c5cda KG	232	};
f16dab98	233
3fd44736 KP	234	crypto@30000 {
	235	compatible = "fsl,sec2.1", "fsl,sec2.0";
	236	reg = <0x30000 0x10000>;
	237	interrupts = <45 2>;
	238	interrupt-parent = <&mpic>;
	239	fsl,num-channels = <4>;
	240	fsl,channel-fifo-len = <24>;
	241	fsl,exec-units-mask = <0xfe>;
	242	fsl,descriptor-types-mask = <0x12b0ebf>;
	243	};
	244
1b3c5cda	245	mpic: pic@40000 {
1b3c5cda KG	246	interrupt-controller;
	247	#address-cells = <0>;
	248	#interrupt-cells = <2>;
32f960e9	249	reg = <0x40000 0x40000>;
1b3c5cda KG	250	compatible = "chrp,open-pic";
1b3c5cda KG	251	device_type = "open-pic";
1b3c5cda	252	};
741edc49 JJ	253
	254	msi@41600 {
	255	compatible = "fsl,mpc8544-msi", "fsl,mpic-msi";
	256	reg = <0x41600 0x80>;
	257	msi-available-ranges = <0 0x100>;
	258	interrupts = <
	259	0xe0 0
	260	0xe1 0
	261	0xe2 0
	262	0xe3 0
	263	0xe4 0
	264	0xe5 0
	265	0xe6 0
	266	0xe7 0>;
	267	interrupt-parent = <&mpic>;
	268	};
1b3c5cda	269	};
f16dab98	270
ea082fa9 KG	271	pci0: pci@e0008000 {
ea082fa9 KG	272	cell-index = <0>;
1b3c5cda KG	273	compatible = "fsl,mpc8540-pci";
1b3c5cda KG	274	device_type = "pci";
32f960e9	275	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	276	interrupt-map = <
	277
	278	/* IDSEL 0x11 J17 Slot 1 */
32f960e9 KG	279	0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
	280	0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
	281	0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
	282	0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
1b3c5cda KG	283
	284	/* IDSEL 0x12 J16 Slot 2 */
	285
32f960e9 KG	286	0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
	287	0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
	288	0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
	289	0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
1b3c5cda KG	290
1b3c5cda KG	291	interrupt-parent = <&mpic>;
32f960e9 KG	292	interrupts = <24 2>;
	293	bus-range = <0 255>;
	294	ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
	295	0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
	296	clock-frequency = <66666666>;
1b3c5cda KG	297	#interrupt-cells = <1>;
	298	#size-cells = <2>;
	299	#address-cells = <3>;
32f960e9	300	reg = <0xe0008000 0x1000>;
1b3c5cda	301	};
f16dab98	302
ea082fa9 KG	303	pci1: pcie@e0009000 {
ea082fa9 KG	304	cell-index = <1>;
1b3c5cda KG	305	compatible = "fsl,mpc8548-pcie";
	306	device_type = "pci";
	307	#interrupt-cells = <1>;
	308	#size-cells = <2>;
	309	#address-cells = <3>;
32f960e9 KG	310	reg = <0xe0009000 0x1000>;
	311	bus-range = <0 255>;
	312	ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
	313	0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
	314	clock-frequency = <33333333>;
1b3c5cda	315	interrupt-parent = <&mpic>;
32f960e9 KG	316	interrupts = <26 2>;
32f960e9 KG	317	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	318	interrupt-map = <
1b3c5cda KG	319	/* IDSEL 0x0 */
32f960e9 KG	320	0000 0x0 0x0 0x1 &mpic 0x4 0x1
	321	0000 0x0 0x0 0x2 &mpic 0x5 0x1
	322	0000 0x0 0x0 0x3 &mpic 0x6 0x1
	323	0000 0x0 0x0 0x4 &mpic 0x7 0x1
1b3c5cda KG	324	>;
1b3c5cda KG	325	pcie@0 {
32f960e9	326	reg = <0x0 0x0 0x0 0x0 0x0>;
f16dab98 RZ	327	#size-cells = <2>;
f16dab98 RZ	328	#address-cells = <3>;
f16dab98	329	device_type = "pci";
32f960e9 KG	330	ranges = <0x2000000 0x0 0x80000000
	331	0x2000000 0x0 0x80000000
	332	0x0 0x20000000
1b3c5cda	333
32f960e9 KG	334	0x1000000 0x0 0x0
	335	0x1000000 0x0 0x0
	336	0x0 0x10000>;
f16dab98	337	};
1b3c5cda	338	};
f16dab98	339
ea082fa9 KG	340	pci2: pcie@e000a000 {
ea082fa9 KG	341	cell-index = <2>;
1b3c5cda KG	342	compatible = "fsl,mpc8548-pcie";
	343	device_type = "pci";
	344	#interrupt-cells = <1>;
	345	#size-cells = <2>;
	346	#address-cells = <3>;
32f960e9 KG	347	reg = <0xe000a000 0x1000>;
	348	bus-range = <0 255>;
	349	ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
	350	0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
	351	clock-frequency = <33333333>;
1b3c5cda	352	interrupt-parent = <&mpic>;
32f960e9 KG	353	interrupts = <25 2>;
32f960e9 KG	354	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	355	interrupt-map = <
1b3c5cda KG	356	/* IDSEL 0x0 */
32f960e9 KG	357	0000 0x0 0x0 0x1 &mpic 0x0 0x1
	358	0000 0x0 0x0 0x2 &mpic 0x1 0x1
	359	0000 0x0 0x0 0x3 &mpic 0x2 0x1
	360	0000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	361	>;
1b3c5cda KG	362	pcie@0 {
32f960e9	363	reg = <0x0 0x0 0x0 0x0 0x0>;
f16dab98 RZ	364	#size-cells = <2>;
f16dab98 RZ	365	#address-cells = <3>;
1b3c5cda	366	device_type = "pci";
32f960e9 KG	367	ranges = <0x2000000 0x0 0xa0000000
	368	0x2000000 0x0 0xa0000000
	369	0x0 0x10000000
1b3c5cda	370
32f960e9 KG	371	0x1000000 0x0 0x0
	372	0x1000000 0x0 0x0
	373	0x0 0x10000>;
f16dab98	374	};
1b3c5cda	375	};
f16dab98	376
ea082fa9 KG	377	pci3: pcie@e000b000 {
ea082fa9 KG	378	cell-index = <3>;
1b3c5cda KG	379	compatible = "fsl,mpc8548-pcie";
	380	device_type = "pci";
	381	#interrupt-cells = <1>;
	382	#size-cells = <2>;
	383	#address-cells = <3>;
32f960e9 KG	384	reg = <0xe000b000 0x1000>;
	385	bus-range = <0 255>;
	386	ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
	387	0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
	388	clock-frequency = <33333333>;
1b3c5cda	389	interrupt-parent = <&mpic>;
32f960e9 KG	390	interrupts = <27 2>;
32f960e9 KG	391	interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
1b3c5cda KG	392	interrupt-map = <
1b3c5cda KG	393	// IDSEL 0x1c USB
32f960e9 KG	394	0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
	395	0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
	396	0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
	397	0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
1b3c5cda KG	398
1b3c5cda KG	399	// IDSEL 0x1d Audio
32f960e9	400	0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
1b3c5cda KG	401
1b3c5cda KG	402	// IDSEL 0x1e Legacy
32f960e9 KG	403	0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
32f960e9 KG	404	0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
1b3c5cda KG	405
1b3c5cda KG	406	// IDSEL 0x1f IDE/SATA
32f960e9 KG	407	0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
32f960e9 KG	408	0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
1b3c5cda KG	409	>;
	410
	411	pcie@0 {
32f960e9	412	reg = <0x0 0x0 0x0 0x0 0x0>;
f16dab98 RZ	413	#size-cells = <2>;
f16dab98 RZ	414	#address-cells = <3>;
1b3c5cda	415	device_type = "pci";
32f960e9 KG	416	ranges = <0x2000000 0x0 0xb0000000
	417	0x2000000 0x0 0xb0000000
	418	0x0 0x100000
1b3c5cda	419
32f960e9 KG	420	0x1000000 0x0 0x0
	421	0x1000000 0x0 0x0
	422	0x0 0x100000>;
1b3c5cda	423
f16dab98	424	uli1575@0 {
32f960e9	425	reg = <0x0 0x0 0x0 0x0 0x0>;
f16dab98 RZ	426	#size-cells = <2>;
f16dab98 RZ	427	#address-cells = <3>;
32f960e9 KG	428	ranges = <0x2000000 0x0 0xb0000000
	429	0x2000000 0x0 0xb0000000
	430	0x0 0x100000
1b3c5cda	431
32f960e9 KG	432	0x1000000 0x0 0x0
	433	0x1000000 0x0 0x0
	434	0x0 0x100000>;
1b3c5cda KG	435	isa@1e {
	436	device_type = "isa";
	437	#interrupt-cells = <2>;
	438	#size-cells = <1>;
	439	#address-cells = <2>;
32f960e9 KG	440	reg = <0xf000 0x0 0x0 0x0 0x0>;
	441	ranges = <0x1 0x0
	442	0x1000000 0x0 0x0
	443	0x1000>;
1b3c5cda KG	444	interrupt-parent = <&i8259>;
	445
	446	i8259: interrupt-controller@20 {
32f960e9 KG	447	reg = <0x1 0x20 0x2
	448	0x1 0xa0 0x2
	449	0x1 0x4d0 0x2>;
1b3c5cda KG	450	interrupt-controller;
	451	device_type = "interrupt-controller";
	452	#address-cells = <0>;
f16dab98	453	#interrupt-cells = <2>;
1b3c5cda KG	454	compatible = "chrp,iic";
	455	interrupts = <9 2>;
	456	interrupt-parent = <&mpic>;
	457	};
	458
	459	i8042@60 {
	460	#size-cells = <0>;
	461	#address-cells = <1>;
32f960e9 KG	462	reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
32f960e9 KG	463	interrupts = <1 3 12 3>;
f16dab98 RZ	464	interrupt-parent = <&i8259>;
f16dab98 RZ	465
1b3c5cda	466	keyboard@0 {
32f960e9	467	reg = <0x0>;
1b3c5cda	468	compatible = "pnpPNP,303";
f16dab98 RZ	469	};
f16dab98 RZ	470
1b3c5cda	471	mouse@1 {
32f960e9	472	reg = <0x1>;
1b3c5cda	473	compatible = "pnpPNP,f03";
f16dab98	474	};
1b3c5cda	475	};
f16dab98	476
1b3c5cda KG	477	rtc@70 {
1b3c5cda KG	478	compatible = "pnpPNP,b00";
32f960e9	479	reg = <0x1 0x70 0x2>;
1b3c5cda	480	};
f16dab98	481
1b3c5cda	482	gpio@400 {
32f960e9	483	reg = <0x1 0x400 0x80>;
f16dab98 RZ	484	};
	485	};
	486	};
f16dab98	487	};
d93daf84 JL	488	};
d93daf84 JL	489	};