projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 26ef5c09 DG |
1 | #ifndef _ASM_POWERPC_CACHE_H |
| 2 | #define _ASM_POWERPC_CACHE_H | |
| 3 | ||
| 4 | #ifdef __KERNEL__ | |
| 5 | ||
| 26ef5c09 DG |
6 | |
| 7 | /* bytes per L1 cache line */ | |
| 8 | #if defined(CONFIG_8xx) || defined(CONFIG_403GCX) | |
| 9 | #define L1_CACHE_SHIFT 4 | |
| 10 | #define MAX_COPY_PREFETCH 1 | |
| 3dfa8773 KG |
11 | #elif defined(CONFIG_PPC_E500MC) |
| 12 | #define L1_CACHE_SHIFT 6 | |
| 13 | #define MAX_COPY_PREFETCH 4 | |
| 26ef5c09 | 14 | #elif defined(CONFIG_PPC32) |
| 26ef5c09 | 15 | #define MAX_COPY_PREFETCH 4 |
| e7f75ad0 DK |
16 | #if defined(CONFIG_PPC_47x) |
| 17 | #define L1_CACHE_SHIFT 7 | |
| 18 | #else | |
| 19 | #define L1_CACHE_SHIFT 5 | |
| 20 | #endif | |
| 26ef5c09 DG |
21 | #else /* CONFIG_PPC64 */ |
| 22 | #define L1_CACHE_SHIFT 7 | |
| 23 | #endif | |
| 24 | ||
| 25 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) | |
| 26 | ||
| 27 | #define SMP_CACHE_BYTES L1_CACHE_BYTES | |
| 26ef5c09 DG |
28 | |
| 29 | #if defined(__powerpc64__) && !defined(__ASSEMBLY__) | |
| 30 | struct ppc64_caches { | |
| 31 | u32 dsize; /* L1 d-cache size */ | |
| 32 | u32 dline_size; /* L1 d-cache line size */ | |
| 33 | u32 log_dline_size; | |
| 34 | u32 dlines_per_page; | |
| 35 | u32 isize; /* L1 i-cache size */ | |
| 36 | u32 iline_size; /* L1 i-cache line size */ | |
| 37 | u32 log_iline_size; | |
| 38 | u32 ilines_per_page; | |
| 39 | }; | |
| 40 | ||
| 41 | extern struct ppc64_caches ppc64_caches; | |
| 42 | #endif /* __powerpc64__ && ! __ASSEMBLY__ */ | |
| 43 | ||
| 0ce63670 KH |
44 | #if defined(__ASSEMBLY__) |
| 45 | /* | |
| 46 | * For a snooping icache, we still need a dummy icbi to purge all the | |
| 47 | * prefetched instructions from the ifetch buffers. We also need a sync | |
| 48 | * before the icbi to order the the actual stores to memory that might | |
| 49 | * have modified instructions with the icbi. | |
| 50 | */ | |
| 51 | #define PURGE_PREFETCHED_INS \ | |
| 52 | sync; \ | |
| 53 | icbi 0,r3; \ | |
| 54 | sync; \ | |
| 55 | isync | |
| ae3a197e | 56 | |
| 0ce63670 | 57 | #else |
| 54cb27a7 | 58 | #define __read_mostly __attribute__((__section__(".data..read_mostly"))) |
| ae3a197e DH |
59 | |
| 60 | #ifdef CONFIG_6xx | |
| 61 | extern long _get_L2CR(void); | |
| 62 | extern long _get_L3CR(void); | |
| 63 | extern void _set_L2CR(unsigned long); | |
| 64 | extern void _set_L3CR(unsigned long); | |
| 65 | #else | |
| 66 | #define _get_L2CR() 0L | |
| 67 | #define _get_L3CR() 0L | |
| 68 | #define _set_L2CR(val) do { } while(0) | |
| 69 | #define _set_L3CR(val) do { } while(0) | |
| bd67fcf9 TB |
70 | #endif |
| 71 | ||
| d6bfa02f CL |
72 | static inline void dcbz(void *addr) |
| 73 | { | |
| 74 | __asm__ __volatile__ ("dcbz 0, %0" : : "r"(addr) : "memory"); | |
| 75 | } | |
| 76 | ||
| 77 | static inline void dcbi(void *addr) | |
| 78 | { | |
| 79 | __asm__ __volatile__ ("dcbi 0, %0" : : "r"(addr) : "memory"); | |
| 80 | } | |
| 81 | ||
| 82 | static inline void dcbf(void *addr) | |
| 83 | { | |
| 84 | __asm__ __volatile__ ("dcbf 0, %0" : : "r"(addr) : "memory"); | |
| 85 | } | |
| 86 | ||
| 87 | static inline void dcbst(void *addr) | |
| 88 | { | |
| 89 | __asm__ __volatile__ ("dcbst 0, %0" : : "r"(addr) : "memory"); | |
| 90 | } | |
| ae3a197e | 91 | #endif /* !__ASSEMBLY__ */ |
| 26ef5c09 DG |
92 | #endif /* __KERNEL__ */ |
| 93 | #endif /* _ASM_POWERPC_CACHE_H */ |