projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'md/4.6-rc6-fix' of git://git.kernel.org/pub/scm/linux/kernel/git/shli/md
[deliverable/linux.git] / arch / powerpc / include / asm / cputable.h
CommitLineData
10b35d99
KG		 1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
d1cdcf22
AB		 4
5#include <asm/asm-compat.h>
c5157e58 6#include <asm/feature-fixups.h>
c3617f72 7#include <uapi/asm/cputable.h>
d1cdcf22 8
10b35d99
KG		 9#ifndef __ASSEMBLY__
10
11/* This structure can grow, it's real size is used by head.S code
12 * via the mkdefs mechanism.
13 */
14struct cpu_spec;
10b35d99 15
10b35d99 16typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
f39b7a55 17typedef void (*cpu_restore_t)(void);
10b35d99 18
32a33994 19enum powerpc_oprofile_type {
7a45fb19
AW		 20 PPC_OPROFILE_INVALID = 0,
21 PPC_OPROFILE_RS64 = 1,
22 PPC_OPROFILE_POWER4 = 2,
23 PPC_OPROFILE_G4 = 3,
39aef685 24 PPC_OPROFILE_FSL_EMB = 4,
18f2190d 25 PPC_OPROFILE_CELL = 5,
25fc530e 26 PPC_OPROFILE_PA6T = 6,
32a33994
AB		 27};
28
1bd2e5ae
OJ		 29enum powerpc_pmc_type {
30 PPC_PMC_DEFAULT = 0,
31 PPC_PMC_IBM = 1,
32 PPC_PMC_PA6T = 2,
b950bdd0 33 PPC_PMC_G4 = 3,
1bd2e5ae
OJ		 34};
35
47c0bd1a
BH		 36struct pt_regs;
37
38extern int machine_check_generic(struct pt_regs *regs);
39extern int machine_check_4xx(struct pt_regs *regs);
40extern int machine_check_440A(struct pt_regs *regs);
fe04b112 41extern int machine_check_e500mc(struct pt_regs *regs);
47c0bd1a
BH		 42extern int machine_check_e500(struct pt_regs *regs);
43extern int machine_check_e200(struct pt_regs *regs);
fc5e7097 44extern int machine_check_47x(struct pt_regs *regs);
47c0bd1a 45
e7affb1d 46extern void cpu_down_flush_e500v2(void);
47extern void cpu_down_flush_e500mc(void);
48extern void cpu_down_flush_e5500(void);
49extern void cpu_down_flush_e6500(void);
50
87a72f9e 51/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
10b35d99
KG		 52struct cpu_spec {
53 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
54 unsigned int pvr_mask;
55 unsigned int pvr_value;
56
57 char *cpu_name;
58 unsigned long cpu_features; /* Kernel features */
59 unsigned int cpu_user_features; /* Userland features */
2171364d 60 unsigned int cpu_user_features2; /* Userland features v2 */
7c03d653 61 unsigned int mmu_features; /* MMU features */
10b35d99
KG		 62
63 /* cache line sizes */
64 unsigned int icache_bsize;
65 unsigned int dcache_bsize;
66
e7affb1d 67 /* flush caches inside the current cpu */
68 void (*cpu_down_flush)(void);
69
10b35d99
KG		 70 /* number of performance monitor counters */
71 unsigned int num_pmcs;
1bd2e5ae 72 enum powerpc_pmc_type pmc_type;
10b35d99
KG		 73
74 /* this is called to initialize various CPU bits like L1 cache,
75 * BHT, SPD, etc... from head.S before branching to identify_machine
76 */
77 cpu_setup_t cpu_setup;
f39b7a55
OJ		 78 /* Used to restore cpu setup on secondary processors and at resume */
79 cpu_restore_t cpu_restore;
10b35d99
KG		 80
81 /* Used by oprofile userspace to select the right counters */
82 char *oprofile_cpu_type;
83
84 /* Processor specific oprofile operations */
32a33994 85 enum powerpc_oprofile_type oprofile_type;
80f15dc7 86
e78dbc80
MN		 87 /* Bit locations inside the mmcra change */
88 unsigned long oprofile_mmcra_sihv;
89 unsigned long oprofile_mmcra_sipr;
90
91 /* Bits to clear during an oprofile exception */
92 unsigned long oprofile_mmcra_clear;
93
80f15dc7
PM		 94 /* Name of processor class, for the ELF AT_PLATFORM entry */
95 char *platform;
47c0bd1a
BH		 96
97 /* Processor specific machine check handling. Return negative
98 * if the error is fatal, 1 if it was fully recovered and 0 to
99 * pass up (not CPU originated) */
100 int (*machine_check)(struct pt_regs *regs);
4c703416
MS		 101
102 /*
103 * Processor specific early machine check handler which is
104 * called in real mode to handle SLB and TLB errors.
105 */
106 long (*machine_check_early)(struct pt_regs *regs);
107
04407050
MS		 108 /*
109 * Processor specific routine to flush tlbs.
110 */
45706bb5 111 void (*flush_tlb)(unsigned int action);
04407050 112
10b35d99
KG		 113};
114
10b35d99 115extern struct cpu_spec *cur_cpu_spec;
10b35d99 116
42c4aaad
BH		 117extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
118
974a76f5 119extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
0909c8c2
BH		 120extern void do_feature_fixups(unsigned long value, void *fixup_start,
121 void *fixup_end);
9b6b563c 122
9115d134
NL		 123extern const char *powerpc_base_platform;
124
45706bb5
MS		 125/* TLB flush actions. Used as argument to cpu_spec.flush_tlb() hook */
126enum {
127 TLB_INVAL_SCOPE_GLOBAL = 0, /* invalidate all TLBs */
128 TLB_INVAL_SCOPE_LPID = 1, /* invalidate TLBs for current LPID */
129};
130
10b35d99
KG		 131#endif /* __ASSEMBLY__ */
132
133/* CPU kernel features */
134
135/* Retain the 32b definitions all use bottom half of word */
cde4d494
MN		 136#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
137#define CPU_FTR_L2CR ASM_CONST(0x00000002)
138#define CPU_FTR_SPEC7450 ASM_CONST(0x00000004)
139#define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
140#define CPU_FTR_TAU ASM_CONST(0x00000010)
141#define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
142#define CPU_FTR_USE_TB ASM_CONST(0x00000040)
143#define CPU_FTR_L2CSR ASM_CONST(0x00000080)
144#define CPU_FTR_601 ASM_CONST(0x00000100)
145#define CPU_FTR_DBELL ASM_CONST(0x00000200)
146#define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
147#define CPU_FTR_L3CR ASM_CONST(0x00000800)
148#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000)
149#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000)
150#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000)
151#define CPU_FTR_NO_DPM ASM_CONST(0x00008000)
152#define CPU_FTR_476_DD2 ASM_CONST(0x00010000)
153#define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000)
154#define CPU_FTR_NO_BTIC ASM_CONST(0x00040000)
155#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000)
156#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000)
157#define CPU_FTR_PPC_LE ASM_CONST(0x00200000)
158#define CPU_FTR_REAL_LE ASM_CONST(0x00400000)
159#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000)
160#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000)
161#define CPU_FTR_SPE ASM_CONST(0x02000000)
162#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000)
163#define CPU_FTR_LWSYNC ASM_CONST(0x08000000)
164#define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000)
165#define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000)
166#define CPU_FTR_EMB_HV ASM_CONST(0x40000000)
10b35d99 167
3965f8c5
PM		 168/*
169 * Add the 64-bit processor unique features in the top half of the word;
170 * on 32-bit, make the names available but defined to be 0.
171 */
10b35d99 172#ifdef __powerpc64__
3965f8c5 173#define LONG_ASM_CONST(x) ASM_CONST(x)
10b35d99 174#else
3965f8c5 175#define LONG_ASM_CONST(x) 0
10b35d99
KG		 176#endif
177
1580b3b8
MN		 178#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000)
179#define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000)
180#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000)
1de2bd4e 181#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000800000000)
c3ab300e 182#define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000001000000000)
1580b3b8
MN		 183#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000)
184#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000)
185#define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000)
186#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000)
187#define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000)
188#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000)
189#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000)
190#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000)
191#define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000)
192#define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000)
193#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000)
194#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000)
195#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000)
196#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000)
197#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000)
198#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000)
199#define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000)
200#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000)
201#define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000)
1de2bd4e 202#define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000)
1580b3b8 203#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
79879c17 204#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
82a9f16a 205#define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000)
68f2f0d4 206#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x1000000000000000)
ce5732a2 207#define CPU_FTR_SUBCORE LONG_ASM_CONST(0x2000000000000000)
3965f8c5 208
10b35d99
KG		 209#ifndef __ASSEMBLY__
210
44ae3ab3
ME		 211#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
212
13b3d13b 213#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
10b35d99
KG		 214
215/* We only set the altivec features if the kernel was compiled with altivec
216 * support
217 */
218#ifdef CONFIG_ALTIVEC
219#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
220#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
221#else
222#define CPU_FTR_ALTIVEC_COMP 0
223#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
224#endif
225
b962ce9d
MN		 226/* We only set the VSX features if the kernel was compiled with VSX
227 * support
228 */
229#ifdef CONFIG_VSX
230#define CPU_FTR_VSX_COMP CPU_FTR_VSX
231#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
232#else
233#define CPU_FTR_VSX_COMP 0
234#define PPC_FEATURE_HAS_VSX_COMP 0
235#endif
236
5e14d21e
KG		 237/* We only set the spe features if the kernel was compiled with spe
238 * support
239 */
240#ifdef CONFIG_SPE
241#define CPU_FTR_SPE_COMP CPU_FTR_SPE
242#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
243#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
244#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
245#else
246#define CPU_FTR_SPE_COMP 0
247#define PPC_FEATURE_HAS_SPE_COMP 0
248#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
249#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
250#endif
251
6a6d541f
MN		 252/* We only set the TM feature if the kernel was compiled with TM supprt */
253#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
b4b56f9e
S		 254#define CPU_FTR_TM_COMP CPU_FTR_TM
255#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
256#define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC
6a6d541f 257#else
b4b56f9e
S		 258#define CPU_FTR_TM_COMP 0
259#define PPC_FEATURE2_HTM_COMP 0
260#define PPC_FEATURE2_HTM_NOSC_COMP 0
6a6d541f
MN		 261#endif
262
11af1192
SW		 263/* We need to mark all pages as being coherent if we're SMP or we have a
264 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
265 * require it for PCI "streaming/prefetch" to work properly.
c9310920 266 * This is also required by 52xx family.
10b35d99 267 */
1775dbbc 268#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
c9310920
PZ		 269 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
270 || defined(CONFIG_PPC_MPC52xx)
10b35d99
KG		 271#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
272#else
273#define CPU_FTR_COMMON 0
274#endif
275
276/* The powersave features NAP & DOZE seems to confuse BDI when
277 debugging. So if a BDI is used, disable theses
278 */
279#ifndef CONFIG_BDI_SWITCH
280#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
281#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
282#else
283#define CPU_FTR_MAYBE_CAN_DOZE 0
284#define CPU_FTR_MAYBE_CAN_NAP 0
285#endif
286
7c03d653 287#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
4508dc21
DG		 288 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
289#define CPU_FTRS_603 (CPU_FTR_COMMON | \
7c92943c 290 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
fab5db97 291 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 292#define CPU_FTRS_604 (CPU_FTR_COMMON | \
7c03d653 293 CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
4508dc21 294#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
7c92943c 295 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 296 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 297#define CPU_FTRS_740 (CPU_FTR_COMMON | \
7c92943c 298 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 299 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 300 CPU_FTR_PPC_LE)
4508dc21 301#define CPU_FTRS_750 (CPU_FTR_COMMON | \
7c92943c 302 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 303 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 304 CPU_FTR_PPC_LE)
7c03d653 305#define CPU_FTRS_750CL (CPU_FTRS_750)
b6f41cc8
JB		 306#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
307#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
7c03d653 308#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
b6f41cc8 309#define CPU_FTRS_750GX (CPU_FTRS_750FX)
4508dc21 310#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
7c92943c 311 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 312 CPU_FTR_ALTIVEC_COMP | \
fab5db97 313 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 314#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
7c92943c 315 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 316 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
fab5db97 317 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 318#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
7c92943c 319 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 320 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
b64f87c1 321 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 322#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
7c92943c
SR		 323 CPU_FTR_USE_TB | \
324 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 325 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 326 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
b64f87c1 327 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 328#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
b64f87c1 329 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 330 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 331 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
fab5db97 332 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 333#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
b64f87c1 334 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 335 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
7c03d653 336 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 337#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
b64f87c1 338 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 339 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 340 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 341 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
7c03d653 342 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 343#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
7c92943c
SR		 344 CPU_FTR_USE_TB | \
345 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 346 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 347 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 348#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
7c92943c
SR		 349 CPU_FTR_USE_TB | \
350 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 351 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1
BB		 352 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
353 CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 354#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
7c92943c
SR		 355 CPU_FTR_USE_TB | \
356 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 357 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 358 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 359#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
7c92943c
SR		 360 CPU_FTR_USE_TB | \
361 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 362 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 363 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 364#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
3d372548
JY		 365 CPU_FTR_USE_TB | \
366 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 367 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 368 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 369#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
7c92943c 370 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
11af1192 371#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 372 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
4508dc21 373#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 374 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
7c92943c 375 CPU_FTR_COMMON)
4508dc21 376#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 377 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
aa42c69c 378 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
7c03d653 379#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
5b2753fc 380#define CPU_FTRS_8XX (CPU_FTR_USE_TB | CPU_FTR_NOEXECUTE)
8309ce72
BH		 381#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
382#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
6d2170be
BH		 383#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
384 CPU_FTR_INDEXED_DCR)
e7f75ad0 385#define CPU_FTRS_47X (CPU_FTRS_440x6)
5e14d21e
KG		 386#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
387 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
52b066fa
SW		 388 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
389 CPU_FTR_DEBUG_LVL_EXC)
fc4033b2 390#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
8309ce72
BH		 391 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
392 CPU_FTR_NOEXECUTE)
fc4033b2 393#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
7c03d653 394 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
8309ce72 395 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
d51ad915 396#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
620165f9 397 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
73196cd3 398 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
d52459ca
SW		 399/*
400 * e5500/e6500 erratum A-006958 is a timebase bug that can use the
401 * same workaround as CPU_FTR_CELL_TB_BUG.
402 */
11ed0db9
KG		 403#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
404 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
d36b4c4f 405 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d52459ca 406 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
10241842
KG		 407#define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
408 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
409 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d52459ca 410 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
e16c8765 411 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
7c92943c 412#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
0b8e2e13
ME		 413
414/* 64-bit CPUs */
2d1b2027 415#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 416 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
f89451fb
AB		 417 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
418 CPU_FTR_STCX_CHECKS_ADDRESS)
2d1b2027 419#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
969391c5 420 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
2a929436 421 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
969391c5 422 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
82a9f16a 423 CPU_FTR_HVMODE | CPU_FTR_DABRX)
2d1b2027 424#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 425 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 426 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 427 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
82a9f16a 428 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
2d1b2027 429#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 430 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
03054d51 431 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 432 CPU_FTR_COHERENT_ICACHE | \
4c198557 433 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
f89451fb 434 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
82a9f16a
MN		 435 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
436 CPU_FTR_DABRX)
2d1b2027 437#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
969391c5 438 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
e952e6c4 439 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 440 CPU_FTR_COHERENT_ICACHE | \
e952e6c4 441 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
f89451fb 442 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
851d2e2f 443 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d2613868 444 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
82a9f16a 445 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)
71e18497
MN		 446#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
447 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
448 CPU_FTR_MMCRA | CPU_FTR_SMT | \
449 CPU_FTR_COHERENT_ICACHE | \
450 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
451 CPU_FTR_DSCR | CPU_FTR_SAO | \
452 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
e5e84f0a 453 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
1de2bd4e 454 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
ce5732a2 455 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_SUBCORE)
68f2f0d4 456#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
bd6ba351 457#define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)
c3ab300e
MN		 458#define CPU_FTRS_POWER9 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
459 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
460 CPU_FTR_MMCRA | CPU_FTR_SMT | \
461 CPU_FTR_COHERENT_ICACHE | \
462 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
463 CPU_FTR_DSCR | CPU_FTR_SAO | \
464 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
465 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
466 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
467 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_ARCH_300)
2d1b2027 468#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 469 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 470 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 471 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
82a9f16a 472 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
2d1b2027 473#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
44ae3ab3 474 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
82a9f16a 475 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
7c03d653 476#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
10b35d99 477
2406f606 478#ifdef __powerpc64__
11ed0db9 479#ifdef CONFIG_PPC_BOOK3E
90029640 480#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500)
11ed0db9 481#else
7c92943c 482#define CPU_FTRS_POSSIBLE \
468a3302
ME		 483 (CPU_FTRS_POWER4 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
484 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
3609e09f 485 CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \
c3ab300e 486 CPU_FTRS_PA6T | CPU_FTR_VSX | CPU_FTRS_POWER9)
11ed0db9 487#endif
2406f606 488#else
7c92943c
SR		 489enum {
490 CPU_FTRS_POSSIBLE =
1e07a0a0 491#ifdef CONFIG_PPC_BOOK3S_32
10b35d99
KG		 492 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
493 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
494 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
495 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
496 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
497 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
498 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
aa42c69c
KP		 499 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
500 CPU_FTRS_CLASSIC32 |
10b35d99
KG		 501#else
502 CPU_FTRS_GENERIC_32 |
503#endif
10b35d99
KG		 504#ifdef CONFIG_8xx
505 CPU_FTRS_8XX |
506#endif
507#ifdef CONFIG_40x
508 CPU_FTRS_40X |
509#endif
510#ifdef CONFIG_44x
6d2170be 511 CPU_FTRS_44X | CPU_FTRS_440x6 |
10b35d99 512#endif
e7f75ad0 513#ifdef CONFIG_PPC_47x
c48d0dba 514 CPU_FTRS_47X | CPU_FTR_476_DD2 |
e7f75ad0 515#endif
10b35d99
KG		 516#ifdef CONFIG_E200
517 CPU_FTRS_E200 |
518#endif
519#ifdef CONFIG_E500
06aae867
SW		 520 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
521#endif
522#ifdef CONFIG_PPC_E500MC
523 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
10b35d99 524#endif
10b35d99 525 0,
7c92943c
SR		 526};
527#endif /* __powerpc64__ */
10b35d99 528
2406f606 529#ifdef __powerpc64__
11ed0db9 530#ifdef CONFIG_PPC_BOOK3E
90029640 531#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500)
11ed0db9 532#else
7c92943c 533#define CPU_FTRS_ALWAYS \
468a3302
ME		 534 (CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
535 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
3609e09f 536 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
c3ab300e
MN		 537 CPU_FTRS_POWER8_DD1 & ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & \
538 CPU_FTRS_POWER9)
11ed0db9 539#endif
2406f606 540#else
7c92943c
SR		 541enum {
542 CPU_FTRS_ALWAYS =
1e07a0a0 543#ifdef CONFIG_PPC_BOOK3S_32
10b35d99
KG		 544 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
545 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
546 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
547 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
548 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
549 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
550 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
aa42c69c
KP		 551 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
552 CPU_FTRS_CLASSIC32 &
10b35d99
KG		 553#else
554 CPU_FTRS_GENERIC_32 &
555#endif
10b35d99
KG		 556#ifdef CONFIG_8xx
557 CPU_FTRS_8XX &
558#endif
559#ifdef CONFIG_40x
560 CPU_FTRS_40X &
561#endif
562#ifdef CONFIG_44x
6d2170be 563 CPU_FTRS_44X & CPU_FTRS_440x6 &
10b35d99
KG		 564#endif
565#ifdef CONFIG_E200
566 CPU_FTRS_E200 &
567#endif
568#ifdef CONFIG_E500
06aae867
SW		 569 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
570#endif
571#ifdef CONFIG_PPC_E500MC
572 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
10b35d99 573#endif
73196cd3 574 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
10b35d99
KG		 575 CPU_FTRS_POSSIBLE,
576};
7c92943c 577#endif /* __powerpc64__ */
10b35d99
KG		 578
579static inline int cpu_has_feature(unsigned long feature)
580{
581 return (CPU_FTRS_ALWAYS & feature) ||
582 (CPU_FTRS_POSSIBLE
10b35d99 583 & cur_cpu_spec->cpu_features
10b35d99
KG		 584 & feature);
585}
586
5aae8a53 587#define HBP_NUM 1
5aae8a53 588
10b35d99
KG		 589#endif /* !__ASSEMBLY__ */
590
10b35d99 591#endif /* __ASM_POWERPC_CPUTABLE_H */
Linux kernel - Deliverables
This page took 0.622534 seconds and 5 git commands to generate.