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powerpc: Add helper functions set the DAWR and CIABR using set_mode
[deliverable/linux.git] / arch / powerpc / include / asm / cputable.h
CommitLineData
10b35d99
KG		 1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
d1cdcf22
AB		 4
5#include <asm/asm-compat.h>
c5157e58 6#include <asm/feature-fixups.h>
c3617f72 7#include <uapi/asm/cputable.h>
d1cdcf22 8
10b35d99
KG		 9#ifndef __ASSEMBLY__
10
11/* This structure can grow, it's real size is used by head.S code
12 * via the mkdefs mechanism.
13 */
14struct cpu_spec;
10b35d99 15
10b35d99 16typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
f39b7a55 17typedef void (*cpu_restore_t)(void);
10b35d99 18
32a33994 19enum powerpc_oprofile_type {
7a45fb19
AW		 20 PPC_OPROFILE_INVALID = 0,
21 PPC_OPROFILE_RS64 = 1,
22 PPC_OPROFILE_POWER4 = 2,
23 PPC_OPROFILE_G4 = 3,
39aef685 24 PPC_OPROFILE_FSL_EMB = 4,
18f2190d 25 PPC_OPROFILE_CELL = 5,
25fc530e 26 PPC_OPROFILE_PA6T = 6,
32a33994
AB		 27};
28
1bd2e5ae
OJ		 29enum powerpc_pmc_type {
30 PPC_PMC_DEFAULT = 0,
31 PPC_PMC_IBM = 1,
32 PPC_PMC_PA6T = 2,
b950bdd0 33 PPC_PMC_G4 = 3,
1bd2e5ae
OJ		 34};
35
47c0bd1a
BH		 36struct pt_regs;
37
38extern int machine_check_generic(struct pt_regs *regs);
39extern int machine_check_4xx(struct pt_regs *regs);
40extern int machine_check_440A(struct pt_regs *regs);
fe04b112 41extern int machine_check_e500mc(struct pt_regs *regs);
47c0bd1a
BH		 42extern int machine_check_e500(struct pt_regs *regs);
43extern int machine_check_e200(struct pt_regs *regs);
fc5e7097 44extern int machine_check_47x(struct pt_regs *regs);
47c0bd1a 45
87a72f9e 46/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
10b35d99
KG		 47struct cpu_spec {
48 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
49 unsigned int pvr_mask;
50 unsigned int pvr_value;
51
52 char *cpu_name;
53 unsigned long cpu_features; /* Kernel features */
54 unsigned int cpu_user_features; /* Userland features */
7c03d653 55 unsigned int mmu_features; /* MMU features */
10b35d99
KG		 56
57 /* cache line sizes */
58 unsigned int icache_bsize;
59 unsigned int dcache_bsize;
60
61 /* number of performance monitor counters */
62 unsigned int num_pmcs;
1bd2e5ae 63 enum powerpc_pmc_type pmc_type;
10b35d99
KG		 64
65 /* this is called to initialize various CPU bits like L1 cache,
66 * BHT, SPD, etc... from head.S before branching to identify_machine
67 */
68 cpu_setup_t cpu_setup;
f39b7a55
OJ		 69 /* Used to restore cpu setup on secondary processors and at resume */
70 cpu_restore_t cpu_restore;
10b35d99
KG		 71
72 /* Used by oprofile userspace to select the right counters */
73 char *oprofile_cpu_type;
74
75 /* Processor specific oprofile operations */
32a33994 76 enum powerpc_oprofile_type oprofile_type;
80f15dc7 77
e78dbc80
MN		 78 /* Bit locations inside the mmcra change */
79 unsigned long oprofile_mmcra_sihv;
80 unsigned long oprofile_mmcra_sipr;
81
82 /* Bits to clear during an oprofile exception */
83 unsigned long oprofile_mmcra_clear;
84
80f15dc7
PM		 85 /* Name of processor class, for the ELF AT_PLATFORM entry */
86 char *platform;
47c0bd1a
BH		 87
88 /* Processor specific machine check handling. Return negative
89 * if the error is fatal, 1 if it was fully recovered and 0 to
90 * pass up (not CPU originated) */
91 int (*machine_check)(struct pt_regs *regs);
10b35d99
KG		 92};
93
10b35d99 94extern struct cpu_spec *cur_cpu_spec;
10b35d99 95
42c4aaad
BH		 96extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
97
974a76f5 98extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
0909c8c2
BH		 99extern void do_feature_fixups(unsigned long value, void *fixup_start,
100 void *fixup_end);
9b6b563c 101
9115d134
NL		 102extern const char *powerpc_base_platform;
103
10b35d99
KG		 104#endif /* __ASSEMBLY__ */
105
106/* CPU kernel features */
107
108/* Retain the 32b definitions all use bottom half of word */
cde4d494
MN		 109#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
110#define CPU_FTR_L2CR ASM_CONST(0x00000002)
111#define CPU_FTR_SPEC7450 ASM_CONST(0x00000004)
112#define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
113#define CPU_FTR_TAU ASM_CONST(0x00000010)
114#define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
115#define CPU_FTR_USE_TB ASM_CONST(0x00000040)
116#define CPU_FTR_L2CSR ASM_CONST(0x00000080)
117#define CPU_FTR_601 ASM_CONST(0x00000100)
118#define CPU_FTR_DBELL ASM_CONST(0x00000200)
119#define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
120#define CPU_FTR_L3CR ASM_CONST(0x00000800)
121#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000)
122#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000)
123#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000)
124#define CPU_FTR_NO_DPM ASM_CONST(0x00008000)
125#define CPU_FTR_476_DD2 ASM_CONST(0x00010000)
126#define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000)
127#define CPU_FTR_NO_BTIC ASM_CONST(0x00040000)
128#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000)
129#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000)
130#define CPU_FTR_PPC_LE ASM_CONST(0x00200000)
131#define CPU_FTR_REAL_LE ASM_CONST(0x00400000)
132#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000)
133#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000)
134#define CPU_FTR_SPE ASM_CONST(0x02000000)
135#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000)
136#define CPU_FTR_LWSYNC ASM_CONST(0x08000000)
137#define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000)
138#define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000)
139#define CPU_FTR_EMB_HV ASM_CONST(0x40000000)
10b35d99 140
3965f8c5
PM		 141/*
142 * Add the 64-bit processor unique features in the top half of the word;
143 * on 32-bit, make the names available but defined to be 0.
144 */
10b35d99 145#ifdef __powerpc64__
3965f8c5 146#define LONG_ASM_CONST(x) ASM_CONST(x)
10b35d99 147#else
3965f8c5 148#define LONG_ASM_CONST(x) 0
10b35d99
KG		 149#endif
150
1580b3b8
MN		 151#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000)
152#define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000)
153#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000)
154#define CPU_FTR_CFAR LONG_ASM_CONST(0x0000000800000000)
155#define CPU_FTR_IABR LONG_ASM_CONST(0x0000001000000000)
156#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000)
157#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000)
158#define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000)
159#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000)
160#define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000)
161#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000)
162#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000)
163#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000)
164#define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000)
165#define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000)
166#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000)
167#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000)
168#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000)
169#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000)
170#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000)
171#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000)
172#define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000)
173#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000)
174#define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000)
175#define CPU_FTR_BCTAR LONG_ASM_CONST(0x0100000000000000)
176#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
3965f8c5 177
10b35d99
KG		 178#ifndef __ASSEMBLY__
179
44ae3ab3
ME		 180#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
181
182#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
183 MMU_FTR_16M_PAGE)
10b35d99
KG		 184
185/* We only set the altivec features if the kernel was compiled with altivec
186 * support
187 */
188#ifdef CONFIG_ALTIVEC
189#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
190#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
191#else
192#define CPU_FTR_ALTIVEC_COMP 0
193#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
194#endif
195
b962ce9d
MN		 196/* We only set the VSX features if the kernel was compiled with VSX
197 * support
198 */
199#ifdef CONFIG_VSX
200#define CPU_FTR_VSX_COMP CPU_FTR_VSX
201#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
202#else
203#define CPU_FTR_VSX_COMP 0
204#define PPC_FEATURE_HAS_VSX_COMP 0
205#endif
206
5e14d21e
KG		 207/* We only set the spe features if the kernel was compiled with spe
208 * support
209 */
210#ifdef CONFIG_SPE
211#define CPU_FTR_SPE_COMP CPU_FTR_SPE
212#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
213#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
214#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
215#else
216#define CPU_FTR_SPE_COMP 0
217#define PPC_FEATURE_HAS_SPE_COMP 0
218#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
219#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
220#endif
221
11af1192
SW		 222/* We need to mark all pages as being coherent if we're SMP or we have a
223 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
224 * require it for PCI "streaming/prefetch" to work properly.
c9310920 225 * This is also required by 52xx family.
10b35d99 226 */
1775dbbc 227#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
c9310920
PZ		 228 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
229 || defined(CONFIG_PPC_MPC52xx)
10b35d99
KG		 230#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
231#else
232#define CPU_FTR_COMMON 0
233#endif
234
235/* The powersave features NAP & DOZE seems to confuse BDI when
236 debugging. So if a BDI is used, disable theses
237 */
238#ifndef CONFIG_BDI_SWITCH
239#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
240#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
241#else
242#define CPU_FTR_MAYBE_CAN_DOZE 0
243#define CPU_FTR_MAYBE_CAN_NAP 0
244#endif
245
246#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
247 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
248 !defined(CONFIG_BOOKE))
249
7c03d653 250#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
4508dc21
DG		 251 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
252#define CPU_FTRS_603 (CPU_FTR_COMMON | \
7c92943c 253 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
fab5db97 254 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 255#define CPU_FTRS_604 (CPU_FTR_COMMON | \
7c03d653 256 CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
4508dc21 257#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
7c92943c 258 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 259 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 260#define CPU_FTRS_740 (CPU_FTR_COMMON | \
7c92943c 261 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 262 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 263 CPU_FTR_PPC_LE)
4508dc21 264#define CPU_FTRS_750 (CPU_FTR_COMMON | \
7c92943c 265 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 266 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 267 CPU_FTR_PPC_LE)
7c03d653 268#define CPU_FTRS_750CL (CPU_FTRS_750)
b6f41cc8
JB		 269#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
270#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
7c03d653 271#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
b6f41cc8 272#define CPU_FTRS_750GX (CPU_FTRS_750FX)
4508dc21 273#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
7c92943c 274 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 275 CPU_FTR_ALTIVEC_COMP | \
fab5db97 276 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 277#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
7c92943c 278 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 279 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
fab5db97 280 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 281#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
7c92943c 282 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 283 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
b64f87c1 284 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 285#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
7c92943c
SR		 286 CPU_FTR_USE_TB | \
287 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 288 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 289 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
b64f87c1 290 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 291#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
b64f87c1 292 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 293 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 294 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
fab5db97 295 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 296#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
b64f87c1 297 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 298 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
7c03d653 299 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 300#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
b64f87c1 301 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 302 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 303 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 304 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
7c03d653 305 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 306#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
7c92943c
SR		 307 CPU_FTR_USE_TB | \
308 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 309 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 310 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 311#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
7c92943c
SR		 312 CPU_FTR_USE_TB | \
313 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 314 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1
BB		 315 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
316 CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 317#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
7c92943c
SR		 318 CPU_FTR_USE_TB | \
319 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 320 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 321 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 322#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
7c92943c
SR		 323 CPU_FTR_USE_TB | \
324 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 325 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 326 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 327#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
3d372548
JY		 328 CPU_FTR_USE_TB | \
329 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 330 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 331 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 332#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
7c92943c 333 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
11af1192 334#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 335 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
4508dc21 336#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 337 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
7c92943c 338 CPU_FTR_COMMON)
4508dc21 339#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 340 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
aa42c69c 341 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
7c03d653 342#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
4508dc21 343#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
8309ce72
BH		 344#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
345#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
6d2170be
BH		 346#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
347 CPU_FTR_INDEXED_DCR)
e7f75ad0 348#define CPU_FTRS_47X (CPU_FTRS_440x6)
5e14d21e
KG		 349#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
350 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
52b066fa
SW		 351 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
352 CPU_FTR_DEBUG_LVL_EXC)
fc4033b2 353#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
8309ce72
BH		 354 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
355 CPU_FTR_NOEXECUTE)
fc4033b2 356#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
7c03d653 357 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
8309ce72 358 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
d51ad915 359#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
620165f9 360 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
73196cd3 361 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
11ed0db9
KG		 362#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
363 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
d36b4c4f 364 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
73196cd3 365 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
10241842
KG		 366#define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
367 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
368 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
9de6fe91 369 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
7c92943c 370#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
0b8e2e13
ME		 371
372/* 64-bit CPUs */
5a0e9b57 373#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
7c03d653 374 CPU_FTR_IABR | CPU_FTR_PPC_LE)
5a0e9b57 375#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
7c03d653 376 CPU_FTR_IABR | \
7c92943c 377 CPU_FTR_MMCRA | CPU_FTR_CTRL)
2d1b2027 378#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 379 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
f89451fb
AB		 380 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
381 CPU_FTR_STCX_CHECKS_ADDRESS)
2d1b2027 382#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
969391c5 383 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
2a929436 384 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
969391c5
PM		 385 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
386 CPU_FTR_HVMODE)
2d1b2027 387#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 388 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 389 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3
ME		 390 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
391 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
2d1b2027 392#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 393 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
03054d51 394 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 395 CPU_FTR_COHERENT_ICACHE | \
4c198557 396 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
f89451fb 397 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
48404f2e 398 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR)
2d1b2027 399#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
969391c5 400 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
e952e6c4 401 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 402 CPU_FTR_COHERENT_ICACHE | \
e952e6c4 403 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
f89451fb 404 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
851d2e2f 405 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d2613868
HM		 406 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
407 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR)
71e18497
MN		 408#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
409 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
410 CPU_FTR_MMCRA | CPU_FTR_SMT | \
411 CPU_FTR_COHERENT_ICACHE | \
412 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
413 CPU_FTR_DSCR | CPU_FTR_SAO | \
414 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
e5e84f0a 415 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
d2613868 416 CPU_FTR_DBELL | CPU_FTR_HAS_PPR)
2d1b2027 417#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 418 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 419 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 420 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
4ec577a2 421 CPU_FTR_UNALIGNED_LD_STD)
2d1b2027 422#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
44ae3ab3
ME		 423 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
424 CPU_FTR_PURR | CPU_FTR_REAL_LE)
7c03d653 425#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
10b35d99 426
76b4eda8 427#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
fac26ad4 428 CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
76b4eda8 429
2406f606 430#ifdef __powerpc64__
11ed0db9 431#ifdef CONFIG_PPC_BOOK3E
10241842 432#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500 | CPU_FTRS_A2)
11ed0db9 433#else
7c92943c
SR		 434#define CPU_FTRS_POSSIBLE \
435 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
03054d51 436 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
71e18497
MN		 437 CPU_FTRS_POWER7 | CPU_FTRS_POWER8 | CPU_FTRS_CELL | \
438 CPU_FTRS_PA6T | CPU_FTR_VSX)
11ed0db9 439#endif
2406f606 440#else
7c92943c
SR		 441enum {
442 CPU_FTRS_POSSIBLE =
10b35d99
KG		 443#if CLASSIC_PPC
444 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
445 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
446 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
447 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
448 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
449 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
450 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
aa42c69c
KP		 451 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
452 CPU_FTRS_CLASSIC32 |
10b35d99
KG		 453#else
454 CPU_FTRS_GENERIC_32 |
455#endif
10b35d99
KG		 456#ifdef CONFIG_8xx
457 CPU_FTRS_8XX |
458#endif
459#ifdef CONFIG_40x
460 CPU_FTRS_40X |
461#endif
462#ifdef CONFIG_44x
6d2170be 463 CPU_FTRS_44X | CPU_FTRS_440x6 |
10b35d99 464#endif
e7f75ad0 465#ifdef CONFIG_PPC_47x
c48d0dba 466 CPU_FTRS_47X | CPU_FTR_476_DD2 |
e7f75ad0 467#endif
10b35d99
KG		 468#ifdef CONFIG_E200
469 CPU_FTRS_E200 |
470#endif
471#ifdef CONFIG_E500
06aae867
SW		 472 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
473#endif
474#ifdef CONFIG_PPC_E500MC
475 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
10b35d99 476#endif
10b35d99 477 0,
7c92943c
SR		 478};
479#endif /* __powerpc64__ */
10b35d99 480
2406f606 481#ifdef __powerpc64__
11ed0db9 482#ifdef CONFIG_PPC_BOOK3E
10241842 483#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500 & CPU_FTRS_A2)
11ed0db9 484#else
7c92943c
SR		 485#define CPU_FTRS_ALWAYS \
486 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
03054d51 487 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
e952e6c4 488 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
11ed0db9 489#endif
2406f606 490#else
7c92943c
SR		 491enum {
492 CPU_FTRS_ALWAYS =
10b35d99
KG		 493#if CLASSIC_PPC
494 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
495 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
496 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
497 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
498 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
499 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
500 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
aa42c69c
KP		 501 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
502 CPU_FTRS_CLASSIC32 &
10b35d99
KG		 503#else
504 CPU_FTRS_GENERIC_32 &
505#endif
10b35d99
KG		 506#ifdef CONFIG_8xx
507 CPU_FTRS_8XX &
508#endif
509#ifdef CONFIG_40x
510 CPU_FTRS_40X &
511#endif
512#ifdef CONFIG_44x
6d2170be 513 CPU_FTRS_44X & CPU_FTRS_440x6 &
10b35d99
KG		 514#endif
515#ifdef CONFIG_E200
516 CPU_FTRS_E200 &
517#endif
518#ifdef CONFIG_E500
06aae867
SW		 519 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
520#endif
521#ifdef CONFIG_PPC_E500MC
522 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
10b35d99 523#endif
73196cd3 524 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
10b35d99
KG		 525 CPU_FTRS_POSSIBLE,
526};
7c92943c 527#endif /* __powerpc64__ */
10b35d99
KG		 528
529static inline int cpu_has_feature(unsigned long feature)
530{
531 return (CPU_FTRS_ALWAYS & feature) ||
532 (CPU_FTRS_POSSIBLE
10b35d99 533 & cur_cpu_spec->cpu_features
10b35d99
KG		 534 & feature);
535}
536
5aae8a53 537#define HBP_NUM 1
5aae8a53 538
10b35d99
KG		 539#endif /* !__ASSEMBLY__ */
540
10b35d99 541#endif /* __ASM_POWERPC_CPUTABLE_H */
Linux kernel - Deliverables
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