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10b35d99 KG |
1 | #ifndef __ASM_POWERPC_CPUTABLE_H |
2 | #define __ASM_POWERPC_CPUTABLE_H | |
3 | ||
d1cdcf22 AB |
4 | |
5 | #include <asm/asm-compat.h> | |
c5157e58 | 6 | #include <asm/feature-fixups.h> |
c3617f72 | 7 | #include <uapi/asm/cputable.h> |
d1cdcf22 | 8 | |
10b35d99 KG |
9 | #ifndef __ASSEMBLY__ |
10 | ||
11 | /* This structure can grow, it's real size is used by head.S code | |
12 | * via the mkdefs mechanism. | |
13 | */ | |
14 | struct cpu_spec; | |
10b35d99 | 15 | |
10b35d99 | 16 | typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec); |
f39b7a55 | 17 | typedef void (*cpu_restore_t)(void); |
10b35d99 | 18 | |
32a33994 | 19 | enum powerpc_oprofile_type { |
7a45fb19 AW |
20 | PPC_OPROFILE_INVALID = 0, |
21 | PPC_OPROFILE_RS64 = 1, | |
22 | PPC_OPROFILE_POWER4 = 2, | |
23 | PPC_OPROFILE_G4 = 3, | |
39aef685 | 24 | PPC_OPROFILE_FSL_EMB = 4, |
18f2190d | 25 | PPC_OPROFILE_CELL = 5, |
25fc530e | 26 | PPC_OPROFILE_PA6T = 6, |
32a33994 AB |
27 | }; |
28 | ||
1bd2e5ae OJ |
29 | enum powerpc_pmc_type { |
30 | PPC_PMC_DEFAULT = 0, | |
31 | PPC_PMC_IBM = 1, | |
32 | PPC_PMC_PA6T = 2, | |
b950bdd0 | 33 | PPC_PMC_G4 = 3, |
1bd2e5ae OJ |
34 | }; |
35 | ||
47c0bd1a BH |
36 | struct pt_regs; |
37 | ||
38 | extern int machine_check_generic(struct pt_regs *regs); | |
39 | extern int machine_check_4xx(struct pt_regs *regs); | |
40 | extern int machine_check_440A(struct pt_regs *regs); | |
fe04b112 | 41 | extern int machine_check_e500mc(struct pt_regs *regs); |
47c0bd1a BH |
42 | extern int machine_check_e500(struct pt_regs *regs); |
43 | extern int machine_check_e200(struct pt_regs *regs); | |
fc5e7097 | 44 | extern int machine_check_47x(struct pt_regs *regs); |
47c0bd1a | 45 | |
87a72f9e | 46 | /* NOTE WELL: Update identify_cpu() if fields are added or removed! */ |
10b35d99 KG |
47 | struct cpu_spec { |
48 | /* CPU is matched via (PVR & pvr_mask) == pvr_value */ | |
49 | unsigned int pvr_mask; | |
50 | unsigned int pvr_value; | |
51 | ||
52 | char *cpu_name; | |
53 | unsigned long cpu_features; /* Kernel features */ | |
54 | unsigned int cpu_user_features; /* Userland features */ | |
2171364d | 55 | unsigned int cpu_user_features2; /* Userland features v2 */ |
7c03d653 | 56 | unsigned int mmu_features; /* MMU features */ |
10b35d99 KG |
57 | |
58 | /* cache line sizes */ | |
59 | unsigned int icache_bsize; | |
60 | unsigned int dcache_bsize; | |
61 | ||
62 | /* number of performance monitor counters */ | |
63 | unsigned int num_pmcs; | |
1bd2e5ae | 64 | enum powerpc_pmc_type pmc_type; |
10b35d99 KG |
65 | |
66 | /* this is called to initialize various CPU bits like L1 cache, | |
67 | * BHT, SPD, etc... from head.S before branching to identify_machine | |
68 | */ | |
69 | cpu_setup_t cpu_setup; | |
f39b7a55 OJ |
70 | /* Used to restore cpu setup on secondary processors and at resume */ |
71 | cpu_restore_t cpu_restore; | |
10b35d99 KG |
72 | |
73 | /* Used by oprofile userspace to select the right counters */ | |
74 | char *oprofile_cpu_type; | |
75 | ||
76 | /* Processor specific oprofile operations */ | |
32a33994 | 77 | enum powerpc_oprofile_type oprofile_type; |
80f15dc7 | 78 | |
e78dbc80 MN |
79 | /* Bit locations inside the mmcra change */ |
80 | unsigned long oprofile_mmcra_sihv; | |
81 | unsigned long oprofile_mmcra_sipr; | |
82 | ||
83 | /* Bits to clear during an oprofile exception */ | |
84 | unsigned long oprofile_mmcra_clear; | |
85 | ||
80f15dc7 PM |
86 | /* Name of processor class, for the ELF AT_PLATFORM entry */ |
87 | char *platform; | |
47c0bd1a BH |
88 | |
89 | /* Processor specific machine check handling. Return negative | |
90 | * if the error is fatal, 1 if it was fully recovered and 0 to | |
91 | * pass up (not CPU originated) */ | |
92 | int (*machine_check)(struct pt_regs *regs); | |
10b35d99 KG |
93 | }; |
94 | ||
10b35d99 | 95 | extern struct cpu_spec *cur_cpu_spec; |
10b35d99 | 96 | |
42c4aaad BH |
97 | extern unsigned int __start___ftr_fixup, __stop___ftr_fixup; |
98 | ||
974a76f5 | 99 | extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr); |
0909c8c2 BH |
100 | extern void do_feature_fixups(unsigned long value, void *fixup_start, |
101 | void *fixup_end); | |
9b6b563c | 102 | |
9115d134 NL |
103 | extern const char *powerpc_base_platform; |
104 | ||
10b35d99 KG |
105 | #endif /* __ASSEMBLY__ */ |
106 | ||
107 | /* CPU kernel features */ | |
108 | ||
109 | /* Retain the 32b definitions all use bottom half of word */ | |
cde4d494 MN |
110 | #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001) |
111 | #define CPU_FTR_L2CR ASM_CONST(0x00000002) | |
112 | #define CPU_FTR_SPEC7450 ASM_CONST(0x00000004) | |
113 | #define CPU_FTR_ALTIVEC ASM_CONST(0x00000008) | |
114 | #define CPU_FTR_TAU ASM_CONST(0x00000010) | |
115 | #define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020) | |
116 | #define CPU_FTR_USE_TB ASM_CONST(0x00000040) | |
117 | #define CPU_FTR_L2CSR ASM_CONST(0x00000080) | |
118 | #define CPU_FTR_601 ASM_CONST(0x00000100) | |
119 | #define CPU_FTR_DBELL ASM_CONST(0x00000200) | |
120 | #define CPU_FTR_CAN_NAP ASM_CONST(0x00000400) | |
121 | #define CPU_FTR_L3CR ASM_CONST(0x00000800) | |
122 | #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000) | |
123 | #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000) | |
124 | #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000) | |
125 | #define CPU_FTR_NO_DPM ASM_CONST(0x00008000) | |
126 | #define CPU_FTR_476_DD2 ASM_CONST(0x00010000) | |
127 | #define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000) | |
128 | #define CPU_FTR_NO_BTIC ASM_CONST(0x00040000) | |
129 | #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000) | |
130 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000) | |
131 | #define CPU_FTR_PPC_LE ASM_CONST(0x00200000) | |
132 | #define CPU_FTR_REAL_LE ASM_CONST(0x00400000) | |
133 | #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000) | |
134 | #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000) | |
135 | #define CPU_FTR_SPE ASM_CONST(0x02000000) | |
136 | #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000) | |
137 | #define CPU_FTR_LWSYNC ASM_CONST(0x08000000) | |
138 | #define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000) | |
139 | #define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000) | |
140 | #define CPU_FTR_EMB_HV ASM_CONST(0x40000000) | |
10b35d99 | 141 | |
3965f8c5 PM |
142 | /* |
143 | * Add the 64-bit processor unique features in the top half of the word; | |
144 | * on 32-bit, make the names available but defined to be 0. | |
145 | */ | |
10b35d99 | 146 | #ifdef __powerpc64__ |
3965f8c5 | 147 | #define LONG_ASM_CONST(x) ASM_CONST(x) |
10b35d99 | 148 | #else |
3965f8c5 | 149 | #define LONG_ASM_CONST(x) 0 |
10b35d99 KG |
150 | #endif |
151 | ||
1580b3b8 MN |
152 | #define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000) |
153 | #define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000) | |
154 | #define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000) | |
1de2bd4e | 155 | #define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000800000000) |
1580b3b8 MN |
156 | #define CPU_FTR_IABR LONG_ASM_CONST(0x0000001000000000) |
157 | #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000) | |
158 | #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000) | |
159 | #define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000) | |
160 | #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000) | |
161 | #define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000) | |
162 | #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000) | |
163 | #define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000) | |
164 | #define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000) | |
165 | #define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000) | |
166 | #define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000) | |
167 | #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000) | |
168 | #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000) | |
169 | #define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000) | |
170 | #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000) | |
171 | #define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000) | |
172 | #define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000) | |
173 | #define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000) | |
174 | #define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000) | |
175 | #define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000) | |
1de2bd4e | 176 | #define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000) |
1580b3b8 | 177 | #define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000) |
79879c17 | 178 | #define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000) |
82a9f16a | 179 | #define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000) |
3965f8c5 | 180 | |
10b35d99 KG |
181 | #ifndef __ASSEMBLY__ |
182 | ||
44ae3ab3 ME |
183 | #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN) |
184 | ||
185 | #define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB | MMU_FTR_TLBIEL | \ | |
186 | MMU_FTR_16M_PAGE) | |
10b35d99 KG |
187 | |
188 | /* We only set the altivec features if the kernel was compiled with altivec | |
189 | * support | |
190 | */ | |
191 | #ifdef CONFIG_ALTIVEC | |
192 | #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC | |
193 | #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC | |
194 | #else | |
195 | #define CPU_FTR_ALTIVEC_COMP 0 | |
196 | #define PPC_FEATURE_HAS_ALTIVEC_COMP 0 | |
197 | #endif | |
198 | ||
b962ce9d MN |
199 | /* We only set the VSX features if the kernel was compiled with VSX |
200 | * support | |
201 | */ | |
202 | #ifdef CONFIG_VSX | |
203 | #define CPU_FTR_VSX_COMP CPU_FTR_VSX | |
204 | #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX | |
205 | #else | |
206 | #define CPU_FTR_VSX_COMP 0 | |
207 | #define PPC_FEATURE_HAS_VSX_COMP 0 | |
208 | #endif | |
209 | ||
5e14d21e KG |
210 | /* We only set the spe features if the kernel was compiled with spe |
211 | * support | |
212 | */ | |
213 | #ifdef CONFIG_SPE | |
214 | #define CPU_FTR_SPE_COMP CPU_FTR_SPE | |
215 | #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE | |
216 | #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE | |
217 | #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE | |
218 | #else | |
219 | #define CPU_FTR_SPE_COMP 0 | |
220 | #define PPC_FEATURE_HAS_SPE_COMP 0 | |
221 | #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0 | |
222 | #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0 | |
223 | #endif | |
224 | ||
6a6d541f MN |
225 | /* We only set the TM feature if the kernel was compiled with TM supprt */ |
226 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
227 | #define CPU_FTR_TM_COMP CPU_FTR_TM | |
cbbc6f1b | 228 | #define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM |
6a6d541f MN |
229 | #else |
230 | #define CPU_FTR_TM_COMP 0 | |
cbbc6f1b | 231 | #define PPC_FEATURE2_HTM_COMP 0 |
6a6d541f MN |
232 | #endif |
233 | ||
11af1192 SW |
234 | /* We need to mark all pages as being coherent if we're SMP or we have a |
235 | * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II | |
236 | * require it for PCI "streaming/prefetch" to work properly. | |
c9310920 | 237 | * This is also required by 52xx family. |
10b35d99 | 238 | */ |
1775dbbc | 239 | #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ |
c9310920 PZ |
240 | || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \ |
241 | || defined(CONFIG_PPC_MPC52xx) | |
10b35d99 KG |
242 | #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT |
243 | #else | |
244 | #define CPU_FTR_COMMON 0 | |
245 | #endif | |
246 | ||
247 | /* The powersave features NAP & DOZE seems to confuse BDI when | |
248 | debugging. So if a BDI is used, disable theses | |
249 | */ | |
250 | #ifndef CONFIG_BDI_SWITCH | |
251 | #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE | |
252 | #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP | |
253 | #else | |
254 | #define CPU_FTR_MAYBE_CAN_DOZE 0 | |
255 | #define CPU_FTR_MAYBE_CAN_NAP 0 | |
256 | #endif | |
257 | ||
258 | #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \ | |
259 | !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \ | |
260 | !defined(CONFIG_BOOKE)) | |
261 | ||
7c03d653 | 262 | #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \ |
4508dc21 DG |
263 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE) |
264 | #define CPU_FTRS_603 (CPU_FTR_COMMON | \ | |
7c92943c | 265 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ |
fab5db97 | 266 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
4508dc21 | 267 | #define CPU_FTRS_604 (CPU_FTR_COMMON | \ |
7c03d653 | 268 | CPU_FTR_USE_TB | CPU_FTR_PPC_LE) |
4508dc21 | 269 | #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \ |
7c92943c | 270 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
7c03d653 | 271 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
4508dc21 | 272 | #define CPU_FTRS_740 (CPU_FTR_COMMON | \ |
7c92943c | 273 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
7c03d653 | 274 | CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ |
fab5db97 | 275 | CPU_FTR_PPC_LE) |
4508dc21 | 276 | #define CPU_FTRS_750 (CPU_FTR_COMMON | \ |
7c92943c | 277 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
7c03d653 | 278 | CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ |
fab5db97 | 279 | CPU_FTR_PPC_LE) |
7c03d653 | 280 | #define CPU_FTRS_750CL (CPU_FTRS_750) |
b6f41cc8 JB |
281 | #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) |
282 | #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM) | |
7c03d653 | 283 | #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX) |
b6f41cc8 | 284 | #define CPU_FTRS_750GX (CPU_FTRS_750FX) |
4508dc21 | 285 | #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \ |
7c92943c | 286 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
7c03d653 | 287 | CPU_FTR_ALTIVEC_COMP | \ |
fab5db97 | 288 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
4508dc21 | 289 | #define CPU_FTRS_7400 (CPU_FTR_COMMON | \ |
7c92943c | 290 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
7c03d653 | 291 | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \ |
fab5db97 | 292 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
4508dc21 | 293 | #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ |
7c92943c | 294 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
7c03d653 | 295 | CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ |
b64f87c1 | 296 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
4508dc21 | 297 | #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ |
7c92943c SR |
298 | CPU_FTR_USE_TB | \ |
299 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | |
7c03d653 | 300 | CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ |
7c92943c | 301 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ |
b64f87c1 | 302 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
4508dc21 | 303 | #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ |
b64f87c1 | 304 | CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ |
7c92943c | 305 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
7c03d653 | 306 | CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ |
fab5db97 | 307 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
4508dc21 | 308 | #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ |
b64f87c1 | 309 | CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ |
7c92943c | 310 | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ |
7c03d653 | 311 | CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
4508dc21 | 312 | #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ |
b64f87c1 | 313 | CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ |
7c92943c | 314 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
7c03d653 | 315 | CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ |
7c92943c | 316 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ |
7c03d653 | 317 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
4508dc21 | 318 | #define CPU_FTRS_7455 (CPU_FTR_COMMON | \ |
7c92943c SR |
319 | CPU_FTR_USE_TB | \ |
320 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | |
7c03d653 | 321 | CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ |
b64f87c1 | 322 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
4508dc21 | 323 | #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ |
7c92943c SR |
324 | CPU_FTR_USE_TB | \ |
325 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | |
7c03d653 | 326 | CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ |
b64f87c1 BB |
327 | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \ |
328 | CPU_FTR_NEED_PAIRED_STWCX) | |
4508dc21 | 329 | #define CPU_FTRS_7447 (CPU_FTR_COMMON | \ |
7c92943c SR |
330 | CPU_FTR_USE_TB | \ |
331 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | |
7c03d653 | 332 | CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ |
b64f87c1 | 333 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
4508dc21 | 334 | #define CPU_FTRS_7447A (CPU_FTR_COMMON | \ |
7c92943c SR |
335 | CPU_FTR_USE_TB | \ |
336 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | |
7c03d653 | 337 | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ |
b64f87c1 | 338 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
4508dc21 | 339 | #define CPU_FTRS_7448 (CPU_FTR_COMMON | \ |
3d372548 JY |
340 | CPU_FTR_USE_TB | \ |
341 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | |
7c03d653 | 342 | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ |
b64f87c1 | 343 | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
4508dc21 | 344 | #define CPU_FTRS_82XX (CPU_FTR_COMMON | \ |
7c92943c | 345 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) |
11af1192 | 346 | #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ |
7c03d653 | 347 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP) |
4508dc21 | 348 | #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ |
7c03d653 | 349 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ |
7c92943c | 350 | CPU_FTR_COMMON) |
4508dc21 | 351 | #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \ |
7c03d653 | 352 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ |
aa42c69c | 353 | CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE) |
7c03d653 | 354 | #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB) |
4508dc21 | 355 | #define CPU_FTRS_8XX (CPU_FTR_USE_TB) |
8309ce72 BH |
356 | #define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) |
357 | #define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) | |
6d2170be BH |
358 | #define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \ |
359 | CPU_FTR_INDEXED_DCR) | |
e7f75ad0 | 360 | #define CPU_FTRS_47X (CPU_FTRS_440x6) |
5e14d21e KG |
361 | #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ |
362 | CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \ | |
52b066fa SW |
363 | CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \ |
364 | CPU_FTR_DEBUG_LVL_EXC) | |
fc4033b2 | 365 | #define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ |
8309ce72 BH |
366 | CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \ |
367 | CPU_FTR_NOEXECUTE) | |
fc4033b2 | 368 | #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ |
7c03d653 | 369 | CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \ |
8309ce72 | 370 | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) |
d51ad915 | 371 | #define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ |
620165f9 | 372 | CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ |
73196cd3 | 373 | CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV) |
11ed0db9 KG |
374 | #define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ |
375 | CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ | |
d36b4c4f | 376 | CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ |
73196cd3 | 377 | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV) |
10241842 KG |
378 | #define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ |
379 | CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ | |
380 | CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ | |
cd66cc2e | 381 | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP) |
7c92943c | 382 | #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) |
0b8e2e13 ME |
383 | |
384 | /* 64-bit CPUs */ | |
5a0e9b57 | 385 | #define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \ |
7c03d653 | 386 | CPU_FTR_IABR | CPU_FTR_PPC_LE) |
5a0e9b57 | 387 | #define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \ |
7c03d653 | 388 | CPU_FTR_IABR | \ |
7c92943c | 389 | CPU_FTR_MMCRA | CPU_FTR_CTRL) |
2d1b2027 | 390 | #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
7c03d653 | 391 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
f89451fb AB |
392 | CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \ |
393 | CPU_FTR_STCX_CHECKS_ADDRESS) | |
2d1b2027 | 394 | #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
969391c5 | 395 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \ |
2a929436 | 396 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ |
969391c5 | 397 | CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \ |
82a9f16a | 398 | CPU_FTR_HVMODE | CPU_FTR_DABRX) |
2d1b2027 | 399 | #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
7c03d653 | 400 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
7c92943c | 401 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
44ae3ab3 | 402 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \ |
82a9f16a | 403 | CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX) |
2d1b2027 | 404 | #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
7c03d653 | 405 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
03054d51 | 406 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
44ae3ab3 | 407 | CPU_FTR_COHERENT_ICACHE | \ |
4c198557 | 408 | CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ |
f89451fb | 409 | CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \ |
82a9f16a MN |
410 | CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \ |
411 | CPU_FTR_DABRX) | |
2d1b2027 | 412 | #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
969391c5 | 413 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ |
e952e6c4 | 414 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
44ae3ab3 | 415 | CPU_FTR_COHERENT_ICACHE | \ |
e952e6c4 | 416 | CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ |
f89451fb | 417 | CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ |
851d2e2f | 418 | CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ |
d2613868 | 419 | CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \ |
82a9f16a | 420 | CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX) |
71e18497 MN |
421 | #define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
422 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ | |
423 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | |
424 | CPU_FTR_COHERENT_ICACHE | \ | |
425 | CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ | |
426 | CPU_FTR_DSCR | CPU_FTR_SAO | \ | |
427 | CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ | |
e5e84f0a | 428 | CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ |
1de2bd4e ME |
429 | CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \ |
430 | CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP) | |
2d1b2027 | 431 | #define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
7c03d653 | 432 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
7c92943c | 433 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
44ae3ab3 | 434 | CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ |
82a9f16a | 435 | CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX) |
2d1b2027 | 436 | #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
44ae3ab3 | 437 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \ |
82a9f16a | 438 | CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX) |
7c03d653 | 439 | #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) |
10b35d99 | 440 | |
76b4eda8 | 441 | #define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \ |
82a9f16a MN |
442 | CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | \ |
443 | CPU_FTR_ICSWX | CPU_FTR_DABRX ) | |
76b4eda8 | 444 | |
2406f606 | 445 | #ifdef __powerpc64__ |
11ed0db9 | 446 | #ifdef CONFIG_PPC_BOOK3E |
10241842 | 447 | #define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500 | CPU_FTRS_A2) |
11ed0db9 | 448 | #else |
7c92943c SR |
449 | #define CPU_FTRS_POSSIBLE \ |
450 | (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ | |
03054d51 | 451 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \ |
71e18497 MN |
452 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8 | CPU_FTRS_CELL | \ |
453 | CPU_FTRS_PA6T | CPU_FTR_VSX) | |
11ed0db9 | 454 | #endif |
2406f606 | 455 | #else |
7c92943c SR |
456 | enum { |
457 | CPU_FTRS_POSSIBLE = | |
10b35d99 KG |
458 | #if CLASSIC_PPC |
459 | CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU | | |
460 | CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 | | |
461 | CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX | | |
462 | CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 | | |
463 | CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 | | |
464 | CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 | | |
465 | CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX | | |
aa42c69c KP |
466 | CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 | |
467 | CPU_FTRS_CLASSIC32 | | |
10b35d99 KG |
468 | #else |
469 | CPU_FTRS_GENERIC_32 | | |
470 | #endif | |
10b35d99 KG |
471 | #ifdef CONFIG_8xx |
472 | CPU_FTRS_8XX | | |
473 | #endif | |
474 | #ifdef CONFIG_40x | |
475 | CPU_FTRS_40X | | |
476 | #endif | |
477 | #ifdef CONFIG_44x | |
6d2170be | 478 | CPU_FTRS_44X | CPU_FTRS_440x6 | |
10b35d99 | 479 | #endif |
e7f75ad0 | 480 | #ifdef CONFIG_PPC_47x |
c48d0dba | 481 | CPU_FTRS_47X | CPU_FTR_476_DD2 | |
e7f75ad0 | 482 | #endif |
10b35d99 KG |
483 | #ifdef CONFIG_E200 |
484 | CPU_FTRS_E200 | | |
485 | #endif | |
486 | #ifdef CONFIG_E500 | |
06aae867 SW |
487 | CPU_FTRS_E500 | CPU_FTRS_E500_2 | |
488 | #endif | |
489 | #ifdef CONFIG_PPC_E500MC | |
490 | CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 | | |
10b35d99 | 491 | #endif |
10b35d99 | 492 | 0, |
7c92943c SR |
493 | }; |
494 | #endif /* __powerpc64__ */ | |
10b35d99 | 495 | |
2406f606 | 496 | #ifdef __powerpc64__ |
11ed0db9 | 497 | #ifdef CONFIG_PPC_BOOK3E |
10241842 | 498 | #define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500 & CPU_FTRS_A2) |
11ed0db9 | 499 | #else |
7c92943c SR |
500 | #define CPU_FTRS_ALWAYS \ |
501 | (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \ | |
03054d51 | 502 | CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \ |
e952e6c4 | 503 | CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE) |
11ed0db9 | 504 | #endif |
2406f606 | 505 | #else |
7c92943c SR |
506 | enum { |
507 | CPU_FTRS_ALWAYS = | |
10b35d99 KG |
508 | #if CLASSIC_PPC |
509 | CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU & | |
510 | CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 & | |
511 | CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX & | |
512 | CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 & | |
513 | CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 & | |
514 | CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 & | |
515 | CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX & | |
aa42c69c KP |
516 | CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 & |
517 | CPU_FTRS_CLASSIC32 & | |
10b35d99 KG |
518 | #else |
519 | CPU_FTRS_GENERIC_32 & | |
520 | #endif | |
10b35d99 KG |
521 | #ifdef CONFIG_8xx |
522 | CPU_FTRS_8XX & | |
523 | #endif | |
524 | #ifdef CONFIG_40x | |
525 | CPU_FTRS_40X & | |
526 | #endif | |
527 | #ifdef CONFIG_44x | |
6d2170be | 528 | CPU_FTRS_44X & CPU_FTRS_440x6 & |
10b35d99 KG |
529 | #endif |
530 | #ifdef CONFIG_E200 | |
531 | CPU_FTRS_E200 & | |
532 | #endif | |
533 | #ifdef CONFIG_E500 | |
06aae867 SW |
534 | CPU_FTRS_E500 & CPU_FTRS_E500_2 & |
535 | #endif | |
536 | #ifdef CONFIG_PPC_E500MC | |
537 | CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 & | |
10b35d99 | 538 | #endif |
73196cd3 | 539 | ~CPU_FTR_EMB_HV & /* can be removed at runtime */ |
10b35d99 KG |
540 | CPU_FTRS_POSSIBLE, |
541 | }; | |
7c92943c | 542 | #endif /* __powerpc64__ */ |
10b35d99 KG |
543 | |
544 | static inline int cpu_has_feature(unsigned long feature) | |
545 | { | |
546 | return (CPU_FTRS_ALWAYS & feature) || | |
547 | (CPU_FTRS_POSSIBLE | |
10b35d99 | 548 | & cur_cpu_spec->cpu_features |
10b35d99 KG |
549 | & feature); |
550 | } | |
551 | ||
5aae8a53 | 552 | #define HBP_NUM 1 |
5aae8a53 | 553 | |
10b35d99 KG |
554 | #endif /* !__ASSEMBLY__ */ |
555 | ||
10b35d99 | 556 | #endif /* __ASM_POWERPC_CPUTABLE_H */ |