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1da177e4 LT |
1 | /* |
2 | * lppaca.h | |
3 | * Copyright (C) 2001 Mike Corrigan IBM Corporation | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
8882a4da DG |
19 | #ifndef _ASM_POWERPC_LPPACA_H |
20 | #define _ASM_POWERPC_LPPACA_H | |
88ced031 | 21 | #ifdef __KERNEL__ |
1da177e4 | 22 | |
94491685 BH |
23 | /* These definitions relate to hypervisors that only exist when using |
24 | * a server type processor | |
25 | */ | |
26 | #ifdef CONFIG_PPC_BOOK3S | |
27 | ||
1da177e4 LT |
28 | //============================================================================= |
29 | // | |
30 | // This control block contains the data that is shared between the | |
448054a6 | 31 | // hypervisor and the OS. |
1da177e4 LT |
32 | // |
33 | // | |
34 | //---------------------------------------------------------------------------- | |
2f6093c8 | 35 | #include <linux/cache.h> |
f2f6dad6 | 36 | #include <linux/threads.h> |
1da177e4 | 37 | #include <asm/types.h> |
2f6093c8 | 38 | #include <asm/mmu.h> |
1da177e4 | 39 | |
f2f6dad6 BH |
40 | /* |
41 | * We only have to have statically allocated lppaca structs on | |
42 | * legacy iSeries, which supports at most 64 cpus. | |
43 | */ | |
f2f6dad6 | 44 | #define NR_LPPACAS 1 |
f2f6dad6 BH |
45 | |
46 | ||
3356bb9f DG |
47 | /* The Hypervisor barfs if the lppaca crosses a page boundary. A 1k |
48 | * alignment is sufficient to prevent this */ | |
c6b3feaf | 49 | struct lppaca { |
1da177e4 LT |
50 | //============================================================================= |
51 | // CACHE_LINE_1 0x0000 - 0x007F Contains read-only data | |
1da177e4 LT |
52 | //============================================================================= |
53 | u32 desc; // Eye catcher 0xD397D781 x00-x03 | |
54 | u16 size; // Size of this struct x04-x05 | |
55 | u16 reserved1; // Reserved x06-x07 | |
56 | u16 reserved2:14; // Reserved x08-x09 | |
57 | u8 shared_proc:1; // Shared processor indicator ... | |
58 | u8 secondary_thread:1; // Secondary thread indicator ... | |
448054a6 | 59 | u8 reserved3[14]; // x0A-x17 |
1da177e4 LT |
60 | volatile u32 dyn_hw_node_id; // Dynamic Hardware Node id x18-x1B |
61 | volatile u32 dyn_hw_proc_id; // Dynamic Hardware Proc Id x1C-x1F | |
448054a6 | 62 | u8 reserved4[56]; // Reserved x20-x57 |
9eff1a38 JL |
63 | volatile u8 vphn_assoc_counts[8]; // Virtual processor home node |
64 | // associativity change counters x58-x5F | |
448054a6 | 65 | u8 reserved5[32]; // Reserved x60-x7F |
1da177e4 LT |
66 | |
67 | //============================================================================= | |
68 | // CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data | |
69 | //============================================================================= | |
1da177e4 | 70 | |
448054a6 | 71 | u8 reserved6[48]; // x00-x2f |
cf8a056a | 72 | u8 cede_latency_hint; /* x30 */ |
448054a6 | 73 | u8 reserved7[7]; /* x31-x37 */ |
098e8957 | 74 | u8 dtl_enable_mask; // Dispatch Trace Log mask x38-x38 |
d8c391a5 | 75 | u8 donate_dedicated_cpu; // Donate dedicated CPU cycles x39-x39 |
1da177e4 LT |
76 | u8 fpregs_in_use; // FP regs in use x3A-x3A |
77 | u8 pmcregs_in_use; // PMC regs in use x3B-x3B | |
448054a6 | 78 | u8 reserved8[28]; // x3C-x57 |
1da177e4 | 79 | u64 wait_state_cycles; // Wait cycles for this proc x58-x5F |
448054a6 | 80 | u8 reserved9[28]; // x60-x7B |
1da177e4 LT |
81 | u16 slb_count; // # of SLBs to maintain x7C-x7D |
82 | u8 idle; // Indicate OS is idle x7E | |
233ccd0d | 83 | u8 vmxregs_in_use; // VMX registers in use x7F |
1da177e4 | 84 | |
1da177e4 | 85 | //============================================================================= |
5cf13911 | 86 | // CACHE_LINE_3 0x0100 - 0x017F: This line is shared with other processors |
1da177e4 LT |
87 | //============================================================================= |
88 | // This is the yield_count. An "odd" value (low bit on) means that | |
89 | // the processor is yielded (either because of an OS yield or a PLIC | |
90 | // preempt). An even value implies that the processor is currently | |
91 | // executing. | |
92 | // NOTE: This value will ALWAYS be zero for dedicated processors and | |
93 | // will NEVER be zero for shared processors (ie, initialized to a 1). | |
94 | volatile u32 yield_count; // PLIC increments each dispatchx00-x03 | |
0559f0a7 | 95 | volatile u32 dispersion_count; // dispatch changed phys cpu x04-x07 |
ffa5abbd BK |
96 | volatile u64 cmo_faults; // CMO page fault count x08-x0F |
97 | volatile u64 cmo_fault_time; // CMO page fault time x10-x17 | |
448054a6 | 98 | u8 reserved10[104]; // Reserved x18-x7F |
1da177e4 LT |
99 | |
100 | //============================================================================= | |
5cf13911 | 101 | // CACHE_LINE_4-5 0x0180 - 0x027F Contains PMC interrupt data |
1da177e4 | 102 | //============================================================================= |
40322783 | 103 | u32 page_ins; // CMO Hint - # page ins by OS x00-x03 |
448054a6 | 104 | u8 reserved11[148]; // Reserved x04-x97 |
098e8957 | 105 | volatile u64 dtl_idx; // Dispatch Trace Log head idx x98-x9F |
448054a6 | 106 | u8 reserved12[96]; // Reserved xA0-xFF |
c6b3feaf | 107 | } __attribute__((__aligned__(0x400))); |
1da177e4 | 108 | |
3356bb9f DG |
109 | extern struct lppaca lppaca[]; |
110 | ||
93c22703 | 111 | #define lppaca_of(cpu) (*paca[cpu].lppaca_ptr) |
8154c5d2 | 112 | |
2f6093c8 MN |
113 | /* |
114 | * SLB shadow buffer structure as defined in the PAPR. The save_area | |
115 | * contains adjacent ESID and VSID pairs for each shadowed SLB. The | |
116 | * ESID is stored in the lower 64bits, then the VSID. | |
117 | */ | |
118 | struct slb_shadow { | |
119 | u32 persistent; // Number of persistent SLBs x00-x03 | |
120 | u32 buffer_length; // Total shadow buffer length x04-x07 | |
121 | u64 reserved; // Alignment x08-x0f | |
122 | struct { | |
123 | u64 esid; | |
124 | u64 vsid; | |
125 | } save_area[SLB_NUM_BOLTED]; // x10-x40 | |
126 | } ____cacheline_aligned; | |
127 | ||
128 | extern struct slb_shadow slb_shadow[]; | |
129 | ||
cf9efce0 PM |
130 | /* |
131 | * Layout of entries in the hypervisor's dispatch trace log buffer. | |
132 | */ | |
133 | struct dtl_entry { | |
134 | u8 dispatch_reason; | |
135 | u8 preempt_reason; | |
136 | u16 processor_id; | |
137 | u32 enqueue_to_dispatch_time; | |
138 | u32 ready_to_enqueue_time; | |
139 | u32 waiting_to_ready_time; | |
140 | u64 timebase; | |
141 | u64 fault_addr; | |
142 | u64 srr0; | |
143 | u64 srr1; | |
144 | }; | |
145 | ||
146 | #define DISPATCH_LOG_BYTES 4096 /* bytes per cpu */ | |
147 | #define N_DISPATCH_LOG (DISPATCH_LOG_BYTES / sizeof(struct dtl_entry)) | |
148 | ||
af442a1b NA |
149 | extern struct kmem_cache *dtl_cache; |
150 | ||
872e439a PM |
151 | /* |
152 | * When CONFIG_VIRT_CPU_ACCOUNTING = y, the cpu accounting code controls | |
153 | * reading from the dispatch trace log. If other code wants to consume | |
154 | * DTL entries, it can set this pointer to a function that will get | |
155 | * called once for each DTL entry that gets processed. | |
156 | */ | |
157 | extern void (*dtl_consumer)(struct dtl_entry *entry, u64 index); | |
158 | ||
94491685 | 159 | #endif /* CONFIG_PPC_BOOK3S */ |
88ced031 | 160 | #endif /* __KERNEL__ */ |
8882a4da | 161 | #endif /* _ASM_POWERPC_LPPACA_H */ |