Commit | Line | Data |
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d800ba12 | 1 | /* |
d7cf83fc | 2 | * OPAL API definitions. |
d800ba12 | 3 | * |
d7cf83fc | 4 | * Copyright 2011-2015 IBM Corp. |
d800ba12 ME |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #ifndef __OPAL_API_H | |
13 | #define __OPAL_API_H | |
14 | ||
15 | /****** OPAL APIs ******/ | |
16 | ||
17 | /* Return codes */ | |
d7cf83fc | 18 | #define OPAL_SUCCESS 0 |
d800ba12 ME |
19 | #define OPAL_PARAMETER -1 |
20 | #define OPAL_BUSY -2 | |
21 | #define OPAL_PARTIAL -3 | |
22 | #define OPAL_CONSTRAINED -4 | |
23 | #define OPAL_CLOSED -5 | |
24 | #define OPAL_HARDWARE -6 | |
25 | #define OPAL_UNSUPPORTED -7 | |
26 | #define OPAL_PERMISSION -8 | |
27 | #define OPAL_NO_MEM -9 | |
28 | #define OPAL_RESOURCE -10 | |
29 | #define OPAL_INTERNAL_ERROR -11 | |
30 | #define OPAL_BUSY_EVENT -12 | |
31 | #define OPAL_HARDWARE_FROZEN -13 | |
32 | #define OPAL_WRONG_STATE -14 | |
33 | #define OPAL_ASYNC_COMPLETION -15 | |
d7cf83fc | 34 | #define OPAL_EMPTY -16 |
d800ba12 ME |
35 | #define OPAL_I2C_TIMEOUT -17 |
36 | #define OPAL_I2C_INVALID_CMD -18 | |
37 | #define OPAL_I2C_LBUS_PARITY -19 | |
38 | #define OPAL_I2C_BKEND_OVERRUN -20 | |
39 | #define OPAL_I2C_BKEND_ACCESS -21 | |
40 | #define OPAL_I2C_ARBT_LOST -22 | |
41 | #define OPAL_I2C_NACK_RCVD -23 | |
42 | #define OPAL_I2C_STOP_ERR -24 | |
43 | ||
44 | /* API Tokens (in r0) */ | |
d7cf83fc ME |
45 | #define OPAL_INVALID_CALL -1 |
46 | #define OPAL_TEST 0 | |
d800ba12 ME |
47 | #define OPAL_CONSOLE_WRITE 1 |
48 | #define OPAL_CONSOLE_READ 2 | |
49 | #define OPAL_RTC_READ 3 | |
50 | #define OPAL_RTC_WRITE 4 | |
51 | #define OPAL_CEC_POWER_DOWN 5 | |
52 | #define OPAL_CEC_REBOOT 6 | |
53 | #define OPAL_READ_NVRAM 7 | |
54 | #define OPAL_WRITE_NVRAM 8 | |
55 | #define OPAL_HANDLE_INTERRUPT 9 | |
56 | #define OPAL_POLL_EVENTS 10 | |
57 | #define OPAL_PCI_SET_HUB_TCE_MEMORY 11 | |
58 | #define OPAL_PCI_SET_PHB_TCE_MEMORY 12 | |
59 | #define OPAL_PCI_CONFIG_READ_BYTE 13 | |
60 | #define OPAL_PCI_CONFIG_READ_HALF_WORD 14 | |
61 | #define OPAL_PCI_CONFIG_READ_WORD 15 | |
62 | #define OPAL_PCI_CONFIG_WRITE_BYTE 16 | |
63 | #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17 | |
64 | #define OPAL_PCI_CONFIG_WRITE_WORD 18 | |
65 | #define OPAL_SET_XIVE 19 | |
66 | #define OPAL_GET_XIVE 20 | |
67 | #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */ | |
68 | #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22 | |
69 | #define OPAL_PCI_EEH_FREEZE_STATUS 23 | |
70 | #define OPAL_PCI_SHPC 24 | |
71 | #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25 | |
72 | #define OPAL_PCI_EEH_FREEZE_CLEAR 26 | |
73 | #define OPAL_PCI_PHB_MMIO_ENABLE 27 | |
74 | #define OPAL_PCI_SET_PHB_MEM_WINDOW 28 | |
75 | #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29 | |
76 | #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30 | |
77 | #define OPAL_PCI_SET_PE 31 | |
78 | #define OPAL_PCI_SET_PELTV 32 | |
79 | #define OPAL_PCI_SET_MVE 33 | |
80 | #define OPAL_PCI_SET_MVE_ENABLE 34 | |
81 | #define OPAL_PCI_GET_XIVE_REISSUE 35 | |
82 | #define OPAL_PCI_SET_XIVE_REISSUE 36 | |
83 | #define OPAL_PCI_SET_XIVE_PE 37 | |
84 | #define OPAL_GET_XIVE_SOURCE 38 | |
85 | #define OPAL_GET_MSI_32 39 | |
86 | #define OPAL_GET_MSI_64 40 | |
87 | #define OPAL_START_CPU 41 | |
88 | #define OPAL_QUERY_CPU_STATUS 42 | |
d7cf83fc | 89 | #define OPAL_WRITE_OPPANEL 43 /* unimplemented */ |
d800ba12 ME |
90 | #define OPAL_PCI_MAP_PE_DMA_WINDOW 44 |
91 | #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45 | |
92 | #define OPAL_PCI_RESET 49 | |
93 | #define OPAL_PCI_GET_HUB_DIAG_DATA 50 | |
94 | #define OPAL_PCI_GET_PHB_DIAG_DATA 51 | |
95 | #define OPAL_PCI_FENCE_PHB 52 | |
96 | #define OPAL_PCI_REINIT 53 | |
97 | #define OPAL_PCI_MASK_PE_ERROR 54 | |
98 | #define OPAL_SET_SLOT_LED_STATUS 55 | |
99 | #define OPAL_GET_EPOW_STATUS 56 | |
100 | #define OPAL_SET_SYSTEM_ATTENTION_LED 57 | |
101 | #define OPAL_RESERVED1 58 | |
102 | #define OPAL_RESERVED2 59 | |
103 | #define OPAL_PCI_NEXT_ERROR 60 | |
104 | #define OPAL_PCI_EEH_FREEZE_STATUS2 61 | |
105 | #define OPAL_PCI_POLL 62 | |
106 | #define OPAL_PCI_MSI_EOI 63 | |
107 | #define OPAL_PCI_GET_PHB_DIAG_DATA2 64 | |
108 | #define OPAL_XSCOM_READ 65 | |
109 | #define OPAL_XSCOM_WRITE 66 | |
110 | #define OPAL_LPC_READ 67 | |
111 | #define OPAL_LPC_WRITE 68 | |
112 | #define OPAL_RETURN_CPU 69 | |
113 | #define OPAL_REINIT_CPUS 70 | |
114 | #define OPAL_ELOG_READ 71 | |
115 | #define OPAL_ELOG_WRITE 72 | |
116 | #define OPAL_ELOG_ACK 73 | |
117 | #define OPAL_ELOG_RESEND 74 | |
118 | #define OPAL_ELOG_SIZE 75 | |
119 | #define OPAL_FLASH_VALIDATE 76 | |
120 | #define OPAL_FLASH_MANAGE 77 | |
121 | #define OPAL_FLASH_UPDATE 78 | |
122 | #define OPAL_RESYNC_TIMEBASE 79 | |
123 | #define OPAL_CHECK_TOKEN 80 | |
124 | #define OPAL_DUMP_INIT 81 | |
125 | #define OPAL_DUMP_INFO 82 | |
126 | #define OPAL_DUMP_READ 83 | |
127 | #define OPAL_DUMP_ACK 84 | |
128 | #define OPAL_GET_MSG 85 | |
129 | #define OPAL_CHECK_ASYNC_COMPLETION 86 | |
130 | #define OPAL_SYNC_HOST_REBOOT 87 | |
131 | #define OPAL_SENSOR_READ 88 | |
132 | #define OPAL_GET_PARAM 89 | |
133 | #define OPAL_SET_PARAM 90 | |
134 | #define OPAL_DUMP_RESEND 91 | |
d7cf83fc ME |
135 | #define OPAL_ELOG_SEND 92 /* Deprecated */ |
136 | #define OPAL_PCI_SET_PHB_CAPI_MODE 93 | |
d800ba12 | 137 | #define OPAL_DUMP_INFO2 94 |
d7cf83fc | 138 | #define OPAL_WRITE_OPPANEL_ASYNC 95 |
d800ba12 ME |
139 | #define OPAL_PCI_ERR_INJECT 96 |
140 | #define OPAL_PCI_EEH_FREEZE_SET 97 | |
141 | #define OPAL_HANDLE_HMI 98 | |
142 | #define OPAL_CONFIG_CPU_IDLE_STATE 99 | |
143 | #define OPAL_SLW_SET_REG 100 | |
144 | #define OPAL_REGISTER_DUMP_REGION 101 | |
145 | #define OPAL_UNREGISTER_DUMP_REGION 102 | |
146 | #define OPAL_WRITE_TPO 103 | |
147 | #define OPAL_READ_TPO 104 | |
d7cf83fc ME |
148 | #define OPAL_GET_DPO_STATUS 105 |
149 | #define OPAL_OLD_I2C_REQUEST 106 /* Deprecated */ | |
d800ba12 ME |
150 | #define OPAL_IPMI_SEND 107 |
151 | #define OPAL_IPMI_RECV 108 | |
152 | #define OPAL_I2C_REQUEST 109 | |
ed59190e CB |
153 | #define OPAL_FLASH_READ 110 |
154 | #define OPAL_FLASH_WRITE 111 | |
155 | #define OPAL_FLASH_ERASE 112 | |
0d7cd855 | 156 | #define OPAL_PRD_MSG 113 |
8a8d9181 AK |
157 | #define OPAL_LEDS_GET_INDICATOR 114 |
158 | #define OPAL_LEDS_SET_INDICATOR 115 | |
e784b649 | 159 | #define OPAL_CEC_REBOOT2 116 |
affddff6 RC |
160 | #define OPAL_CONSOLE_FLUSH 117 |
161 | #define OPAL_LAST 117 | |
d800ba12 ME |
162 | |
163 | /* Device tree flags */ | |
164 | ||
165 | /* Flags set in power-mgmt nodes in device tree if | |
166 | * respective idle states are supported in the platform. | |
167 | */ | |
d7cf83fc ME |
168 | #define OPAL_PM_NAP_ENABLED 0x00010000 |
169 | #define OPAL_PM_SLEEP_ENABLED 0x00020000 | |
170 | #define OPAL_PM_WINKLE_ENABLED 0x00040000 | |
171 | #define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000 /* with workaround */ | |
d800ba12 | 172 | |
5703d2f4 SP |
173 | /* |
174 | * OPAL_CONFIG_CPU_IDLE_STATE parameters | |
175 | */ | |
176 | #define OPAL_CONFIG_IDLE_FASTSLEEP 1 | |
177 | #define OPAL_CONFIG_IDLE_UNDO 0 | |
178 | #define OPAL_CONFIG_IDLE_APPLY 1 | |
179 | ||
d800ba12 ME |
180 | #ifndef __ASSEMBLY__ |
181 | ||
182 | /* Other enums */ | |
d800ba12 ME |
183 | enum OpalFreezeState { |
184 | OPAL_EEH_STOPPED_NOT_FROZEN = 0, | |
185 | OPAL_EEH_STOPPED_MMIO_FREEZE = 1, | |
186 | OPAL_EEH_STOPPED_DMA_FREEZE = 2, | |
187 | OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3, | |
188 | OPAL_EEH_STOPPED_RESET = 4, | |
189 | OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5, | |
190 | OPAL_EEH_STOPPED_PERM_UNAVAIL = 6 | |
191 | }; | |
192 | ||
193 | enum OpalEehFreezeActionToken { | |
194 | OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1, | |
195 | OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2, | |
196 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3, | |
197 | ||
198 | OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1, | |
199 | OPAL_EEH_ACTION_SET_FREEZE_DMA = 2, | |
200 | OPAL_EEH_ACTION_SET_FREEZE_ALL = 3 | |
201 | }; | |
202 | ||
203 | enum OpalPciStatusToken { | |
204 | OPAL_EEH_NO_ERROR = 0, | |
205 | OPAL_EEH_IOC_ERROR = 1, | |
206 | OPAL_EEH_PHB_ERROR = 2, | |
207 | OPAL_EEH_PE_ERROR = 3, | |
208 | OPAL_EEH_PE_MMIO_ERROR = 4, | |
209 | OPAL_EEH_PE_DMA_ERROR = 5 | |
210 | }; | |
211 | ||
212 | enum OpalPciErrorSeverity { | |
213 | OPAL_EEH_SEV_NO_ERROR = 0, | |
214 | OPAL_EEH_SEV_IOC_DEAD = 1, | |
215 | OPAL_EEH_SEV_PHB_DEAD = 2, | |
216 | OPAL_EEH_SEV_PHB_FENCED = 3, | |
217 | OPAL_EEH_SEV_PE_ER = 4, | |
218 | OPAL_EEH_SEV_INF = 5 | |
219 | }; | |
220 | ||
221 | enum OpalErrinjectType { | |
222 | OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR = 0, | |
223 | OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64 = 1, | |
224 | }; | |
225 | ||
226 | enum OpalErrinjectFunc { | |
227 | /* IOA bus specific errors */ | |
228 | OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR = 0, | |
229 | OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA = 1, | |
230 | OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR = 2, | |
231 | OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA = 3, | |
232 | OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR = 4, | |
233 | OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA = 5, | |
234 | OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR = 6, | |
235 | OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA = 7, | |
236 | OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR = 8, | |
237 | OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA = 9, | |
238 | OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR = 10, | |
239 | OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA = 11, | |
240 | OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR = 12, | |
241 | OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA = 13, | |
242 | OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER = 14, | |
243 | OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET = 15, | |
244 | OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR = 16, | |
245 | OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA = 17, | |
246 | OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER = 18, | |
247 | OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET = 19, | |
248 | }; | |
249 | ||
d800ba12 ME |
250 | enum OpalMmioWindowType { |
251 | OPAL_M32_WINDOW_TYPE = 1, | |
252 | OPAL_M64_WINDOW_TYPE = 2, | |
d7cf83fc | 253 | OPAL_IO_WINDOW_TYPE = 3 |
d800ba12 ME |
254 | }; |
255 | ||
d800ba12 | 256 | enum OpalExceptionHandler { |
d7cf83fc | 257 | OPAL_MACHINE_CHECK_HANDLER = 1, |
d800ba12 | 258 | OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2, |
d7cf83fc | 259 | OPAL_SOFTPATCH_HANDLER = 3 |
d800ba12 ME |
260 | }; |
261 | ||
262 | enum OpalPendingState { | |
d7cf83fc ME |
263 | OPAL_EVENT_OPAL_INTERNAL = 0x1, |
264 | OPAL_EVENT_NVRAM = 0x2, | |
265 | OPAL_EVENT_RTC = 0x4, | |
266 | OPAL_EVENT_CONSOLE_OUTPUT = 0x8, | |
267 | OPAL_EVENT_CONSOLE_INPUT = 0x10, | |
268 | OPAL_EVENT_ERROR_LOG_AVAIL = 0x20, | |
269 | OPAL_EVENT_ERROR_LOG = 0x40, | |
270 | OPAL_EVENT_EPOW = 0x80, | |
271 | OPAL_EVENT_LED_STATUS = 0x100, | |
272 | OPAL_EVENT_PCI_ERROR = 0x200, | |
273 | OPAL_EVENT_DUMP_AVAIL = 0x400, | |
274 | OPAL_EVENT_MSG_PENDING = 0x800, | |
d800ba12 ME |
275 | }; |
276 | ||
277 | enum OpalThreadStatus { | |
278 | OPAL_THREAD_INACTIVE = 0x0, | |
279 | OPAL_THREAD_STARTED = 0x1, | |
280 | OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */ | |
281 | }; | |
282 | ||
283 | enum OpalPciBusCompare { | |
284 | OpalPciBusAny = 0, /* Any bus number match */ | |
285 | OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */ | |
286 | OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */ | |
287 | OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */ | |
288 | OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */ | |
289 | OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */ | |
290 | OpalPciBusAll = 7, /* Match bus number exactly */ | |
291 | }; | |
292 | ||
293 | enum OpalDeviceCompare { | |
294 | OPAL_IGNORE_RID_DEVICE_NUMBER = 0, | |
295 | OPAL_COMPARE_RID_DEVICE_NUMBER = 1 | |
296 | }; | |
297 | ||
298 | enum OpalFuncCompare { | |
299 | OPAL_IGNORE_RID_FUNCTION_NUMBER = 0, | |
300 | OPAL_COMPARE_RID_FUNCTION_NUMBER = 1 | |
301 | }; | |
302 | ||
303 | enum OpalPeAction { | |
304 | OPAL_UNMAP_PE = 0, | |
305 | OPAL_MAP_PE = 1 | |
306 | }; | |
307 | ||
308 | enum OpalPeltvAction { | |
309 | OPAL_REMOVE_PE_FROM_DOMAIN = 0, | |
310 | OPAL_ADD_PE_TO_DOMAIN = 1 | |
311 | }; | |
312 | ||
313 | enum OpalMveEnableAction { | |
314 | OPAL_DISABLE_MVE = 0, | |
315 | OPAL_ENABLE_MVE = 1 | |
316 | }; | |
317 | ||
d7cf83fc | 318 | enum OpalM64Action { |
d800ba12 ME |
319 | OPAL_DISABLE_M64 = 0, |
320 | OPAL_ENABLE_M64_SPLIT = 1, | |
321 | OPAL_ENABLE_M64_NON_SPLIT = 2 | |
322 | }; | |
323 | ||
324 | enum OpalPciResetScope { | |
325 | OPAL_RESET_PHB_COMPLETE = 1, | |
326 | OPAL_RESET_PCI_LINK = 2, | |
327 | OPAL_RESET_PHB_ERROR = 3, | |
328 | OPAL_RESET_PCI_HOT = 4, | |
329 | OPAL_RESET_PCI_FUNDAMENTAL = 5, | |
330 | OPAL_RESET_PCI_IODA_TABLE = 6 | |
331 | }; | |
332 | ||
333 | enum OpalPciReinitScope { | |
d7cf83fc ME |
334 | /* |
335 | * Note: we chose values that do not overlap | |
336 | * OpalPciResetScope as OPAL v2 used the same | |
337 | * enum for both | |
338 | */ | |
d800ba12 ME |
339 | OPAL_REINIT_PCI_DEV = 1000 |
340 | }; | |
341 | ||
342 | enum OpalPciResetState { | |
343 | OPAL_DEASSERT_RESET = 0, | |
d7cf83fc | 344 | OPAL_ASSERT_RESET = 1 |
d800ba12 ME |
345 | }; |
346 | ||
5d53be7d ME |
347 | enum OpalSlotLedType { |
348 | OPAL_SLOT_LED_TYPE_ID = 0, /* IDENTIFY LED */ | |
349 | OPAL_SLOT_LED_TYPE_FAULT = 1, /* FAULT LED */ | |
350 | OPAL_SLOT_LED_TYPE_ATTN = 2, /* System Attention LED */ | |
351 | OPAL_SLOT_LED_TYPE_MAX = 3 | |
352 | }; | |
353 | ||
354 | enum OpalSlotLedState { | |
355 | OPAL_SLOT_LED_STATE_OFF = 0, /* LED is OFF */ | |
356 | OPAL_SLOT_LED_STATE_ON = 1 /* LED is ON */ | |
357 | }; | |
358 | ||
d800ba12 ME |
359 | /* |
360 | * Address cycle types for LPC accesses. These also correspond | |
361 | * to the content of the first cell of the "reg" property for | |
362 | * device nodes on the LPC bus | |
363 | */ | |
364 | enum OpalLPCAddressType { | |
365 | OPAL_LPC_MEM = 0, | |
366 | OPAL_LPC_IO = 1, | |
367 | OPAL_LPC_FW = 2, | |
368 | }; | |
369 | ||
d7cf83fc ME |
370 | enum opal_msg_type { |
371 | OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc, | |
372 | * additional params function-specific | |
373 | */ | |
374 | OPAL_MSG_MEM_ERR, | |
375 | OPAL_MSG_EPOW, | |
376 | OPAL_MSG_SHUTDOWN, /* params[0] = 1 reboot, 0 shutdown */ | |
377 | OPAL_MSG_HMI_EVT, | |
378 | OPAL_MSG_DPO, | |
0d7cd855 | 379 | OPAL_MSG_PRD, |
196ba2d5 | 380 | OPAL_MSG_OCC, |
d7cf83fc | 381 | OPAL_MSG_TYPE_MAX, |
d800ba12 ME |
382 | }; |
383 | ||
384 | struct opal_msg { | |
385 | __be32 msg_type; | |
386 | __be32 reserved; | |
387 | __be64 params[8]; | |
388 | }; | |
389 | ||
d7cf83fc ME |
390 | /* System parameter permission */ |
391 | enum OpalSysparamPerm { | |
392 | OPAL_SYSPARAM_READ = 0x1, | |
393 | OPAL_SYSPARAM_WRITE = 0x2, | |
394 | OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE), | |
395 | }; | |
396 | ||
d800ba12 ME |
397 | enum { |
398 | OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1, | |
399 | }; | |
400 | ||
401 | struct opal_ipmi_msg { | |
d7cf83fc ME |
402 | uint8_t version; |
403 | uint8_t netfn; | |
404 | uint8_t cmd; | |
405 | uint8_t data[]; | |
d800ba12 ME |
406 | }; |
407 | ||
408 | /* FSP memory errors handling */ | |
409 | enum OpalMemErr_Version { | |
410 | OpalMemErr_V1 = 1, | |
411 | }; | |
412 | ||
413 | enum OpalMemErrType { | |
414 | OPAL_MEM_ERR_TYPE_RESILIENCE = 0, | |
415 | OPAL_MEM_ERR_TYPE_DYN_DALLOC, | |
d800ba12 ME |
416 | }; |
417 | ||
418 | /* Memory Reilience error type */ | |
419 | enum OpalMemErr_ResilErrType { | |
420 | OPAL_MEM_RESILIENCE_CE = 0, | |
421 | OPAL_MEM_RESILIENCE_UE, | |
422 | OPAL_MEM_RESILIENCE_UE_SCRUB, | |
423 | }; | |
424 | ||
425 | /* Dynamic Memory Deallocation type */ | |
426 | enum OpalMemErr_DynErrType { | |
427 | OPAL_MEM_DYNAMIC_DEALLOC = 0, | |
428 | }; | |
429 | ||
d800ba12 ME |
430 | struct OpalMemoryErrorData { |
431 | enum OpalMemErr_Version version:8; /* 0x00 */ | |
432 | enum OpalMemErrType type:8; /* 0x01 */ | |
433 | __be16 flags; /* 0x02 */ | |
434 | uint8_t reserved_1[4]; /* 0x04 */ | |
435 | ||
436 | union { | |
437 | /* Memory Resilience corrected/uncorrected error info */ | |
438 | struct { | |
d7cf83fc ME |
439 | enum OpalMemErr_ResilErrType resil_err_type:8; |
440 | uint8_t reserved_1[7]; | |
441 | __be64 physical_address_start; | |
442 | __be64 physical_address_end; | |
d800ba12 ME |
443 | } resilience; |
444 | /* Dynamic memory deallocation error info */ | |
445 | struct { | |
d7cf83fc ME |
446 | enum OpalMemErr_DynErrType dyn_err_type:8; |
447 | uint8_t reserved_1[7]; | |
448 | __be64 physical_address_start; | |
449 | __be64 physical_address_end; | |
d800ba12 ME |
450 | } dyn_dealloc; |
451 | } u; | |
452 | }; | |
453 | ||
454 | /* HMI interrupt event */ | |
455 | enum OpalHMI_Version { | |
456 | OpalHMIEvt_V1 = 1, | |
c33e11d0 | 457 | OpalHMIEvt_V2 = 2, |
d800ba12 ME |
458 | }; |
459 | ||
460 | enum OpalHMI_Severity { | |
461 | OpalHMI_SEV_NO_ERROR = 0, | |
462 | OpalHMI_SEV_WARNING = 1, | |
463 | OpalHMI_SEV_ERROR_SYNC = 2, | |
464 | OpalHMI_SEV_FATAL = 3, | |
465 | }; | |
466 | ||
467 | enum OpalHMI_Disposition { | |
468 | OpalHMI_DISPOSITION_RECOVERED = 0, | |
469 | OpalHMI_DISPOSITION_NOT_RECOVERED = 1, | |
470 | }; | |
471 | ||
472 | enum OpalHMI_ErrType { | |
473 | OpalHMI_ERROR_MALFUNC_ALERT = 0, | |
474 | OpalHMI_ERROR_PROC_RECOV_DONE, | |
475 | OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN, | |
476 | OpalHMI_ERROR_PROC_RECOV_MASKED, | |
477 | OpalHMI_ERROR_TFAC, | |
478 | OpalHMI_ERROR_TFMR_PARITY, | |
479 | OpalHMI_ERROR_HA_OVERFLOW_WARN, | |
480 | OpalHMI_ERROR_XSCOM_FAIL, | |
481 | OpalHMI_ERROR_XSCOM_DONE, | |
482 | OpalHMI_ERROR_SCOM_FIR, | |
483 | OpalHMI_ERROR_DEBUG_TRIG_FIR, | |
484 | OpalHMI_ERROR_HYP_RESOURCE, | |
d7cf83fc | 485 | OpalHMI_ERROR_CAPP_RECOVERY, |
d800ba12 ME |
486 | }; |
487 | ||
c33e11d0 MS |
488 | enum OpalHMI_XstopType { |
489 | CHECKSTOP_TYPE_UNKNOWN = 0, | |
490 | CHECKSTOP_TYPE_CORE = 1, | |
491 | CHECKSTOP_TYPE_NX = 2, | |
492 | }; | |
493 | ||
494 | enum OpalHMI_CoreXstopReason { | |
495 | CORE_CHECKSTOP_IFU_REGFILE = 0x00000001, | |
496 | CORE_CHECKSTOP_IFU_LOGIC = 0x00000002, | |
497 | CORE_CHECKSTOP_PC_DURING_RECOV = 0x00000004, | |
498 | CORE_CHECKSTOP_ISU_REGFILE = 0x00000008, | |
499 | CORE_CHECKSTOP_ISU_LOGIC = 0x00000010, | |
500 | CORE_CHECKSTOP_FXU_LOGIC = 0x00000020, | |
501 | CORE_CHECKSTOP_VSU_LOGIC = 0x00000040, | |
502 | CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE = 0x00000080, | |
503 | CORE_CHECKSTOP_LSU_REGFILE = 0x00000100, | |
504 | CORE_CHECKSTOP_PC_FWD_PROGRESS = 0x00000200, | |
505 | CORE_CHECKSTOP_LSU_LOGIC = 0x00000400, | |
506 | CORE_CHECKSTOP_PC_LOGIC = 0x00000800, | |
507 | CORE_CHECKSTOP_PC_HYP_RESOURCE = 0x00001000, | |
508 | CORE_CHECKSTOP_PC_HANG_RECOV_FAILED = 0x00002000, | |
509 | CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED = 0x00004000, | |
510 | CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ = 0x00008000, | |
511 | CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ = 0x00010000, | |
512 | }; | |
513 | ||
514 | enum OpalHMI_NestAccelXstopReason { | |
515 | NX_CHECKSTOP_SHM_INVAL_STATE_ERR = 0x00000001, | |
516 | NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1 = 0x00000002, | |
517 | NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2 = 0x00000004, | |
518 | NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR = 0x00000008, | |
519 | NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR = 0x00000010, | |
520 | NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR = 0x00000020, | |
521 | NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR = 0x00000040, | |
522 | NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR = 0x00000080, | |
523 | NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR = 0x00000100, | |
524 | NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR = 0x00000200, | |
525 | NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR = 0x00000400, | |
526 | NX_CHECKSTOP_DMA_CRB_UE = 0x00000800, | |
527 | NX_CHECKSTOP_DMA_CRB_SUE = 0x00001000, | |
528 | NX_CHECKSTOP_PBI_ISN_UE = 0x00002000, | |
529 | }; | |
530 | ||
d800ba12 ME |
531 | struct OpalHMIEvent { |
532 | uint8_t version; /* 0x00 */ | |
533 | uint8_t severity; /* 0x01 */ | |
534 | uint8_t type; /* 0x02 */ | |
535 | uint8_t disposition; /* 0x03 */ | |
536 | uint8_t reserved_1[4]; /* 0x04 */ | |
537 | ||
538 | __be64 hmer; | |
539 | /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */ | |
540 | __be64 tfmr; | |
c33e11d0 MS |
541 | |
542 | /* version 2 and later */ | |
543 | union { | |
544 | /* | |
545 | * checkstop info (Core/NX). | |
546 | * Valid for OpalHMI_ERROR_MALFUNC_ALERT. | |
547 | */ | |
548 | struct { | |
549 | uint8_t xstop_type; /* enum OpalHMI_XstopType */ | |
550 | uint8_t reserved_1[3]; | |
551 | __be32 xstop_reason; | |
552 | union { | |
553 | __be32 pir; /* for CHECKSTOP_TYPE_CORE */ | |
554 | __be32 chip_id; /* for CHECKSTOP_TYPE_NX */ | |
555 | } u; | |
556 | } xstop_error; | |
557 | } u; | |
d800ba12 ME |
558 | }; |
559 | ||
560 | enum { | |
561 | OPAL_P7IOC_DIAG_TYPE_NONE = 0, | |
562 | OPAL_P7IOC_DIAG_TYPE_RGC = 1, | |
563 | OPAL_P7IOC_DIAG_TYPE_BI = 2, | |
564 | OPAL_P7IOC_DIAG_TYPE_CI = 3, | |
565 | OPAL_P7IOC_DIAG_TYPE_MISC = 4, | |
566 | OPAL_P7IOC_DIAG_TYPE_I2C = 5, | |
567 | OPAL_P7IOC_DIAG_TYPE_LAST = 6 | |
568 | }; | |
569 | ||
570 | struct OpalIoP7IOCErrorData { | |
571 | __be16 type; | |
572 | ||
573 | /* GEM */ | |
574 | __be64 gemXfir; | |
575 | __be64 gemRfir; | |
576 | __be64 gemRirqfir; | |
577 | __be64 gemMask; | |
578 | __be64 gemRwof; | |
579 | ||
580 | /* LEM */ | |
581 | __be64 lemFir; | |
582 | __be64 lemErrMask; | |
583 | __be64 lemAction0; | |
584 | __be64 lemAction1; | |
585 | __be64 lemWof; | |
586 | ||
587 | union { | |
588 | struct OpalIoP7IOCRgcErrorData { | |
589 | __be64 rgcStatus; /* 3E1C10 */ | |
590 | __be64 rgcLdcp; /* 3E1C18 */ | |
591 | }rgc; | |
592 | struct OpalIoP7IOCBiErrorData { | |
593 | __be64 biLdcp0; /* 3C0100, 3C0118 */ | |
594 | __be64 biLdcp1; /* 3C0108, 3C0120 */ | |
595 | __be64 biLdcp2; /* 3C0110, 3C0128 */ | |
596 | __be64 biFenceStatus; /* 3C0130, 3C0130 */ | |
597 | ||
d7cf83fc | 598 | uint8_t biDownbound; /* BI Downbound or Upbound */ |
d800ba12 ME |
599 | }bi; |
600 | struct OpalIoP7IOCCiErrorData { | |
601 | __be64 ciPortStatus; /* 3Dn008 */ | |
602 | __be64 ciPortLdcp; /* 3Dn010 */ | |
603 | ||
d7cf83fc | 604 | uint8_t ciPort; /* Index of CI port: 0/1 */ |
d800ba12 ME |
605 | }ci; |
606 | }; | |
607 | }; | |
608 | ||
609 | /** | |
610 | * This structure defines the overlay which will be used to store PHB error | |
611 | * data upon request. | |
612 | */ | |
613 | enum { | |
614 | OPAL_PHB_ERROR_DATA_VERSION_1 = 1, | |
615 | }; | |
616 | ||
617 | enum { | |
618 | OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1, | |
619 | OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2 | |
620 | }; | |
621 | ||
622 | enum { | |
623 | OPAL_P7IOC_NUM_PEST_REGS = 128, | |
624 | OPAL_PHB3_NUM_PEST_REGS = 256 | |
625 | }; | |
626 | ||
d800ba12 ME |
627 | struct OpalIoPhbErrorCommon { |
628 | __be32 version; | |
629 | __be32 ioType; | |
630 | __be32 len; | |
631 | }; | |
632 | ||
633 | struct OpalIoP7IOCPhbErrorData { | |
634 | struct OpalIoPhbErrorCommon common; | |
635 | ||
636 | __be32 brdgCtl; | |
637 | ||
638 | // P7IOC utl regs | |
639 | __be32 portStatusReg; | |
640 | __be32 rootCmplxStatus; | |
641 | __be32 busAgentStatus; | |
642 | ||
643 | // P7IOC cfg regs | |
644 | __be32 deviceStatus; | |
645 | __be32 slotStatus; | |
646 | __be32 linkStatus; | |
647 | __be32 devCmdStatus; | |
648 | __be32 devSecStatus; | |
649 | ||
650 | // cfg AER regs | |
651 | __be32 rootErrorStatus; | |
652 | __be32 uncorrErrorStatus; | |
653 | __be32 corrErrorStatus; | |
654 | __be32 tlpHdr1; | |
655 | __be32 tlpHdr2; | |
656 | __be32 tlpHdr3; | |
657 | __be32 tlpHdr4; | |
658 | __be32 sourceId; | |
659 | ||
660 | __be32 rsv3; | |
661 | ||
662 | // Record data about the call to allocate a buffer. | |
663 | __be64 errorClass; | |
664 | __be64 correlator; | |
665 | ||
666 | //P7IOC MMIO Error Regs | |
667 | __be64 p7iocPlssr; // n120 | |
668 | __be64 p7iocCsr; // n110 | |
669 | __be64 lemFir; // nC00 | |
670 | __be64 lemErrorMask; // nC18 | |
671 | __be64 lemWOF; // nC40 | |
672 | __be64 phbErrorStatus; // nC80 | |
673 | __be64 phbFirstErrorStatus; // nC88 | |
674 | __be64 phbErrorLog0; // nCC0 | |
675 | __be64 phbErrorLog1; // nCC8 | |
676 | __be64 mmioErrorStatus; // nD00 | |
677 | __be64 mmioFirstErrorStatus; // nD08 | |
678 | __be64 mmioErrorLog0; // nD40 | |
679 | __be64 mmioErrorLog1; // nD48 | |
680 | __be64 dma0ErrorStatus; // nD80 | |
681 | __be64 dma0FirstErrorStatus; // nD88 | |
682 | __be64 dma0ErrorLog0; // nDC0 | |
683 | __be64 dma0ErrorLog1; // nDC8 | |
684 | __be64 dma1ErrorStatus; // nE00 | |
685 | __be64 dma1FirstErrorStatus; // nE08 | |
686 | __be64 dma1ErrorLog0; // nE40 | |
687 | __be64 dma1ErrorLog1; // nE48 | |
688 | __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS]; | |
689 | __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS]; | |
690 | }; | |
691 | ||
692 | struct OpalIoPhb3ErrorData { | |
693 | struct OpalIoPhbErrorCommon common; | |
694 | ||
695 | __be32 brdgCtl; | |
696 | ||
697 | /* PHB3 UTL regs */ | |
698 | __be32 portStatusReg; | |
699 | __be32 rootCmplxStatus; | |
700 | __be32 busAgentStatus; | |
701 | ||
702 | /* PHB3 cfg regs */ | |
703 | __be32 deviceStatus; | |
704 | __be32 slotStatus; | |
705 | __be32 linkStatus; | |
706 | __be32 devCmdStatus; | |
707 | __be32 devSecStatus; | |
708 | ||
709 | /* cfg AER regs */ | |
710 | __be32 rootErrorStatus; | |
711 | __be32 uncorrErrorStatus; | |
712 | __be32 corrErrorStatus; | |
713 | __be32 tlpHdr1; | |
714 | __be32 tlpHdr2; | |
715 | __be32 tlpHdr3; | |
716 | __be32 tlpHdr4; | |
717 | __be32 sourceId; | |
718 | ||
719 | __be32 rsv3; | |
720 | ||
721 | /* Record data about the call to allocate a buffer */ | |
722 | __be64 errorClass; | |
723 | __be64 correlator; | |
724 | ||
d7cf83fc | 725 | /* PHB3 MMIO Error Regs */ |
d800ba12 ME |
726 | __be64 nFir; /* 000 */ |
727 | __be64 nFirMask; /* 003 */ | |
728 | __be64 nFirWOF; /* 008 */ | |
d800ba12 ME |
729 | __be64 phbPlssr; /* 120 */ |
730 | __be64 phbCsr; /* 110 */ | |
731 | __be64 lemFir; /* C00 */ | |
732 | __be64 lemErrorMask; /* C18 */ | |
733 | __be64 lemWOF; /* C40 */ | |
734 | __be64 phbErrorStatus; /* C80 */ | |
735 | __be64 phbFirstErrorStatus; /* C88 */ | |
736 | __be64 phbErrorLog0; /* CC0 */ | |
737 | __be64 phbErrorLog1; /* CC8 */ | |
738 | __be64 mmioErrorStatus; /* D00 */ | |
739 | __be64 mmioFirstErrorStatus; /* D08 */ | |
740 | __be64 mmioErrorLog0; /* D40 */ | |
741 | __be64 mmioErrorLog1; /* D48 */ | |
742 | __be64 dma0ErrorStatus; /* D80 */ | |
743 | __be64 dma0FirstErrorStatus; /* D88 */ | |
744 | __be64 dma0ErrorLog0; /* DC0 */ | |
745 | __be64 dma0ErrorLog1; /* DC8 */ | |
746 | __be64 dma1ErrorStatus; /* E00 */ | |
747 | __be64 dma1FirstErrorStatus; /* E08 */ | |
748 | __be64 dma1ErrorLog0; /* E40 */ | |
749 | __be64 dma1ErrorLog1; /* E48 */ | |
750 | __be64 pestA[OPAL_PHB3_NUM_PEST_REGS]; | |
751 | __be64 pestB[OPAL_PHB3_NUM_PEST_REGS]; | |
752 | }; | |
753 | ||
754 | enum { | |
755 | OPAL_REINIT_CPUS_HILE_BE = (1 << 0), | |
756 | OPAL_REINIT_CPUS_HILE_LE = (1 << 1), | |
757 | }; | |
758 | ||
759 | typedef struct oppanel_line { | |
d7cf83fc ME |
760 | __be64 line; |
761 | __be64 line_len; | |
d800ba12 ME |
762 | } oppanel_line_t; |
763 | ||
0d7cd855 JK |
764 | enum opal_prd_msg_type { |
765 | OPAL_PRD_MSG_TYPE_INIT = 0, /* HBRT --> OPAL */ | |
766 | OPAL_PRD_MSG_TYPE_FINI, /* HBRT/kernel --> OPAL */ | |
767 | OPAL_PRD_MSG_TYPE_ATTN, /* HBRT <-- OPAL */ | |
768 | OPAL_PRD_MSG_TYPE_ATTN_ACK, /* HBRT --> OPAL */ | |
769 | OPAL_PRD_MSG_TYPE_OCC_ERROR, /* HBRT <-- OPAL */ | |
770 | OPAL_PRD_MSG_TYPE_OCC_RESET, /* HBRT <-- OPAL */ | |
771 | }; | |
772 | ||
773 | struct opal_prd_msg_header { | |
774 | uint8_t type; | |
775 | uint8_t pad[1]; | |
776 | __be16 size; | |
777 | }; | |
778 | ||
779 | struct opal_prd_msg; | |
780 | ||
196ba2d5 SB |
781 | #define OCC_RESET 0 |
782 | #define OCC_LOAD 1 | |
783 | #define OCC_THROTTLE 2 | |
784 | #define OCC_MAX_THROTTLE_STATUS 5 | |
785 | ||
786 | struct opal_occ_msg { | |
787 | __be64 type; | |
788 | __be64 chip; | |
789 | __be64 throttle_status; | |
790 | }; | |
791 | ||
d800ba12 ME |
792 | /* |
793 | * SG entries | |
794 | * | |
795 | * WARNING: The current implementation requires each entry | |
796 | * to represent a block that is 4k aligned *and* each block | |
797 | * size except the last one in the list to be as well. | |
798 | */ | |
799 | struct opal_sg_entry { | |
800 | __be64 data; | |
801 | __be64 length; | |
802 | }; | |
803 | ||
d7cf83fc ME |
804 | /* |
805 | * Candiate image SG list. | |
806 | * | |
807 | * length = VER | length | |
808 | */ | |
d800ba12 ME |
809 | struct opal_sg_list { |
810 | __be64 length; | |
811 | __be64 next; | |
812 | struct opal_sg_entry entry[]; | |
813 | }; | |
814 | ||
815 | /* | |
816 | * Dump region ID range usable by the OS | |
817 | */ | |
818 | #define OPAL_DUMP_REGION_HOST_START 0x80 | |
819 | #define OPAL_DUMP_REGION_LOG_BUF 0x80 | |
820 | #define OPAL_DUMP_REGION_HOST_END 0xFF | |
821 | ||
d7cf83fc ME |
822 | /* CAPI modes for PHB */ |
823 | enum { | |
824 | OPAL_PHB_CAPI_MODE_PCIE = 0, | |
825 | OPAL_PHB_CAPI_MODE_CAPI = 1, | |
826 | OPAL_PHB_CAPI_MODE_SNOOP_OFF = 2, | |
827 | OPAL_PHB_CAPI_MODE_SNOOP_ON = 3, | |
828 | }; | |
829 | ||
d800ba12 ME |
830 | /* OPAL I2C request */ |
831 | struct opal_i2c_request { | |
832 | uint8_t type; | |
833 | #define OPAL_I2C_RAW_READ 0 | |
834 | #define OPAL_I2C_RAW_WRITE 1 | |
835 | #define OPAL_I2C_SM_READ 2 | |
836 | #define OPAL_I2C_SM_WRITE 3 | |
837 | uint8_t flags; | |
838 | #define OPAL_I2C_ADDR_10 0x01 /* Not supported yet */ | |
839 | uint8_t subaddr_sz; /* Max 4 */ | |
840 | uint8_t reserved; | |
841 | __be16 addr; /* 7 or 10 bit address */ | |
842 | __be16 reserved2; | |
843 | __be32 subaddr; /* Sub-address if any */ | |
844 | __be32 size; /* Data size */ | |
845 | __be64 buffer_ra; /* Buffer real address */ | |
846 | }; | |
847 | ||
3b476aad VP |
848 | /* |
849 | * EPOW status sharing (OPAL and the host) | |
850 | * | |
851 | * The host will pass on OPAL, a buffer of length OPAL_SYSEPOW_MAX | |
852 | * with individual elements being 16 bits wide to fetch the system | |
853 | * wide EPOW status. Each element in the buffer will contain the | |
854 | * EPOW status in it's bit representation for a particular EPOW sub | |
855 | * class as defiend here. So multiple detailed EPOW status bits | |
856 | * specific for any sub class can be represented in a single buffer | |
857 | * element as it's bit representation. | |
858 | */ | |
859 | ||
860 | /* System EPOW type */ | |
861 | enum OpalSysEpow { | |
862 | OPAL_SYSEPOW_POWER = 0, /* Power EPOW */ | |
863 | OPAL_SYSEPOW_TEMP = 1, /* Temperature EPOW */ | |
864 | OPAL_SYSEPOW_COOLING = 2, /* Cooling EPOW */ | |
865 | OPAL_SYSEPOW_MAX = 3, /* Max EPOW categories */ | |
866 | }; | |
867 | ||
868 | /* Power EPOW */ | |
869 | enum OpalSysPower { | |
870 | OPAL_SYSPOWER_UPS = 0x0001, /* System on UPS power */ | |
871 | OPAL_SYSPOWER_CHNG = 0x0002, /* System power config change */ | |
872 | OPAL_SYSPOWER_FAIL = 0x0004, /* System impending power failure */ | |
873 | OPAL_SYSPOWER_INCL = 0x0008, /* System incomplete power */ | |
874 | }; | |
875 | ||
876 | /* Temperature EPOW */ | |
877 | enum OpalSysTemp { | |
878 | OPAL_SYSTEMP_AMB = 0x0001, /* System over ambient temperature */ | |
879 | OPAL_SYSTEMP_INT = 0x0002, /* System over internal temperature */ | |
880 | OPAL_SYSTEMP_HMD = 0x0004, /* System over ambient humidity */ | |
881 | }; | |
882 | ||
883 | /* Cooling EPOW */ | |
884 | enum OpalSysCooling { | |
885 | OPAL_SYSCOOL_INSF = 0x0001, /* System insufficient cooling */ | |
886 | }; | |
887 | ||
e784b649 MS |
888 | /* Argument to OPAL_CEC_REBOOT2() */ |
889 | enum { | |
890 | OPAL_REBOOT_NORMAL = 0, | |
891 | OPAL_REBOOT_PLATFORM_ERROR = 1, | |
892 | }; | |
893 | ||
d800ba12 ME |
894 | #endif /* __ASSEMBLY__ */ |
895 | ||
896 | #endif /* __OPAL_API_H */ |