[deliverable/linux.git] / arch / powerpc / include / asm / page_32.h

#ifndef _ASM_POWERPC_PAGE_32_H
#define _ASM_POWERPC_PAGE_32_H

#include <asm/cache.h>

#if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0)
#if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0
#error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN"
#endif
#endif

#define VM_DATA_DEFAULT_FLAGS	VM_DATA_DEFAULT_FLAGS32

#ifdef CONFIG_NOT_COHERENT_CACHE
#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
#endif

#ifdef CONFIG_PTE_64BIT
#define PTE_FLAGS_OFFSET	4	/* offset of PTE flags, in bytes */
#else
#define PTE_FLAGS_OFFSET	0
#endif

#ifdef CONFIG_PPC_256K_PAGES
#define PTE_SHIFT	(PAGE_SHIFT - PTE_T_LOG2 - 2)	/* 1/4 of a page */
#else
#define PTE_SHIFT	(PAGE_SHIFT - PTE_T_LOG2)	/* full page */
#endif

#ifndef __ASSEMBLY__
/*
 * The basic type of a PTE - 64 bits for those CPUs with > 32 bit
 * physical addressing.
 */
#ifdef CONFIG_PTE_64BIT
typedef unsigned long long pte_basic_t;
#else
typedef unsigned long pte_basic_t;
#endif

/*
 * Clear page using the dcbz instruction, which doesn't cause any
 * memory traffic (except to write out any cache lines which get
 * displaced).  This only works on cacheable memory.
 */
static inline void clear_page(void *addr)
{
	unsigned int i;

	for (i = 0; i < PAGE_SIZE / L1_CACHE_BYTES; i++, addr += L1_CACHE_BYTES)
		dcbz(addr);
}
extern void copy_page(void *to, void *from);

#include <asm-generic/getorder.h>

#define PGD_T_LOG2	(__builtin_ffs(sizeof(pgd_t)) - 1)
#define PTE_T_LOG2	(__builtin_ffs(sizeof(pte_t)) - 1)

#endif /* __ASSEMBLY__ */

#endif /* _ASM_POWERPC_PAGE_32_H */
Commit	Line	Data
5cd16ee9 ME	1	#ifndef _ASM_POWERPC_PAGE_32_H
	2	#define _ASM_POWERPC_PAGE_32_H
	3
5736f96d CL	4	#include <asm/cache.h>
5736f96d CL	5
37dd2bad KG	6	#if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0)
	7	#if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0
	8	#error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN"
	9	#endif
	10	#endif
	11
5cd16ee9 ME	12	#define VM_DATA_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS32
5cd16ee9 ME	13
52142e75	14	#ifdef CONFIG_NOT_COHERENT_CACHE
a6eb9fe1	15	#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
52142e75 BH	16	#endif
52142e75 BH	17
4ee7084e BB	18	#ifdef CONFIG_PTE_64BIT
	19	#define PTE_FLAGS_OFFSET 4 /* offset of PTE flags, in bytes */
	20	#else
	21	#define PTE_FLAGS_OFFSET 0
	22	#endif
	23
e1240122 YT	24	#ifdef CONFIG_PPC_256K_PAGES
	25	#define PTE_SHIFT (PAGE_SHIFT - PTE_T_LOG2 - 2) /* 1/4 of a page */
	26	#else
ca9153a3	27	#define PTE_SHIFT (PAGE_SHIFT - PTE_T_LOG2) /* full page */
e1240122	28	#endif
ca9153a3	29
5cd16ee9 ME	30	#ifndef __ASSEMBLY__
	31	/*
	32	* The basic type of a PTE - 64 bits for those CPUs with > 32 bit
4ee7084e	33	* physical addressing.
5cd16ee9 ME	34	*/
	35	#ifdef CONFIG_PTE_64BIT
	36	typedef unsigned long long pte_basic_t;
5cd16ee9 ME	37	#else
5cd16ee9 ME	38	typedef unsigned long pte_basic_t;
5cd16ee9 ME	39	#endif
5cd16ee9 ME	40
5736f96d CL	41	/*
	42	* Clear page using the dcbz instruction, which doesn't cause any
	43	* memory traffic (except to write out any cache lines which get
	44	* displaced). This only works on cacheable memory.
	45	*/
	46	static inline void clear_page(void *addr)
	47	{
	48	unsigned int i;
	49
	50	for (i = 0; i < PAGE_SIZE / L1_CACHE_BYTES; i++, addr += L1_CACHE_BYTES)
	51	dcbz(addr);
	52	}
5cd16ee9 ME	53	extern void copy_page(void to, void from);
5cd16ee9 ME	54
5b17e1cd	55	#include <asm-generic/getorder.h>
5cd16ee9	56
ca9153a3 IY	57	#define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1)
	58	#define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1)
	59
5cd16ee9 ME	60	#endif /* __ASSEMBLY__ */
	61
	62	#endif /* _ASM_POWERPC_PAGE_32_H */