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a1110654 SW |
1 | /* |
2 | * Performance event support - PowerPC classic/server specific definitions. | |
3 | * | |
4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/types.h> | |
13 | #include <asm/hw_irq.h> | |
1c53a270 | 14 | #include <linux/device.h> |
8d7c55d0 | 15 | #include <uapi/asm/perf_event.h> |
a1110654 | 16 | |
5f6d0380 | 17 | /* Update perf_event_print_debug() if this changes */ |
a1110654 SW |
18 | #define MAX_HWEVENTS 8 |
19 | #define MAX_EVENT_ALTERNATIVES 8 | |
20 | #define MAX_LIMITED_HWCOUNTERS 2 | |
21 | ||
8abd818f ME |
22 | struct perf_event; |
23 | ||
a1110654 SW |
24 | /* |
25 | * This struct provides the constants and functions needed to | |
26 | * describe the PMU on a particular POWER-family CPU. | |
27 | */ | |
28 | struct power_pmu { | |
29 | const char *name; | |
30 | int n_counter; | |
31 | int max_alternatives; | |
32 | unsigned long add_fields; | |
33 | unsigned long test_adder; | |
34 | int (*compute_mmcr)(u64 events[], int n_ev, | |
8abd818f ME |
35 | unsigned int hwc[], unsigned long mmcr[], |
36 | struct perf_event *pevents[]); | |
a1110654 SW |
37 | int (*get_constraint)(u64 event_id, unsigned long *mskp, |
38 | unsigned long *valp); | |
39 | int (*get_alternatives)(u64 event_id, unsigned int flags, | |
40 | u64 alt[]); | |
5afc9b52 AK |
41 | u64 (*bhrb_filter_map)(u64 branch_sample_type); |
42 | void (*config_bhrb)(u64 pmu_bhrb_filter); | |
a1110654 SW |
43 | void (*disable_pmc)(unsigned int pmc, unsigned long mmcr[]); |
44 | int (*limited_pmc_event)(u64 event_id); | |
45 | u32 flags; | |
1c53a270 | 46 | const struct attribute_group **attr_groups; |
a1110654 SW |
47 | int n_generic; |
48 | int *generic_events; | |
49 | int (*cache_events)[PERF_COUNT_HW_CACHE_MAX] | |
50 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
51 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
5afc9b52 AK |
52 | |
53 | /* BHRB entries in the PMU */ | |
54 | int bhrb_nr; | |
a1110654 SW |
55 | }; |
56 | ||
57 | /* | |
58 | * Values for power_pmu.flags | |
59 | */ | |
6f79cb81 AK |
60 | #define PPMU_LIMITED_PMC5_6 0x00000001 /* PMC5/6 have limited function */ |
61 | #define PPMU_ALT_SIPR 0x00000002 /* uses alternate posn for SIPR/HV */ | |
62 | #define PPMU_NO_SIPR 0x00000004 /* no SIPR/HV in MMCRA at all */ | |
63 | #define PPMU_NO_CONT_SAMPLING 0x00000008 /* no continuous sampling */ | |
64 | #define PPMU_SIAR_VALID 0x00000010 /* Processor has SIAR Valid bit */ | |
7a786832 | 65 | #define PPMU_HAS_SSLOT 0x00000020 /* Has sampled slot in MMCRA */ |
8f61aa32 | 66 | #define PPMU_HAS_SIER 0x00000040 /* Has SIER */ |
4d9690dd | 67 | #define PPMU_ARCH_207S 0x00000080 /* PMC is architecture v2.07S */ |
a1110654 SW |
68 | |
69 | /* | |
70 | * Values for flags to get_alternatives() | |
71 | */ | |
72 | #define PPMU_LIMITED_PMC_OK 1 /* can put this on a limited PMC */ | |
73 | #define PPMU_LIMITED_PMC_REQD 2 /* have to put this on a limited PMC */ | |
74 | #define PPMU_ONLY_COUNT_RUN 4 /* only counting in run state */ | |
75 | ||
76 | extern int register_power_pmu(struct power_pmu *); | |
77 | ||
78 | struct pt_regs; | |
79 | extern unsigned long perf_misc_flags(struct pt_regs *regs); | |
80 | extern unsigned long perf_instruction_pointer(struct pt_regs *regs); | |
3925f46b | 81 | extern unsigned long int read_bhrb(int n); |
a1110654 | 82 | |
a1110654 SW |
83 | /* |
84 | * Only override the default definitions in include/linux/perf_event.h | |
85 | * if we have hardware PMU support. | |
86 | */ | |
87 | #ifdef CONFIG_PPC_PERF_CTRS | |
88 | #define perf_misc_flags(regs) perf_misc_flags(regs) | |
89 | #endif | |
90 | ||
91 | /* | |
92 | * The power_pmu.get_constraint function returns a 32/64-bit value and | |
93 | * a 32/64-bit mask that express the constraints between this event_id and | |
94 | * other events. | |
95 | * | |
96 | * The value and mask are divided up into (non-overlapping) bitfields | |
97 | * of three different types: | |
98 | * | |
99 | * Select field: this expresses the constraint that some set of bits | |
100 | * in MMCR* needs to be set to a specific value for this event_id. For a | |
101 | * select field, the mask contains 1s in every bit of the field, and | |
102 | * the value contains a unique value for each possible setting of the | |
103 | * MMCR* bits. The constraint checking code will ensure that two events | |
104 | * that set the same field in their masks have the same value in their | |
105 | * value dwords. | |
106 | * | |
107 | * Add field: this expresses the constraint that there can be at most | |
108 | * N events in a particular class. A field of k bits can be used for | |
109 | * N <= 2^(k-1) - 1. The mask has the most significant bit of the field | |
110 | * set (and the other bits 0), and the value has only the least significant | |
111 | * bit of the field set. In addition, the 'add_fields' and 'test_adder' | |
112 | * in the struct power_pmu for this processor come into play. The | |
113 | * add_fields value contains 1 in the LSB of the field, and the | |
114 | * test_adder contains 2^(k-1) - 1 - N in the field. | |
115 | * | |
116 | * NAND field: this expresses the constraint that you may not have events | |
117 | * in all of a set of classes. (For example, on PPC970, you can't select | |
118 | * events from the FPU, ISU and IDU simultaneously, although any two are | |
119 | * possible.) For N classes, the field is N+1 bits wide, and each class | |
120 | * is assigned one bit from the least-significant N bits. The mask has | |
121 | * only the most-significant bit set, and the value has only the bit | |
122 | * for the event_id's class set. The test_adder has the least significant | |
123 | * bit set in the field. | |
124 | * | |
125 | * If an event_id is not subject to the constraint expressed by a particular | |
126 | * field, then it will have 0 in both the mask and value for that field. | |
127 | */ | |
1c53a270 SB |
128 | |
129 | extern ssize_t power_events_sysfs_show(struct device *dev, | |
130 | struct device_attribute *attr, char *page); | |
131 | ||
132 | /* | |
133 | * EVENT_VAR() is same as PMU_EVENT_VAR with a suffix. | |
134 | * | |
135 | * Having a suffix allows us to have aliases in sysfs - eg: the generic | |
136 | * event 'cpu-cycles' can have two entries in sysfs: 'cpu-cycles' and | |
137 | * 'PM_CYC' where the latter is the name by which the event is known in | |
138 | * POWER CPU specification. | |
e0728b50 SB |
139 | * |
140 | * Similarly, some hardware and cache events use the same event code. Eg. | |
141 | * on POWER8, both "cache-references" and "L1-dcache-loads" events refer | |
142 | * to the same event, PM_LD_REF_L1. The suffix, allows us to have two | |
143 | * sysfs objects for the same event and thus two entries/aliases in sysfs. | |
1c53a270 SB |
144 | */ |
145 | #define EVENT_VAR(_id, _suffix) event_attr_##_id##_suffix | |
f2b4367a | 146 | #define EVENT_PTR(_id, _suffix) &EVENT_VAR(_id, _suffix).attr.attr |
1c53a270 SB |
147 | |
148 | #define EVENT_ATTR(_name, _id, _suffix) \ | |
d4969e24 | 149 | PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), _id, \ |
1c53a270 SB |
150 | power_events_sysfs_show) |
151 | ||
152 | #define GENERIC_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _g) | |
153 | #define GENERIC_EVENT_PTR(_id) EVENT_PTR(_id, _g) | |
886c3b2d | 154 | |
e0728b50 SB |
155 | #define CACHE_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _c) |
156 | #define CACHE_EVENT_PTR(_id) EVENT_PTR(_id, _c) | |
157 | ||
cfe0d8ba | 158 | #define POWER_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _p) |
886c3b2d | 159 | #define POWER_EVENT_PTR(_id) EVENT_PTR(_id, _p) |