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powerpc: modules: implement stubs for ELFv2 ABI.
[deliverable/linux.git] / arch / powerpc / include / asm / ppc_asm.h
CommitLineData
1da177e4 1/*
1da177e4 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
1da177e4 3 */
5f7c6907
KG		 4#ifndef _ASM_POWERPC_PPC_ASM_H
5#define _ASM_POWERPC_PPC_ASM_H
6
40ef8cbc 7#include <linux/stringify.h>
3ddfbcf1 8#include <asm/asm-compat.h>
9c75a31c 9#include <asm/processor.h>
16c57b36 10#include <asm/ppc-opcode.h>
cf9efce0 11#include <asm/firmware.h>
40ef8cbc 12
3ddfbcf1
DG		 13#ifndef __ASSEMBLY__
14#error __FILE__ should only be used in assembler files
15#else
16
17#define SZL (BITS_PER_LONG/8)
1da177e4 18
c6622f63
PM		 19/*
20 * Stuff for accurate CPU time accounting.
21 * These macros handle transitions between user and system state
22 * in exception entry and exit and accumulate time to the
23 * user_time and system_time fields in the paca.
24 */
25
abf917cd 26#ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
c6622f63
PM		 27#define ACCOUNT_CPU_USER_ENTRY(ra, rb)
28#define ACCOUNT_CPU_USER_EXIT(ra, rb)
cf9efce0 29#define ACCOUNT_STOLEN_TIME
c6622f63
PM		 30#else
31#define ACCOUNT_CPU_USER_ENTRY(ra, rb) \
cf9efce0
PM		 32 MFTB(ra); /* get timebase */ \
33 ld rb,PACA_STARTTIME_USER(r13); \
34 std ra,PACA_STARTTIME(r13); \
c6622f63
PM		 35 subf rb,rb,ra; /* subtract start value */ \
36 ld ra,PACA_USER_TIME(r13); \
37 add ra,ra,rb; /* add on to user time */ \
38 std ra,PACA_USER_TIME(r13); \
c6622f63
PM		 39
40#define ACCOUNT_CPU_USER_EXIT(ra, rb) \
cf9efce0
PM		 41 MFTB(ra); /* get timebase */ \
42 ld rb,PACA_STARTTIME(r13); \
43 std ra,PACA_STARTTIME_USER(r13); \
c6622f63
PM		 44 subf rb,rb,ra; /* subtract start value */ \
45 ld ra,PACA_SYSTEM_TIME(r13); \
cf9efce0
PM		 46 add ra,ra,rb; /* add on to system time */ \
47 std ra,PACA_SYSTEM_TIME(r13)
48
49#ifdef CONFIG_PPC_SPLPAR
50#define ACCOUNT_STOLEN_TIME \
51BEGIN_FW_FTR_SECTION; \
52 beq 33f; \
53 /* from user - see if there are any DTL entries to process */ \
54 ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \
55 ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \
7ffcf8ec
AB		 56 addi r10,r10,LPPACA_DTLIDX; \
57 LDX_BE r10,0,r10; /* get log write index */ \
cf9efce0
PM		 58 cmpd cr1,r11,r10; \
59 beq+ cr1,33f; \
b1576fec 60 bl accumulate_stolen_time; \
990118c8
BH		 61 ld r12,_MSR(r1); \
62 andi. r10,r12,MSR_PR; /* Restore cr0 (coming from user) */ \
cf9efce0
PM		 6333: \
64END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
65
66#else /* CONFIG_PPC_SPLPAR */
67#define ACCOUNT_STOLEN_TIME
68
69#endif /* CONFIG_PPC_SPLPAR */
70
abf917cd 71#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
c6622f63 72
1da177e4
LT		 73/*
74 * Macros for storing registers into and loading registers from
75 * exception frames.
76 */
5f7c6907
KG		 77#ifdef __powerpc64__
78#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
79#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
80#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
81#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
82#else
1da177e4 83#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
5f7c6907
KG		 84#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
85#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
86 SAVE_10GPRS(22, base)
87#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
88 REST_10GPRS(22, base)
89#endif
90
1da177e4
LT		 91#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
92#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
93#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
94#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
1da177e4
LT		 95#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
96#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
97#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
98#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
99
de79f7b9 100#define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base)
1da177e4
LT		 101#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
102#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
103#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
104#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
105#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
de79f7b9 106#define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base)
1da177e4
LT		 107#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
108#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
109#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
110#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
111#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
112
de79f7b9 113#define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b
5f7c6907
KG		 114#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
115#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
116#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
117#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
118#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
de79f7b9 119#define REST_VR(n,b,base) li b,16*(n); lvx n,base,b
5f7c6907
KG		 120#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
121#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
122#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
123#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
124#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
1da177e4 125
926f160f
AB		 126#ifdef __BIG_ENDIAN__
127#define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base)
128#define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base)
129#else
130#define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \
131 STXVD2X(n,b,base); \
132 XXSWAPD(n,n)
133
134#define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \
135 XXSWAPD(n,n)
136#endif
72ffff5b 137/* Save the lower 32 VSRs in the thread VSR region */
3ad26e5c 138#define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b)
72ffff5b
MN		 139#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
140#define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
141#define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
142#define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
143#define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
3ad26e5c 144#define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b)
72ffff5b
MN		 145#define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
146#define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
147#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
148#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
149#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
72ffff5b 150
c51584d5
SW		 151/*
152 * b = base register for addressing, o = base offset from register of 1st EVR
153 * n = first EVR, s = scratch
154 */
155#define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b)
156#define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o)
157#define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o)
158#define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o)
159#define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o)
160#define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o)
161#define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n
162#define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o)
163#define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o)
164#define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o)
165#define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o)
166#define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o)
5f7c6907 167
8c71632f
ME		 168/* Macros to adjust thread priority for hardware multithreading */
169#define HMT_VERY_LOW or 31,31,31 # very low priority
170#define HMT_LOW or 1,1,1
171#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
172#define HMT_MEDIUM or 2,2,2
173#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
174#define HMT_HIGH or 3,3,3
50fb8ebe 175#define HMT_EXTRA_HIGH or 7,7,7 # power7 only
5f7c6907 176
d72be892
MN		 177#ifdef CONFIG_PPC64
178#define ULONG_SIZE 8
179#else
180#define ULONG_SIZE 4
181#endif
0b7673c3
MN		 182#define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
183#define VCPU_GPR(n) __VCPU_GPR(__REG_##n)
d72be892 184
88ced031 185#ifdef __KERNEL__
40ef8cbc
PM		 186#ifdef CONFIG_PPC64
187
44ce6a5e 188#define STACKFRAMESIZE 256
0b7673c3
MN		 189#define __STK_REG(i) (112 + ((i)-14)*8)
190#define STK_REG(i) __STK_REG(__REG_##i)
44ce6a5e 191
b37c10d1 192#if defined(_CALL_ELF) && _CALL_ELF == 2
6403105b 193#define STK_GOT 24
b37c10d1
AB		 194#define __STK_PARAM(i) (32 + ((i)-3)*8)
195#else
6403105b 196#define STK_GOT 40
0b7673c3 197#define __STK_PARAM(i) (48 + ((i)-3)*8)
b37c10d1 198#endif
0b7673c3 199#define STK_PARAM(i) __STK_PARAM(__REG_##i)
44ce6a5e 200
7167af7c
AB		 201#if defined(_CALL_ELF) && _CALL_ELF == 2
202
203#define _GLOBAL(name) \
204 .section ".text"; \
205 .align 2 ; \
206 .type name,@function; \
207 .globl name; \
208name:
209
210#define _KPROBE(name) \
211 .section ".kprobes.text","a"; \
212 .align 2 ; \
213 .type name,@function; \
214 .globl name; \
215name:
216
217#define DOTSYM(a) a
218
219#else
220
40ef8cbc
PM		 221#define XGLUE(a,b) a##b
222#define GLUE(a,b) XGLUE(a,b)
223
224#define _GLOBAL(name) \
225 .section ".text"; \
226 .align 2 ; \
227 .globl name; \
228 .globl GLUE(.,name); \
229 .section ".opd","aw"; \
230name: \
231 .quad GLUE(.,name); \
232 .quad .TOC.@tocbase; \
233 .quad 0; \
234 .previous; \
235 .type GLUE(.,name),@function; \
236GLUE(.,name):
237
238#define _KPROBE(name) \
239 .section ".kprobes.text","a"; \
240 .align 2 ; \
241 .globl name; \
242 .globl GLUE(.,name); \
243 .section ".opd","aw"; \
244name: \
245 .quad GLUE(.,name); \
246 .quad .TOC.@tocbase; \
247 .quad 0; \
248 .previous; \
249 .type GLUE(.,name),@function; \
250GLUE(.,name):
251
c1fb0194
AB		 252#define DOTSYM(a) GLUE(.,a)
253
7167af7c
AB		 254#endif
255
40ef8cbc
PM		 256#else /* 32-bit */
257
748a7683
KG		 258#define _ENTRY(n) \
259 .globl n; \
260n:
261
40ef8cbc
PM		 262#define _GLOBAL(n) \
263 .text; \
264 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
265 .globl n; \
266n:
267
268#define _KPROBE(n) \
269 .section ".kprobes.text","a"; \
270 .globl n; \
271n:
272
273#endif
274
5f7c6907 275/*
e58c3495
DG		 276 * LOAD_REG_IMMEDIATE(rn, expr)
277 * Loads the value of the constant expression 'expr' into register 'rn'
278 * using immediate instructions only. Use this when it's important not
279 * to reference other data (i.e. on ppc64 when the TOC pointer is not
e31aa453 280 * valid) and when 'expr' is a constant or absolute address.
5f7c6907 281 *
e58c3495
DG		 282 * LOAD_REG_ADDR(rn, name)
283 * Loads the address of label 'name' into register 'rn'. Use this when
284 * you don't particularly need immediate instructions only, but you need
285 * the whole address in one register (e.g. it's a structure address and
286 * you want to access various offsets within it). On ppc32 this is
287 * identical to LOAD_REG_IMMEDIATE.
288 *
1c49abec
KH		 289 * LOAD_REG_ADDR_PIC(rn, name)
290 * Loads the address of label 'name' into register 'run'. Use this when
291 * the kernel doesn't run at the linked or relocated address. Please
292 * note that this macro will clobber the lr register.
293 *
e58c3495
DG		 294 * LOAD_REG_ADDRBASE(rn, name)
295 * ADDROFF(name)
296 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
297 * register 'rn'. ADDROFF(name) returns the remainder of the address as
298 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
299 * in size, so is suitable for use directly as an offset in load and store
300 * instructions. Use this when loading/storing a single word or less as:
301 * LOAD_REG_ADDRBASE(rX, name)
302 * ld rY,ADDROFF(name)(rX)
5f7c6907 303 */
1c49abec
KH		 304
305/* Be careful, this will clobber the lr register. */
306#define LOAD_REG_ADDR_PIC(reg, name) \
307 bl 0f; \
3080: mflr reg; \
309 addis reg,reg,(name - 0b)@ha; \
310 addi reg,reg,(name - 0b)@l;
311
5f7c6907 312#ifdef __powerpc64__
e58c3495 313#define LOAD_REG_IMMEDIATE(reg,expr) \
564aa5cf
MN		 314 lis reg,(expr)@highest; \
315 ori reg,reg,(expr)@higher; \
316 rldicr reg,reg,32,31; \
317 oris reg,reg,(expr)@h; \
318 ori reg,reg,(expr)@l;
e58c3495
DG		 319
320#define LOAD_REG_ADDR(reg,name) \
564aa5cf 321 ld reg,name@got(r2)
e58c3495
DG		 322
323#define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
324#define ADDROFF(name) 0
b85a046a 325
f78541dc
PM		 326/* offsets for stack frame layout */
327#define LRSAVE 16
b85a046a
PM		 328
329#else /* 32-bit */
70620186 330
e58c3495 331#define LOAD_REG_IMMEDIATE(reg,expr) \
564aa5cf
MN		 332 lis reg,(expr)@ha; \
333 addi reg,reg,(expr)@l;
e58c3495
DG		 334
335#define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name)
b85a046a 336
564aa5cf 337#define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha
e58c3495 338#define ADDROFF(name) name@l
b85a046a 339
f78541dc
PM		 340/* offsets for stack frame layout */
341#define LRSAVE 4
b85a046a 342
5f7c6907 343#endif
1da177e4 344
5f7c6907 345/* various errata or part fixups */
1da177e4
LT		 346#ifdef CONFIG_PPC601_SYNC_FIX
347#define SYNC \
348BEGIN_FTR_SECTION \
349 sync; \
350 isync; \
351END_FTR_SECTION_IFSET(CPU_FTR_601)
352#define SYNC_601 \
353BEGIN_FTR_SECTION \
354 sync; \
355END_FTR_SECTION_IFSET(CPU_FTR_601)
356#define ISYNC_601 \
357BEGIN_FTR_SECTION \
358 isync; \
359END_FTR_SECTION_IFSET(CPU_FTR_601)
360#else
361#define SYNC
362#define SYNC_601
363#define ISYNC_601
364#endif
365
d52459ca 366#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
859deea9 367#define MFTB(dest) \
beb2dc0a 36890: mfspr dest, SPRN_TBRL; \
859deea9
BH		 369BEGIN_FTR_SECTION_NESTED(96); \
370 cmpwi dest,0; \
371 beq- 90b; \
372END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
ae2163be
LC		 373#elif defined(CONFIG_8xx)
374#define MFTB(dest) mftb dest
859deea9 375#else
beb2dc0a 376#define MFTB(dest) mfspr dest, SPRN_TBRL
859deea9 377#endif
5f7c6907 378
1da177e4
LT		 379#ifndef CONFIG_SMP
380#define TLBSYNC
381#else /* CONFIG_SMP */
382/* tlbsync is not implemented on 601 */
383#define TLBSYNC \
384BEGIN_FTR_SECTION \
385 tlbsync; \
386 sync; \
387END_FTR_SECTION_IFCLR(CPU_FTR_601)
388#endif
389
694caf02
AB		 390#ifdef CONFIG_PPC64
391#define MTOCRF(FXM, RS) \
392 BEGIN_FTR_SECTION_NESTED(848); \
86e32fdc 393 mtcrf (FXM), RS; \
694caf02 394 FTR_SECTION_ELSE_NESTED(848); \
86e32fdc 395 mtocrf (FXM), RS; \
694caf02 396 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
13e7a8e8
HM		 397
398/*
399 * PPR restore macros used in entry_64.S
400 * Used for P7 or later processors
401 */
402#define HMT_MEDIUM_LOW_HAS_PPR \
403BEGIN_FTR_SECTION_NESTED(944) \
404 HMT_MEDIUM_LOW; \
405END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,944)
406
407#define SET_DEFAULT_THREAD_PPR(ra, rb) \
408BEGIN_FTR_SECTION_NESTED(945) \
409 lis ra,INIT_PPR@highest; /* default ppr=3 */ \
410 ld rb,PACACURRENT(r13); \
411 sldi ra,ra,32; /* 11- 13 bits are used for ppr */ \
412 std ra,TASKTHREADPPR(rb); \
413END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,945)
414
694caf02
AB		 415#endif
416
1da177e4
LT		 417/*
418 * This instruction is not implemented on the PPC 603 or 601; however, on
419 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
420 * All of these instructions exist in the 8xx, they have magical powers,
421 * and they must be used.
422 */
423
424#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
425#define tlbia \
426 li r4,1024; \
427 mtctr r4; \
428 lis r4,KERNELBASE@h; \
4290: tlbie r4; \
430 addi r4,r4,0x1000; \
431 bdnz 0b
432#endif
433
5f7c6907 434
5f7c6907
KG		 435#ifdef CONFIG_IBM440EP_ERR42
436#define PPC440EP_ERR42 isync
437#else
438#define PPC440EP_ERR42
439#endif
440
a515348f
MN		 441/* The following stops all load and store data streams associated with stream
442 * ID (ie. streams created explicitly). The embedded and server mnemonics for
443 * dcbt are different so we use machine "power4" here explicitly.
444 */
445#define DCBT_STOP_ALL_STREAM_IDS(scratch) \
446.machine push ; \
447.machine "power4" ; \
448 lis scratch,0x60000000@h; \
449 dcbt r0,scratch,0b01010; \
450.machine pop
451
44c58ccc
BH		 452/*
453 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
454 * keep the address intact to be compatible with code shared with
455 * 32-bit classic.
456 *
457 * On the other hand, I find it useful to have them behave as expected
458 * by their name (ie always do the addition) on 64-bit BookE
459 */
460#if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
6316222e
PM		 461#define toreal(rd)
462#define fromreal(rd)
463
2ca7633d
RM		 464/*
465 * We use addis to ensure compatibility with the "classic" ppc versions of
466 * these macros, which use rs = 0 to get the tophys offset in rd, rather than
467 * converting the address in r0, and so this version has to do that too
468 * (i.e. set register rd to 0 when rs == 0).
469 */
1da177e4
LT		 470#define tophys(rd,rs) \
471 addis rd,rs,0
472
473#define tovirt(rd,rs) \
474 addis rd,rs,0
475
5f7c6907 476#elif defined(CONFIG_PPC64)
6316222e
PM		 477#define toreal(rd) /* we can access c000... in real mode */
478#define fromreal(rd)
479
5f7c6907 480#define tophys(rd,rs) \
6316222e 481 clrldi rd,rs,2
5f7c6907
KG		 482
483#define tovirt(rd,rs) \
6316222e
PM		 484 rotldi rd,rs,16; \
485 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
486 rotldi rd,rd,48
5f7c6907 487#else
1da177e4
LT		 488/*
489 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
490 * physical base address of RAM at compile time.
491 */
6316222e
PM		 492#define toreal(rd) tophys(rd,rd)
493#define fromreal(rd) tovirt(rd,rd)
494
1da177e4 495#define tophys(rd,rs) \
ccdcef72 4960: addis rd,rs,-PAGE_OFFSET@h; \
1da177e4
LT		 497 .section ".vtop_fixup","aw"; \
498 .align 1; \
499 .long 0b; \
500 .previous
501
502#define tovirt(rd,rs) \
ccdcef72 5030: addis rd,rs,PAGE_OFFSET@h; \
1da177e4
LT		 504 .section ".ptov_fixup","aw"; \
505 .align 1; \
506 .long 0b; \
507 .previous
5f7c6907 508#endif
1da177e4 509
44c58ccc 510#ifdef CONFIG_PPC_BOOK3S_64
40ef8cbc
PM		 511#define RFI rfid
512#define MTMSRD(r) mtmsrd r
b38c77d8 513#define MTMSR_EERI(reg) mtmsrd reg,1
1da177e4
LT		 514#else
515#define FIX_SRR1(ra, rb)
516#ifndef CONFIG_40x
517#define RFI rfi
518#else
519#define RFI rfi; b . /* Prevent prefetch past rfi */
520#endif
521#define MTMSRD(r) mtmsr r
b38c77d8 522#define MTMSR_EERI(reg) mtmsr reg
1da177e4 523#define CLR_TOP32(r)
c9cf73ae
MP		 524#endif
525
88ced031
AB		 526#endif /* __KERNEL__ */
527
1da177e4
LT		 528/* The boring bits... */
529
530/* Condition Register Bit Fields */
531
532#define cr0 0
533#define cr1 1
534#define cr2 2
535#define cr3 3
536#define cr4 4
537#define cr5 5
538#define cr6 6
539#define cr7 7
540
541
9a13a524
MN		 542/*
543 * General Purpose Registers (GPRs)
544 *
545 * The lower case r0-r31 should be used in preference to the upper
546 * case R0-R31 as they provide more error checking in the assembler.
547 * Use R0-31 only when really nessesary.
548 */
549
550#define r0 %r0
551#define r1 %r1
552#define r2 %r2
553#define r3 %r3
554#define r4 %r4
555#define r5 %r5
556#define r6 %r6
557#define r7 %r7
558#define r8 %r8
559#define r9 %r9
560#define r10 %r10
561#define r11 %r11
562#define r12 %r12
563#define r13 %r13
564#define r14 %r14
565#define r15 %r15
566#define r16 %r16
567#define r17 %r17
568#define r18 %r18
569#define r19 %r19
570#define r20 %r20
571#define r21 %r21
572#define r22 %r22
573#define r23 %r23
574#define r24 %r24
575#define r25 %r25
576#define r26 %r26
577#define r27 %r27
578#define r28 %r28
579#define r29 %r29
580#define r30 %r30
581#define r31 %r31
1da177e4
LT		 582
583
584/* Floating Point Registers (FPRs) */
585
586#define fr0 0
587#define fr1 1
588#define fr2 2
589#define fr3 3
590#define fr4 4
591#define fr5 5
592#define fr6 6
593#define fr7 7
594#define fr8 8
595#define fr9 9
596#define fr10 10
597#define fr11 11
598#define fr12 12
599#define fr13 13
600#define fr14 14
601#define fr15 15
602#define fr16 16
603#define fr17 17
604#define fr18 18
605#define fr19 19
606#define fr20 20
607#define fr21 21
608#define fr22 22
609#define fr23 23
610#define fr24 24
611#define fr25 25
612#define fr26 26
613#define fr27 27
614#define fr28 28
615#define fr29 29
616#define fr30 30
617#define fr31 31
618
5f7c6907
KG		 619/* AltiVec Registers (VPRs) */
620
1da177e4
LT		 621#define vr0 0
622#define vr1 1
623#define vr2 2
624#define vr3 3
625#define vr4 4
626#define vr5 5
627#define vr6 6
628#define vr7 7
629#define vr8 8
630#define vr9 9
631#define vr10 10
632#define vr11 11
633#define vr12 12
634#define vr13 13
635#define vr14 14
636#define vr15 15
637#define vr16 16
638#define vr17 17
639#define vr18 18
640#define vr19 19
641#define vr20 20
642#define vr21 21
643#define vr22 22
644#define vr23 23
645#define vr24 24
646#define vr25 25
647#define vr26 26
648#define vr27 27
649#define vr28 28
650#define vr29 29
651#define vr30 30
652#define vr31 31
653
72ffff5b
MN		 654/* VSX Registers (VSRs) */
655
656#define vsr0 0
657#define vsr1 1
658#define vsr2 2
659#define vsr3 3
660#define vsr4 4
661#define vsr5 5
662#define vsr6 6
663#define vsr7 7
664#define vsr8 8
665#define vsr9 9
666#define vsr10 10
667#define vsr11 11
668#define vsr12 12
669#define vsr13 13
670#define vsr14 14
671#define vsr15 15
672#define vsr16 16
673#define vsr17 17
674#define vsr18 18
675#define vsr19 19
676#define vsr20 20
677#define vsr21 21
678#define vsr22 22
679#define vsr23 23
680#define vsr24 24
681#define vsr25 25
682#define vsr26 26
683#define vsr27 27
684#define vsr28 28
685#define vsr29 29
686#define vsr30 30
687#define vsr31 31
688#define vsr32 32
689#define vsr33 33
690#define vsr34 34
691#define vsr35 35
692#define vsr36 36
693#define vsr37 37
694#define vsr38 38
695#define vsr39 39
696#define vsr40 40
697#define vsr41 41
698#define vsr42 42
699#define vsr43 43
700#define vsr44 44
701#define vsr45 45
702#define vsr46 46
703#define vsr47 47
704#define vsr48 48
705#define vsr49 49
706#define vsr50 50
707#define vsr51 51
708#define vsr52 52
709#define vsr53 53
710#define vsr54 54
711#define vsr55 55
712#define vsr56 56
713#define vsr57 57
714#define vsr58 58
715#define vsr59 59
716#define vsr60 60
717#define vsr61 61
718#define vsr62 62
719#define vsr63 63
720
5f7c6907
KG		 721/* SPE Registers (EVPRs) */
722
1da177e4
LT		 723#define evr0 0
724#define evr1 1
725#define evr2 2
726#define evr3 3
727#define evr4 4
728#define evr5 5
729#define evr6 6
730#define evr7 7
731#define evr8 8
732#define evr9 9
733#define evr10 10
734#define evr11 11
735#define evr12 12
736#define evr13 13
737#define evr14 14
738#define evr15 15
739#define evr16 16
740#define evr17 17
741#define evr18 18
742#define evr19 19
743#define evr20 20
744#define evr21 21
745#define evr22 22
746#define evr23 23
747#define evr24 24
748#define evr25 25
749#define evr26 26
750#define evr27 27
751#define evr28 28
752#define evr29 29
753#define evr30 30
754#define evr31 31
755
756/* some stab codes */
757#define N_FUN 36
758#define N_RSYM 64
759#define N_SLINE 68
760#define N_SO 100
5f7c6907 761
5c0484e2
BH		 762/*
763 * Create an endian fixup trampoline
764 *
765 * This starts with a "tdi 0,0,0x48" instruction which is
766 * essentially a "trap never", and thus akin to a nop.
767 *
768 * The opcode for this instruction read with the wrong endian
769 * however results in a b . + 8
770 *
771 * So essentially we use that trick to execute the following
772 * trampoline in "reverse endian" if we are running with the
773 * MSR_LE bit set the "wrong" way for whatever endianness the
774 * kernel is built for.
775 */
5f7c6907 776
5c0484e2
BH		 777#ifdef CONFIG_PPC_BOOK3E
778#define FIXUP_ENDIAN
779#else
780#define FIXUP_ENDIAN \
781 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
782 b $+36; /* Skip trampoline if endian is good */ \
783 .long 0x05009f42; /* bcl 20,31,$+4 */ \
784 .long 0xa602487d; /* mflr r10 */ \
785 .long 0x1c004a39; /* addi r10,r10,28 */ \
786 .long 0xa600607d; /* mfmsr r11 */ \
787 .long 0x01006b69; /* xori r11,r11,1 */ \
788 .long 0xa6035a7d; /* mtsrr0 r10 */ \
789 .long 0xa6037b7d; /* mtsrr1 r11 */ \
790 .long 0x2400004c /* rfid */
791#endif /* !CONFIG_PPC_BOOK3E */
792#endif /* __ASSEMBLY__ */
5f7c6907 793#endif /* _ASM_POWERPC_PPC_ASM_H */
Linux kernel - Deliverables
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