projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 82876526 BB |
1 | /* |
| 2 | * Contains register definitions common to the Book E PowerPC | |
| 3 | * specification. Notice that while the IBM-40x series of CPUs | |
| 4 | * are not true Book E PowerPCs, they borrowed a number of features | |
| 25985edc | 5 | * before Book E was finalized, and are included here as well. Unfortunately, |
| 82876526 | 6 | * they sometimes used different locations than true Book E CPUs did. |
| fe04b112 SW |
7 | * |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License version 2 | |
| 10 | * as published by the Free Software Foundation. | |
| 11 | * | |
| 12 | * Copyright 2009-2010 Freescale Semiconductor, Inc. | |
| 82876526 BB |
13 | */ |
| 14 | #ifdef __KERNEL__ | |
| 15 | #ifndef __ASM_POWERPC_REG_BOOKE_H__ | |
| 16 | #define __ASM_POWERPC_REG_BOOKE_H__ | |
| 17 | ||
| 82876526 | 18 | /* Machine State Register (MSR) Fields */ |
| 9dca4efe | 19 | #define MSR_GS (1<<28) /* Guest state */ |
| 82876526 BB |
20 | #define MSR_UCLE (1<<26) /* User-mode cache lock enable */ |
| 21 | #define MSR_SPE (1<<25) /* Enable SPE */ | |
| 22 | #define MSR_DWE (1<<10) /* Debug Wait Enable */ | |
| 23 | #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ | |
| 24 | #define MSR_IS MSR_IR /* Instruction Space */ | |
| 25 | #define MSR_DS MSR_DR /* Data Space */ | |
| 26 | #define MSR_PMM (1<<2) /* Performance monitor mark bit */ | |
| 0257c99c | 27 | #define MSR_CM (1<<31) /* Computation Mode (0=32-bit, 1=64-bit) */ |
| 82876526 | 28 | |
| 0257c99c | 29 | #if defined(CONFIG_PPC_BOOK3E_64) |
| 9d4a2925 ME |
30 | #define MSR_64BIT MSR_CM |
| 31 | ||
| 594bd383 AB |
32 | #define MSR_ (MSR_ME | MSR_CE) |
| 33 | #define MSR_KERNEL (MSR_ | MSR_64BIT) | |
| 34 | #define MSR_USER32 (MSR_ | MSR_PR | MSR_EE) | |
| 35 | #define MSR_USER64 (MSR_USER32 | MSR_64BIT) | |
| 0257c99c | 36 | #elif defined (CONFIG_40x) |
| 82876526 | 37 | #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE) |
| 0257c99c BH |
38 | #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) |
| 39 | #else | |
| 82876526 | 40 | #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE) |
| 0257c99c | 41 | #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) |
| 82876526 BB |
42 | #endif |
| 43 | ||
| 44 | /* Special Purpose Registers (SPRNs)*/ | |
| 45 | #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ | |
| 46 | #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ | |
| 47 | #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ | |
| 0257c99c | 48 | #define SPRN_SPRG3R 0x103 /* Special Purpose Register General 3 Read */ |
| 82876526 BB |
49 | #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ |
| 50 | #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ | |
| 51 | #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ | |
| 52 | #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ | |
| 53 | #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ | |
| 54 | #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ | |
| 55 | #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ | |
| 56 | #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ | |
| 0257c99c | 57 | #define SPRN_EPCR 0x133 /* Embedded Processor Control Register */ |
| 82876526 | 58 | #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ |
| ee53e560 | 59 | #define SPRN_DBCR4 0x233 /* Debug Control Register 4 */ |
| d30f6e48 | 60 | #define SPRN_MSRP 0x137 /* MSR Protect Register */ |
| 82876526 BB |
61 | #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ |
| 62 | #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ | |
| 63 | #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ | |
| 64 | #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ | |
| d30f6e48 | 65 | #define SPRN_LPID 0x152 /* Logical Partition ID */ |
| 0257c99c BH |
66 | #define SPRN_MAS8 0x155 /* MMU Assist Register 8 */ |
| 67 | #define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */ | |
| f0b8b341 | 68 | #define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */ |
| 0257c99c BH |
69 | #define SPRN_MAS5_MAS6 0x15c /* MMU Assist Register 5 || 6 */ |
| 70 | #define SPRN_MAS8_MAS1 0x15d /* MMU Assist Register 8 || 1 */ | |
| f2b26c92 | 71 | #define SPRN_EPTCFG 0x15e /* Embedded Page Table Config */ |
| d30f6e48 SW |
72 | #define SPRN_GSPRG0 0x170 /* Guest SPRG0 */ |
| 73 | #define SPRN_GSPRG1 0x171 /* Guest SPRG1 */ | |
| 74 | #define SPRN_GSPRG2 0x172 /* Guest SPRG2 */ | |
| 75 | #define SPRN_GSPRG3 0x173 /* Guest SPRG3 */ | |
| 0257c99c BH |
76 | #define SPRN_MAS7_MAS3 0x174 /* MMU Assist Register 7 || 3 */ |
| 77 | #define SPRN_MAS0_MAS1 0x175 /* MMU Assist Register 0 || 1 */ | |
| d30f6e48 SW |
78 | #define SPRN_GSRR0 0x17A /* Guest SRR0 */ |
| 79 | #define SPRN_GSRR1 0x17B /* Guest SRR1 */ | |
| 80 | #define SPRN_GEPR 0x17C /* Guest EPR */ | |
| 81 | #define SPRN_GDEAR 0x17D /* Guest DEAR */ | |
| 82 | #define SPRN_GPIR 0x17E /* Guest PIR */ | |
| 83 | #define SPRN_GESR 0x17F /* Guest Exception Syndrome Register */ | |
| 82876526 BB |
84 | #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ |
| 85 | #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ | |
| 86 | #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ | |
| 87 | #define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ | |
| 88 | #define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ | |
| 89 | #define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ | |
| 90 | #define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ | |
| 91 | #define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ | |
| 92 | #define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ | |
| 93 | #define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ | |
| 94 | #define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */ | |
| 95 | #define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */ | |
| 96 | #define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */ | |
| 97 | #define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */ | |
| 98 | #define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */ | |
| 99 | #define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */ | |
| 3a6e9bd7 SW |
100 | #define SPRN_IVOR38 0x1B0 /* Interrupt Vector Offset Register 38 */ |
| 101 | #define SPRN_IVOR39 0x1B1 /* Interrupt Vector Offset Register 39 */ | |
| 102 | #define SPRN_IVOR40 0x1B2 /* Interrupt Vector Offset Register 40 */ | |
| 103 | #define SPRN_IVOR41 0x1B3 /* Interrupt Vector Offset Register 41 */ | |
| 228b1a47 | 104 | #define SPRN_IVOR42 0x1B4 /* Interrupt Vector Offset Register 42 */ |
| d30f6e48 SW |
105 | #define SPRN_GIVOR2 0x1B8 /* Guest IVOR2 */ |
| 106 | #define SPRN_GIVOR3 0x1B9 /* Guest IVOR3 */ | |
| 107 | #define SPRN_GIVOR4 0x1BA /* Guest IVOR4 */ | |
| 108 | #define SPRN_GIVOR8 0x1BB /* Guest IVOR8 */ | |
| 109 | #define SPRN_GIVOR13 0x1BC /* Guest IVOR13 */ | |
| 110 | #define SPRN_GIVOR14 0x1BD /* Guest IVOR14 */ | |
| 111 | #define SPRN_GIVPR 0x1BF /* Guest IVPR */ | |
| 82876526 BB |
112 | #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ |
| 113 | #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ | |
| 114 | #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ | |
| fc4033b2 KG |
115 | #define SPRN_L1CFG0 0x203 /* L1 Cache Configure Register 0 */ |
| 116 | #define SPRN_L1CFG1 0x204 /* L1 Cache Configure Register 1 */ | |
| fd351b89 KG |
117 | #define SPRN_ATB 0x20E /* Alternate Time Base */ |
| 118 | #define SPRN_ATBL 0x20E /* Alternate Time Base Lower */ | |
| 119 | #define SPRN_ATBU 0x20F /* Alternate Time Base Upper */ | |
| 82876526 BB |
120 | #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ |
| 121 | #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ | |
| 122 | #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ | |
| 123 | #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ | |
| fd351b89 KG |
124 | #define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */ |
| 125 | #define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */ | |
| fe04b112 | 126 | #define SPRN_MCARU 0x239 /* Machine Check Address Register Upper */ |
| 82876526 BB |
127 | #define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */ |
| 128 | #define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ | |
| 129 | #define SPRN_MCSR 0x23C /* Machine Check Status Register */ | |
| 130 | #define SPRN_MCAR 0x23D /* Machine Check Address Register */ | |
| 131 | #define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */ | |
| 132 | #define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */ | |
| fd351b89 KG |
133 | #define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */ |
| 134 | #define SPRN_SPRG9 0x25D /* Special Purpose Register General 9 */ | |
| aba11fc5 | 135 | #define SPRN_L1CSR2 0x25E /* L1 Cache Control and Status Register 2 */ |
| 82876526 BB |
136 | #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ |
| 137 | #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ | |
| 138 | #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ | |
| 139 | #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ | |
| 140 | #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ | |
| 05e02d7f | 141 | #define SPRN_MAS5 0x153 /* MMU Assist Register 5 */ |
| 82876526 | 142 | #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ |
| 82876526 BB |
143 | #define SPRN_PID1 0x279 /* Process ID Register 1 */ |
| 144 | #define SPRN_PID2 0x27A /* Process ID Register 2 */ | |
| 145 | #define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ | |
| 146 | #define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ | |
| bb1af71e KG |
147 | #define SPRN_TLB2CFG 0x2B2 /* TLB 2 Config Register */ |
| 148 | #define SPRN_TLB3CFG 0x2B3 /* TLB 3 Config Register */ | |
| fd351b89 | 149 | #define SPRN_EPR 0x2BE /* External Proxy Register */ |
| 82876526 BB |
150 | #define SPRN_CCR1 0x378 /* Core Configuration Register 1 */ |
| 151 | #define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */ | |
| fd351b89 | 152 | #define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ |
| 82876526 BB |
153 | #define SPRN_MMUCR 0x3B2 /* MMU Control Register */ |
| 154 | #define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ | |
| fd351b89 KG |
155 | #define SPRN_EPLC 0x3B3 /* External Process ID Load Context */ |
| 156 | #define SPRN_EPSC 0x3B4 /* External Process ID Store Context */ | |
| 82876526 BB |
157 | #define SPRN_SGR 0x3B9 /* Storage Guarded Register */ |
| 158 | #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ | |
| 159 | #define SPRN_SLER 0x3BB /* Little-endian real mode */ | |
| 160 | #define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */ | |
| 161 | #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ | |
| 162 | #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ | |
| 163 | #define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ | |
| 164 | #define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ | |
| 165 | #define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ | |
| 0ba3418b | 166 | #define SPRN_MMUCSR0 0x3F4 /* MMU Control and Status Register 0 */ |
| 105c31df | 167 | #define SPRN_MMUCFG 0x3F7 /* MMU Configuration Register */ |
| 82876526 | 168 | #define SPRN_PIT 0x3DB /* Programmable Interval Timer */ |
| fd351b89 | 169 | #define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */ |
| aba11fc5 KG |
170 | #define SPRN_L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */ |
| 171 | #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */ | |
| 82876526 BB |
172 | #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ |
| 173 | #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ | |
| 174 | #define SPRN_SVR 0x3FF /* System Version Register */ | |
| 175 | ||
| 176 | /* | |
| 177 | * SPRs which have conflicting definitions on true Book E versus classic, | |
| 178 | * or IBM 40x. | |
| 179 | */ | |
| 180 | #ifdef CONFIG_BOOKE | |
| 82876526 BB |
181 | #define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */ |
| 182 | #define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */ | |
| 183 | #define SPRN_DEAR 0x03D /* Data Error Address Register */ | |
| 184 | #define SPRN_ESR 0x03E /* Exception Syndrome Register */ | |
| 185 | #define SPRN_PIR 0x11E /* Processor Identification Register */ | |
| 186 | #define SPRN_DBSR 0x130 /* Debug Status Register */ | |
| 187 | #define SPRN_DBCR0 0x134 /* Debug Control Register 0 */ | |
| 188 | #define SPRN_DBCR1 0x135 /* Debug Control Register 1 */ | |
| 189 | #define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */ | |
| 190 | #define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */ | |
| 191 | #define SPRN_DAC1 0x13C /* Data Address Compare 1 */ | |
| 192 | #define SPRN_DAC2 0x13D /* Data Address Compare 2 */ | |
| 193 | #define SPRN_TSR 0x150 /* Timer Status Register */ | |
| 194 | #define SPRN_TCR 0x154 /* Timer Control Register */ | |
| 195 | #endif /* Book E */ | |
| 196 | #ifdef CONFIG_40x | |
| 82876526 BB |
197 | #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ |
| 198 | #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ | |
| 199 | #define SPRN_DEAR 0x3D5 /* Data Error Address Register */ | |
| 200 | #define SPRN_TSR 0x3D8 /* Timer Status Register */ | |
| 201 | #define SPRN_TCR 0x3DA /* Timer Control Register */ | |
| 202 | #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ | |
| 203 | #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ | |
| 204 | #define SPRN_DBSR 0x3F0 /* Debug Status Register */ | |
| 205 | #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ | |
| 206 | #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ | |
| 207 | #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ | |
| 208 | #define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */ | |
| 209 | #define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */ | |
| 210 | #endif | |
| 211 | ||
| fac26ad4 JX |
212 | #ifdef CONFIG_PPC_ICSWX |
| 213 | #define SPRN_HACOP 0x15F /* Hypervisor Available Coprocessor Register */ | |
| 214 | #endif | |
| 215 | ||
| 82876526 BB |
216 | /* Bit definitions for CCR1. */ |
| 217 | #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ | |
| 218 | #define CCR1_TCS 0x00000080 /* Timer Clock Select */ | |
| 219 | ||
| 220 | /* Bit definitions for the MCSR. */ | |
| 82876526 BB |
221 | #define MCSR_MCS 0x80000000 /* Machine Check Summary */ |
| 222 | #define MCSR_IB 0x40000000 /* Instruction PLB Error */ | |
| 223 | #define MCSR_DRB 0x20000000 /* Data Read PLB Error */ | |
| 224 | #define MCSR_DWB 0x10000000 /* Data Write PLB Error */ | |
| 225 | #define MCSR_TLBP 0x08000000 /* TLB Parity Error */ | |
| 226 | #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ | |
| 227 | #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ | |
| 228 | #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ | |
| 229 | #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ | |
| 47c0bd1a | 230 | |
| e7f75ad0 DK |
231 | #define PPC47x_MCSR_GPR 0x01000000 /* GPR parity error */ |
| 232 | #define PPC47x_MCSR_FPR 0x00800000 /* FPR parity error */ | |
| 233 | #define PPC47x_MCSR_IPR 0x00400000 /* Imprecise Machine Check Exception */ | |
| 234 | ||
| 82876526 | 235 | #ifdef CONFIG_E500 |
| fe04b112 | 236 | /* All e500 */ |
| 82876526 BB |
237 | #define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ |
| 238 | #define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */ | |
| fe04b112 SW |
239 | |
| 240 | /* e500v1/v2 */ | |
| 82876526 BB |
241 | #define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */ |
| 242 | #define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */ | |
| 82876526 BB |
243 | #define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */ |
| 244 | #define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */ | |
| 245 | #define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */ | |
| 246 | #define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */ | |
| 247 | #define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */ | |
| 248 | #define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */ | |
| 249 | #define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */ | |
| 250 | #define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */ | |
| 86d7a9a9 | 251 | |
| fe04b112 SW |
252 | /* e500mc */ |
| 253 | #define MCSR_DCPERR_MC 0x20000000UL /* D-Cache Parity Error */ | |
| 254 | #define MCSR_L2MMU_MHIT 0x04000000UL /* Hit on multiple TLB entries */ | |
| 255 | #define MCSR_NMI 0x00100000UL /* Non-Maskable Interrupt */ | |
| 256 | #define MCSR_MAV 0x00080000UL /* MCAR address valid */ | |
| 257 | #define MCSR_MEA 0x00040000UL /* MCAR is effective address */ | |
| 258 | #define MCSR_IF 0x00010000UL /* Instruction Fetch */ | |
| 259 | #define MCSR_LD 0x00008000UL /* Load */ | |
| 260 | #define MCSR_ST 0x00004000UL /* Store */ | |
| 261 | #define MCSR_LDG 0x00002000UL /* Guarded Load */ | |
| 262 | #define MCSR_TLBSYNC 0x00000002UL /* Multiple tlbsyncs detected */ | |
| 263 | #define MCSR_BSL2_ERR 0x00000001UL /* Backside L2 cache error */ | |
| d30f6e48 SW |
264 | |
| 265 | #define MSRP_UCLEP 0x04000000 /* Protect MSR[UCLE] */ | |
| 266 | #define MSRP_DEP 0x00000200 /* Protect MSR[DE] */ | |
| 267 | #define MSRP_PMMP 0x00000004 /* Protect MSR[PMM] */ | |
| 82876526 | 268 | #endif |
| fe04b112 | 269 | |
| 82876526 BB |
270 | #ifdef CONFIG_E200 |
| 271 | #define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ | |
| 272 | #define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */ | |
| 273 | #define MCSR_CPERR 0x10000000UL /* Cache Parity Error */ | |
| 274 | #define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn | |
| 275 | fetch for an exception handler */ | |
| 276 | #define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/ | |
| 277 | #define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */ | |
| 278 | #define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered | |
| 279 | store or cache line push */ | |
| 280 | #endif | |
| 281 | ||
| 86985db6 LY |
282 | /* Bit definitions for the HID1 */ |
| 283 | #ifdef CONFIG_E500 | |
| 284 | /* e500v1/v2 */ | |
| 285 | #define HID1_PLL_CFG_MASK 0xfc000000 /* PLL_CFG input pins */ | |
| 286 | #define HID1_RFXE 0x00020000 /* Read fault exception enable */ | |
| 287 | #define HID1_R1DPE 0x00008000 /* R1 data bus parity enable */ | |
| 288 | #define HID1_R2DPE 0x00004000 /* R2 data bus parity enable */ | |
| 289 | #define HID1_ASTME 0x00002000 /* Address bus streaming mode enable */ | |
| 290 | #define HID1_ABE 0x00001000 /* Address broadcast enable */ | |
| 291 | #define HID1_MPXTT 0x00000400 /* MPX re-map transfer type */ | |
| 292 | #define HID1_ATS 0x00000080 /* Atomic status */ | |
| 293 | #define HID1_MID_MASK 0x0000000f /* MID input pins */ | |
| 294 | #endif | |
| 295 | ||
| 82876526 BB |
296 | /* Bit definitions for the DBSR. */ |
| 297 | /* | |
| 298 | * DBSR bits which have conflicting definitions on true Book E versus IBM 40x. | |
| 299 | */ | |
| 300 | #ifdef CONFIG_BOOKE | |
| 301 | #define DBSR_IC 0x08000000 /* Instruction Completion */ | |
| 302 | #define DBSR_BT 0x04000000 /* Branch Taken */ | |
| bccaea8f | 303 | #define DBSR_IRPT 0x02000000 /* Exception Debug Event */ |
| 82876526 BB |
304 | #define DBSR_TIE 0x01000000 /* Trap Instruction Event */ |
| 305 | #define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */ | |
| 306 | #define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */ | |
| 307 | #define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */ | |
| 308 | #define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */ | |
| 309 | #define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */ | |
| 310 | #define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */ | |
| 311 | #define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */ | |
| 312 | #define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */ | |
| bccaea8f JY |
313 | #define DBSR_RET 0x00008000 /* Return Debug Event */ |
| 314 | #define DBSR_CIRPT 0x00000040 /* Critical Interrupt Taken Event */ | |
| 315 | #define DBSR_CRET 0x00000020 /* Critical Return Debug Event */ | |
| 99396ac1 DK |
316 | #define DBSR_IAC12ATS 0x00000002 /* Instr Address Compare 1/2 Toggle */ |
| 317 | #define DBSR_IAC34ATS 0x00000001 /* Instr Address Compare 3/4 Toggle */ | |
| 82876526 BB |
318 | #endif |
| 319 | #ifdef CONFIG_40x | |
| 320 | #define DBSR_IC 0x80000000 /* Instruction Completion */ | |
| 321 | #define DBSR_BT 0x40000000 /* Branch taken */ | |
| bccaea8f | 322 | #define DBSR_IRPT 0x20000000 /* Exception Debug Event */ |
| 82876526 BB |
323 | #define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */ |
| 324 | #define DBSR_IAC1 0x04000000 /* Instruction Address Compare 1 Event */ | |
| 325 | #define DBSR_IAC2 0x02000000 /* Instruction Address Compare 2 Event */ | |
| 326 | #define DBSR_IAC3 0x00080000 /* Instruction Address Compare 3 Event */ | |
| 327 | #define DBSR_IAC4 0x00040000 /* Instruction Address Compare 4 Event */ | |
| 328 | #define DBSR_DAC1R 0x01000000 /* Data Address Compare 1 Read Event */ | |
| 329 | #define DBSR_DAC1W 0x00800000 /* Data Address Compare 1 Write Event */ | |
| 330 | #define DBSR_DAC2R 0x00400000 /* Data Address Compare 2 Read Event */ | |
| 331 | #define DBSR_DAC2W 0x00200000 /* Data Address Compare 2 Write Event */ | |
| 332 | #endif | |
| 333 | ||
| 334 | /* Bit definitions related to the ESR. */ | |
| 335 | #define ESR_MCI 0x80000000 /* Machine Check - Instruction */ | |
| 336 | #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ | |
| 337 | #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ | |
| 338 | #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ | |
| 339 | #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ | |
| 340 | #define ESR_PIL 0x08000000 /* Program Exception - Illegal */ | |
| 567e9fdd | 341 | #define ESR_PPR 0x04000000 /* Program Exception - Privileged */ |
| 82876526 BB |
342 | #define ESR_PTR 0x02000000 /* Program Exception - Trap */ |
| 343 | #define ESR_FP 0x01000000 /* Floating Point Operation */ | |
| 344 | #define ESR_DST 0x00800000 /* Storage Exception - Data miss */ | |
| 345 | #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ | |
| 346 | #define ESR_ST 0x00800000 /* Store Operation */ | |
| 347 | #define ESR_DLK 0x00200000 /* Data Cache Locking */ | |
| 348 | #define ESR_ILK 0x00100000 /* Instr. Cache Locking */ | |
| 349 | #define ESR_PUO 0x00040000 /* Unimplemented Operation exception */ | |
| 350 | #define ESR_BO 0x00020000 /* Byte Ordering */ | |
| 4cd35f67 | 351 | #define ESR_SPV 0x00000080 /* Signal Processing operation */ |
| 82876526 BB |
352 | |
| 353 | /* Bit definitions related to the DBCR0. */ | |
| bccaea8f | 354 | #if defined(CONFIG_40x) |
| 82876526 BB |
355 | #define DBCR0_EDM 0x80000000 /* External Debug Mode */ |
| 356 | #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ | |
| 357 | #define DBCR0_RST 0x30000000 /* all the bits in the RST field */ | |
| 358 | #define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */ | |
| 359 | #define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */ | |
| 360 | #define DBCR0_RST_CORE 0x10000000 /* Core Reset */ | |
| 361 | #define DBCR0_RST_NONE 0x00000000 /* No Reset */ | |
| 362 | #define DBCR0_IC 0x08000000 /* Instruction Completion */ | |
| bccaea8f | 363 | #define DBCR0_ICMP DBCR0_IC |
| 82876526 | 364 | #define DBCR0_BT 0x04000000 /* Branch Taken */ |
| bccaea8f | 365 | #define DBCR0_BRT DBCR0_BT |
| 82876526 | 366 | #define DBCR0_EDE 0x02000000 /* Exception Debug Event */ |
| bccaea8f | 367 | #define DBCR0_IRPT DBCR0_EDE |
| 82876526 BB |
368 | #define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ |
| 369 | #define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */ | |
| bccaea8f | 370 | #define DBCR0_IAC1 DBCR0_IA1 |
| 82876526 | 371 | #define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */ |
| bccaea8f | 372 | #define DBCR0_IAC2 DBCR0_IA2 |
| 82876526 BB |
373 | #define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */ |
| 374 | #define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */ | |
| 375 | #define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */ | |
| bccaea8f | 376 | #define DBCR0_IAC3 DBCR0_IA3 |
| 82876526 | 377 | #define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */ |
| bccaea8f | 378 | #define DBCR0_IAC4 DBCR0_IA4 |
| 82876526 BB |
379 | #define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */ |
| 380 | #define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */ | |
| 381 | #define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */ | |
| 382 | #define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */ | |
| 383 | #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ | |
| 99396ac1 | 384 | |
| 51ae8d4a | 385 | #define dbcr_iac_range(task) ((task)->thread.debug.dbcr0) |
| 99396ac1 DK |
386 | #define DBCR_IAC12I DBCR0_IA12 /* Range Inclusive */ |
| 387 | #define DBCR_IAC12X (DBCR0_IA12 | DBCR0_IA12X) /* Range Exclusive */ | |
| 388 | #define DBCR_IAC12MODE (DBCR0_IA12 | DBCR0_IA12X) /* IAC 1-2 Mode Bits */ | |
| 389 | #define DBCR_IAC34I DBCR0_IA34 /* Range Inclusive */ | |
| 390 | #define DBCR_IAC34X (DBCR0_IA34 | DBCR0_IA34X) /* Range Exclusive */ | |
| 391 | #define DBCR_IAC34MODE (DBCR0_IA34 | DBCR0_IA34X) /* IAC 3-4 Mode Bits */ | |
| 392 | ||
| 393 | /* Bit definitions related to the DBCR1. */ | |
| 394 | #define DBCR1_DAC1R 0x80000000 /* DAC1 Read Debug Event */ | |
| 395 | #define DBCR1_DAC2R 0x40000000 /* DAC2 Read Debug Event */ | |
| 396 | #define DBCR1_DAC1W 0x20000000 /* DAC1 Write Debug Event */ | |
| 397 | #define DBCR1_DAC2W 0x10000000 /* DAC2 Write Debug Event */ | |
| 398 | ||
| 51ae8d4a | 399 | #define dbcr_dac(task) ((task)->thread.debug.dbcr1) |
| 99396ac1 DK |
400 | #define DBCR_DAC1R DBCR1_DAC1R |
| 401 | #define DBCR_DAC1W DBCR1_DAC1W | |
| 402 | #define DBCR_DAC2R DBCR1_DAC2R | |
| 403 | #define DBCR_DAC2W DBCR1_DAC2W | |
| 404 | ||
| 405 | /* | |
| 406 | * Are there any active Debug Events represented in the | |
| 407 | * Debug Control Registers? | |
| 408 | */ | |
| 409 | #define DBCR0_ACTIVE_EVENTS (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \ | |
| 410 | DBCR0_IAC3 | DBCR0_IAC4) | |
| 411 | #define DBCR1_ACTIVE_EVENTS (DBCR1_DAC1R | DBCR1_DAC2R | \ | |
| 412 | DBCR1_DAC1W | DBCR1_DAC2W) | |
| 413 | #define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1) (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \ | |
| 414 | ((dbcr1) & DBCR1_ACTIVE_EVENTS)) | |
| 415 | ||
| bccaea8f JY |
416 | #elif defined(CONFIG_BOOKE) |
| 417 | #define DBCR0_EDM 0x80000000 /* External Debug Mode */ | |
| 418 | #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ | |
| 419 | #define DBCR0_RST 0x30000000 /* all the bits in the RST field */ | |
| 420 | /* DBCR0_RST_* is 44x specific and not followed in fsl booke */ | |
| 421 | #define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */ | |
| 422 | #define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */ | |
| 423 | #define DBCR0_RST_CORE 0x10000000 /* Core Reset */ | |
| 424 | #define DBCR0_RST_NONE 0x00000000 /* No Reset */ | |
| 425 | #define DBCR0_ICMP 0x08000000 /* Instruction Completion */ | |
| 426 | #define DBCR0_IC DBCR0_ICMP | |
| 427 | #define DBCR0_BRT 0x04000000 /* Branch Taken */ | |
| 428 | #define DBCR0_BT DBCR0_BRT | |
| 429 | #define DBCR0_IRPT 0x02000000 /* Exception Debug Event */ | |
| 430 | #define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ | |
| 431 | #define DBCR0_TIE DBCR0_TDE | |
| 432 | #define DBCR0_IAC1 0x00800000 /* Instr Addr compare 1 enable */ | |
| 433 | #define DBCR0_IAC2 0x00400000 /* Instr Addr compare 2 enable */ | |
| 434 | #define DBCR0_IAC3 0x00200000 /* Instr Addr compare 3 enable */ | |
| 435 | #define DBCR0_IAC4 0x00100000 /* Instr Addr compare 4 enable */ | |
| 436 | #define DBCR0_DAC1R 0x00080000 /* DAC 1 Read enable */ | |
| 437 | #define DBCR0_DAC1W 0x00040000 /* DAC 1 Write enable */ | |
| 438 | #define DBCR0_DAC2R 0x00020000 /* DAC 2 Read enable */ | |
| 439 | #define DBCR0_DAC2W 0x00010000 /* DAC 2 Write enable */ | |
| 440 | #define DBCR0_RET 0x00008000 /* Return Debug Event */ | |
| 441 | #define DBCR0_CIRPT 0x00000040 /* Critical Interrupt Taken Event */ | |
| 442 | #define DBCR0_CRET 0x00000020 /* Critical Return Debug Event */ | |
| 443 | #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ | |
| 444 | ||
| 51ae8d4a | 445 | #define dbcr_dac(task) ((task)->thread.debug.dbcr0) |
| 99396ac1 DK |
446 | #define DBCR_DAC1R DBCR0_DAC1R |
| 447 | #define DBCR_DAC1W DBCR0_DAC1W | |
| 448 | #define DBCR_DAC2R DBCR0_DAC2R | |
| 449 | #define DBCR_DAC2W DBCR0_DAC2W | |
| 450 | ||
| bccaea8f | 451 | /* Bit definitions related to the DBCR1. */ |
| 99396ac1 DK |
452 | #define DBCR1_IAC1US 0xC0000000 /* Instr Addr Cmp 1 Sup/User */ |
| 453 | #define DBCR1_IAC1ER 0x30000000 /* Instr Addr Cmp 1 Eff/Real */ | |
| 454 | #define DBCR1_IAC1ER_01 0x10000000 /* reserved */ | |
| 455 | #define DBCR1_IAC1ER_10 0x20000000 /* Instr Addr Cmp 1 Eff/Real MSR[IS]=0 */ | |
| 456 | #define DBCR1_IAC1ER_11 0x30000000 /* Instr Addr Cmp 1 Eff/Real MSR[IS]=1 */ | |
| 457 | #define DBCR1_IAC2US 0x0C000000 /* Instr Addr Cmp 2 Sup/User */ | |
| 458 | #define DBCR1_IAC2ER 0x03000000 /* Instr Addr Cmp 2 Eff/Real */ | |
| 459 | #define DBCR1_IAC2ER_01 0x01000000 /* reserved */ | |
| 460 | #define DBCR1_IAC2ER_10 0x02000000 /* Instr Addr Cmp 2 Eff/Real MSR[IS]=0 */ | |
| 461 | #define DBCR1_IAC2ER_11 0x03000000 /* Instr Addr Cmp 2 Eff/Real MSR[IS]=1 */ | |
| bccaea8f JY |
462 | #define DBCR1_IAC12M 0x00800000 /* Instr Addr 1-2 range enable */ |
| 463 | #define DBCR1_IAC12MX 0x00C00000 /* Instr Addr 1-2 range eXclusive */ | |
| 464 | #define DBCR1_IAC12AT 0x00010000 /* Instr Addr 1-2 range Toggle */ | |
| 99396ac1 DK |
465 | #define DBCR1_IAC3US 0x0000C000 /* Instr Addr Cmp 3 Sup/User */ |
| 466 | #define DBCR1_IAC3ER 0x00003000 /* Instr Addr Cmp 3 Eff/Real */ | |
| 467 | #define DBCR1_IAC3ER_01 0x00001000 /* reserved */ | |
| 468 | #define DBCR1_IAC3ER_10 0x00002000 /* Instr Addr Cmp 3 Eff/Real MSR[IS]=0 */ | |
| 469 | #define DBCR1_IAC3ER_11 0x00003000 /* Instr Addr Cmp 3 Eff/Real MSR[IS]=1 */ | |
| 470 | #define DBCR1_IAC4US 0x00000C00 /* Instr Addr Cmp 4 Sup/User */ | |
| 471 | #define DBCR1_IAC4ER 0x00000300 /* Instr Addr Cmp 4 Eff/Real */ | |
| 472 | #define DBCR1_IAC4ER_01 0x00000100 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */ | |
| 473 | #define DBCR1_IAC4ER_10 0x00000200 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */ | |
| 474 | #define DBCR1_IAC4ER_11 0x00000300 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=1 */ | |
| bccaea8f JY |
475 | #define DBCR1_IAC34M 0x00000080 /* Instr Addr 3-4 range enable */ |
| 476 | #define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */ | |
| 477 | #define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */ | |
| 478 | ||
| 51ae8d4a | 479 | #define dbcr_iac_range(task) ((task)->thread.debug.dbcr1) |
| 99396ac1 DK |
480 | #define DBCR_IAC12I DBCR1_IAC12M /* Range Inclusive */ |
| 481 | #define DBCR_IAC12X DBCR1_IAC12MX /* Range Exclusive */ | |
| 482 | #define DBCR_IAC12MODE DBCR1_IAC12MX /* IAC 1-2 Mode Bits */ | |
| 483 | #define DBCR_IAC34I DBCR1_IAC34M /* Range Inclusive */ | |
| 484 | #define DBCR_IAC34X DBCR1_IAC34MX /* Range Exclusive */ | |
| 485 | #define DBCR_IAC34MODE DBCR1_IAC34MX /* IAC 3-4 Mode Bits */ | |
| 486 | ||
| bccaea8f | 487 | /* Bit definitions related to the DBCR2. */ |
| 99396ac1 DK |
488 | #define DBCR2_DAC1US 0xC0000000 /* Data Addr Cmp 1 Sup/User */ |
| 489 | #define DBCR2_DAC1ER 0x30000000 /* Data Addr Cmp 1 Eff/Real */ | |
| 856f70a3 DK |
490 | #define DBCR2_DAC2US 0x0C000000 /* Data Addr Cmp 2 Sup/User */ |
| 491 | #define DBCR2_DAC2ER 0x03000000 /* Data Addr Cmp 2 Eff/Real */ | |
| bccaea8f | 492 | #define DBCR2_DAC12M 0x00800000 /* DAC 1-2 range enable */ |
| 99396ac1 | 493 | #define DBCR2_DAC12MM 0x00400000 /* DAC 1-2 Mask mode*/ |
| bccaea8f | 494 | #define DBCR2_DAC12MX 0x00C00000 /* DAC 1-2 range eXclusive */ |
| 99396ac1 | 495 | #define DBCR2_DAC12MODE 0x00C00000 /* DAC 1-2 Mode Bits */ |
| bccaea8f | 496 | #define DBCR2_DAC12A 0x00200000 /* DAC 1-2 Asynchronous */ |
| 99396ac1 DK |
497 | #define DBCR2_DVC1M 0x000C0000 /* Data Value Comp 1 Mode */ |
| 498 | #define DBCR2_DVC1M_SHIFT 18 /* # of bits to shift DBCR2_DVC1M */ | |
| 499 | #define DBCR2_DVC2M 0x00030000 /* Data Value Comp 2 Mode */ | |
| 500 | #define DBCR2_DVC2M_SHIFT 16 /* # of bits to shift DBCR2_DVC2M */ | |
| 501 | #define DBCR2_DVC1BE 0x00000F00 /* Data Value Comp 1 Byte */ | |
| 502 | #define DBCR2_DVC1BE_SHIFT 8 /* # of bits to shift DBCR2_DVC1BE */ | |
| 503 | #define DBCR2_DVC2BE 0x0000000F /* Data Value Comp 2 Byte */ | |
| 504 | #define DBCR2_DVC2BE_SHIFT 0 /* # of bits to shift DBCR2_DVC2BE */ | |
| 505 | ||
| 506 | /* | |
| 507 | * Are there any active Debug Events represented in the | |
| 508 | * Debug Control Registers? | |
| 509 | */ | |
| 510 | #define DBCR0_ACTIVE_EVENTS (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \ | |
| 511 | DBCR0_IAC3 | DBCR0_IAC4 | DBCR0_DAC1R | \ | |
| 512 | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W) | |
| 513 | #define DBCR1_ACTIVE_EVENTS 0 | |
| 514 | ||
| 515 | #define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1) (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \ | |
| 516 | ((dbcr1) & DBCR1_ACTIVE_EVENTS)) | |
| 517 | #endif /* #elif defined(CONFIG_BOOKE) */ | |
| 82876526 BB |
518 | |
| 519 | /* Bit definitions related to the TCR. */ | |
| 520 | #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ | |
| 521 | #define TCR_WP_MASK TCR_WP(3) | |
| 522 | #define WP_2_17 0 /* 2^17 clocks */ | |
| 523 | #define WP_2_21 1 /* 2^21 clocks */ | |
| 524 | #define WP_2_25 2 /* 2^25 clocks */ | |
| 525 | #define WP_2_29 3 /* 2^29 clocks */ | |
| 526 | #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ | |
| 527 | #define TCR_WRC_MASK TCR_WRC(3) | |
| 528 | #define WRC_NONE 0 /* No reset will occur */ | |
| 529 | #define WRC_CORE 1 /* Core reset will occur */ | |
| 530 | #define WRC_CHIP 2 /* Chip reset will occur */ | |
| 531 | #define WRC_SYSTEM 3 /* System reset will occur */ | |
| 532 | #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ | |
| 533 | #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ | |
| 534 | #define TCR_DIE TCR_PIE /* DEC Interrupt Enable */ | |
| 535 | #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ | |
| 536 | #define TCR_FP_MASK TCR_FP(3) | |
| 537 | #define FP_2_9 0 /* 2^9 clocks */ | |
| 538 | #define FP_2_13 1 /* 2^13 clocks */ | |
| 539 | #define FP_2_17 2 /* 2^17 clocks */ | |
| 540 | #define FP_2_21 3 /* 2^21 clocks */ | |
| 541 | #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ | |
| 542 | #define TCR_ARE 0x00400000 /* Auto Reload Enable */ | |
| 543 | ||
| f61c94bb BB |
544 | #ifdef CONFIG_E500 |
| 545 | #define TCR_GET_WP(tcr) ((((tcr) & 0xC0000000) >> 30) | \ | |
| 546 | (((tcr) & 0x1E0000) >> 15)) | |
| 547 | #else | |
| 548 | #define TCR_GET_WP(tcr) (((tcr) & 0xC0000000) >> 30) | |
| 549 | #endif | |
| 550 | ||
| 82876526 BB |
551 | /* Bit definitions for the TSR. */ |
| 552 | #define TSR_ENW 0x80000000 /* Enable Next Watchdog */ | |
| 553 | #define TSR_WIS 0x40000000 /* WDT Interrupt Status */ | |
| 554 | #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ | |
| 555 | #define WRS_NONE 0 /* No WDT reset occurred */ | |
| 556 | #define WRS_CORE 1 /* WDT forced core reset */ | |
| 557 | #define WRS_CHIP 2 /* WDT forced chip reset */ | |
| 558 | #define WRS_SYSTEM 3 /* WDT forced system reset */ | |
| 559 | #define TSR_PIS 0x08000000 /* PIT Interrupt Status */ | |
| 560 | #define TSR_DIS TSR_PIS /* DEC Interrupt Status */ | |
| 561 | #define TSR_FIS 0x04000000 /* FIT Interrupt Status */ | |
| 562 | ||
| 563 | /* Bit definitions for the DCCR. */ | |
| 564 | #define DCCR_NOCACHE 0 /* Noncacheable */ | |
| 565 | #define DCCR_CACHE 1 /* Cacheable */ | |
| 566 | ||
| 567 | /* Bit definitions for DCWR. */ | |
| 568 | #define DCWR_COPY 0 /* Copy-back */ | |
| 569 | #define DCWR_WRITE 1 /* Write-through */ | |
| 570 | ||
| 571 | /* Bit definitions for ICCR. */ | |
| 572 | #define ICCR_NOCACHE 0 /* Noncacheable */ | |
| 573 | #define ICCR_CACHE 1 /* Cacheable */ | |
| 574 | ||
| 575 | /* Bit definitions for L1CSR0. */ | |
| cab888e6 | 576 | #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ |
| 82876526 BB |
577 | #define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */ |
| 578 | #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ | |
| 579 | #define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */ | |
| 580 | #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ | |
| 581 | ||
| 582 | /* Bit definitions for L1CSR1. */ | |
| cab888e6 | 583 | #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ |
| 82876526 BB |
584 | #define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ |
| 585 | #define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ | |
| 586 | #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ | |
| 587 | ||
| 37caf9f2 KG |
588 | /* Bit definitions for L1CSR2. */ |
| 589 | #define L1CSR2_DCWS 0x40000000 /* Data Cache write shadow */ | |
| 590 | ||
| aba11fc5 KG |
591 | /* Bit definitions for L2CSR0. */ |
| 592 | #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ | |
| 593 | #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ | |
| 594 | #define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */ | |
| 595 | #define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */ | |
| 596 | #define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */ | |
| 597 | #define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */ | |
| 598 | #define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */ | |
| 599 | #define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */ | |
| 600 | #define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */ | |
| 601 | #define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */ | |
| 602 | #define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */ | |
| 603 | #define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */ | |
| 604 | ||
| 82876526 BB |
605 | /* Bit definitions for SGR. */ |
| 606 | #define SGR_NORMAL 0 /* Speculative fetching allowed. */ | |
| 607 | #define SGR_GUARDED 1 /* Speculative fetching disallowed. */ | |
| 608 | ||
| 0257c99c BH |
609 | /* Bit definitions for EPCR */ |
| 610 | #define SPRN_EPCR_EXTGS 0x80000000 /* External Input interrupt | |
| 611 | * directed to Guest state */ | |
| 612 | #define SPRN_EPCR_DTLBGS 0x40000000 /* Data TLB Error interrupt | |
| 613 | * directed to guest state */ | |
| 614 | #define SPRN_EPCR_ITLBGS 0x20000000 /* Instr. TLB error interrupt | |
| 615 | * directed to guest state */ | |
| 616 | #define SPRN_EPCR_DSIGS 0x10000000 /* Data Storage interrupt | |
| 617 | * directed to guest state */ | |
| 618 | #define SPRN_EPCR_ISIGS 0x08000000 /* Instr. Storage interrupt | |
| 619 | * directed to guest state */ | |
| 620 | #define SPRN_EPCR_DUVD 0x04000000 /* Disable Hypervisor Debug */ | |
| 621 | #define SPRN_EPCR_ICM 0x02000000 /* Interrupt computation mode | |
| 622 | * (copied to MSR:CM on intr) */ | |
| 623 | #define SPRN_EPCR_GICM 0x01000000 /* Guest Interrupt Comp. mode */ | |
| 624 | #define SPRN_EPCR_DGTMI 0x00800000 /* Disable TLB Guest Management | |
| 625 | * instructions */ | |
| 626 | #define SPRN_EPCR_DMIUH 0x00400000 /* Disable MAS Interrupt updates | |
| 627 | * for hypervisor */ | |
| 628 | ||
| d30f6e48 SW |
629 | /* Bit definitions for EPLC/EPSC */ |
| 630 | #define EPC_EPR 0x80000000 /* 1 = user, 0 = kernel */ | |
| 631 | #define EPC_EPR_SHIFT 31 | |
| 632 | #define EPC_EAS 0x40000000 /* Address Space */ | |
| 633 | #define EPC_EAS_SHIFT 30 | |
| 634 | #define EPC_EGS 0x20000000 /* 1 = guest, 0 = hypervisor */ | |
| 635 | #define EPC_EGS_SHIFT 29 | |
| 636 | #define EPC_ELPID 0x00ff0000 | |
| 637 | #define EPC_ELPID_SHIFT 16 | |
| 638 | #define EPC_EPID 0x00003fff | |
| 639 | #define EPC_EPID_SHIFT 0 | |
| 0257c99c | 640 | |
| 82876526 BB |
641 | /* |
| 642 | * The IBM-403 is an even more odd special case, as it is much | |
| 643 | * older than the IBM-405 series. We put these down here incase someone | |
| 644 | * wishes to support these machines again. | |
| 645 | */ | |
| 646 | #ifdef CONFIG_403GCX | |
| 647 | /* Special Purpose Registers (SPRNs)*/ | |
| 648 | #define SPRN_TBHU 0x3CC /* Time Base High User-mode */ | |
| 649 | #define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ | |
| 650 | #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ | |
| 651 | #define SPRN_TBHI 0x3DC /* Time Base High */ | |
| 652 | #define SPRN_TBLO 0x3DD /* Time Base Low */ | |
| 653 | #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ | |
| 654 | #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ | |
| 655 | #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ | |
| 656 | #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ | |
| 657 | #define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ | |
| 658 | ||
| 659 | ||
| 660 | /* Bit definitions for the DBCR. */ | |
| 661 | #define DBCR_EDM DBCR0_EDM | |
| 662 | #define DBCR_IDM DBCR0_IDM | |
| 663 | #define DBCR_RST(x) (((x) & 0x3) << 28) | |
| 664 | #define DBCR_RST_NONE 0 | |
| 665 | #define DBCR_RST_CORE 1 | |
| 666 | #define DBCR_RST_CHIP 2 | |
| 667 | #define DBCR_RST_SYSTEM 3 | |
| 668 | #define DBCR_IC DBCR0_IC /* Instruction Completion Debug Evnt */ | |
| 669 | #define DBCR_BT DBCR0_BT /* Branch Taken Debug Event */ | |
| 670 | #define DBCR_EDE DBCR0_EDE /* Exception Debug Event */ | |
| 671 | #define DBCR_TDE DBCR0_TDE /* TRAP Debug Event */ | |
| 672 | #define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ | |
| 673 | #define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ | |
| 674 | #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ | |
| 675 | #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ | |
| 676 | #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ | |
| 677 | #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ | |
| 678 | #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ | |
| 679 | #define DAC_BYTE 0 | |
| 680 | #define DAC_HALF 1 | |
| 681 | #define DAC_WORD 2 | |
| 682 | #define DAC_QUAD 3 | |
| 683 | #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ | |
| 684 | #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ | |
| 685 | #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ | |
| 686 | #define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ | |
| 687 | #define DBCR_SED 0x00000020 /* Second Exception Debug Event */ | |
| 688 | #define DBCR_STD 0x00000010 /* Second Trap Debug Event */ | |
| 689 | #define DBCR_SIA 0x00000008 /* Second IAC Enable */ | |
| 690 | #define DBCR_SDA 0x00000004 /* Second DAC Enable */ | |
| 691 | #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ | |
| 692 | #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ | |
| 693 | #endif /* 403GCX */ | |
| e7f75ad0 DK |
694 | |
| 695 | /* Some 476 specific registers */ | |
| 696 | #define SPRN_SSPCR 830 | |
| 697 | #define SPRN_USPCR 831 | |
| 698 | #define SPRN_ISPCR 829 | |
| 699 | #define SPRN_MMUBE0 820 | |
| 700 | #define MMUBE0_IBE0_SHIFT 24 | |
| 701 | #define MMUBE0_IBE1_SHIFT 16 | |
| 702 | #define MMUBE0_IBE2_SHIFT 8 | |
| 703 | #define MMUBE0_VBE0 0x00000004 | |
| 704 | #define MMUBE0_VBE1 0x00000002 | |
| 705 | #define MMUBE0_VBE2 0x00000001 | |
| 706 | #define SPRN_MMUBE1 821 | |
| 707 | #define MMUBE1_IBE3_SHIFT 24 | |
| 708 | #define MMUBE1_IBE4_SHIFT 16 | |
| 709 | #define MMUBE1_IBE5_SHIFT 8 | |
| 710 | #define MMUBE1_VBE3 0x00000004 | |
| 711 | #define MMUBE1_VBE4 0x00000002 | |
| 712 | #define MMUBE1_VBE5 0x00000001 | |
| 713 | ||
| 82876526 BB |
714 | #endif /* __ASM_POWERPC_REG_BOOKE_H__ */ |
| 715 | #endif /* __KERNEL__ */ |