Commit | Line | Data |
---|---|---|
0b05ac6e | 1 | /* |
446957ba | 2 | * Common definitions across all variants of ICP and ICS interrupt |
0b05ac6e BH |
3 | * controllers. |
4 | */ | |
5 | ||
6 | #ifndef _XICS_H | |
7 | #define _XICS_H | |
8 | ||
cd852579 ME |
9 | #include <linux/interrupt.h> |
10 | ||
0b05ac6e BH |
11 | #define XICS_IPI 2 |
12 | #define XICS_IRQ_SPURIOUS 0 | |
13 | ||
14 | /* Want a priority other than 0. Various HW issues require this. */ | |
15 | #define DEFAULT_PRIORITY 5 | |
16 | ||
17 | /* | |
a3a9f3b4 YZ |
18 | * Mark IPIs as higher priority so we can take them inside interrupts |
19 | * FIXME: still true now? | |
0b05ac6e BH |
20 | */ |
21 | #define IPI_PRIORITY 4 | |
22 | ||
23 | /* The least favored priority */ | |
24 | #define LOWEST_PRIORITY 0xFF | |
25 | ||
26 | /* The number of priorities defined above */ | |
27 | #define MAX_NUM_PRIORITIES 3 | |
28 | ||
29 | /* Native ICP */ | |
5c7c1e94 | 30 | #ifdef CONFIG_PPC_ICP_NATIVE |
0b05ac6e | 31 | extern int icp_native_init(void); |
d6a4f709 | 32 | extern void icp_native_flush_interrupt(void); |
ec13e9b6 | 33 | extern void icp_native_cause_ipi_rm(int cpu); |
5c7c1e94 BH |
34 | #else |
35 | static inline int icp_native_init(void) { return -ENODEV; } | |
36 | #endif | |
0b05ac6e BH |
37 | |
38 | /* PAPR ICP */ | |
5c7c1e94 | 39 | #ifdef CONFIG_PPC_ICP_HV |
0b05ac6e | 40 | extern int icp_hv_init(void); |
5c7c1e94 BH |
41 | #else |
42 | static inline int icp_hv_init(void) { return -ENODEV; } | |
43 | #endif | |
0b05ac6e BH |
44 | |
45 | /* ICP ops */ | |
46 | struct icp_ops { | |
47 | unsigned int (*get_irq)(void); | |
48 | void (*eoi)(struct irq_data *d); | |
49 | void (*set_priority)(unsigned char prio); | |
50 | void (*teardown_cpu)(void); | |
51 | void (*flush_ipi)(void); | |
52 | #ifdef CONFIG_SMP | |
23d72bfd | 53 | void (*cause_ipi)(int cpu, unsigned long data); |
0b05ac6e BH |
54 | irq_handler_t ipi_action; |
55 | #endif | |
56 | }; | |
57 | ||
58 | extern const struct icp_ops *icp_ops; | |
59 | ||
60 | /* Native ICS */ | |
61 | extern int ics_native_init(void); | |
62 | ||
63 | /* RTAS ICS */ | |
5c7c1e94 | 64 | #ifdef CONFIG_PPC_ICS_RTAS |
0b05ac6e | 65 | extern int ics_rtas_init(void); |
5c7c1e94 BH |
66 | #else |
67 | static inline int ics_rtas_init(void) { return -ENODEV; } | |
68 | #endif | |
69 | ||
70 | /* HAL ICS */ | |
71 | #ifdef CONFIG_PPC_POWERNV | |
72 | extern int ics_opal_init(void); | |
73 | #else | |
74 | static inline int ics_opal_init(void) { return -ENODEV; } | |
75 | #endif | |
0b05ac6e BH |
76 | |
77 | /* ICS instance, hooked up to chip_data of an irq */ | |
78 | struct ics { | |
79 | struct list_head link; | |
80 | int (*map)(struct ics *ics, unsigned int virq); | |
81 | void (*mask_unknown)(struct ics *ics, unsigned long vec); | |
82 | long (*get_server)(struct ics *ics, unsigned long vec); | |
5ca12376 | 83 | int (*host_match)(struct ics *ics, struct device_node *node); |
0b05ac6e BH |
84 | char data[]; |
85 | }; | |
86 | ||
87 | /* Commons */ | |
88 | extern unsigned int xics_default_server; | |
89 | extern unsigned int xics_default_distrib_server; | |
90 | extern unsigned int xics_interrupt_server_size; | |
bae1d8f1 | 91 | extern struct irq_domain *xics_host; |
0b05ac6e BH |
92 | |
93 | struct xics_cppr { | |
94 | unsigned char stack[MAX_NUM_PRIORITIES]; | |
95 | int index; | |
96 | }; | |
97 | ||
98 | DECLARE_PER_CPU(struct xics_cppr, xics_cppr); | |
99 | ||
100 | static inline void xics_push_cppr(unsigned int vec) | |
101 | { | |
69111bac | 102 | struct xics_cppr *os_cppr = this_cpu_ptr(&xics_cppr); |
0b05ac6e BH |
103 | |
104 | if (WARN_ON(os_cppr->index >= MAX_NUM_PRIORITIES - 1)) | |
105 | return; | |
106 | ||
107 | if (vec == XICS_IPI) | |
108 | os_cppr->stack[++os_cppr->index] = IPI_PRIORITY; | |
109 | else | |
110 | os_cppr->stack[++os_cppr->index] = DEFAULT_PRIORITY; | |
111 | } | |
112 | ||
113 | static inline unsigned char xics_pop_cppr(void) | |
114 | { | |
69111bac | 115 | struct xics_cppr *os_cppr = this_cpu_ptr(&xics_cppr); |
0b05ac6e BH |
116 | |
117 | if (WARN_ON(os_cppr->index < 1)) | |
118 | return LOWEST_PRIORITY; | |
119 | ||
120 | return os_cppr->stack[--os_cppr->index]; | |
121 | } | |
122 | ||
123 | static inline void xics_set_base_cppr(unsigned char cppr) | |
124 | { | |
69111bac | 125 | struct xics_cppr *os_cppr = this_cpu_ptr(&xics_cppr); |
0b05ac6e BH |
126 | |
127 | /* we only really want to set the priority when there's | |
128 | * just one cppr value on the stack | |
129 | */ | |
130 | WARN_ON(os_cppr->index != 0); | |
131 | ||
132 | os_cppr->stack[0] = cppr; | |
133 | } | |
134 | ||
135 | static inline unsigned char xics_cppr_top(void) | |
136 | { | |
69111bac | 137 | struct xics_cppr *os_cppr = this_cpu_ptr(&xics_cppr); |
0b05ac6e BH |
138 | |
139 | return os_cppr->stack[os_cppr->index]; | |
140 | } | |
141 | ||
142 | DECLARE_PER_CPU_SHARED_ALIGNED(unsigned long, xics_ipi_message); | |
143 | ||
144 | extern void xics_init(void); | |
145 | extern void xics_setup_cpu(void); | |
146 | extern void xics_update_irq_servers(void); | |
147 | extern void xics_set_cpu_giq(unsigned int gserver, unsigned int join); | |
148 | extern void xics_mask_unknown_vec(unsigned int vec); | |
149 | extern irqreturn_t xics_ipi_dispatch(int cpu); | |
a7f4ee1f | 150 | extern void xics_smp_probe(void); |
0b05ac6e BH |
151 | extern void xics_register_ics(struct ics *ics); |
152 | extern void xics_teardown_cpu(void); | |
153 | extern void xics_kexec_teardown_cpu(int secondary); | |
154 | extern void xics_migrate_irqs_away(void); | |
137436c9 | 155 | extern void icp_native_eoi(struct irq_data *d); |
0b05ac6e BH |
156 | #ifdef CONFIG_SMP |
157 | extern int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask, | |
158 | unsigned int strict_check); | |
159 | #else | |
160 | #define xics_get_irq_server(virq, cpumask, strict_check) (xics_default_server) | |
161 | #endif | |
162 | ||
163 | ||
164 | #endif /* _XICS_H */ |