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0dde1a1d SW |
1 | /* |
2 | * Embedded Planet EP8248E support | |
3 | * | |
4 | * Copyright 2007 Freescale Semiconductor, Inc. | |
5 | * Author: Scott Wood <scottwood@freescale.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/fsl_devices.h> | |
16 | #include <linux/mdio-bitbang.h> | |
fd84f0ee | 17 | #include <linux/of_mdio.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
0dde1a1d SW |
19 | #include <linux/of_platform.h> |
20 | ||
21 | #include <asm/io.h> | |
22 | #include <asm/cpm2.h> | |
23 | #include <asm/udbg.h> | |
24 | #include <asm/machdep.h> | |
25 | #include <asm/time.h> | |
26 | #include <asm/mpc8260.h> | |
27 | #include <asm/prom.h> | |
28 | ||
29 | #include <sysdev/fsl_soc.h> | |
30 | #include <sysdev/cpm2_pic.h> | |
31 | ||
32 | #include "pq2.h" | |
33 | ||
34 | static u8 __iomem *ep8248e_bcsr; | |
35 | static struct device_node *ep8248e_bcsr_node; | |
36 | ||
37 | #define BCSR7_SCC2_ENABLE 0x10 | |
38 | ||
39 | #define BCSR8_PHY1_ENABLE 0x80 | |
40 | #define BCSR8_PHY1_POWER 0x40 | |
41 | #define BCSR8_PHY2_ENABLE 0x20 | |
42 | #define BCSR8_PHY2_POWER 0x10 | |
43 | #define BCSR8_MDIO_READ 0x04 | |
44 | #define BCSR8_MDIO_CLOCK 0x02 | |
45 | #define BCSR8_MDIO_DATA 0x01 | |
46 | ||
47 | #define BCSR9_USB_ENABLE 0x80 | |
48 | #define BCSR9_USB_POWER 0x40 | |
49 | #define BCSR9_USB_HOST 0x20 | |
50 | #define BCSR9_USB_FULL_SPEED_TARGET 0x10 | |
51 | ||
52 | static void __init ep8248e_pic_init(void) | |
53 | { | |
54 | struct device_node *np = of_find_compatible_node(NULL, NULL, "fsl,pq2-pic"); | |
55 | if (!np) { | |
56 | printk(KERN_ERR "PIC init: can not find cpm-pic node\n"); | |
57 | return; | |
58 | } | |
59 | ||
60 | cpm2_pic_init(np); | |
61 | of_node_put(np); | |
62 | } | |
63 | ||
64 | static void ep8248e_set_mdc(struct mdiobb_ctrl *ctrl, int level) | |
65 | { | |
66 | if (level) | |
67 | setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_CLOCK); | |
68 | else | |
69 | clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_CLOCK); | |
70 | ||
71 | /* Read back to flush the write. */ | |
72 | in_8(&ep8248e_bcsr[8]); | |
73 | } | |
74 | ||
75 | static void ep8248e_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) | |
76 | { | |
77 | if (output) | |
78 | clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_READ); | |
79 | else | |
80 | setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_READ); | |
81 | ||
82 | /* Read back to flush the write. */ | |
83 | in_8(&ep8248e_bcsr[8]); | |
84 | } | |
85 | ||
86 | static void ep8248e_set_mdio_data(struct mdiobb_ctrl *ctrl, int data) | |
87 | { | |
88 | if (data) | |
89 | setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_DATA); | |
90 | else | |
91 | clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_DATA); | |
92 | ||
93 | /* Read back to flush the write. */ | |
94 | in_8(&ep8248e_bcsr[8]); | |
95 | } | |
96 | ||
97 | static int ep8248e_get_mdio_data(struct mdiobb_ctrl *ctrl) | |
98 | { | |
99 | return in_8(&ep8248e_bcsr[8]) & BCSR8_MDIO_DATA; | |
100 | } | |
101 | ||
102 | static const struct mdiobb_ops ep8248e_mdio_ops = { | |
103 | .set_mdc = ep8248e_set_mdc, | |
104 | .set_mdio_dir = ep8248e_set_mdio_dir, | |
105 | .set_mdio_data = ep8248e_set_mdio_data, | |
106 | .get_mdio_data = ep8248e_get_mdio_data, | |
107 | .owner = THIS_MODULE, | |
108 | }; | |
109 | ||
110 | static struct mdiobb_ctrl ep8248e_mdio_ctrl = { | |
111 | .ops = &ep8248e_mdio_ops, | |
112 | }; | |
113 | ||
114 | static int __devinit ep8248e_mdio_probe(struct of_device *ofdev, | |
115 | const struct of_device_id *match) | |
116 | { | |
117 | struct mii_bus *bus; | |
118 | struct resource res; | |
119 | struct device_node *node; | |
fd84f0ee | 120 | int ret; |
0dde1a1d | 121 | |
61c7a080 | 122 | node = of_get_parent(ofdev->dev.of_node); |
0dde1a1d SW |
123 | of_node_put(node); |
124 | if (node != ep8248e_bcsr_node) | |
125 | return -ENODEV; | |
126 | ||
61c7a080 | 127 | ret = of_address_to_resource(ofdev->dev.of_node, 0, &res); |
0dde1a1d SW |
128 | if (ret) |
129 | return ret; | |
130 | ||
131 | bus = alloc_mdio_bitbang(&ep8248e_mdio_ctrl); | |
132 | if (!bus) | |
133 | return -ENOMEM; | |
134 | ||
0dde1a1d | 135 | bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); |
58459a4e RK |
136 | if (bus->irq == NULL) { |
137 | ret = -ENOMEM; | |
138 | goto err_free_bus; | |
139 | } | |
0dde1a1d | 140 | |
0dde1a1d | 141 | bus->name = "ep8248e-mdio-bitbang"; |
18ee49dd | 142 | bus->parent = &ofdev->dev; |
9d9326d3 | 143 | snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start); |
0dde1a1d | 144 | |
61c7a080 | 145 | ret = of_mdiobus_register(bus, ofdev->dev.of_node); |
58459a4e RK |
146 | if (ret) |
147 | goto err_free_irq; | |
148 | ||
149 | return 0; | |
150 | err_free_irq: | |
151 | kfree(bus->irq); | |
152 | err_free_bus: | |
153 | free_mdio_bitbang(bus); | |
154 | return ret; | |
0dde1a1d SW |
155 | } |
156 | ||
157 | static int ep8248e_mdio_remove(struct of_device *ofdev) | |
158 | { | |
159 | BUG(); | |
160 | return 0; | |
161 | } | |
162 | ||
163 | static const struct of_device_id ep8248e_mdio_match[] = { | |
164 | { | |
165 | .compatible = "fsl,ep8248e-mdio-bitbang", | |
166 | }, | |
167 | {}, | |
168 | }; | |
169 | ||
170 | static struct of_platform_driver ep8248e_mdio_driver = { | |
171 | .driver = { | |
172 | .name = "ep8248e-mdio-bitbang", | |
173 | }, | |
174 | .match_table = ep8248e_mdio_match, | |
175 | .probe = ep8248e_mdio_probe, | |
176 | .remove = ep8248e_mdio_remove, | |
177 | }; | |
178 | ||
179 | struct cpm_pin { | |
180 | int port, pin, flags; | |
181 | }; | |
182 | ||
183 | static __initdata struct cpm_pin ep8248e_pins[] = { | |
184 | /* SMC1 */ | |
185 | {2, 4, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
186 | {2, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
187 | ||
188 | /* SCC1 */ | |
189 | {2, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
190 | {2, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
191 | {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
192 | {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, | |
193 | {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
194 | ||
195 | /* FCC1 */ | |
196 | {0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
197 | {0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
198 | {0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
199 | {0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
200 | {0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
201 | {0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
202 | {0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
203 | {0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
204 | {0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, | |
205 | {0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, | |
206 | {0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, | |
207 | {0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, | |
208 | {0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, | |
209 | {0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, | |
210 | {2, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
211 | {2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
212 | ||
213 | /* FCC2 */ | |
214 | {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
215 | {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
216 | {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
217 | {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
218 | {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
219 | {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
220 | {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
221 | {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
222 | {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
223 | {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
224 | {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
225 | {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, | |
226 | {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
227 | {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
228 | {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
229 | {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
230 | ||
231 | /* I2C */ | |
232 | {4, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, | |
233 | {4, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, | |
234 | ||
235 | /* USB */ | |
236 | {2, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
237 | {2, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
238 | {2, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
239 | {2, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
240 | {3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
241 | {3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | |
242 | {3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | |
243 | }; | |
244 | ||
245 | static void __init init_ioports(void) | |
246 | { | |
247 | int i; | |
248 | ||
249 | for (i = 0; i < ARRAY_SIZE(ep8248e_pins); i++) { | |
250 | const struct cpm_pin *pin = &ep8248e_pins[i]; | |
251 | cpm2_set_pin(pin->port, pin->pin, pin->flags); | |
252 | } | |
253 | ||
254 | cpm2_smc_clk_setup(CPM_CLK_SMC1, CPM_BRG7); | |
255 | cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX); | |
256 | cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX); | |
257 | cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_TX); /* USB */ | |
258 | cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK11, CPM_CLK_RX); | |
259 | cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_TX); | |
260 | cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX); | |
261 | cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX); | |
262 | } | |
263 | ||
264 | static void __init ep8248e_setup_arch(void) | |
265 | { | |
266 | if (ppc_md.progress) | |
267 | ppc_md.progress("ep8248e_setup_arch()", 0); | |
268 | ||
269 | cpm2_reset(); | |
270 | ||
271 | /* When this is set, snooping CPM DMA from RAM causes | |
272 | * machine checks. See erratum SIU18. | |
273 | */ | |
274 | clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP); | |
275 | ||
276 | ep8248e_bcsr_node = | |
277 | of_find_compatible_node(NULL, NULL, "fsl,ep8248e-bcsr"); | |
278 | if (!ep8248e_bcsr_node) { | |
279 | printk(KERN_ERR "No bcsr in device tree\n"); | |
280 | return; | |
281 | } | |
282 | ||
283 | ep8248e_bcsr = of_iomap(ep8248e_bcsr_node, 0); | |
284 | if (!ep8248e_bcsr) { | |
285 | printk(KERN_ERR "Cannot map BCSR registers\n"); | |
286 | of_node_put(ep8248e_bcsr_node); | |
287 | ep8248e_bcsr_node = NULL; | |
288 | return; | |
289 | } | |
290 | ||
291 | setbits8(&ep8248e_bcsr[7], BCSR7_SCC2_ENABLE); | |
292 | setbits8(&ep8248e_bcsr[8], BCSR8_PHY1_ENABLE | BCSR8_PHY1_POWER | | |
293 | BCSR8_PHY2_ENABLE | BCSR8_PHY2_POWER); | |
294 | ||
295 | init_ioports(); | |
296 | ||
297 | if (ppc_md.progress) | |
298 | ppc_md.progress("ep8248e_setup_arch(), finish", 0); | |
299 | } | |
300 | ||
301 | static __initdata struct of_device_id of_bus_ids[] = { | |
302 | { .compatible = "simple-bus", }, | |
303 | { .compatible = "fsl,ep8248e-bcsr", }, | |
304 | {}, | |
305 | }; | |
306 | ||
307 | static int __init declare_of_platform_devices(void) | |
308 | { | |
309 | of_platform_bus_probe(NULL, of_bus_ids, NULL); | |
310 | of_register_platform_driver(&ep8248e_mdio_driver); | |
311 | ||
312 | return 0; | |
313 | } | |
314 | machine_device_initcall(ep8248e, declare_of_platform_devices); | |
315 | ||
316 | /* | |
317 | * Called very early, device-tree isn't unflattened | |
318 | */ | |
319 | static int __init ep8248e_probe(void) | |
320 | { | |
321 | unsigned long root = of_get_flat_dt_root(); | |
322 | return of_flat_dt_is_compatible(root, "fsl,ep8248e"); | |
323 | } | |
324 | ||
325 | define_machine(ep8248e) | |
326 | { | |
327 | .name = "Embedded Planet EP8248E", | |
328 | .probe = ep8248e_probe, | |
329 | .setup_arch = ep8248e_setup_arch, | |
330 | .init_IRQ = ep8248e_pic_init, | |
331 | .get_irq = cpm2_get_irq, | |
332 | .calibrate_decr = generic_calibrate_decr, | |
333 | .restart = pq2_restart, | |
334 | .progress = udbg_progress, | |
335 | }; |