Commit | Line | Data |
---|---|---|
cff65c4f | 1 | /* |
ba180fd4 | 2 | * Copyright (C) 2000 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com) |
1da177e4 LT |
3 | * Licensed under the GPL |
4 | */ | |
5 | ||
c5d4bb17 | 6 | #include <linux/clockchips.h> |
7d195a54 | 7 | #include <linux/init.h> |
c5d4bb17 JD |
8 | #include <linux/interrupt.h> |
9 | #include <linux/jiffies.h> | |
10 | #include <linux/threads.h> | |
11 | #include <asm/irq.h> | |
12 | #include <asm/param.h> | |
37185b33 AV |
13 | #include <kern_util.h> |
14 | #include <os.h> | |
1da177e4 | 15 | |
d3c1cfcd | 16 | void timer_handler(int sig, struct siginfo *unused_si, struct uml_pt_regs *regs) |
1da177e4 | 17 | { |
31ccc1f5 | 18 | unsigned long flags; |
31ccc1f5 JD |
19 | |
20 | local_irq_save(flags); | |
d2753a6d | 21 | do_IRQ(TIMER_IRQ, regs); |
31ccc1f5 | 22 | local_irq_restore(flags); |
1da177e4 LT |
23 | } |
24 | ||
31ccc1f5 JD |
25 | static void itimer_set_mode(enum clock_event_mode mode, |
26 | struct clock_event_device *evt) | |
cff65c4f | 27 | { |
c5d4bb17 | 28 | switch (mode) { |
31ccc1f5 JD |
29 | case CLOCK_EVT_MODE_PERIODIC: |
30 | set_interval(); | |
31 | break; | |
32 | ||
33 | case CLOCK_EVT_MODE_SHUTDOWN: | |
34 | case CLOCK_EVT_MODE_UNUSED: | |
31ccc1f5 | 35 | case CLOCK_EVT_MODE_ONESHOT: |
d2753a6d | 36 | disable_timer(); |
31ccc1f5 JD |
37 | break; |
38 | ||
39 | case CLOCK_EVT_MODE_RESUME: | |
40 | break; | |
41 | } | |
cff65c4f GS |
42 | } |
43 | ||
d2753a6d JD |
44 | static int itimer_next_event(unsigned long delta, |
45 | struct clock_event_device *evt) | |
46 | { | |
47 | return timer_one_shot(delta + 1); | |
48 | } | |
49 | ||
31ccc1f5 JD |
50 | static struct clock_event_device itimer_clockevent = { |
51 | .name = "itimer", | |
52 | .rating = 250, | |
320ab2b0 | 53 | .cpumask = cpu_all_mask, |
d2753a6d | 54 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
31ccc1f5 | 55 | .set_mode = itimer_set_mode, |
d2753a6d | 56 | .set_next_event = itimer_next_event, |
31ccc1f5 JD |
57 | .shift = 32, |
58 | .irq = 0, | |
59 | }; | |
60 | ||
61 | static irqreturn_t um_timer(int irq, void *dev) | |
1da177e4 | 62 | { |
31ccc1f5 | 63 | (*itimer_clockevent.event_handler)(&itimer_clockevent); |
cff65c4f | 64 | |
572e6147 | 65 | return IRQ_HANDLED; |
1da177e4 LT |
66 | } |
67 | ||
8e19608e | 68 | static cycle_t itimer_read(struct clocksource *cs) |
791a644a | 69 | { |
cfd28f66 | 70 | return os_nsecs() / 1000; |
791a644a JD |
71 | } |
72 | ||
73 | static struct clocksource itimer_clocksource = { | |
74 | .name = "itimer", | |
75 | .rating = 300, | |
76 | .read = itimer_read, | |
77 | .mask = CLOCKSOURCE_MASK(64), | |
791a644a JD |
78 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
79 | }; | |
80 | ||
31ccc1f5 | 81 | static void __init setup_itimer(void) |
aceb3434 JD |
82 | { |
83 | int err; | |
84 | ||
c0b79a90 | 85 | err = request_irq(TIMER_IRQ, um_timer, 0, "timer", NULL); |
ba180fd4 | 86 | if (err != 0) |
537ae946 | 87 | printk(KERN_ERR "register_timer : request_irq failed - " |
aceb3434 JD |
88 | "errno = %d\n", -err); |
89 | ||
31ccc1f5 JD |
90 | itimer_clockevent.mult = div_sc(HZ, NSEC_PER_SEC, 32); |
91 | itimer_clockevent.max_delta_ns = | |
92 | clockevent_delta2ns(60 * HZ, &itimer_clockevent); | |
93 | itimer_clockevent.min_delta_ns = | |
94 | clockevent_delta2ns(1, &itimer_clockevent); | |
60d687e7 | 95 | err = clocksource_register_hz(&itimer_clocksource, USEC_PER_SEC); |
791a644a | 96 | if (err) { |
60d687e7 | 97 | printk(KERN_ERR "clocksource_register_hz returned %d\n", err); |
791a644a JD |
98 | return; |
99 | } | |
31ccc1f5 | 100 | clockevents_register_device(&itimer_clockevent); |
aceb3434 JD |
101 | } |
102 | ||
9f31f577 JS |
103 | void read_persistent_clock(struct timespec *ts) |
104 | { | |
b2923076 TG |
105 | long long nsecs = os_nsecs(); |
106 | ||
9f31f577 JS |
107 | set_normalized_timespec(ts, nsecs / NSEC_PER_SEC, |
108 | nsecs % NSEC_PER_SEC); | |
109 | } | |
110 | ||
31ccc1f5 | 111 | void __init time_init(void) |
aceb3434 | 112 | { |
31ccc1f5 | 113 | timer_init(); |
31ccc1f5 | 114 | late_time_init = setup_itimer; |
1da177e4 | 115 | } |