Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
773763df | 27 | #include <linux/cpu.h> |
ba7eda4c | 28 | #include <linux/clockchips.h> |
70a20025 | 29 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 30 | #include <linux/module.h> |
773763df | 31 | #include <linux/dmi.h> |
6e1cb38a | 32 | #include <linux/dmar.h> |
1da177e4 LT |
33 | |
34 | #include <asm/atomic.h> | |
35 | #include <asm/smp.h> | |
36 | #include <asm/mtrr.h> | |
37 | #include <asm/mpspec.h> | |
efa2559f | 38 | #include <asm/desc.h> |
773763df | 39 | #include <asm/arch_hooks.h> |
e83a5fdc | 40 | #include <asm/hpet.h> |
1da177e4 | 41 | #include <asm/pgalloc.h> |
773763df | 42 | #include <asm/i8253.h> |
75152114 | 43 | #include <asm/nmi.h> |
95833c83 | 44 | #include <asm/idle.h> |
73dea47f AK |
45 | #include <asm/proto.h> |
46 | #include <asm/timex.h> | |
2c8c0e6b | 47 | #include <asm/apic.h> |
6e1cb38a | 48 | #include <asm/i8259.h> |
1da177e4 | 49 | |
dd46e3ca | 50 | #include <mach_apic.h> |
773763df YL |
51 | #include <mach_apicdef.h> |
52 | #include <mach_ipi.h> | |
5af5573e | 53 | |
80e5609c CG |
54 | /* |
55 | * Sanity check | |
56 | */ | |
57 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) | |
58 | # error SPURIOUS_APIC_VECTOR definition error | |
59 | #endif | |
60 | ||
b3c51170 YL |
61 | #ifdef CONFIG_X86_32 |
62 | /* | |
63 | * Knob to control our willingness to enable the local APIC. | |
64 | * | |
65 | * +1=force-enable | |
66 | */ | |
67 | static int force_enable_local_apic; | |
68 | /* | |
69 | * APIC command line parameters | |
70 | */ | |
71 | static int __init parse_lapic(char *arg) | |
72 | { | |
73 | force_enable_local_apic = 1; | |
74 | return 0; | |
75 | } | |
76 | early_param("lapic", parse_lapic); | |
f28c0ae2 YL |
77 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
78 | static int enabled_via_apicbase; | |
79 | ||
b3c51170 YL |
80 | #endif |
81 | ||
82 | #ifdef CONFIG_X86_64 | |
bc1d99c1 | 83 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
84 | static __init int setup_apicpmtimer(char *s) |
85 | { | |
86 | apic_calibrate_pmtmr = 1; | |
87 | notsc_setup(NULL); | |
88 | return 0; | |
89 | } | |
90 | __setup("apicpmtimer", setup_apicpmtimer); | |
91 | #endif | |
92 | ||
49899eac YL |
93 | #ifdef CONFIG_X86_64 |
94 | #define HAVE_X2APIC | |
95 | #endif | |
96 | ||
97 | #ifdef HAVE_X2APIC | |
89027d35 | 98 | int x2apic; |
6e1cb38a SS |
99 | /* x2apic enabled before OS handover */ |
100 | int x2apic_preenabled; | |
49899eac YL |
101 | int disable_x2apic; |
102 | static __init int setup_nox2apic(char *str) | |
103 | { | |
104 | disable_x2apic = 1; | |
105 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
106 | return 0; | |
107 | } | |
108 | early_param("nox2apic", setup_nox2apic); | |
109 | #endif | |
1da177e4 | 110 | |
b3c51170 YL |
111 | unsigned long mp_lapic_addr; |
112 | int disable_apic; | |
113 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
114 | static int disable_apic_timer __cpuinitdata; | |
e83a5fdc | 115 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
116 | int local_apic_timer_c2_ok; |
117 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
118 | ||
efa2559f YL |
119 | int first_system_vector = 0xfe; |
120 | ||
e83a5fdc HS |
121 | /* |
122 | * Debug level, exported for io_apic.c | |
123 | */ | |
baa13188 | 124 | unsigned int apic_verbosity; |
e83a5fdc | 125 | |
89c38c28 CG |
126 | int pic_mode; |
127 | ||
bab4b27c AS |
128 | /* Have we found an MP table */ |
129 | int smp_found_config; | |
130 | ||
39928722 AD |
131 | static struct resource lapic_resource = { |
132 | .name = "Local APIC", | |
133 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
134 | }; | |
135 | ||
d03030e9 TG |
136 | static unsigned int calibration_result; |
137 | ||
ba7eda4c TG |
138 | static int lapic_next_event(unsigned long delta, |
139 | struct clock_event_device *evt); | |
140 | static void lapic_timer_setup(enum clock_event_mode mode, | |
141 | struct clock_event_device *evt); | |
e7986739 | 142 | static void lapic_timer_broadcast(const cpumask_t *mask); |
0e078e2f | 143 | static void apic_pm_activate(void); |
ba7eda4c | 144 | |
274cfe59 CG |
145 | /* |
146 | * The local apic timer can be used for any function which is CPU local. | |
147 | */ | |
ba7eda4c TG |
148 | static struct clock_event_device lapic_clockevent = { |
149 | .name = "lapic", | |
150 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
151 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
152 | .shift = 32, | |
153 | .set_mode = lapic_timer_setup, | |
154 | .set_next_event = lapic_next_event, | |
155 | .broadcast = lapic_timer_broadcast, | |
156 | .rating = 100, | |
157 | .irq = -1, | |
158 | }; | |
159 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
160 | ||
d3432896 AK |
161 | static unsigned long apic_phys; |
162 | ||
0e078e2f TG |
163 | /* |
164 | * Get the LAPIC version | |
165 | */ | |
166 | static inline int lapic_get_version(void) | |
ba7eda4c | 167 | { |
0e078e2f | 168 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
169 | } |
170 | ||
0e078e2f | 171 | /* |
9c803869 | 172 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
173 | */ |
174 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 175 | { |
9c803869 | 176 | #ifdef CONFIG_X86_64 |
0e078e2f | 177 | return 1; |
9c803869 CG |
178 | #else |
179 | return APIC_INTEGRATED(lapic_get_version()); | |
180 | #endif | |
ba7eda4c TG |
181 | } |
182 | ||
183 | /* | |
0e078e2f | 184 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 185 | */ |
0e078e2f | 186 | static int modern_apic(void) |
ba7eda4c | 187 | { |
0e078e2f TG |
188 | /* AMD systems use old APIC versions, so check the CPU */ |
189 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
190 | boot_cpu_data.x86 >= 0xf) | |
191 | return 1; | |
192 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
193 | } |
194 | ||
274cfe59 CG |
195 | /* |
196 | * Paravirt kernels also might be using these below ops. So we still | |
197 | * use generic apic_read()/apic_write(), which might be pointing to different | |
198 | * ops in PARAVIRT case. | |
199 | */ | |
1b374e4d | 200 | void xapic_wait_icr_idle(void) |
8339e9fb FLV |
201 | { |
202 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
203 | cpu_relax(); | |
204 | } | |
205 | ||
1b374e4d | 206 | u32 safe_xapic_wait_icr_idle(void) |
8339e9fb | 207 | { |
3c6bb07a | 208 | u32 send_status; |
8339e9fb FLV |
209 | int timeout; |
210 | ||
211 | timeout = 0; | |
212 | do { | |
213 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
214 | if (!send_status) | |
215 | break; | |
216 | udelay(100); | |
217 | } while (timeout++ < 1000); | |
218 | ||
219 | return send_status; | |
220 | } | |
221 | ||
1b374e4d SS |
222 | void xapic_icr_write(u32 low, u32 id) |
223 | { | |
ed4e5ec1 | 224 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
225 | apic_write(APIC_ICR, low); |
226 | } | |
227 | ||
228 | u64 xapic_icr_read(void) | |
229 | { | |
230 | u32 icr1, icr2; | |
231 | ||
232 | icr2 = apic_read(APIC_ICR2); | |
233 | icr1 = apic_read(APIC_ICR); | |
234 | ||
cf9768d7 | 235 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
236 | } |
237 | ||
238 | static struct apic_ops xapic_ops = { | |
239 | .read = native_apic_mem_read, | |
240 | .write = native_apic_mem_write, | |
1b374e4d SS |
241 | .icr_read = xapic_icr_read, |
242 | .icr_write = xapic_icr_write, | |
243 | .wait_icr_idle = xapic_wait_icr_idle, | |
244 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
245 | }; | |
246 | ||
247 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
1b374e4d SS |
248 | EXPORT_SYMBOL_GPL(apic_ops); |
249 | ||
49899eac | 250 | #ifdef HAVE_X2APIC |
13c88fb5 SS |
251 | static void x2apic_wait_icr_idle(void) |
252 | { | |
253 | /* no need to wait for icr idle in x2apic */ | |
254 | return; | |
255 | } | |
256 | ||
257 | static u32 safe_x2apic_wait_icr_idle(void) | |
258 | { | |
259 | /* no need to wait for icr idle in x2apic */ | |
260 | return 0; | |
261 | } | |
262 | ||
263 | void x2apic_icr_write(u32 low, u32 id) | |
264 | { | |
265 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
266 | } | |
267 | ||
268 | u64 x2apic_icr_read(void) | |
269 | { | |
270 | unsigned long val; | |
271 | ||
272 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
273 | return val; | |
274 | } | |
275 | ||
276 | static struct apic_ops x2apic_ops = { | |
277 | .read = native_apic_msr_read, | |
278 | .write = native_apic_msr_write, | |
13c88fb5 SS |
279 | .icr_read = x2apic_icr_read, |
280 | .icr_write = x2apic_icr_write, | |
281 | .wait_icr_idle = x2apic_wait_icr_idle, | |
282 | .safe_wait_icr_idle = safe_x2apic_wait_icr_idle, | |
283 | }; | |
49899eac | 284 | #endif |
13c88fb5 | 285 | |
0e078e2f TG |
286 | /** |
287 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
288 | */ | |
e9427101 | 289 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 290 | { |
11a8e778 | 291 | unsigned int v; |
6935d1f9 TG |
292 | |
293 | /* unmask and set to NMI */ | |
294 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
295 | |
296 | /* Level triggered for 82489DX (32bit mode) */ | |
297 | if (!lapic_is_integrated()) | |
298 | v |= APIC_LVT_LEVEL_TRIGGER; | |
299 | ||
11a8e778 | 300 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
301 | } |
302 | ||
7c37e48b CG |
303 | #ifdef CONFIG_X86_32 |
304 | /** | |
305 | * get_physical_broadcast - Get number of physical broadcast IDs | |
306 | */ | |
307 | int get_physical_broadcast(void) | |
308 | { | |
309 | return modern_apic() ? 0xff : 0xf; | |
310 | } | |
311 | #endif | |
312 | ||
0e078e2f TG |
313 | /** |
314 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
315 | */ | |
37e650c7 | 316 | int lapic_get_maxlvt(void) |
1da177e4 | 317 | { |
36a028de | 318 | unsigned int v; |
1da177e4 LT |
319 | |
320 | v = apic_read(APIC_LVR); | |
36a028de CG |
321 | /* |
322 | * - we always have APIC integrated on 64bit mode | |
323 | * - 82489DXs do not report # of LVT entries | |
324 | */ | |
325 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
326 | } |
327 | ||
274cfe59 CG |
328 | /* |
329 | * Local APIC timer | |
330 | */ | |
331 | ||
c40aaec6 | 332 | /* Clock divisor */ |
c40aaec6 | 333 | #define APIC_DIVISOR 16 |
f07f4f90 | 334 | |
0e078e2f TG |
335 | /* |
336 | * This function sets up the local APIC timer, with a timeout of | |
337 | * 'clocks' APIC bus clock. During calibration we actually call | |
338 | * this function twice on the boot CPU, once with a bogus timeout | |
339 | * value, second time for real. The other (noncalibrating) CPUs | |
340 | * call this function only once, with the real, calibrated value. | |
341 | * | |
342 | * We do reads before writes even if unnecessary, to get around the | |
343 | * P5 APIC double write bug. | |
344 | */ | |
0e078e2f | 345 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 346 | { |
0e078e2f | 347 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 348 | |
0e078e2f TG |
349 | lvtt_value = LOCAL_TIMER_VECTOR; |
350 | if (!oneshot) | |
351 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
352 | if (!lapic_is_integrated()) |
353 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
354 | ||
0e078e2f TG |
355 | if (!irqen) |
356 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 357 | |
0e078e2f | 358 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
359 | |
360 | /* | |
0e078e2f | 361 | * Divide PICLK by 16 |
1da177e4 | 362 | */ |
0e078e2f | 363 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
364 | apic_write(APIC_TDCR, |
365 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
366 | APIC_TDR_DIV_16); | |
0e078e2f TG |
367 | |
368 | if (!oneshot) | |
f07f4f90 | 369 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
370 | } |
371 | ||
0e078e2f | 372 | /* |
7b83dae7 RR |
373 | * Setup extended LVT, AMD specific (K8, family 10h) |
374 | * | |
375 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
376 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
286f5718 RR |
377 | * |
378 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
379 | * enables the vector. See also the BKDGs. | |
0e078e2f | 380 | */ |
7b83dae7 RR |
381 | |
382 | #define APIC_EILVT_LVTOFF_MCE 0 | |
383 | #define APIC_EILVT_LVTOFF_IBS 1 | |
384 | ||
385 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 386 | { |
7b83dae7 | 387 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 388 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 389 | |
0e078e2f | 390 | apic_write(reg, v); |
1da177e4 LT |
391 | } |
392 | ||
7b83dae7 RR |
393 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
394 | { | |
395 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
396 | return APIC_EILVT_LVTOFF_MCE; | |
397 | } | |
398 | ||
399 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
400 | { | |
401 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
402 | return APIC_EILVT_LVTOFF_IBS; | |
403 | } | |
6aa360e6 | 404 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
7b83dae7 | 405 | |
0e078e2f TG |
406 | /* |
407 | * Program the next event, relative to now | |
408 | */ | |
409 | static int lapic_next_event(unsigned long delta, | |
410 | struct clock_event_device *evt) | |
1da177e4 | 411 | { |
0e078e2f TG |
412 | apic_write(APIC_TMICT, delta); |
413 | return 0; | |
1da177e4 LT |
414 | } |
415 | ||
0e078e2f TG |
416 | /* |
417 | * Setup the lapic timer in periodic or oneshot mode | |
418 | */ | |
419 | static void lapic_timer_setup(enum clock_event_mode mode, | |
420 | struct clock_event_device *evt) | |
9b7711f0 HS |
421 | { |
422 | unsigned long flags; | |
0e078e2f | 423 | unsigned int v; |
9b7711f0 | 424 | |
0e078e2f TG |
425 | /* Lapic used as dummy for broadcast ? */ |
426 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
427 | return; |
428 | ||
429 | local_irq_save(flags); | |
430 | ||
0e078e2f TG |
431 | switch (mode) { |
432 | case CLOCK_EVT_MODE_PERIODIC: | |
433 | case CLOCK_EVT_MODE_ONESHOT: | |
434 | __setup_APIC_LVTT(calibration_result, | |
435 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
436 | break; | |
437 | case CLOCK_EVT_MODE_UNUSED: | |
438 | case CLOCK_EVT_MODE_SHUTDOWN: | |
439 | v = apic_read(APIC_LVTT); | |
440 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
441 | apic_write(APIC_LVTT, v); | |
a98f8fd2 | 442 | apic_write(APIC_TMICT, 0xffffffff); |
0e078e2f TG |
443 | break; |
444 | case CLOCK_EVT_MODE_RESUME: | |
445 | /* Nothing to do here */ | |
446 | break; | |
447 | } | |
9b7711f0 HS |
448 | |
449 | local_irq_restore(flags); | |
450 | } | |
451 | ||
1da177e4 | 452 | /* |
0e078e2f | 453 | * Local APIC timer broadcast function |
1da177e4 | 454 | */ |
e7986739 | 455 | static void lapic_timer_broadcast(const cpumask_t *mask) |
1da177e4 | 456 | { |
0e078e2f | 457 | #ifdef CONFIG_SMP |
e7986739 | 458 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
0e078e2f TG |
459 | #endif |
460 | } | |
1da177e4 | 461 | |
0e078e2f TG |
462 | /* |
463 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
464 | * of the boot CPU and register the clock event in the framework. | |
465 | */ | |
db4b5525 | 466 | static void __cpuinit setup_APIC_timer(void) |
0e078e2f TG |
467 | { |
468 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 469 | |
0e078e2f | 470 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 471 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 472 | |
0e078e2f TG |
473 | clockevents_register_device(levt); |
474 | } | |
1da177e4 | 475 | |
2f04fa88 YL |
476 | /* |
477 | * In this functions we calibrate APIC bus clocks to the external timer. | |
478 | * | |
479 | * We want to do the calibration only once since we want to have local timer | |
480 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
481 | * frequency. | |
482 | * | |
483 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
484 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
485 | * readout is broken, so it never gets out of the wait loop again. This was | |
486 | * also reported by others. | |
487 | * | |
488 | * Monitoring the jiffies value is inaccurate and the clockevents | |
489 | * infrastructure allows us to do a simple substitution of the interrupt | |
490 | * handler. | |
491 | * | |
492 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
493 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
494 | * back to normal later in the boot process). | |
495 | */ | |
496 | ||
497 | #define LAPIC_CAL_LOOPS (HZ/10) | |
498 | ||
499 | static __initdata int lapic_cal_loops = -1; | |
500 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
501 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
502 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
503 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
504 | ||
505 | /* | |
506 | * Temporary interrupt handler. | |
507 | */ | |
508 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
509 | { | |
510 | unsigned long long tsc = 0; | |
511 | long tapic = apic_read(APIC_TMCCT); | |
512 | unsigned long pm = acpi_pm_read_early(); | |
513 | ||
514 | if (cpu_has_tsc) | |
515 | rdtscll(tsc); | |
516 | ||
517 | switch (lapic_cal_loops++) { | |
518 | case 0: | |
519 | lapic_cal_t1 = tapic; | |
520 | lapic_cal_tsc1 = tsc; | |
521 | lapic_cal_pm1 = pm; | |
522 | lapic_cal_j1 = jiffies; | |
523 | break; | |
524 | ||
525 | case LAPIC_CAL_LOOPS: | |
526 | lapic_cal_t2 = tapic; | |
527 | lapic_cal_tsc2 = tsc; | |
528 | if (pm < lapic_cal_pm1) | |
529 | pm += ACPI_PM_OVRRUN; | |
530 | lapic_cal_pm2 = pm; | |
531 | lapic_cal_j2 = jiffies; | |
532 | break; | |
533 | } | |
534 | } | |
535 | ||
b189892d CG |
536 | static int __init calibrate_by_pmtimer(long deltapm, long *delta) |
537 | { | |
538 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
539 | const long pm_thresh = pm_100ms / 100; | |
540 | unsigned long mult; | |
541 | u64 res; | |
542 | ||
543 | #ifndef CONFIG_X86_PM_TIMER | |
544 | return -1; | |
545 | #endif | |
546 | ||
547 | apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm); | |
548 | ||
549 | /* Check, if the PM timer is available */ | |
550 | if (!deltapm) | |
551 | return -1; | |
552 | ||
553 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
554 | ||
555 | if (deltapm > (pm_100ms - pm_thresh) && | |
556 | deltapm < (pm_100ms + pm_thresh)) { | |
557 | apic_printk(APIC_VERBOSE, "... PM timer result ok\n"); | |
558 | } else { | |
559 | res = (((u64)deltapm) * mult) >> 22; | |
560 | do_div(res, 1000000); | |
ba21ebb6 | 561 | pr_warning("APIC calibration not consistent " |
b189892d CG |
562 | "with PM Timer: %ldms instead of 100ms\n", |
563 | (long)res); | |
564 | /* Correct the lapic counter value */ | |
565 | res = (((u64)(*delta)) * pm_100ms); | |
566 | do_div(res, deltapm); | |
ba21ebb6 | 567 | pr_info("APIC delta adjusted to PM-Timer: " |
b189892d CG |
568 | "%lu (%ld)\n", (unsigned long)res, *delta); |
569 | *delta = (long)res; | |
570 | } | |
571 | ||
572 | return 0; | |
573 | } | |
574 | ||
2f04fa88 YL |
575 | static int __init calibrate_APIC_clock(void) |
576 | { | |
577 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
2f04fa88 YL |
578 | void (*real_handler)(struct clock_event_device *dev); |
579 | unsigned long deltaj; | |
b189892d | 580 | long delta; |
2f04fa88 YL |
581 | int pm_referenced = 0; |
582 | ||
583 | local_irq_disable(); | |
584 | ||
585 | /* Replace the global interrupt handler */ | |
586 | real_handler = global_clock_event->event_handler; | |
587 | global_clock_event->event_handler = lapic_cal_handler; | |
588 | ||
589 | /* | |
81608f3c | 590 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
591 | * can underflow in the 100ms detection time frame |
592 | */ | |
81608f3c | 593 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 YL |
594 | |
595 | /* Let the interrupts run */ | |
596 | local_irq_enable(); | |
597 | ||
598 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
599 | cpu_relax(); | |
600 | ||
601 | local_irq_disable(); | |
602 | ||
603 | /* Restore the real event handler */ | |
604 | global_clock_event->event_handler = real_handler; | |
605 | ||
606 | /* Build delta t1-t2 as apic timer counts down */ | |
607 | delta = lapic_cal_t1 - lapic_cal_t2; | |
608 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
609 | ||
b189892d CG |
610 | /* we trust the PM based calibration if possible */ |
611 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
612 | &delta); | |
2f04fa88 YL |
613 | |
614 | /* Calculate the scaled math multiplication factor */ | |
615 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, | |
616 | lapic_clockevent.shift); | |
617 | lapic_clockevent.max_delta_ns = | |
618 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
619 | lapic_clockevent.min_delta_ns = | |
620 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
621 | ||
622 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; | |
623 | ||
624 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
625 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); | |
626 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", | |
627 | calibration_result); | |
628 | ||
629 | if (cpu_has_tsc) { | |
630 | delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); | |
631 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " | |
632 | "%ld.%04ld MHz.\n", | |
633 | (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ), | |
634 | (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
635 | } | |
636 | ||
637 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
638 | "%u.%04u MHz.\n", | |
639 | calibration_result / (1000000 / HZ), | |
640 | calibration_result % (1000000 / HZ)); | |
641 | ||
642 | /* | |
643 | * Do a sanity check on the APIC calibration result | |
644 | */ | |
645 | if (calibration_result < (1000000 / HZ)) { | |
646 | local_irq_enable(); | |
ba21ebb6 | 647 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
648 | return -1; |
649 | } | |
650 | ||
651 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
652 | ||
b189892d CG |
653 | /* |
654 | * PM timer calibration failed or not turned on | |
655 | * so lets try APIC timer based calibration | |
656 | */ | |
2f04fa88 YL |
657 | if (!pm_referenced) { |
658 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
659 | ||
660 | /* | |
661 | * Setup the apic timer manually | |
662 | */ | |
663 | levt->event_handler = lapic_cal_handler; | |
664 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
665 | lapic_cal_loops = -1; | |
666 | ||
667 | /* Let the interrupts run */ | |
668 | local_irq_enable(); | |
669 | ||
670 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
671 | cpu_relax(); | |
672 | ||
2f04fa88 YL |
673 | /* Stop the lapic timer */ |
674 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
675 | ||
2f04fa88 YL |
676 | /* Jiffies delta */ |
677 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
678 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
679 | ||
680 | /* Check, if the jiffies result is consistent */ | |
681 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
682 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
683 | else | |
684 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
685 | } else | |
686 | local_irq_enable(); | |
687 | ||
688 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
ba21ebb6 | 689 | pr_warning("APIC timer disabled due to verification failure.\n"); |
2f04fa88 YL |
690 | return -1; |
691 | } | |
692 | ||
693 | return 0; | |
694 | } | |
695 | ||
e83a5fdc HS |
696 | /* |
697 | * Setup the boot APIC | |
698 | * | |
699 | * Calibrate and verify the result. | |
700 | */ | |
0e078e2f TG |
701 | void __init setup_boot_APIC_clock(void) |
702 | { | |
703 | /* | |
274cfe59 CG |
704 | * The local apic timer can be disabled via the kernel |
705 | * commandline or from the CPU detection code. Register the lapic | |
706 | * timer as a dummy clock event source on SMP systems, so the | |
707 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
708 | */ |
709 | if (disable_apic_timer) { | |
ba21ebb6 | 710 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 711 | /* No broadcast on UP ! */ |
9d09951d TG |
712 | if (num_possible_cpus() > 1) { |
713 | lapic_clockevent.mult = 1; | |
0e078e2f | 714 | setup_APIC_timer(); |
9d09951d | 715 | } |
0e078e2f TG |
716 | return; |
717 | } | |
718 | ||
274cfe59 CG |
719 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
720 | "calibrating APIC timer ...\n"); | |
721 | ||
89b3b1f4 | 722 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
723 | /* No broadcast on UP ! */ |
724 | if (num_possible_cpus() > 1) | |
725 | setup_APIC_timer(); | |
726 | return; | |
727 | } | |
728 | ||
0e078e2f TG |
729 | /* |
730 | * If nmi_watchdog is set to IO_APIC, we need the | |
731 | * PIT/HPET going. Otherwise register lapic as a dummy | |
732 | * device. | |
733 | */ | |
734 | if (nmi_watchdog != NMI_IO_APIC) | |
735 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
736 | else | |
ba21ebb6 | 737 | pr_warning("APIC timer registered as dummy," |
116f570e | 738 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f | 739 | |
274cfe59 | 740 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
741 | setup_APIC_timer(); |
742 | } | |
743 | ||
0e078e2f TG |
744 | void __cpuinit setup_secondary_APIC_clock(void) |
745 | { | |
0e078e2f TG |
746 | setup_APIC_timer(); |
747 | } | |
748 | ||
749 | /* | |
750 | * The guts of the apic timer interrupt | |
751 | */ | |
752 | static void local_apic_timer_interrupt(void) | |
753 | { | |
754 | int cpu = smp_processor_id(); | |
755 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
756 | ||
757 | /* | |
758 | * Normally we should not be here till LAPIC has been initialized but | |
759 | * in some cases like kdump, its possible that there is a pending LAPIC | |
760 | * timer interrupt from previous kernel's context and is delivered in | |
761 | * new kernel the moment interrupts are enabled. | |
762 | * | |
763 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
764 | * its possible that when we get here evt->event_handler is NULL. | |
765 | * Check for event_handler being NULL and discard the interrupt as | |
766 | * spurious. | |
767 | */ | |
768 | if (!evt->event_handler) { | |
ba21ebb6 | 769 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
0e078e2f TG |
770 | /* Switch it off */ |
771 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
772 | return; | |
773 | } | |
774 | ||
775 | /* | |
776 | * the NMI deadlock-detector uses this. | |
777 | */ | |
0b23e8cf | 778 | #ifdef CONFIG_X86_64 |
0e078e2f | 779 | add_pda(apic_timer_irqs, 1); |
0b23e8cf CG |
780 | #else |
781 | per_cpu(irq_stat, cpu).apic_timer_irqs++; | |
782 | #endif | |
0e078e2f TG |
783 | |
784 | evt->event_handler(evt); | |
785 | } | |
786 | ||
787 | /* | |
788 | * Local APIC timer interrupt. This is the most natural way for doing | |
789 | * local interrupts, but local timer interrupts can be emulated by | |
790 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
791 | * | |
792 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
793 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
794 | */ | |
795 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
796 | { | |
797 | struct pt_regs *old_regs = set_irq_regs(regs); | |
798 | ||
799 | /* | |
800 | * NOTE! We'd better ACK the irq immediately, | |
801 | * because timer handling can be slow. | |
802 | */ | |
803 | ack_APIC_irq(); | |
804 | /* | |
805 | * update_process_times() expects us to have done irq_enter(). | |
806 | * Besides, if we don't timer interrupts ignore the global | |
807 | * interrupt lock, which is the WrongThing (tm) to do. | |
808 | */ | |
6460bc73 | 809 | #ifdef CONFIG_X86_64 |
0e078e2f | 810 | exit_idle(); |
6460bc73 | 811 | #endif |
0e078e2f TG |
812 | irq_enter(); |
813 | local_apic_timer_interrupt(); | |
814 | irq_exit(); | |
274cfe59 | 815 | |
0e078e2f TG |
816 | set_irq_regs(old_regs); |
817 | } | |
818 | ||
819 | int setup_profiling_timer(unsigned int multiplier) | |
820 | { | |
821 | return -EINVAL; | |
822 | } | |
823 | ||
0e078e2f TG |
824 | /* |
825 | * Local APIC start and shutdown | |
826 | */ | |
827 | ||
828 | /** | |
829 | * clear_local_APIC - shutdown the local APIC | |
830 | * | |
831 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
832 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
833 | * leftovers during boot. | |
834 | */ | |
835 | void clear_local_APIC(void) | |
836 | { | |
2584a82d | 837 | int maxlvt; |
0e078e2f TG |
838 | u32 v; |
839 | ||
d3432896 AK |
840 | /* APIC hasn't been mapped yet */ |
841 | if (!apic_phys) | |
842 | return; | |
843 | ||
844 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
845 | /* |
846 | * Masking an LVT entry can trigger a local APIC error | |
847 | * if the vector is zero. Mask LVTERR first to prevent this. | |
848 | */ | |
849 | if (maxlvt >= 3) { | |
850 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
851 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
852 | } | |
853 | /* | |
854 | * Careful: we have to set masks only first to deassert | |
855 | * any level-triggered sources. | |
856 | */ | |
857 | v = apic_read(APIC_LVTT); | |
858 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
859 | v = apic_read(APIC_LVT0); | |
860 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
861 | v = apic_read(APIC_LVT1); | |
862 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
863 | if (maxlvt >= 4) { | |
864 | v = apic_read(APIC_LVTPC); | |
865 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
866 | } | |
867 | ||
6764014b CG |
868 | /* lets not touch this if we didn't frob it */ |
869 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) | |
870 | if (maxlvt >= 5) { | |
871 | v = apic_read(APIC_LVTTHMR); | |
872 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
873 | } | |
874 | #endif | |
0e078e2f TG |
875 | /* |
876 | * Clean APIC state for other OSs: | |
877 | */ | |
878 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
879 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
880 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
881 | if (maxlvt >= 3) | |
882 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
883 | if (maxlvt >= 4) | |
884 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
885 | |
886 | /* Integrated APIC (!82489DX) ? */ | |
887 | if (lapic_is_integrated()) { | |
888 | if (maxlvt > 3) | |
889 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
890 | apic_write(APIC_ESR, 0); | |
891 | apic_read(APIC_ESR); | |
892 | } | |
0e078e2f TG |
893 | } |
894 | ||
895 | /** | |
896 | * disable_local_APIC - clear and disable the local APIC | |
897 | */ | |
898 | void disable_local_APIC(void) | |
899 | { | |
900 | unsigned int value; | |
901 | ||
902 | clear_local_APIC(); | |
903 | ||
904 | /* | |
905 | * Disable APIC (implies clearing of registers | |
906 | * for 82489DX!). | |
907 | */ | |
908 | value = apic_read(APIC_SPIV); | |
909 | value &= ~APIC_SPIV_APIC_ENABLED; | |
910 | apic_write(APIC_SPIV, value); | |
990b183e CG |
911 | |
912 | #ifdef CONFIG_X86_32 | |
913 | /* | |
914 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
915 | * restore the disabled state. | |
916 | */ | |
917 | if (enabled_via_apicbase) { | |
918 | unsigned int l, h; | |
919 | ||
920 | rdmsr(MSR_IA32_APICBASE, l, h); | |
921 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
922 | wrmsr(MSR_IA32_APICBASE, l, h); | |
923 | } | |
924 | #endif | |
0e078e2f TG |
925 | } |
926 | ||
fe4024dc CG |
927 | /* |
928 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
929 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
930 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
931 | * for the case where Linux didn't enable the LAPIC. | |
932 | */ | |
0e078e2f TG |
933 | void lapic_shutdown(void) |
934 | { | |
935 | unsigned long flags; | |
936 | ||
937 | if (!cpu_has_apic) | |
938 | return; | |
939 | ||
940 | local_irq_save(flags); | |
941 | ||
fe4024dc CG |
942 | #ifdef CONFIG_X86_32 |
943 | if (!enabled_via_apicbase) | |
944 | clear_local_APIC(); | |
945 | else | |
946 | #endif | |
947 | disable_local_APIC(); | |
948 | ||
0e078e2f TG |
949 | |
950 | local_irq_restore(flags); | |
951 | } | |
952 | ||
953 | /* | |
954 | * This is to verify that we're looking at a real local APIC. | |
955 | * Check these against your board if the CPUs aren't getting | |
956 | * started for no apparent reason. | |
957 | */ | |
958 | int __init verify_local_APIC(void) | |
959 | { | |
960 | unsigned int reg0, reg1; | |
961 | ||
962 | /* | |
963 | * The version register is read-only in a real APIC. | |
964 | */ | |
965 | reg0 = apic_read(APIC_LVR); | |
966 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
967 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
968 | reg1 = apic_read(APIC_LVR); | |
969 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
970 | ||
971 | /* | |
972 | * The two version reads above should print the same | |
973 | * numbers. If the second one is different, then we | |
974 | * poke at a non-APIC. | |
975 | */ | |
976 | if (reg1 != reg0) | |
977 | return 0; | |
978 | ||
979 | /* | |
980 | * Check if the version looks reasonably. | |
981 | */ | |
982 | reg1 = GET_APIC_VERSION(reg0); | |
983 | if (reg1 == 0x00 || reg1 == 0xff) | |
984 | return 0; | |
985 | reg1 = lapic_get_maxlvt(); | |
986 | if (reg1 < 0x02 || reg1 == 0xff) | |
987 | return 0; | |
988 | ||
989 | /* | |
990 | * The ID register is read/write in a real APIC. | |
991 | */ | |
2d7a66d0 | 992 | reg0 = apic_read(APIC_ID); |
0e078e2f TG |
993 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
994 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
2d7a66d0 | 995 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
996 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
997 | apic_write(APIC_ID, reg0); | |
998 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
999 | return 0; | |
1000 | ||
1001 | /* | |
1da177e4 LT |
1002 | * The next two are just to see if we have sane values. |
1003 | * They're only really relevant if we're in Virtual Wire | |
1004 | * compatibility mode, but most boxes are anymore. | |
1005 | */ | |
1006 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 1007 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
1008 | reg1 = apic_read(APIC_LVT1); |
1009 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
1010 | ||
1011 | return 1; | |
1012 | } | |
1013 | ||
0e078e2f TG |
1014 | /** |
1015 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1016 | */ | |
1da177e4 LT |
1017 | void __init sync_Arb_IDs(void) |
1018 | { | |
296cb951 CG |
1019 | /* |
1020 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1021 | * needed on AMD. | |
1022 | */ | |
1023 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1024 | return; |
1025 | ||
1026 | /* | |
1027 | * Wait for idle. | |
1028 | */ | |
1029 | apic_wait_icr_idle(); | |
1030 | ||
1031 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1032 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1033 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1034 | } |
1035 | ||
1da177e4 LT |
1036 | /* |
1037 | * An initial setup of the virtual wire mode. | |
1038 | */ | |
1039 | void __init init_bsp_APIC(void) | |
1040 | { | |
11a8e778 | 1041 | unsigned int value; |
1da177e4 LT |
1042 | |
1043 | /* | |
1044 | * Don't do the setup now if we have a SMP BIOS as the | |
1045 | * through-I/O-APIC virtual wire mode might be active. | |
1046 | */ | |
1047 | if (smp_found_config || !cpu_has_apic) | |
1048 | return; | |
1049 | ||
1da177e4 LT |
1050 | /* |
1051 | * Do not trust the local APIC being empty at bootup. | |
1052 | */ | |
1053 | clear_local_APIC(); | |
1054 | ||
1055 | /* | |
1056 | * Enable APIC. | |
1057 | */ | |
1058 | value = apic_read(APIC_SPIV); | |
1059 | value &= ~APIC_VECTOR_MASK; | |
1060 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
1061 | |
1062 | #ifdef CONFIG_X86_32 | |
1063 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1064 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1065 | (boot_cpu_data.x86 == 15)) | |
1066 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1067 | else | |
1068 | #endif | |
1069 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1070 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 1071 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1072 | |
1073 | /* | |
1074 | * Set up the virtual wire mode. | |
1075 | */ | |
11a8e778 | 1076 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 1077 | value = APIC_DM_NMI; |
638c0411 CG |
1078 | if (!lapic_is_integrated()) /* 82489DX */ |
1079 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1080 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
1081 | } |
1082 | ||
c43da2f5 CG |
1083 | static void __cpuinit lapic_setup_esr(void) |
1084 | { | |
9df08f10 CG |
1085 | unsigned int oldvalue, value, maxlvt; |
1086 | ||
1087 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1088 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1089 | return; |
1090 | } | |
c43da2f5 | 1091 | |
9df08f10 | 1092 | if (esr_disable) { |
c43da2f5 | 1093 | /* |
9df08f10 CG |
1094 | * Something untraceable is creating bad interrupts on |
1095 | * secondary quads ... for the moment, just leave the | |
1096 | * ESR disabled - we can't do anything useful with the | |
1097 | * errors anyway - mbligh | |
c43da2f5 | 1098 | */ |
ba21ebb6 | 1099 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1100 | return; |
c43da2f5 | 1101 | } |
9df08f10 CG |
1102 | |
1103 | maxlvt = lapic_get_maxlvt(); | |
1104 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1105 | apic_write(APIC_ESR, 0); | |
1106 | oldvalue = apic_read(APIC_ESR); | |
1107 | ||
1108 | /* enables sending errors */ | |
1109 | value = ERROR_APIC_VECTOR; | |
1110 | apic_write(APIC_LVTERR, value); | |
1111 | ||
1112 | /* | |
1113 | * spec says clear errors after enabling vector. | |
1114 | */ | |
1115 | if (maxlvt > 3) | |
1116 | apic_write(APIC_ESR, 0); | |
1117 | value = apic_read(APIC_ESR); | |
1118 | if (value != oldvalue) | |
1119 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1120 | "vector: 0x%08x after: 0x%08x\n", | |
1121 | oldvalue, value); | |
c43da2f5 CG |
1122 | } |
1123 | ||
1124 | ||
0e078e2f TG |
1125 | /** |
1126 | * setup_local_APIC - setup the local APIC | |
1127 | */ | |
1128 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 1129 | { |
739f33b3 | 1130 | unsigned int value; |
da7ed9f9 | 1131 | int i, j; |
1da177e4 | 1132 | |
89c38c28 CG |
1133 | #ifdef CONFIG_X86_32 |
1134 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08ad776e | 1135 | if (lapic_is_integrated() && esr_disable) { |
89c38c28 CG |
1136 | apic_write(APIC_ESR, 0); |
1137 | apic_write(APIC_ESR, 0); | |
1138 | apic_write(APIC_ESR, 0); | |
1139 | apic_write(APIC_ESR, 0); | |
1140 | } | |
1141 | #endif | |
1142 | ||
ac23d4ee | 1143 | preempt_disable(); |
1da177e4 | 1144 | |
1da177e4 LT |
1145 | /* |
1146 | * Double-check whether this APIC is really registered. | |
1147 | * This is meaningless in clustered apic mode, so we skip it. | |
1148 | */ | |
1149 | if (!apic_id_registered()) | |
1150 | BUG(); | |
1151 | ||
1152 | /* | |
1153 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1154 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1155 | * document number 292116). So here it goes... | |
1156 | */ | |
1157 | init_apic_ldr(); | |
1158 | ||
1159 | /* | |
1160 | * Set Task Priority to 'accept all'. We never change this | |
1161 | * later on. | |
1162 | */ | |
1163 | value = apic_read(APIC_TASKPRI); | |
1164 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1165 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1166 | |
da7ed9f9 VG |
1167 | /* |
1168 | * After a crash, we no longer service the interrupts and a pending | |
1169 | * interrupt from previous kernel might still have ISR bit set. | |
1170 | * | |
1171 | * Most probably by now CPU has serviced that pending interrupt and | |
1172 | * it might not have done the ack_APIC_irq() because it thought, | |
1173 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1174 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1175 | * the interrupt. Hence a vector might get locked. It was noticed | |
1176 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1177 | */ | |
1178 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1179 | value = apic_read(APIC_ISR + i*0x10); | |
1180 | for (j = 31; j >= 0; j--) { | |
1181 | if (value & (1<<j)) | |
1182 | ack_APIC_irq(); | |
1183 | } | |
1184 | } | |
1185 | ||
1da177e4 LT |
1186 | /* |
1187 | * Now that we are all set up, enable the APIC | |
1188 | */ | |
1189 | value = apic_read(APIC_SPIV); | |
1190 | value &= ~APIC_VECTOR_MASK; | |
1191 | /* | |
1192 | * Enable APIC | |
1193 | */ | |
1194 | value |= APIC_SPIV_APIC_ENABLED; | |
1195 | ||
89c38c28 CG |
1196 | #ifdef CONFIG_X86_32 |
1197 | /* | |
1198 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1199 | * certain networking cards. If high frequency interrupts are | |
1200 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1201 | * entry is masked/unmasked at a high rate as well then sooner or | |
1202 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1203 | * from the device. If focus CPU is disabled then the hang goes | |
1204 | * away, oh well :-( | |
1205 | * | |
1206 | * [ This bug can be reproduced easily with a level-triggered | |
1207 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1208 | * BX chipset. ] | |
1209 | */ | |
1210 | /* | |
1211 | * Actually disabling the focus CPU check just makes the hang less | |
1212 | * frequent as it makes the interrupt distributon model be more | |
1213 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1214 | * See also the comment in end_level_ioapic_irq(). --macro | |
1215 | */ | |
1216 | ||
1217 | /* | |
1218 | * - enable focus processor (bit==0) | |
1219 | * - 64bit mode always use processor focus | |
1220 | * so no need to set it | |
1221 | */ | |
1222 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1223 | #endif | |
3f14c746 | 1224 | |
1da177e4 LT |
1225 | /* |
1226 | * Set spurious IRQ vector | |
1227 | */ | |
1228 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1229 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1230 | |
1231 | /* | |
1232 | * Set up LVT0, LVT1: | |
1233 | * | |
1234 | * set up through-local-APIC on the BP's LINT0. This is not | |
1235 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1236 | * we delegate interrupts to the 8259A. | |
1237 | */ | |
1238 | /* | |
1239 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1240 | */ | |
1241 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
89c38c28 | 1242 | if (!smp_processor_id() && (pic_mode || !value)) { |
1da177e4 | 1243 | value = APIC_DM_EXTINT; |
bc1d99c1 | 1244 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
89c38c28 | 1245 | smp_processor_id()); |
1da177e4 LT |
1246 | } else { |
1247 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 | 1248 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
89c38c28 | 1249 | smp_processor_id()); |
1da177e4 | 1250 | } |
11a8e778 | 1251 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1252 | |
1253 | /* | |
1254 | * only the BP should see the LINT1 NMI signal, obviously. | |
1255 | */ | |
1256 | if (!smp_processor_id()) | |
1257 | value = APIC_DM_NMI; | |
1258 | else | |
1259 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1260 | if (!lapic_is_integrated()) /* 82489DX */ |
1261 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1262 | apic_write(APIC_LVT1, value); |
89c38c28 | 1263 | |
ac23d4ee | 1264 | preempt_enable(); |
739f33b3 | 1265 | } |
1da177e4 | 1266 | |
739f33b3 AK |
1267 | void __cpuinit end_local_APIC_setup(void) |
1268 | { | |
1269 | lapic_setup_esr(); | |
fa6b95fc CG |
1270 | |
1271 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1272 | { |
1273 | unsigned int value; | |
1274 | /* Disable the local apic timer */ | |
1275 | value = apic_read(APIC_LVTT); | |
1276 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1277 | apic_write(APIC_LVTT, value); | |
1278 | } | |
fa6b95fc CG |
1279 | #endif |
1280 | ||
f2802e7f | 1281 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 1282 | apic_pm_activate(); |
1da177e4 | 1283 | } |
1da177e4 | 1284 | |
49899eac | 1285 | #ifdef HAVE_X2APIC |
6e1cb38a SS |
1286 | void check_x2apic(void) |
1287 | { | |
1288 | int msr, msr2; | |
1289 | ||
1290 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1291 | ||
1292 | if (msr & X2APIC_ENABLE) { | |
ba21ebb6 | 1293 | pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); |
6e1cb38a SS |
1294 | x2apic_preenabled = x2apic = 1; |
1295 | apic_ops = &x2apic_ops; | |
1296 | } | |
1297 | } | |
1298 | ||
1299 | void enable_x2apic(void) | |
1300 | { | |
1301 | int msr, msr2; | |
1302 | ||
1303 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1304 | if (!(msr & X2APIC_ENABLE)) { | |
ba21ebb6 | 1305 | pr_info("Enabling x2apic\n"); |
6e1cb38a SS |
1306 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); |
1307 | } | |
1308 | } | |
1309 | ||
2236d252 | 1310 | void __init enable_IR_x2apic(void) |
6e1cb38a SS |
1311 | { |
1312 | #ifdef CONFIG_INTR_REMAP | |
1313 | int ret; | |
1314 | unsigned long flags; | |
1315 | ||
1316 | if (!cpu_has_x2apic) | |
1317 | return; | |
1318 | ||
1319 | if (!x2apic_preenabled && disable_x2apic) { | |
ba21ebb6 CG |
1320 | pr_info("Skipped enabling x2apic and Interrupt-remapping " |
1321 | "because of nox2apic\n"); | |
6e1cb38a SS |
1322 | return; |
1323 | } | |
1324 | ||
1325 | if (x2apic_preenabled && disable_x2apic) | |
1326 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | |
1327 | ||
1328 | if (!x2apic_preenabled && skip_ioapic_setup) { | |
ba21ebb6 CG |
1329 | pr_info("Skipped enabling x2apic and Interrupt-remapping " |
1330 | "because of skipping io-apic setup\n"); | |
6e1cb38a SS |
1331 | return; |
1332 | } | |
1333 | ||
1334 | ret = dmar_table_init(); | |
1335 | if (ret) { | |
ba21ebb6 | 1336 | pr_info("dmar_table_init() failed with %d:\n", ret); |
6e1cb38a SS |
1337 | |
1338 | if (x2apic_preenabled) | |
1339 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1340 | else | |
ba21ebb6 | 1341 | pr_info("Not enabling x2apic,Intr-remapping\n"); |
6e1cb38a SS |
1342 | return; |
1343 | } | |
1344 | ||
1345 | local_irq_save(flags); | |
1346 | mask_8259A(); | |
5ffa4eb2 CG |
1347 | |
1348 | ret = save_mask_IO_APIC_setup(); | |
1349 | if (ret) { | |
ba21ebb6 | 1350 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
5ffa4eb2 CG |
1351 | goto end; |
1352 | } | |
6e1cb38a SS |
1353 | |
1354 | ret = enable_intr_remapping(1); | |
1355 | ||
1356 | if (ret && x2apic_preenabled) { | |
1357 | local_irq_restore(flags); | |
1358 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1359 | } | |
1360 | ||
1361 | if (ret) | |
5ffa4eb2 | 1362 | goto end_restore; |
6e1cb38a SS |
1363 | |
1364 | if (!x2apic) { | |
1365 | x2apic = 1; | |
1366 | apic_ops = &x2apic_ops; | |
1367 | enable_x2apic(); | |
1368 | } | |
5ffa4eb2 CG |
1369 | |
1370 | end_restore: | |
6e1cb38a SS |
1371 | if (ret) |
1372 | /* | |
1373 | * IR enabling failed | |
1374 | */ | |
1375 | restore_IO_APIC_setup(); | |
1376 | else | |
1377 | reinit_intr_remapped_IO_APIC(x2apic_preenabled); | |
1378 | ||
5ffa4eb2 | 1379 | end: |
6e1cb38a SS |
1380 | unmask_8259A(); |
1381 | local_irq_restore(flags); | |
1382 | ||
1383 | if (!ret) { | |
1384 | if (!x2apic_preenabled) | |
ba21ebb6 | 1385 | pr_info("Enabled x2apic and interrupt-remapping\n"); |
6e1cb38a | 1386 | else |
ba21ebb6 | 1387 | pr_info("Enabled Interrupt-remapping\n"); |
6e1cb38a | 1388 | } else |
ba21ebb6 | 1389 | pr_err("Failed to enable Interrupt-remapping and x2apic\n"); |
6e1cb38a SS |
1390 | #else |
1391 | if (!cpu_has_x2apic) | |
1392 | return; | |
1393 | ||
1394 | if (x2apic_preenabled) | |
1395 | panic("x2apic enabled prior OS handover," | |
1396 | " enable CONFIG_INTR_REMAP"); | |
1397 | ||
ba21ebb6 CG |
1398 | pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping " |
1399 | " and x2apic\n"); | |
6e1cb38a SS |
1400 | #endif |
1401 | ||
1402 | return; | |
1403 | } | |
49899eac | 1404 | #endif /* HAVE_X2APIC */ |
6e1cb38a | 1405 | |
be7a656f | 1406 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1407 | /* |
1408 | * Detect and enable local APICs on non-SMP boards. | |
1409 | * Original code written by Keir Fraser. | |
1410 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1411 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1412 | */ |
0e078e2f | 1413 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1414 | { |
1415 | if (!cpu_has_apic) { | |
ba21ebb6 | 1416 | pr_info("No local APIC present\n"); |
1da177e4 LT |
1417 | return -1; |
1418 | } | |
1419 | ||
1420 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1421 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1422 | return 0; |
1423 | } | |
be7a656f YL |
1424 | #else |
1425 | /* | |
1426 | * Detect and initialize APIC | |
1427 | */ | |
1428 | static int __init detect_init_APIC(void) | |
1429 | { | |
1430 | u32 h, l, features; | |
1431 | ||
1432 | /* Disabled by kernel option? */ | |
1433 | if (disable_apic) | |
1434 | return -1; | |
1435 | ||
1436 | switch (boot_cpu_data.x86_vendor) { | |
1437 | case X86_VENDOR_AMD: | |
1438 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
1439 | (boot_cpu_data.x86 == 15)) | |
1440 | break; | |
1441 | goto no_apic; | |
1442 | case X86_VENDOR_INTEL: | |
1443 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1444 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1445 | break; | |
1446 | goto no_apic; | |
1447 | default: | |
1448 | goto no_apic; | |
1449 | } | |
1450 | ||
1451 | if (!cpu_has_apic) { | |
1452 | /* | |
1453 | * Over-ride BIOS and try to enable the local APIC only if | |
1454 | * "lapic" specified. | |
1455 | */ | |
1456 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
1457 | pr_info("Local APIC disabled by BIOS -- " |
1458 | "you can enable it with \"lapic\"\n"); | |
be7a656f YL |
1459 | return -1; |
1460 | } | |
1461 | /* | |
1462 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1463 | * MSR. This can only be done in software for Intel P6 or later | |
1464 | * and AMD K7 (Model > 1) or later. | |
1465 | */ | |
1466 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1467 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
ba21ebb6 | 1468 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); |
be7a656f YL |
1469 | l &= ~MSR_IA32_APICBASE_BASE; |
1470 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1471 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1472 | enabled_via_apicbase = 1; | |
1473 | } | |
1474 | } | |
1475 | /* | |
1476 | * The APIC feature bit should now be enabled | |
1477 | * in `cpuid' | |
1478 | */ | |
1479 | features = cpuid_edx(1); | |
1480 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
ba21ebb6 | 1481 | pr_warning("Could not enable APIC!\n"); |
be7a656f YL |
1482 | return -1; |
1483 | } | |
1484 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1485 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1486 | ||
1487 | /* The BIOS may have set up the APIC at some other address */ | |
1488 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1489 | if (l & MSR_IA32_APICBASE_ENABLE) | |
1490 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1491 | ||
ba21ebb6 | 1492 | pr_info("Found and enabled local APIC!\n"); |
be7a656f YL |
1493 | |
1494 | apic_pm_activate(); | |
1495 | ||
1496 | return 0; | |
1497 | ||
1498 | no_apic: | |
ba21ebb6 | 1499 | pr_info("No local APIC present or hardware disabled\n"); |
be7a656f YL |
1500 | return -1; |
1501 | } | |
1502 | #endif | |
1da177e4 | 1503 | |
f28c0ae2 | 1504 | #ifdef CONFIG_X86_64 |
8643f9d0 YL |
1505 | void __init early_init_lapic_mapping(void) |
1506 | { | |
431ee79d | 1507 | unsigned long phys_addr; |
8643f9d0 YL |
1508 | |
1509 | /* | |
1510 | * If no local APIC can be found then go out | |
1511 | * : it means there is no mpatable and MADT | |
1512 | */ | |
1513 | if (!smp_found_config) | |
1514 | return; | |
1515 | ||
431ee79d | 1516 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1517 | |
431ee79d | 1518 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1519 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1520 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1521 | |
1522 | /* | |
1523 | * Fetch the APIC ID of the BSP in case we have a | |
1524 | * default configuration (or the MP table is broken). | |
1525 | */ | |
4c9961d5 | 1526 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 | 1527 | } |
f28c0ae2 | 1528 | #endif |
8643f9d0 | 1529 | |
0e078e2f TG |
1530 | /** |
1531 | * init_apic_mappings - initialize APIC mappings | |
1532 | */ | |
1da177e4 LT |
1533 | void __init init_apic_mappings(void) |
1534 | { | |
49899eac | 1535 | #ifdef HAVE_X2APIC |
6e1cb38a | 1536 | if (x2apic) { |
4c9961d5 | 1537 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1538 | return; |
1539 | } | |
49899eac | 1540 | #endif |
6e1cb38a | 1541 | |
1da177e4 LT |
1542 | /* |
1543 | * If no local APIC can be found then set up a fake all | |
1544 | * zeroes page to simulate the local APIC and another | |
1545 | * one for the IO-APIC. | |
1546 | */ | |
1547 | if (!smp_found_config && detect_init_APIC()) { | |
1548 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1549 | apic_phys = __pa(apic_phys); | |
1550 | } else | |
1551 | apic_phys = mp_lapic_addr; | |
1552 | ||
1553 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
79c09698 | 1554 | apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", |
7ffeeb1e | 1555 | APIC_BASE, apic_phys); |
1da177e4 LT |
1556 | |
1557 | /* | |
1558 | * Fetch the APIC ID of the BSP in case we have a | |
1559 | * default configuration (or the MP table is broken). | |
1560 | */ | |
f28c0ae2 YL |
1561 | if (boot_cpu_physical_apicid == -1U) |
1562 | boot_cpu_physical_apicid = read_apic_id(); | |
1da177e4 LT |
1563 | } |
1564 | ||
1565 | /* | |
0e078e2f TG |
1566 | * This initializes the IO-APIC and APIC hardware if this is |
1567 | * a UP kernel. | |
1da177e4 | 1568 | */ |
1b313f4a CG |
1569 | int apic_version[MAX_APICS]; |
1570 | ||
0e078e2f | 1571 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1572 | { |
fa2bd35a | 1573 | #ifdef CONFIG_X86_64 |
0e078e2f | 1574 | if (disable_apic) { |
ba21ebb6 | 1575 | pr_info("Apic disabled\n"); |
0e078e2f TG |
1576 | return -1; |
1577 | } | |
1578 | if (!cpu_has_apic) { | |
1579 | disable_apic = 1; | |
ba21ebb6 | 1580 | pr_info("Apic disabled by BIOS\n"); |
0e078e2f TG |
1581 | return -1; |
1582 | } | |
fa2bd35a YL |
1583 | #else |
1584 | if (!smp_found_config && !cpu_has_apic) | |
1585 | return -1; | |
1586 | ||
1587 | /* | |
1588 | * Complain if the BIOS pretends there is one. | |
1589 | */ | |
1590 | if (!cpu_has_apic && | |
1591 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
ba21ebb6 CG |
1592 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
1593 | boot_cpu_physical_apicid); | |
fa2bd35a YL |
1594 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1595 | return -1; | |
1596 | } | |
1597 | #endif | |
1598 | ||
49899eac | 1599 | #ifdef HAVE_X2APIC |
6e1cb38a | 1600 | enable_IR_x2apic(); |
49899eac | 1601 | #endif |
fa2bd35a | 1602 | #ifdef CONFIG_X86_64 |
6e1cb38a | 1603 | setup_apic_routing(); |
fa2bd35a | 1604 | #endif |
6e1cb38a | 1605 | |
0e078e2f | 1606 | verify_local_APIC(); |
b5841765 GC |
1607 | connect_bsp_APIC(); |
1608 | ||
fa2bd35a | 1609 | #ifdef CONFIG_X86_64 |
c70dcb74 | 1610 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
fa2bd35a YL |
1611 | #else |
1612 | /* | |
1613 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1614 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1615 | * might be zero if read from MP tables. Get it from LAPIC. | |
1616 | */ | |
1617 | # ifdef CONFIG_CRASH_DUMP | |
1618 | boot_cpu_physical_apicid = read_apic_id(); | |
1619 | # endif | |
1620 | #endif | |
1621 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
0e078e2f | 1622 | setup_local_APIC(); |
1da177e4 | 1623 | |
fa2bd35a | 1624 | #ifdef CONFIG_X86_64 |
739f33b3 AK |
1625 | /* |
1626 | * Now enable IO-APICs, actually call clear_IO_APIC | |
1627 | * We need clear_IO_APIC before enabling vector on BP | |
1628 | */ | |
1629 | if (!skip_ioapic_setup && nr_ioapics) | |
1630 | enable_IO_APIC(); | |
fa2bd35a | 1631 | #endif |
739f33b3 | 1632 | |
fa2bd35a | 1633 | #ifdef CONFIG_X86_IO_APIC |
acae7d90 | 1634 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) |
fa2bd35a | 1635 | #endif |
acae7d90 | 1636 | localise_nmi_watchdog(); |
739f33b3 AK |
1637 | end_local_APIC_setup(); |
1638 | ||
fa2bd35a | 1639 | #ifdef CONFIG_X86_IO_APIC |
0e078e2f TG |
1640 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1641 | setup_IO_APIC(); | |
fa2bd35a | 1642 | # ifdef CONFIG_X86_64 |
0e078e2f TG |
1643 | else |
1644 | nr_ioapics = 0; | |
fa2bd35a YL |
1645 | # endif |
1646 | #endif | |
1647 | ||
1648 | #ifdef CONFIG_X86_64 | |
0e078e2f TG |
1649 | setup_boot_APIC_clock(); |
1650 | check_nmi_watchdog(); | |
fa2bd35a YL |
1651 | #else |
1652 | setup_boot_clock(); | |
1653 | #endif | |
1654 | ||
0e078e2f | 1655 | return 0; |
1da177e4 LT |
1656 | } |
1657 | ||
1658 | /* | |
0e078e2f | 1659 | * Local APIC interrupts |
1da177e4 LT |
1660 | */ |
1661 | ||
0e078e2f TG |
1662 | /* |
1663 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1664 | */ | |
dc1528dd | 1665 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 | 1666 | { |
dc1528dd YL |
1667 | u32 v; |
1668 | ||
1669 | #ifdef CONFIG_X86_64 | |
0e078e2f | 1670 | exit_idle(); |
dc1528dd | 1671 | #endif |
0e078e2f | 1672 | irq_enter(); |
1da177e4 | 1673 | /* |
0e078e2f TG |
1674 | * Check if this really is a spurious interrupt and ACK it |
1675 | * if it is a vectored one. Just in case... | |
1676 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1677 | */ |
0e078e2f TG |
1678 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1679 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1680 | ack_APIC_irq(); | |
c4d58cbd | 1681 | |
dc1528dd | 1682 | #ifdef CONFIG_X86_64 |
0e078e2f | 1683 | add_pda(irq_spurious_count, 1); |
dc1528dd YL |
1684 | #else |
1685 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
ba21ebb6 CG |
1686 | pr_info("spurious APIC interrupt on CPU#%d, " |
1687 | "should never happen.\n", smp_processor_id()); | |
dc1528dd YL |
1688 | __get_cpu_var(irq_stat).irq_spurious_count++; |
1689 | #endif | |
0e078e2f TG |
1690 | irq_exit(); |
1691 | } | |
1da177e4 | 1692 | |
0e078e2f TG |
1693 | /* |
1694 | * This interrupt should never happen with our APIC/SMP architecture | |
1695 | */ | |
dc1528dd | 1696 | void smp_error_interrupt(struct pt_regs *regs) |
0e078e2f | 1697 | { |
dc1528dd | 1698 | u32 v, v1; |
1da177e4 | 1699 | |
dc1528dd | 1700 | #ifdef CONFIG_X86_64 |
0e078e2f | 1701 | exit_idle(); |
dc1528dd | 1702 | #endif |
0e078e2f TG |
1703 | irq_enter(); |
1704 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1705 | v = apic_read(APIC_ESR); | |
1706 | apic_write(APIC_ESR, 0); | |
1707 | v1 = apic_read(APIC_ESR); | |
1708 | ack_APIC_irq(); | |
1709 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1710 | |
ba21ebb6 CG |
1711 | /* |
1712 | * Here is what the APIC error bits mean: | |
1713 | * 0: Send CS error | |
1714 | * 1: Receive CS error | |
1715 | * 2: Send accept error | |
1716 | * 3: Receive accept error | |
1717 | * 4: Reserved | |
1718 | * 5: Send illegal vector | |
1719 | * 6: Received illegal vector | |
1720 | * 7: Illegal register address | |
1721 | */ | |
1722 | pr_debug("APIC error on CPU%d: %02x(%02x)\n", | |
0e078e2f TG |
1723 | smp_processor_id(), v , v1); |
1724 | irq_exit(); | |
1da177e4 LT |
1725 | } |
1726 | ||
b5841765 | 1727 | /** |
36c9d674 CG |
1728 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1729 | */ | |
b5841765 GC |
1730 | void __init connect_bsp_APIC(void) |
1731 | { | |
36c9d674 CG |
1732 | #ifdef CONFIG_X86_32 |
1733 | if (pic_mode) { | |
1734 | /* | |
1735 | * Do not trust the local APIC being empty at bootup. | |
1736 | */ | |
1737 | clear_local_APIC(); | |
1738 | /* | |
1739 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1740 | * local APIC to INT and NMI lines. | |
1741 | */ | |
1742 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1743 | "enabling APIC mode.\n"); | |
1744 | outb(0x70, 0x22); | |
1745 | outb(0x01, 0x23); | |
1746 | } | |
1747 | #endif | |
b5841765 GC |
1748 | enable_apic_mode(); |
1749 | } | |
1750 | ||
274cfe59 CG |
1751 | /** |
1752 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1753 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1754 | * | |
1755 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1756 | * APIC is disabled. | |
1757 | */ | |
0e078e2f | 1758 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1759 | { |
1b4ee4e4 CG |
1760 | unsigned int value; |
1761 | ||
c177b0bc CG |
1762 | #ifdef CONFIG_X86_32 |
1763 | if (pic_mode) { | |
1764 | /* | |
1765 | * Put the board back into PIC mode (has an effect only on | |
1766 | * certain older boards). Note that APIC interrupts, including | |
1767 | * IPIs, won't work beyond this point! The only exception are | |
1768 | * INIT IPIs. | |
1769 | */ | |
1770 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1771 | "entering PIC mode.\n"); | |
1772 | outb(0x70, 0x22); | |
1773 | outb(0x00, 0x23); | |
1774 | return; | |
1775 | } | |
1776 | #endif | |
1777 | ||
0e078e2f | 1778 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1779 | |
0e078e2f TG |
1780 | /* For the spurious interrupt use vector F, and enable it */ |
1781 | value = apic_read(APIC_SPIV); | |
1782 | value &= ~APIC_VECTOR_MASK; | |
1783 | value |= APIC_SPIV_APIC_ENABLED; | |
1784 | value |= 0xf; | |
1785 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1786 | |
0e078e2f TG |
1787 | if (!virt_wire_setup) { |
1788 | /* | |
1789 | * For LVT0 make it edge triggered, active high, | |
1790 | * external and enabled | |
1791 | */ | |
1792 | value = apic_read(APIC_LVT0); | |
1793 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1794 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1795 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1796 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1797 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1798 | apic_write(APIC_LVT0, value); | |
1799 | } else { | |
1800 | /* Disable LVT0 */ | |
1801 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1802 | } | |
b8ce3359 | 1803 | |
c177b0bc CG |
1804 | /* |
1805 | * For LVT1 make it edge triggered, active high, | |
1806 | * nmi and enabled | |
1807 | */ | |
0e078e2f TG |
1808 | value = apic_read(APIC_LVT1); |
1809 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1810 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1811 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1812 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1813 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1814 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1815 | } |
1816 | ||
be8a5685 AS |
1817 | void __cpuinit generic_processor_info(int apicid, int version) |
1818 | { | |
1819 | int cpu; | |
be8a5685 | 1820 | |
1b313f4a CG |
1821 | /* |
1822 | * Validate version | |
1823 | */ | |
1824 | if (version == 0x0) { | |
ba21ebb6 | 1825 | pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " |
3b11ce7f MT |
1826 | "fixing up to 0x10. (tell your hw vendor)\n", |
1827 | version); | |
1b313f4a | 1828 | version = 0x10; |
be8a5685 | 1829 | } |
1b313f4a | 1830 | apic_version[apicid] = version; |
be8a5685 | 1831 | |
3b11ce7f MT |
1832 | if (num_processors >= nr_cpu_ids) { |
1833 | int max = nr_cpu_ids; | |
1834 | int thiscpu = max + disabled_cpus; | |
1835 | ||
1836 | pr_warning( | |
1837 | "ACPI: NR_CPUS/possible_cpus limit of %i reached." | |
1838 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
1839 | ||
1840 | disabled_cpus++; | |
be8a5685 AS |
1841 | return; |
1842 | } | |
1843 | ||
1844 | num_processors++; | |
3b11ce7f | 1845 | cpu = cpumask_next_zero(-1, cpu_present_mask); |
be8a5685 AS |
1846 | |
1847 | physid_set(apicid, phys_cpu_present_map); | |
1848 | if (apicid == boot_cpu_physical_apicid) { | |
1849 | /* | |
1850 | * x86_bios_cpu_apicid is required to have processors listed | |
1851 | * in same order as logical cpu numbers. Hence the first | |
1852 | * entry is BSP, and so on. | |
1853 | */ | |
1854 | cpu = 0; | |
1855 | } | |
e0da3364 YL |
1856 | if (apicid > max_physical_apicid) |
1857 | max_physical_apicid = apicid; | |
1858 | ||
1b313f4a CG |
1859 | #ifdef CONFIG_X86_32 |
1860 | /* | |
1861 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1862 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1863 | * before this can be done without some confusion. | |
1864 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1865 | * - Ashok Raj <ashok.raj@intel.com> | |
1866 | */ | |
1867 | if (max_physical_apicid >= 8) { | |
1868 | switch (boot_cpu_data.x86_vendor) { | |
1869 | case X86_VENDOR_INTEL: | |
1870 | if (!APIC_XAPIC(version)) { | |
1871 | def_to_bigsmp = 0; | |
1872 | break; | |
1873 | } | |
1874 | /* If P4 and above fall through */ | |
1875 | case X86_VENDOR_AMD: | |
1876 | def_to_bigsmp = 1; | |
1877 | } | |
1878 | } | |
1879 | #endif | |
1880 | ||
1881 | #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64) | |
be8a5685 | 1882 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1883 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1884 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1885 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
be8a5685 AS |
1886 | |
1887 | cpu_to_apicid[cpu] = apicid; | |
1888 | bios_cpu_apicid[cpu] = apicid; | |
1889 | } else { | |
1890 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1891 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1892 | } | |
1b313f4a | 1893 | #endif |
be8a5685 | 1894 | |
1de88cd4 MT |
1895 | set_cpu_possible(cpu, true); |
1896 | set_cpu_present(cpu, true); | |
be8a5685 AS |
1897 | } |
1898 | ||
3491998d | 1899 | #ifdef CONFIG_X86_64 |
0c81c746 SS |
1900 | int hard_smp_processor_id(void) |
1901 | { | |
1902 | return read_apic_id(); | |
1903 | } | |
3491998d | 1904 | #endif |
0c81c746 | 1905 | |
89039b37 | 1906 | /* |
0e078e2f | 1907 | * Power management |
89039b37 | 1908 | */ |
0e078e2f TG |
1909 | #ifdef CONFIG_PM |
1910 | ||
1911 | static struct { | |
274cfe59 CG |
1912 | /* |
1913 | * 'active' is true if the local APIC was enabled by us and | |
1914 | * not the BIOS; this signifies that we are also responsible | |
1915 | * for disabling it before entering apm/acpi suspend | |
1916 | */ | |
0e078e2f TG |
1917 | int active; |
1918 | /* r/w apic fields */ | |
1919 | unsigned int apic_id; | |
1920 | unsigned int apic_taskpri; | |
1921 | unsigned int apic_ldr; | |
1922 | unsigned int apic_dfr; | |
1923 | unsigned int apic_spiv; | |
1924 | unsigned int apic_lvtt; | |
1925 | unsigned int apic_lvtpc; | |
1926 | unsigned int apic_lvt0; | |
1927 | unsigned int apic_lvt1; | |
1928 | unsigned int apic_lvterr; | |
1929 | unsigned int apic_tmict; | |
1930 | unsigned int apic_tdcr; | |
1931 | unsigned int apic_thmr; | |
1932 | } apic_pm_state; | |
1933 | ||
1934 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1935 | { | |
1936 | unsigned long flags; | |
1937 | int maxlvt; | |
89039b37 | 1938 | |
0e078e2f TG |
1939 | if (!apic_pm_state.active) |
1940 | return 0; | |
89039b37 | 1941 | |
0e078e2f | 1942 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1943 | |
2d7a66d0 | 1944 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1945 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1946 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1947 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1948 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1949 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1950 | if (maxlvt >= 4) | |
1951 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1952 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1953 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1954 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1955 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1956 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 1957 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1958 | if (maxlvt >= 5) |
1959 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1960 | #endif | |
24968cfd | 1961 | |
0e078e2f TG |
1962 | local_irq_save(flags); |
1963 | disable_local_APIC(); | |
1964 | local_irq_restore(flags); | |
1965 | return 0; | |
1da177e4 LT |
1966 | } |
1967 | ||
0e078e2f | 1968 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1969 | { |
0e078e2f TG |
1970 | unsigned int l, h; |
1971 | unsigned long flags; | |
1972 | int maxlvt; | |
1da177e4 | 1973 | |
0e078e2f TG |
1974 | if (!apic_pm_state.active) |
1975 | return 0; | |
89b831ef | 1976 | |
0e078e2f | 1977 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1978 | |
0e078e2f | 1979 | local_irq_save(flags); |
92206c90 | 1980 | |
49899eac | 1981 | #ifdef HAVE_X2APIC |
92206c90 CG |
1982 | if (x2apic) |
1983 | enable_x2apic(); | |
1984 | else | |
1985 | #endif | |
d5e629a6 | 1986 | { |
92206c90 CG |
1987 | /* |
1988 | * Make sure the APICBASE points to the right address | |
1989 | * | |
1990 | * FIXME! This will be wrong if we ever support suspend on | |
1991 | * SMP! We'll need to do this as part of the CPU restore! | |
1992 | */ | |
6e1cb38a SS |
1993 | rdmsr(MSR_IA32_APICBASE, l, h); |
1994 | l &= ~MSR_IA32_APICBASE_BASE; | |
1995 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1996 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 1997 | } |
6e1cb38a | 1998 | |
0e078e2f TG |
1999 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2000 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2001 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2002 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2003 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2004 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2005 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2006 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 2007 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
2008 | if (maxlvt >= 5) |
2009 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
2010 | #endif | |
2011 | if (maxlvt >= 4) | |
2012 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2013 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2014 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2015 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2016 | apic_write(APIC_ESR, 0); | |
2017 | apic_read(APIC_ESR); | |
2018 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2019 | apic_write(APIC_ESR, 0); | |
2020 | apic_read(APIC_ESR); | |
92206c90 | 2021 | |
0e078e2f | 2022 | local_irq_restore(flags); |
92206c90 | 2023 | |
0e078e2f TG |
2024 | return 0; |
2025 | } | |
b8ce3359 | 2026 | |
274cfe59 CG |
2027 | /* |
2028 | * This device has no shutdown method - fully functioning local APICs | |
2029 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2030 | */ | |
2031 | ||
0e078e2f TG |
2032 | static struct sysdev_class lapic_sysclass = { |
2033 | .name = "lapic", | |
2034 | .resume = lapic_resume, | |
2035 | .suspend = lapic_suspend, | |
2036 | }; | |
b8ce3359 | 2037 | |
0e078e2f | 2038 | static struct sys_device device_lapic = { |
e83a5fdc HS |
2039 | .id = 0, |
2040 | .cls = &lapic_sysclass, | |
0e078e2f | 2041 | }; |
b8ce3359 | 2042 | |
0e078e2f TG |
2043 | static void __cpuinit apic_pm_activate(void) |
2044 | { | |
2045 | apic_pm_state.active = 1; | |
1da177e4 LT |
2046 | } |
2047 | ||
0e078e2f | 2048 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2049 | { |
0e078e2f | 2050 | int error; |
e83a5fdc | 2051 | |
0e078e2f TG |
2052 | if (!cpu_has_apic) |
2053 | return 0; | |
2054 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 2055 | |
0e078e2f TG |
2056 | error = sysdev_class_register(&lapic_sysclass); |
2057 | if (!error) | |
2058 | error = sysdev_register(&device_lapic); | |
2059 | return error; | |
1da177e4 | 2060 | } |
0e078e2f TG |
2061 | device_initcall(init_lapic_sysfs); |
2062 | ||
2063 | #else /* CONFIG_PM */ | |
2064 | ||
2065 | static void apic_pm_activate(void) { } | |
2066 | ||
2067 | #endif /* CONFIG_PM */ | |
1da177e4 | 2068 | |
f28c0ae2 | 2069 | #ifdef CONFIG_X86_64 |
1da177e4 | 2070 | /* |
f8bf3c65 | 2071 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
2072 | * |
2073 | * Thus far, the major user of this is IBM's Summit2 series: | |
2074 | * | |
637029c6 | 2075 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
2076 | * multi-chassis. Use available data to take a good guess. |
2077 | * If in doubt, go HPET. | |
2078 | */ | |
f8bf3c65 | 2079 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
2080 | { |
2081 | int i, clusters, zeros; | |
2082 | unsigned id; | |
322850af | 2083 | u16 *bios_cpu_apicid; |
1da177e4 LT |
2084 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
2085 | ||
322850af YL |
2086 | /* |
2087 | * there is not this kind of box with AMD CPU yet. | |
2088 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
2089 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 2090 | * vsmp box still need checking... |
322850af | 2091 | */ |
1cb68487 | 2092 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
2093 | return 0; |
2094 | ||
23ca4bba | 2095 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 2096 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 | 2097 | |
168ef543 | 2098 | for (i = 0; i < nr_cpu_ids; i++) { |
e8c10ef9 | 2099 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
2100 | if (bios_cpu_apicid) { |
2101 | id = bios_cpu_apicid[i]; | |
e8c10ef9 | 2102 | } |
2103 | else if (i < nr_cpu_ids) { | |
2104 | if (cpu_present(i)) | |
2105 | id = per_cpu(x86_bios_cpu_apicid, i); | |
2106 | else | |
2107 | continue; | |
2108 | } | |
2109 | else | |
2110 | break; | |
2111 | ||
1da177e4 LT |
2112 | if (id != BAD_APICID) |
2113 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
2114 | } | |
2115 | ||
2116 | /* Problem: Partially populated chassis may not have CPUs in some of | |
2117 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 2118 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
2119 | * Since clusters are allocated sequentially, count zeros only if | |
2120 | * they are bounded by ones. | |
1da177e4 LT |
2121 | */ |
2122 | clusters = 0; | |
2123 | zeros = 0; | |
2124 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
2125 | if (test_bit(i, clustermap)) { | |
2126 | clusters += 1 + zeros; | |
2127 | zeros = 0; | |
2128 | } else | |
2129 | ++zeros; | |
2130 | } | |
2131 | ||
1cb68487 RT |
2132 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
2133 | * not guaranteed to be synced between boards | |
2134 | */ | |
2135 | if (is_vsmp_box() && clusters > 1) | |
2136 | return 1; | |
2137 | ||
1da177e4 | 2138 | /* |
f8bf3c65 | 2139 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
2140 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
2141 | * out, but AFAIK this will work even for them. | |
2142 | */ | |
2143 | return (clusters > 2); | |
2144 | } | |
f28c0ae2 | 2145 | #endif |
1da177e4 LT |
2146 | |
2147 | /* | |
0e078e2f | 2148 | * APIC command line parameters |
1da177e4 | 2149 | */ |
789fa735 | 2150 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2151 | { |
1da177e4 | 2152 | disable_apic = 1; |
9175fc06 | 2153 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2154 | return 0; |
2155 | } | |
2156 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2157 | |
2c8c0e6b | 2158 | /* same as disableapic, for compatibility */ |
789fa735 | 2159 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2160 | { |
789fa735 | 2161 | return setup_disableapic(arg); |
6935d1f9 | 2162 | } |
2c8c0e6b | 2163 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2164 | |
2e7c2838 LT |
2165 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2166 | { | |
2167 | local_apic_timer_c2_ok = 1; | |
2168 | return 0; | |
2169 | } | |
2170 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2171 | ||
36fef094 | 2172 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2173 | { |
1da177e4 | 2174 | disable_apic_timer = 1; |
36fef094 | 2175 | return 0; |
6935d1f9 | 2176 | } |
36fef094 CG |
2177 | early_param("noapictimer", parse_disable_apic_timer); |
2178 | ||
2179 | static int __init parse_nolapic_timer(char *arg) | |
2180 | { | |
2181 | disable_apic_timer = 1; | |
2182 | return 0; | |
6935d1f9 | 2183 | } |
36fef094 | 2184 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2185 | |
79af9bec CG |
2186 | static int __init apic_set_verbosity(char *arg) |
2187 | { | |
2188 | if (!arg) { | |
2189 | #ifdef CONFIG_X86_64 | |
2190 | skip_ioapic_setup = 0; | |
79af9bec CG |
2191 | return 0; |
2192 | #endif | |
2193 | return -EINVAL; | |
2194 | } | |
2195 | ||
2196 | if (strcmp("debug", arg) == 0) | |
2197 | apic_verbosity = APIC_DEBUG; | |
2198 | else if (strcmp("verbose", arg) == 0) | |
2199 | apic_verbosity = APIC_VERBOSE; | |
2200 | else { | |
ba21ebb6 | 2201 | pr_warning("APIC Verbosity level %s not recognised" |
79af9bec CG |
2202 | " use apic=verbose or apic=debug\n", arg); |
2203 | return -EINVAL; | |
2204 | } | |
2205 | ||
2206 | return 0; | |
2207 | } | |
2208 | early_param("apic", apic_set_verbosity); | |
2209 | ||
1e934dda YL |
2210 | static int __init lapic_insert_resource(void) |
2211 | { | |
2212 | if (!apic_phys) | |
2213 | return -1; | |
2214 | ||
2215 | /* Put local APIC into the resource map. */ | |
2216 | lapic_resource.start = apic_phys; | |
2217 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2218 | insert_resource(&iomem_resource, &lapic_resource); | |
2219 | ||
2220 | return 0; | |
2221 | } | |
2222 | ||
2223 | /* | |
2224 | * need call insert after e820_reserve_resources() | |
2225 | * that is using request_resource | |
2226 | */ | |
2227 | late_initcall(lapic_insert_resource); |