Commit | Line | Data |
---|---|---|
da6b737b SAS |
1 | /* |
2 | * Architecture specific OF callbacks. | |
3 | */ | |
4 | #include <linux/bootmem.h> | |
69c60c88 | 5 | #include <linux/export.h> |
da6b737b | 6 | #include <linux/io.h> |
19c4f5f7 | 7 | #include <linux/interrupt.h> |
da6b737b SAS |
8 | #include <linux/list.h> |
9 | #include <linux/of.h> | |
10 | #include <linux/of_fdt.h> | |
3879a6f3 | 11 | #include <linux/of_address.h> |
da6b737b | 12 | #include <linux/of_platform.h> |
96e0a079 | 13 | #include <linux/of_irq.h> |
da6b737b | 14 | #include <linux/slab.h> |
96e0a079 SAS |
15 | #include <linux/pci.h> |
16 | #include <linux/of_pci.h> | |
977cb76d | 17 | #include <linux/initrd.h> |
da6b737b | 18 | |
ffb9fc68 | 19 | #include <asm/hpet.h> |
19c4f5f7 | 20 | #include <asm/irq_controller.h> |
3879a6f3 | 21 | #include <asm/apic.h> |
96e0a079 | 22 | #include <asm/pci_x86.h> |
19c4f5f7 | 23 | |
3879a6f3 | 24 | __initdata u64 initial_dtb; |
da6b737b | 25 | char __initdata cmd_line[COMMAND_LINE_SIZE]; |
19c4f5f7 SAS |
26 | static LIST_HEAD(irq_domains); |
27 | static DEFINE_RAW_SPINLOCK(big_irq_lock); | |
28 | ||
3879a6f3 SAS |
29 | int __initdata of_ioapic; |
30 | ||
a906fdaa | 31 | #ifdef CONFIG_X86_IO_APIC |
4a66b1d9 | 32 | static void add_interrupt_host(struct irq_domain *ih) |
19c4f5f7 SAS |
33 | { |
34 | unsigned long flags; | |
35 | ||
36 | raw_spin_lock_irqsave(&big_irq_lock, flags); | |
37 | list_add(&ih->l, &irq_domains); | |
38 | raw_spin_unlock_irqrestore(&big_irq_lock, flags); | |
39 | } | |
a906fdaa | 40 | #endif |
19c4f5f7 SAS |
41 | |
42 | static struct irq_domain *get_ih_from_node(struct device_node *controller) | |
43 | { | |
44 | struct irq_domain *ih, *found = NULL; | |
45 | unsigned long flags; | |
46 | ||
47 | raw_spin_lock_irqsave(&big_irq_lock, flags); | |
48 | list_for_each_entry(ih, &irq_domains, l) { | |
49 | if (ih->controller == controller) { | |
50 | found = ih; | |
51 | break; | |
52 | } | |
53 | } | |
54 | raw_spin_unlock_irqrestore(&big_irq_lock, flags); | |
55 | return found; | |
56 | } | |
da6b737b SAS |
57 | |
58 | unsigned int irq_create_of_mapping(struct device_node *controller, | |
59 | const u32 *intspec, unsigned int intsize) | |
60 | { | |
19c4f5f7 SAS |
61 | struct irq_domain *ih; |
62 | u32 virq, type; | |
63 | int ret; | |
da6b737b | 64 | |
19c4f5f7 SAS |
65 | ih = get_ih_from_node(controller); |
66 | if (!ih) | |
67 | return 0; | |
68 | ret = ih->xlate(ih, intspec, intsize, &virq, &type); | |
69 | if (ret) | |
00a30b25 | 70 | return 0; |
19c4f5f7 SAS |
71 | if (type == IRQ_TYPE_NONE) |
72 | return virq; | |
07611dbd | 73 | irq_set_irq_type(virq, type); |
19c4f5f7 | 74 | return virq; |
da6b737b SAS |
75 | } |
76 | EXPORT_SYMBOL_GPL(irq_create_of_mapping); | |
77 | ||
78 | unsigned long pci_address_to_pio(phys_addr_t address) | |
79 | { | |
80 | /* | |
81 | * The ioport address can be directly used by inX / outX | |
82 | */ | |
83 | BUG_ON(address >= (1 << 16)); | |
84 | return (unsigned long)address; | |
85 | } | |
86 | EXPORT_SYMBOL_GPL(pci_address_to_pio); | |
87 | ||
88 | void __init early_init_dt_scan_chosen_arch(unsigned long node) | |
89 | { | |
90 | BUG(); | |
91 | } | |
92 | ||
93 | void __init early_init_dt_add_memory_arch(u64 base, u64 size) | |
94 | { | |
95 | BUG(); | |
96 | } | |
97 | ||
98 | void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) | |
99 | { | |
100 | return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS)); | |
101 | } | |
102 | ||
977cb76d FF |
103 | #ifdef CONFIG_BLK_DEV_INITRD |
104 | void __init early_init_dt_setup_initrd_arch(unsigned long start, | |
105 | unsigned long end) | |
106 | { | |
107 | initrd_start = (unsigned long)__va(start); | |
108 | initrd_end = (unsigned long)__va(end); | |
109 | initrd_below_start_ok = 1; | |
110 | } | |
111 | #endif | |
112 | ||
da6b737b SAS |
113 | void __init add_dtb(u64 data) |
114 | { | |
3879a6f3 SAS |
115 | initial_dtb = data + offsetof(struct setup_data, data); |
116 | } | |
117 | ||
9079b353 SAS |
118 | /* |
119 | * CE4100 ids. Will be moved to machine_device_initcall() once we have it. | |
120 | */ | |
121 | static struct of_device_id __initdata ce4100_ids[] = { | |
122 | { .compatible = "intel,ce4100-cp", }, | |
123 | { .compatible = "isa", }, | |
124 | { .compatible = "pci", }, | |
125 | {}, | |
126 | }; | |
127 | ||
128 | static int __init add_bus_probe(void) | |
129 | { | |
4a66b1d9 | 130 | if (!of_have_populated_dt()) |
9079b353 SAS |
131 | return 0; |
132 | ||
133 | return of_platform_bus_probe(NULL, ce4100_ids, NULL); | |
134 | } | |
135 | module_init(add_bus_probe); | |
136 | ||
96e0a079 | 137 | #ifdef CONFIG_PCI |
3d5fe5a6 BH |
138 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) |
139 | { | |
140 | struct device_node *np; | |
141 | ||
142 | for_each_node_by_type(np, "pci") { | |
143 | const void *prop; | |
144 | unsigned int bus_min; | |
145 | ||
146 | prop = of_get_property(np, "bus-range", NULL); | |
147 | if (!prop) | |
148 | continue; | |
149 | bus_min = be32_to_cpup(prop); | |
150 | if (bus->number == bus_min) | |
151 | return np; | |
152 | } | |
153 | return NULL; | |
154 | } | |
155 | ||
96e0a079 SAS |
156 | static int x86_of_pci_irq_enable(struct pci_dev *dev) |
157 | { | |
158 | struct of_irq oirq; | |
159 | u32 virq; | |
160 | int ret; | |
161 | u8 pin; | |
162 | ||
163 | ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); | |
164 | if (ret) | |
165 | return ret; | |
166 | if (!pin) | |
167 | return 0; | |
168 | ||
169 | ret = of_irq_map_pci(dev, &oirq); | |
170 | if (ret) | |
171 | return ret; | |
172 | ||
173 | virq = irq_create_of_mapping(oirq.controller, oirq.specifier, | |
174 | oirq.size); | |
175 | if (virq == 0) | |
176 | return -EINVAL; | |
177 | dev->irq = virq; | |
178 | return 0; | |
179 | } | |
180 | ||
181 | static void x86_of_pci_irq_disable(struct pci_dev *dev) | |
182 | { | |
183 | } | |
184 | ||
185 | void __cpuinit x86_of_pci_init(void) | |
186 | { | |
96e0a079 SAS |
187 | pcibios_enable_irq = x86_of_pci_irq_enable; |
188 | pcibios_disable_irq = x86_of_pci_irq_disable; | |
96e0a079 SAS |
189 | } |
190 | #endif | |
191 | ||
ffb9fc68 SAS |
192 | static void __init dtb_setup_hpet(void) |
193 | { | |
4a66b1d9 | 194 | #ifdef CONFIG_HPET_TIMER |
ffb9fc68 SAS |
195 | struct device_node *dn; |
196 | struct resource r; | |
197 | int ret; | |
198 | ||
199 | dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet"); | |
200 | if (!dn) | |
201 | return; | |
202 | ret = of_address_to_resource(dn, 0, &r); | |
203 | if (ret) { | |
204 | WARN_ON(1); | |
205 | return; | |
206 | } | |
207 | hpet_address = r.start; | |
4a66b1d9 | 208 | #endif |
ffb9fc68 SAS |
209 | } |
210 | ||
3879a6f3 SAS |
211 | static void __init dtb_lapic_setup(void) |
212 | { | |
213 | #ifdef CONFIG_X86_LOCAL_APIC | |
a906fdaa TG |
214 | struct device_node *dn; |
215 | struct resource r; | |
216 | int ret; | |
217 | ||
218 | dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic"); | |
219 | if (!dn) | |
3879a6f3 SAS |
220 | return; |
221 | ||
a906fdaa TG |
222 | ret = of_address_to_resource(dn, 0, &r); |
223 | if (WARN_ON(ret)) | |
224 | return; | |
225 | ||
226 | /* Did the boot loader setup the local APIC ? */ | |
227 | if (!cpu_has_apic) { | |
228 | if (apic_force_enable(r.start)) | |
229 | return; | |
230 | } | |
3879a6f3 SAS |
231 | smp_found_config = 1; |
232 | pic_mode = 1; | |
a906fdaa | 233 | register_lapic_address(r.start); |
3879a6f3 | 234 | generic_processor_info(boot_cpu_physical_apicid, |
a906fdaa | 235 | GET_APIC_VERSION(apic_read(APIC_LVR))); |
3879a6f3 SAS |
236 | #endif |
237 | } | |
238 | ||
239 | #ifdef CONFIG_X86_IO_APIC | |
240 | static unsigned int ioapic_id; | |
241 | ||
242 | static void __init dtb_add_ioapic(struct device_node *dn) | |
243 | { | |
244 | struct resource r; | |
245 | int ret; | |
246 | ||
247 | ret = of_address_to_resource(dn, 0, &r); | |
248 | if (ret) { | |
249 | printk(KERN_ERR "Can't obtain address from node %s.\n", | |
250 | dn->full_name); | |
251 | return; | |
252 | } | |
253 | mp_register_ioapic(++ioapic_id, r.start, gsi_top); | |
254 | } | |
255 | ||
256 | static void __init dtb_ioapic_setup(void) | |
257 | { | |
258 | struct device_node *dn; | |
259 | ||
3879a6f3 SAS |
260 | for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic") |
261 | dtb_add_ioapic(dn); | |
262 | ||
263 | if (nr_ioapics) { | |
264 | of_ioapic = 1; | |
265 | return; | |
266 | } | |
267 | printk(KERN_ERR "Error: No information about IO-APIC in OF.\n"); | |
3879a6f3 SAS |
268 | } |
269 | #else | |
270 | static void __init dtb_ioapic_setup(void) {} | |
271 | #endif | |
272 | ||
273 | static void __init dtb_apic_setup(void) | |
274 | { | |
275 | dtb_lapic_setup(); | |
276 | dtb_ioapic_setup(); | |
277 | } | |
278 | ||
4a66b1d9 SAS |
279 | #ifdef CONFIG_OF_FLATTREE |
280 | static void __init x86_flattree_get_config(void) | |
3879a6f3 SAS |
281 | { |
282 | u32 size, map_len; | |
283 | void *new_dtb; | |
284 | ||
285 | if (!initial_dtb) | |
286 | return; | |
287 | ||
288 | map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), | |
289 | (u64)sizeof(struct boot_param_header)); | |
290 | ||
291 | initial_boot_params = early_memremap(initial_dtb, map_len); | |
292 | size = be32_to_cpu(initial_boot_params->totalsize); | |
293 | if (map_len < size) { | |
294 | early_iounmap(initial_boot_params, map_len); | |
295 | initial_boot_params = early_memremap(initial_dtb, size); | |
296 | map_len = size; | |
297 | } | |
298 | ||
299 | new_dtb = alloc_bootmem(size); | |
300 | memcpy(new_dtb, initial_boot_params, size); | |
301 | early_iounmap(initial_boot_params, map_len); | |
302 | ||
303 | initial_boot_params = new_dtb; | |
304 | ||
305 | /* root level address cells */ | |
306 | of_scan_flat_dt(early_init_dt_scan_root, NULL); | |
307 | ||
308 | unflatten_device_tree(); | |
4a66b1d9 SAS |
309 | } |
310 | #else | |
311 | static inline void x86_flattree_get_config(void) { } | |
312 | #endif | |
313 | ||
a906fdaa | 314 | void __init x86_dtb_init(void) |
4a66b1d9 SAS |
315 | { |
316 | x86_flattree_get_config(); | |
317 | ||
318 | if (!of_have_populated_dt()) | |
319 | return; | |
320 | ||
ffb9fc68 | 321 | dtb_setup_hpet(); |
3879a6f3 | 322 | dtb_apic_setup(); |
da6b737b | 323 | } |
bcc7c124 SAS |
324 | |
325 | #ifdef CONFIG_X86_IO_APIC | |
326 | ||
327 | struct of_ioapic_type { | |
328 | u32 out_type; | |
329 | u32 trigger; | |
330 | u32 polarity; | |
331 | }; | |
332 | ||
333 | static struct of_ioapic_type of_ioapic_type[] = | |
334 | { | |
335 | { | |
336 | .out_type = IRQ_TYPE_EDGE_RISING, | |
337 | .trigger = IOAPIC_EDGE, | |
338 | .polarity = 1, | |
339 | }, | |
340 | { | |
341 | .out_type = IRQ_TYPE_LEVEL_LOW, | |
342 | .trigger = IOAPIC_LEVEL, | |
343 | .polarity = 0, | |
344 | }, | |
345 | { | |
346 | .out_type = IRQ_TYPE_LEVEL_HIGH, | |
347 | .trigger = IOAPIC_LEVEL, | |
348 | .polarity = 1, | |
349 | }, | |
350 | { | |
351 | .out_type = IRQ_TYPE_EDGE_FALLING, | |
352 | .trigger = IOAPIC_EDGE, | |
353 | .polarity = 0, | |
354 | }, | |
355 | }; | |
356 | ||
357 | static int ioapic_xlate(struct irq_domain *id, const u32 *intspec, u32 intsize, | |
358 | u32 *out_hwirq, u32 *out_type) | |
359 | { | |
c040aaeb | 360 | struct mp_ioapic_gsi *gsi_cfg; |
bcc7c124 SAS |
361 | struct io_apic_irq_attr attr; |
362 | struct of_ioapic_type *it; | |
363 | u32 line, idx, type; | |
364 | ||
365 | if (intsize < 2) | |
366 | return -EINVAL; | |
367 | ||
368 | line = *intspec; | |
369 | idx = (u32) id->priv; | |
c040aaeb SS |
370 | gsi_cfg = mp_ioapic_gsi_routing(idx); |
371 | *out_hwirq = line + gsi_cfg->gsi_base; | |
bcc7c124 SAS |
372 | |
373 | intspec++; | |
374 | type = *intspec; | |
375 | ||
376 | if (type >= ARRAY_SIZE(of_ioapic_type)) | |
377 | return -EINVAL; | |
378 | ||
379 | it = of_ioapic_type + type; | |
380 | *out_type = it->out_type; | |
381 | ||
382 | set_io_apic_irq_attr(&attr, idx, line, it->trigger, it->polarity); | |
383 | ||
20443598 | 384 | return io_apic_setup_irq_pin_once(*out_hwirq, cpu_to_node(0), &attr); |
bcc7c124 SAS |
385 | } |
386 | ||
387 | static void __init ioapic_add_ofnode(struct device_node *np) | |
388 | { | |
389 | struct resource r; | |
390 | int i, ret; | |
391 | ||
392 | ret = of_address_to_resource(np, 0, &r); | |
393 | if (ret) { | |
394 | printk(KERN_ERR "Failed to obtain address for %s\n", | |
395 | np->full_name); | |
396 | return; | |
397 | } | |
398 | ||
399 | for (i = 0; i < nr_ioapics; i++) { | |
d5371430 | 400 | if (r.start == mpc_ioapic_addr(i)) { |
bcc7c124 SAS |
401 | struct irq_domain *id; |
402 | ||
403 | id = kzalloc(sizeof(*id), GFP_KERNEL); | |
404 | BUG_ON(!id); | |
405 | id->controller = np; | |
406 | id->xlate = ioapic_xlate; | |
407 | id->priv = (void *)i; | |
408 | add_interrupt_host(id); | |
409 | return; | |
410 | } | |
411 | } | |
412 | printk(KERN_ERR "IOxAPIC at %s is not registered.\n", np->full_name); | |
413 | } | |
414 | ||
415 | void __init x86_add_irq_domains(void) | |
416 | { | |
417 | struct device_node *dp; | |
418 | ||
4a66b1d9 | 419 | if (!of_have_populated_dt()) |
bcc7c124 SAS |
420 | return; |
421 | ||
422 | for_each_node_with_property(dp, "interrupt-controller") { | |
423 | if (of_device_is_compatible(dp, "intel,ce4100-ioapic")) | |
424 | ioapic_add_ofnode(dp); | |
425 | } | |
426 | } | |
427 | #else | |
428 | void __init x86_add_irq_domains(void) { } | |
429 | #endif |