[deliverable/linux.git] / arch / x86 / kernel / devicetree.c

/*
 * Architecture specific OF callbacks.
 */
#include <linux/bootmem.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/of_pci.h>

#include <asm/hpet.h>
#include <asm/irq_controller.h>
#include <asm/apic.h>
#include <asm/pci_x86.h>

__initdata u64 initial_dtb;
char __initdata cmd_line[COMMAND_LINE_SIZE];
static LIST_HEAD(irq_domains);
static DEFINE_RAW_SPINLOCK(big_irq_lock);

int __initdata of_ioapic;

#ifdef CONFIG_X86_IO_APIC
static void add_interrupt_host(struct irq_domain *ih)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&big_irq_lock, flags);
	list_add(&ih->l, &irq_domains);
	raw_spin_unlock_irqrestore(&big_irq_lock, flags);
}
#endif

static struct irq_domain *get_ih_from_node(struct device_node *controller)
{
	struct irq_domain *ih, *found = NULL;
	unsigned long flags;

	raw_spin_lock_irqsave(&big_irq_lock, flags);
	list_for_each_entry(ih, &irq_domains, l) {
		if (ih->controller ==  controller) {
			found = ih;
			break;
		}
	}
	raw_spin_unlock_irqrestore(&big_irq_lock, flags);
	return found;
}

unsigned int irq_create_of_mapping(struct device_node *controller,
				   const u32 *intspec, unsigned int intsize)
{
	struct irq_domain *ih;
	u32 virq, type;
	int ret;

	ih = get_ih_from_node(controller);
	if (!ih)
		return 0;
	ret = ih->xlate(ih, intspec, intsize, &virq, &type);
	if (ret)
		return 0;
	if (type == IRQ_TYPE_NONE)
		return virq;
	irq_set_irq_type(virq, type);
	return virq;
}
EXPORT_SYMBOL_GPL(irq_create_of_mapping);

unsigned long pci_address_to_pio(phys_addr_t address)
{
	/*
	 * The ioport address can be directly used by inX / outX
	 */
	BUG_ON(address >= (1 << 16));
	return (unsigned long)address;
}
EXPORT_SYMBOL_GPL(pci_address_to_pio);

void __init early_init_dt_scan_chosen_arch(unsigned long node)
{
	BUG();
}

void __init early_init_dt_add_memory_arch(u64 base, u64 size)
{
	BUG();
}

void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
{
	return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS));
}

void __init add_dtb(u64 data)
{
	initial_dtb = data + offsetof(struct setup_data, data);
}

/*
 * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
 */
static struct of_device_id __initdata ce4100_ids[] = {
	{ .compatible = "intel,ce4100-cp", },
	{ .compatible = "isa", },
	{ .compatible = "pci", },
	{},
};

static int __init add_bus_probe(void)
{
	if (!of_have_populated_dt())
		return 0;

	return of_platform_bus_probe(NULL, ce4100_ids, NULL);
}
module_init(add_bus_probe);

#ifdef CONFIG_PCI
static int x86_of_pci_irq_enable(struct pci_dev *dev)
{
	struct of_irq oirq;
	u32 virq;
	int ret;
	u8 pin;

	ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
	if (ret)
		return ret;
	if (!pin)
		return 0;

	ret = of_irq_map_pci(dev, &oirq);
	if (ret)
		return ret;

	virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
			oirq.size);
	if (virq == 0)
		return -EINVAL;
	dev->irq = virq;
	return 0;
}

static void x86_of_pci_irq_disable(struct pci_dev *dev)
{
}

void __cpuinit x86_of_pci_init(void)
{
	struct device_node *np;

	pcibios_enable_irq = x86_of_pci_irq_enable;
	pcibios_disable_irq = x86_of_pci_irq_disable;

	for_each_node_by_type(np, "pci") {
		const void *prop;
		struct pci_bus *bus;
		unsigned int bus_min;
		struct device_node *child;

		prop = of_get_property(np, "bus-range", NULL);
		if (!prop)
			continue;
		bus_min = be32_to_cpup(prop);

		bus = pci_find_bus(0, bus_min);
		if (!bus) {
			printk(KERN_ERR "Can't find a node for bus %s.\n",
					np->full_name);
			continue;
		}

		if (bus->self)
			bus->self->dev.of_node = np;
		else
			bus->dev.of_node = np;

		for_each_child_of_node(np, child) {
			struct pci_dev *dev;
			u32 devfn;

			prop = of_get_property(child, "reg", NULL);
			if (!prop)
				continue;

			devfn = (be32_to_cpup(prop) >> 8) & 0xff;
			dev = pci_get_slot(bus, devfn);
			if (!dev)
				continue;
			dev->dev.of_node = child;
			pci_dev_put(dev);
		}
	}
}
#endif

static void __init dtb_setup_hpet(void)
{
#ifdef CONFIG_HPET_TIMER
	struct device_node *dn;
	struct resource r;
	int ret;

	dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
	if (!dn)
		return;
	ret = of_address_to_resource(dn, 0, &r);
	if (ret) {
		WARN_ON(1);
		return;
	}
	hpet_address = r.start;
#endif
}

static void __init dtb_lapic_setup(void)
{
#ifdef CONFIG_X86_LOCAL_APIC
	struct device_node *dn;
	struct resource r;
	int ret;

	dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
	if (!dn)
		return;

	ret = of_address_to_resource(dn, 0, &r);
	if (WARN_ON(ret))
		return;

	/* Did the boot loader setup the local APIC ? */
	if (!cpu_has_apic) {
		if (apic_force_enable(r.start))
			return;
	}
	smp_found_config = 1;
	pic_mode = 1;
	register_lapic_address(r.start);
	generic_processor_info(boot_cpu_physical_apicid,
			       GET_APIC_VERSION(apic_read(APIC_LVR)));
#endif
}

#ifdef CONFIG_X86_IO_APIC
static unsigned int ioapic_id;

static void __init dtb_add_ioapic(struct device_node *dn)
{
	struct resource r;
	int ret;

	ret = of_address_to_resource(dn, 0, &r);
	if (ret) {
		printk(KERN_ERR "Can't obtain address from node %s.\n",
				dn->full_name);
		return;
	}
	mp_register_ioapic(++ioapic_id, r.start, gsi_top);
}

static void __init dtb_ioapic_setup(void)
{
	struct device_node *dn;

	for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
		dtb_add_ioapic(dn);

	if (nr_ioapics) {
		of_ioapic = 1;
		return;
	}
	printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
}
#else
static void __init dtb_ioapic_setup(void) {}
#endif

static void __init dtb_apic_setup(void)
{
	dtb_lapic_setup();
	dtb_ioapic_setup();
}

#ifdef CONFIG_OF_FLATTREE
static void __init x86_flattree_get_config(void)
{
	u32 size, map_len;
	void *new_dtb;

	if (!initial_dtb)
		return;

	map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK),
			(u64)sizeof(struct boot_param_header));

	initial_boot_params = early_memremap(initial_dtb, map_len);
	size = be32_to_cpu(initial_boot_params->totalsize);
	if (map_len < size) {
		early_iounmap(initial_boot_params, map_len);
		initial_boot_params = early_memremap(initial_dtb, size);
		map_len = size;
	}

	new_dtb = alloc_bootmem(size);
	memcpy(new_dtb, initial_boot_params, size);
	early_iounmap(initial_boot_params, map_len);

	initial_boot_params = new_dtb;

	/* root level address cells */
	of_scan_flat_dt(early_init_dt_scan_root, NULL);

	unflatten_device_tree();
}
#else
static inline void x86_flattree_get_config(void) { }
#endif

void __init x86_dtb_init(void)
{
	x86_flattree_get_config();

	if (!of_have_populated_dt())
		return;

	dtb_setup_hpet();
	dtb_apic_setup();
}

#ifdef CONFIG_X86_IO_APIC

struct of_ioapic_type {
	u32 out_type;
	u32 trigger;
	u32 polarity;
};

static struct of_ioapic_type of_ioapic_type[] =
{
	{
		.out_type	= IRQ_TYPE_EDGE_RISING,
		.trigger	= IOAPIC_EDGE,
		.polarity	= 1,
	},
	{
		.out_type	= IRQ_TYPE_LEVEL_LOW,
		.trigger	= IOAPIC_LEVEL,
		.polarity	= 0,
	},
	{
		.out_type	= IRQ_TYPE_LEVEL_HIGH,
		.trigger	= IOAPIC_LEVEL,
		.polarity	= 1,
	},
	{
		.out_type	= IRQ_TYPE_EDGE_FALLING,
		.trigger	= IOAPIC_EDGE,
		.polarity	= 0,
	},
};

static int ioapic_xlate(struct irq_domain *id, const u32 *intspec, u32 intsize,
			u32 *out_hwirq, u32 *out_type)
{
	struct mp_ioapic_gsi *gsi_cfg;
	struct io_apic_irq_attr attr;
	struct of_ioapic_type *it;
	u32 line, idx, type;

	if (intsize < 2)
		return -EINVAL;

	line = *intspec;
	idx = (u32) id->priv;
	gsi_cfg = mp_ioapic_gsi_routing(idx);
	*out_hwirq = line + gsi_cfg->gsi_base;

	intspec++;
	type = *intspec;

	if (type >= ARRAY_SIZE(of_ioapic_type))
		return -EINVAL;

	it = of_ioapic_type + type;
	*out_type = it->out_type;

	set_io_apic_irq_attr(&attr, idx, line, it->trigger, it->polarity);

	return io_apic_setup_irq_pin_once(*out_hwirq, cpu_to_node(0), &attr);
}

static void __init ioapic_add_ofnode(struct device_node *np)
{
	struct resource r;
	int i, ret;

	ret = of_address_to_resource(np, 0, &r);
	if (ret) {
		printk(KERN_ERR "Failed to obtain address for %s\n",
				np->full_name);
		return;
	}

	for (i = 0; i < nr_ioapics; i++) {
		if (r.start == mpc_ioapic_addr(i)) {
			struct irq_domain *id;

			id = kzalloc(sizeof(*id), GFP_KERNEL);
			BUG_ON(!id);
			id->controller = np;
			id->xlate = ioapic_xlate;
			id->priv = (void *)i;
			add_interrupt_host(id);
			return;
		}
	}
	printk(KERN_ERR "IOxAPIC at %s is not registered.\n", np->full_name);
}

void __init x86_add_irq_domains(void)
{
	struct device_node *dp;

	if (!of_have_populated_dt())
		return;

	for_each_node_with_property(dp, "interrupt-controller") {
		if (of_device_is_compatible(dp, "intel,ce4100-ioapic"))
			ioapic_add_ofnode(dp);
	}
}
#else
void __init x86_add_irq_domains(void) { }
#endif
Commit	Line	Data
da6b737b SAS	1	/*
	2	* Architecture specific OF callbacks.
	3	*/
	4	#include <linux/bootmem.h>
	5	#include <linux/io.h>
19c4f5f7	6	#include <linux/interrupt.h>
da6b737b SAS	7	#include <linux/list.h>
	8	#include <linux/of.h>
	9	#include <linux/of_fdt.h>
3879a6f3	10	#include <linux/of_address.h>
da6b737b	11	#include <linux/of_platform.h>
96e0a079	12	#include <linux/of_irq.h>
da6b737b	13	#include <linux/slab.h>
96e0a079 SAS	14	#include <linux/pci.h>
96e0a079 SAS	15	#include <linux/of_pci.h>
da6b737b	16
ffb9fc68	17	#include <asm/hpet.h>
19c4f5f7	18	#include <asm/irq_controller.h>
3879a6f3	19	#include <asm/apic.h>
96e0a079	20	#include <asm/pci_x86.h>
19c4f5f7	21
3879a6f3	22	__initdata u64 initial_dtb;
da6b737b	23	char __initdata cmd_line[COMMAND_LINE_SIZE];
19c4f5f7 SAS	24	static LIST_HEAD(irq_domains);
	25	static DEFINE_RAW_SPINLOCK(big_irq_lock);
	26
3879a6f3 SAS	27	int __initdata of_ioapic;
3879a6f3 SAS	28
a906fdaa	29	#ifdef CONFIG_X86_IO_APIC
4a66b1d9	30	static void add_interrupt_host(struct irq_domain *ih)
19c4f5f7 SAS	31	{
	32	unsigned long flags;
	33
	34	raw_spin_lock_irqsave(&big_irq_lock, flags);
	35	list_add(&ih->l, &irq_domains);
	36	raw_spin_unlock_irqrestore(&big_irq_lock, flags);
	37	}
a906fdaa	38	#endif
19c4f5f7 SAS	39
	40	static struct irq_domain get_ih_from_node(struct device_node controller)
	41	{
	42	struct irq_domain ih, found = NULL;
	43	unsigned long flags;
	44
	45	raw_spin_lock_irqsave(&big_irq_lock, flags);
	46	list_for_each_entry(ih, &irq_domains, l) {
	47	if (ih->controller == controller) {
	48	found = ih;
	49	break;
	50	}
	51	}
	52	raw_spin_unlock_irqrestore(&big_irq_lock, flags);
	53	return found;
	54	}
da6b737b SAS	55
	56	unsigned int irq_create_of_mapping(struct device_node *controller,
	57	const u32 *intspec, unsigned int intsize)
	58	{
19c4f5f7 SAS	59	struct irq_domain *ih;
	60	u32 virq, type;
	61	int ret;
da6b737b	62
19c4f5f7 SAS	63	ih = get_ih_from_node(controller);
	64	if (!ih)
	65	return 0;
	66	ret = ih->xlate(ih, intspec, intsize, &virq, &type);
	67	if (ret)
00a30b25	68	return 0;
19c4f5f7 SAS	69	if (type == IRQ_TYPE_NONE)
19c4f5f7 SAS	70	return virq;
07611dbd	71	irq_set_irq_type(virq, type);
19c4f5f7	72	return virq;
da6b737b SAS	73	}
	74	EXPORT_SYMBOL_GPL(irq_create_of_mapping);
	75
	76	unsigned long pci_address_to_pio(phys_addr_t address)
	77	{
	78	/*
	79	* The ioport address can be directly used by inX / outX
	80	*/
	81	BUG_ON(address >= (1 << 16));
	82	return (unsigned long)address;
	83	}
	84	EXPORT_SYMBOL_GPL(pci_address_to_pio);
	85
	86	void __init early_init_dt_scan_chosen_arch(unsigned long node)
	87	{
	88	BUG();
	89	}
	90
	91	void __init early_init_dt_add_memory_arch(u64 base, u64 size)
	92	{
	93	BUG();
	94	}
	95
	96	void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
	97	{
	98	return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS));
	99	}
	100
	101	void __init add_dtb(u64 data)
	102	{
3879a6f3 SAS	103	initial_dtb = data + offsetof(struct setup_data, data);
	104	}
	105
9079b353 SAS	106	/*
	107	* CE4100 ids. Will be moved to machine_device_initcall() once we have it.
	108	*/
	109	static struct of_device_id __initdata ce4100_ids[] = {
	110	{ .compatible = "intel,ce4100-cp", },
	111	{ .compatible = "isa", },
	112	{ .compatible = "pci", },
	113	{},
	114	};
	115
	116	static int __init add_bus_probe(void)
	117	{
4a66b1d9	118	if (!of_have_populated_dt())
9079b353 SAS	119	return 0;
	120
	121	return of_platform_bus_probe(NULL, ce4100_ids, NULL);
	122	}
	123	module_init(add_bus_probe);
	124
96e0a079 SAS	125	#ifdef CONFIG_PCI
	126	static int x86_of_pci_irq_enable(struct pci_dev *dev)
	127	{
	128	struct of_irq oirq;
	129	u32 virq;
	130	int ret;
	131	u8 pin;
	132
	133	ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
	134	if (ret)
	135	return ret;
	136	if (!pin)
	137	return 0;
	138
	139	ret = of_irq_map_pci(dev, &oirq);
	140	if (ret)
	141	return ret;
	142
	143	virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
	144	oirq.size);
	145	if (virq == 0)
	146	return -EINVAL;
	147	dev->irq = virq;
	148	return 0;
	149	}
	150
	151	static void x86_of_pci_irq_disable(struct pci_dev *dev)
	152	{
	153	}
	154
	155	void __cpuinit x86_of_pci_init(void)
	156	{
	157	struct device_node *np;
	158
	159	pcibios_enable_irq = x86_of_pci_irq_enable;
	160	pcibios_disable_irq = x86_of_pci_irq_disable;
	161
	162	for_each_node_by_type(np, "pci") {
	163	const void *prop;
	164	struct pci_bus *bus;
	165	unsigned int bus_min;
	166	struct device_node *child;
	167
	168	prop = of_get_property(np, "bus-range", NULL);
	169	if (!prop)
	170	continue;
	171	bus_min = be32_to_cpup(prop);
	172
	173	bus = pci_find_bus(0, bus_min);
	174	if (!bus) {
	175	printk(KERN_ERR "Can't find a node for bus %s.\n",
	176	np->full_name);
	177	continue;
	178	}
	179
	180	if (bus->self)
	181	bus->self->dev.of_node = np;
	182	else
	183	bus->dev.of_node = np;
	184
	185	for_each_child_of_node(np, child) {
	186	struct pci_dev *dev;
	187	u32 devfn;
	188
189	prop = of_get_property(child, "reg", NULL);
190	if (!prop)
191	continue;
192
193	devfn = (be32_to_cpup(prop) >> 8) & 0xff;
194	dev = pci_get_slot(bus, devfn);
195	if (!dev)
196	continue;
197	dev->dev.of_node = child;
198	pci_dev_put(dev);
199	}
200	}
201	}
202	#endif
203
ffb9fc68 SAS	204	static void __init dtb_setup_hpet(void)
ffb9fc68 SAS	205	{
4a66b1d9	206	#ifdef CONFIG_HPET_TIMER
ffb9fc68 SAS	207	struct device_node *dn;
	208	struct resource r;
	209	int ret;
	210
	211	dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
	212	if (!dn)
	213	return;
	214	ret = of_address_to_resource(dn, 0, &r);
	215	if (ret) {
	216	WARN_ON(1);
	217	return;
	218	}
	219	hpet_address = r.start;
4a66b1d9	220	#endif
ffb9fc68 SAS	221	}
ffb9fc68 SAS	222
3879a6f3 SAS	223	static void __init dtb_lapic_setup(void)
	224	{
	225	#ifdef CONFIG_X86_LOCAL_APIC
a906fdaa TG	226	struct device_node *dn;
	227	struct resource r;
	228	int ret;
	229
	230	dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
	231	if (!dn)
3879a6f3 SAS	232	return;
3879a6f3 SAS	233
a906fdaa TG	234	ret = of_address_to_resource(dn, 0, &r);
	235	if (WARN_ON(ret))
	236	return;
	237
	238	/* Did the boot loader setup the local APIC ? */
	239	if (!cpu_has_apic) {
	240	if (apic_force_enable(r.start))
	241	return;
	242	}
3879a6f3 SAS	243	smp_found_config = 1;
3879a6f3 SAS	244	pic_mode = 1;
a906fdaa	245	register_lapic_address(r.start);
3879a6f3	246	generic_processor_info(boot_cpu_physical_apicid,
a906fdaa	247	GET_APIC_VERSION(apic_read(APIC_LVR)));
3879a6f3 SAS	248	#endif
	249	}
	250
	251	#ifdef CONFIG_X86_IO_APIC
	252	static unsigned int ioapic_id;
	253
	254	static void __init dtb_add_ioapic(struct device_node *dn)
	255	{
	256	struct resource r;
	257	int ret;
	258
	259	ret = of_address_to_resource(dn, 0, &r);
	260	if (ret) {
	261	printk(KERN_ERR "Can't obtain address from node %s.\n",
	262	dn->full_name);
	263	return;
	264	}
	265	mp_register_ioapic(++ioapic_id, r.start, gsi_top);
	266	}
	267
	268	static void __init dtb_ioapic_setup(void)
	269	{
	270	struct device_node *dn;
	271
3879a6f3 SAS	272	for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
	273	dtb_add_ioapic(dn);
	274
	275	if (nr_ioapics) {
	276	of_ioapic = 1;
	277	return;
	278	}
	279	printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
3879a6f3 SAS	280	}
	281	#else
	282	static void __init dtb_ioapic_setup(void) {}
	283	#endif
	284
	285	static void __init dtb_apic_setup(void)
	286	{
	287	dtb_lapic_setup();
	288	dtb_ioapic_setup();
	289	}
	290
4a66b1d9 SAS	291	#ifdef CONFIG_OF_FLATTREE
4a66b1d9 SAS	292	static void __init x86_flattree_get_config(void)
3879a6f3 SAS	293	{
	294	u32 size, map_len;
	295	void *new_dtb;
	296
	297	if (!initial_dtb)
	298	return;
	299
	300	map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK),
	301	(u64)sizeof(struct boot_param_header));
	302
	303	initial_boot_params = early_memremap(initial_dtb, map_len);
	304	size = be32_to_cpu(initial_boot_params->totalsize);
	305	if (map_len < size) {
	306	early_iounmap(initial_boot_params, map_len);
	307	initial_boot_params = early_memremap(initial_dtb, size);
	308	map_len = size;
	309	}
	310
	311	new_dtb = alloc_bootmem(size);
	312	memcpy(new_dtb, initial_boot_params, size);
	313	early_iounmap(initial_boot_params, map_len);
	314
	315	initial_boot_params = new_dtb;
	316
	317	/* root level address cells */
	318	of_scan_flat_dt(early_init_dt_scan_root, NULL);
	319
	320	unflatten_device_tree();
4a66b1d9 SAS	321	}
	322	#else
	323	static inline void x86_flattree_get_config(void) { }
	324	#endif
	325
a906fdaa	326	void __init x86_dtb_init(void)
4a66b1d9 SAS	327	{
	328	x86_flattree_get_config();
	329
	330	if (!of_have_populated_dt())
	331	return;
	332
ffb9fc68	333	dtb_setup_hpet();
3879a6f3	334	dtb_apic_setup();
da6b737b	335	}
bcc7c124 SAS	336
	337	#ifdef CONFIG_X86_IO_APIC
	338
	339	struct of_ioapic_type {
	340	u32 out_type;
	341	u32 trigger;
	342	u32 polarity;
	343	};
	344
	345	static struct of_ioapic_type of_ioapic_type[] =
	346	{
	347	{
	348	.out_type = IRQ_TYPE_EDGE_RISING,
	349	.trigger = IOAPIC_EDGE,
	350	.polarity = 1,
	351	},
	352	{
	353	.out_type = IRQ_TYPE_LEVEL_LOW,
	354	.trigger = IOAPIC_LEVEL,
	355	.polarity = 0,
	356	},
	357	{
	358	.out_type = IRQ_TYPE_LEVEL_HIGH,
	359	.trigger = IOAPIC_LEVEL,
	360	.polarity = 1,
	361	},
	362	{
	363	.out_type = IRQ_TYPE_EDGE_FALLING,
	364	.trigger = IOAPIC_EDGE,
	365	.polarity = 0,
	366	},
	367	};
	368
	369	static int ioapic_xlate(struct irq_domain id, const u32 intspec, u32 intsize,
	370	u32 out_hwirq, u32 out_type)
	371	{
c040aaeb	372	struct mp_ioapic_gsi *gsi_cfg;
bcc7c124 SAS	373	struct io_apic_irq_attr attr;
	374	struct of_ioapic_type *it;
	375	u32 line, idx, type;
	376
	377	if (intsize < 2)
	378	return -EINVAL;
	379
	380	line = *intspec;
	381	idx = (u32) id->priv;
c040aaeb SS	382	gsi_cfg = mp_ioapic_gsi_routing(idx);
c040aaeb SS	383	*out_hwirq = line + gsi_cfg->gsi_base;
bcc7c124 SAS	384
	385	intspec++;
	386	type = *intspec;
	387
	388	if (type >= ARRAY_SIZE(of_ioapic_type))
	389	return -EINVAL;
	390
	391	it = of_ioapic_type + type;
	392	*out_type = it->out_type;
	393
	394	set_io_apic_irq_attr(&attr, idx, line, it->trigger, it->polarity);
	395
20443598	396	return io_apic_setup_irq_pin_once(*out_hwirq, cpu_to_node(0), &attr);
bcc7c124 SAS	397	}
	398
	399	static void __init ioapic_add_ofnode(struct device_node *np)
	400	{
	401	struct resource r;
	402	int i, ret;
	403
	404	ret = of_address_to_resource(np, 0, &r);
	405	if (ret) {
	406	printk(KERN_ERR "Failed to obtain address for %s\n",
	407	np->full_name);
	408	return;
	409	}
	410
	411	for (i = 0; i < nr_ioapics; i++) {
d5371430	412	if (r.start == mpc_ioapic_addr(i)) {
bcc7c124 SAS	413	struct irq_domain *id;
	414
	415	id = kzalloc(sizeof(*id), GFP_KERNEL);
	416	BUG_ON(!id);
	417	id->controller = np;
	418	id->xlate = ioapic_xlate;
	419	id->priv = (void *)i;
	420	add_interrupt_host(id);
	421	return;
	422	}
	423	}
	424	printk(KERN_ERR "IOxAPIC at %s is not registered.\n", np->full_name);
	425	}
	426
	427	void __init x86_add_irq_domains(void)
	428	{
	429	struct device_node *dp;
	430
4a66b1d9	431	if (!of_have_populated_dt())
bcc7c124 SAS	432	return;
	433
	434	for_each_node_with_property(dp, "interrupt-controller") {
	435	if (of_device_is_compatible(dp, "intel,ce4100-ioapic"))
	436	ioapic_add_ofnode(dp);
	437	}
	438	}
	439	#else
	440	void __init x86_add_irq_domains(void) { }
	441	#endif