Commit | Line | Data |
---|---|---|
e465058d JM |
1 | /* |
2 | * Derived from arch/powerpc/kernel/iommu.c | |
3 | * | |
9882234b | 4 | * Copyright IBM Corporation, 2006-2007 |
d8d2bedf | 5 | * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us> |
e465058d | 6 | * |
d8d2bedf | 7 | * Author: Jon Mason <jdmason@kudzu.us> |
aa0a9f37 MBY |
8 | * Author: Muli Ben-Yehuda <muli@il.ibm.com> |
9 | ||
e465058d JM |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | */ | |
24 | ||
e465058d JM |
25 | #include <linux/kernel.h> |
26 | #include <linux/init.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/spinlock.h> | |
31 | #include <linux/string.h> | |
95b68dec | 32 | #include <linux/crash_dump.h> |
e465058d | 33 | #include <linux/dma-mapping.h> |
e465058d JM |
34 | #include <linux/bitops.h> |
35 | #include <linux/pci_ids.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/delay.h> | |
8b87d9f4 | 38 | #include <linux/scatterlist.h> |
1b39b077 | 39 | #include <linux/iommu-helper.h> |
1956a96d | 40 | |
46a7fa27 | 41 | #include <asm/iommu.h> |
e465058d JM |
42 | #include <asm/calgary.h> |
43 | #include <asm/tce.h> | |
44 | #include <asm/pci-direct.h> | |
45 | #include <asm/system.h> | |
46 | #include <asm/dma.h> | |
b34e90b8 | 47 | #include <asm/rio.h> |
ae5830a6 | 48 | #include <asm/bios_ebda.h> |
e465058d | 49 | |
bff6547b MBY |
50 | #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT |
51 | int use_calgary __read_mostly = 1; | |
52 | #else | |
53 | int use_calgary __read_mostly = 0; | |
54 | #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */ | |
55 | ||
e465058d | 56 | #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1 |
8a244590 | 57 | #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308 |
e465058d | 58 | |
e465058d | 59 | /* register offsets inside the host bridge space */ |
cb01fc72 MBY |
60 | #define CALGARY_CONFIG_REG 0x0108 |
61 | #define PHB_CSR_OFFSET 0x0110 /* Channel Status */ | |
e465058d JM |
62 | #define PHB_PLSSR_OFFSET 0x0120 |
63 | #define PHB_CONFIG_RW_OFFSET 0x0160 | |
64 | #define PHB_IOBASE_BAR_LOW 0x0170 | |
65 | #define PHB_IOBASE_BAR_HIGH 0x0180 | |
66 | #define PHB_MEM_1_LOW 0x0190 | |
67 | #define PHB_MEM_1_HIGH 0x01A0 | |
68 | #define PHB_IO_ADDR_SIZE 0x01B0 | |
69 | #define PHB_MEM_1_SIZE 0x01C0 | |
70 | #define PHB_MEM_ST_OFFSET 0x01D0 | |
71 | #define PHB_AER_OFFSET 0x0200 | |
72 | #define PHB_CONFIG_0_HIGH 0x0220 | |
73 | #define PHB_CONFIG_0_LOW 0x0230 | |
74 | #define PHB_CONFIG_0_END 0x0240 | |
75 | #define PHB_MEM_2_LOW 0x02B0 | |
76 | #define PHB_MEM_2_HIGH 0x02C0 | |
77 | #define PHB_MEM_2_SIZE_HIGH 0x02D0 | |
78 | #define PHB_MEM_2_SIZE_LOW 0x02E0 | |
79 | #define PHB_DOSHOLE_OFFSET 0x08E0 | |
80 | ||
c3860108 | 81 | /* CalIOC2 specific */ |
8bcf7705 MBY |
82 | #define PHB_SAVIOR_L2 0x0DB0 |
83 | #define PHB_PAGE_MIG_CTRL 0x0DA8 | |
84 | #define PHB_PAGE_MIG_DEBUG 0x0DA0 | |
8cb32dc7 | 85 | #define PHB_ROOT_COMPLEX_STATUS 0x0CB0 |
c3860108 | 86 | |
e465058d JM |
87 | /* PHB_CONFIG_RW */ |
88 | #define PHB_TCE_ENABLE 0x20000000 | |
89 | #define PHB_SLOT_DISABLE 0x1C000000 | |
90 | #define PHB_DAC_DISABLE 0x01000000 | |
91 | #define PHB_MEM2_ENABLE 0x00400000 | |
92 | #define PHB_MCSR_ENABLE 0x00100000 | |
93 | /* TAR (Table Address Register) */ | |
94 | #define TAR_SW_BITS 0x0000ffffffff800fUL | |
95 | #define TAR_VALID 0x0000000000000008UL | |
96 | /* CSR (Channel/DMA Status Register) */ | |
97 | #define CSR_AGENT_MASK 0xffe0ffff | |
cb01fc72 | 98 | /* CCR (Calgary Configuration Register) */ |
8bcf7705 | 99 | #define CCR_2SEC_TIMEOUT 0x000000000000000EUL |
00be3fa4 | 100 | /* PMCR/PMDR (Page Migration Control/Debug Registers */ |
8bcf7705 MBY |
101 | #define PMR_SOFTSTOP 0x80000000 |
102 | #define PMR_SOFTSTOPFAULT 0x40000000 | |
103 | #define PMR_HARDSTOP 0x20000000 | |
e465058d JM |
104 | |
105 | #define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */ | |
d2105b10 | 106 | #define MAX_NUM_CHASSIS 8 /* max number of chassis */ |
4ea8a5d8 MBY |
107 | /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */ |
108 | #define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2) | |
e465058d JM |
109 | #define PHBS_PER_CALGARY 4 |
110 | ||
111 | /* register offsets in Calgary's internal register space */ | |
112 | static const unsigned long tar_offsets[] = { | |
113 | 0x0580 /* TAR0 */, | |
114 | 0x0588 /* TAR1 */, | |
115 | 0x0590 /* TAR2 */, | |
116 | 0x0598 /* TAR3 */ | |
117 | }; | |
118 | ||
119 | static const unsigned long split_queue_offsets[] = { | |
120 | 0x4870 /* SPLIT QUEUE 0 */, | |
121 | 0x5870 /* SPLIT QUEUE 1 */, | |
122 | 0x6870 /* SPLIT QUEUE 2 */, | |
123 | 0x7870 /* SPLIT QUEUE 3 */ | |
124 | }; | |
125 | ||
126 | static const unsigned long phb_offsets[] = { | |
127 | 0x8000 /* PHB0 */, | |
128 | 0x9000 /* PHB1 */, | |
129 | 0xA000 /* PHB2 */, | |
130 | 0xB000 /* PHB3 */ | |
131 | }; | |
132 | ||
b34e90b8 LV |
133 | /* PHB debug registers */ |
134 | ||
135 | static const unsigned long phb_debug_offsets[] = { | |
136 | 0x4000 /* PHB 0 DEBUG */, | |
137 | 0x5000 /* PHB 1 DEBUG */, | |
138 | 0x6000 /* PHB 2 DEBUG */, | |
139 | 0x7000 /* PHB 3 DEBUG */ | |
140 | }; | |
141 | ||
142 | /* | |
143 | * STUFF register for each debug PHB, | |
144 | * byte 1 = start bus number, byte 2 = end bus number | |
145 | */ | |
146 | ||
147 | #define PHB_DEBUG_STUFF_OFFSET 0x0020 | |
148 | ||
310adfdd MBY |
149 | #define EMERGENCY_PAGES 32 /* = 128KB */ |
150 | ||
e465058d JM |
151 | unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED; |
152 | static int translate_empty_slots __read_mostly = 0; | |
153 | static int calgary_detected __read_mostly = 0; | |
154 | ||
b34e90b8 LV |
155 | static struct rio_table_hdr *rio_table_hdr __initdata; |
156 | static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata; | |
eae93755 | 157 | static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata; |
b34e90b8 | 158 | |
f38db651 MBY |
159 | struct calgary_bus_info { |
160 | void *tce_space; | |
0577f148 | 161 | unsigned char translation_disabled; |
f38db651 | 162 | signed char phbid; |
b34e90b8 | 163 | void __iomem *bbar; |
f38db651 MBY |
164 | }; |
165 | ||
ff297b8c MBY |
166 | static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); |
167 | static void calgary_tce_cache_blast(struct iommu_table *tbl); | |
8cb32dc7 | 168 | static void calgary_dump_error_regs(struct iommu_table *tbl); |
c3860108 | 169 | static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); |
00be3fa4 | 170 | static void calioc2_tce_cache_blast(struct iommu_table *tbl); |
8cb32dc7 | 171 | static void calioc2_dump_error_regs(struct iommu_table *tbl); |
95b68dec C |
172 | static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl); |
173 | static void get_tce_space_from_tar(void); | |
ff297b8c MBY |
174 | |
175 | static struct cal_chipset_ops calgary_chip_ops = { | |
176 | .handle_quirks = calgary_handle_quirks, | |
8cb32dc7 MBY |
177 | .tce_cache_blast = calgary_tce_cache_blast, |
178 | .dump_error_regs = calgary_dump_error_regs | |
ff297b8c | 179 | }; |
e465058d | 180 | |
c3860108 MBY |
181 | static struct cal_chipset_ops calioc2_chip_ops = { |
182 | .handle_quirks = calioc2_handle_quirks, | |
8cb32dc7 MBY |
183 | .tce_cache_blast = calioc2_tce_cache_blast, |
184 | .dump_error_regs = calioc2_dump_error_regs | |
c3860108 MBY |
185 | }; |
186 | ||
ff297b8c | 187 | static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, }; |
e465058d JM |
188 | |
189 | /* enable this to stress test the chip's TCE cache */ | |
190 | #ifdef CONFIG_IOMMU_DEBUG | |
ed65260b | 191 | static int debugging = 1; |
de684652 | 192 | |
796e4390 MBY |
193 | static inline unsigned long verify_bit_range(unsigned long* bitmap, |
194 | int expected, unsigned long start, unsigned long end) | |
195 | { | |
196 | unsigned long idx = start; | |
197 | ||
198 | BUG_ON(start >= end); | |
199 | ||
200 | while (idx < end) { | |
201 | if (!!test_bit(idx, bitmap) != expected) | |
202 | return idx; | |
203 | ++idx; | |
204 | } | |
205 | ||
206 | /* all bits have the expected value */ | |
207 | return ~0UL; | |
208 | } | |
de684652 | 209 | #else /* debugging is disabled */ |
ed65260b | 210 | static int debugging; |
de684652 | 211 | |
796e4390 MBY |
212 | static inline unsigned long verify_bit_range(unsigned long* bitmap, |
213 | int expected, unsigned long start, unsigned long end) | |
214 | { | |
215 | return ~0UL; | |
216 | } | |
8a244590 | 217 | |
de684652 | 218 | #endif /* CONFIG_IOMMU_DEBUG */ |
e465058d JM |
219 | |
220 | static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen) | |
221 | { | |
222 | unsigned int npages; | |
223 | ||
224 | npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK); | |
225 | npages >>= PAGE_SHIFT; | |
226 | ||
227 | return npages; | |
228 | } | |
229 | ||
d588ba8c MBY |
230 | static inline int translation_enabled(struct iommu_table *tbl) |
231 | { | |
232 | /* only PHBs with translation enabled have an IOMMU table */ | |
233 | return (tbl != NULL); | |
234 | } | |
235 | ||
e465058d | 236 | static void iommu_range_reserve(struct iommu_table *tbl, |
8bcf7705 | 237 | unsigned long start_addr, unsigned int npages) |
e465058d JM |
238 | { |
239 | unsigned long index; | |
240 | unsigned long end; | |
796e4390 | 241 | unsigned long badbit; |
820a1497 | 242 | unsigned long flags; |
e465058d JM |
243 | |
244 | index = start_addr >> PAGE_SHIFT; | |
245 | ||
246 | /* bail out if we're asked to reserve a region we don't cover */ | |
247 | if (index >= tbl->it_size) | |
248 | return; | |
249 | ||
250 | end = index + npages; | |
251 | if (end > tbl->it_size) /* don't go off the table */ | |
252 | end = tbl->it_size; | |
253 | ||
820a1497 MBY |
254 | spin_lock_irqsave(&tbl->it_lock, flags); |
255 | ||
796e4390 MBY |
256 | badbit = verify_bit_range(tbl->it_map, 0, index, end); |
257 | if (badbit != ~0UL) { | |
258 | if (printk_ratelimit()) | |
e465058d JM |
259 | printk(KERN_ERR "Calgary: entry already allocated at " |
260 | "0x%lx tbl %p dma 0x%lx npages %u\n", | |
796e4390 | 261 | badbit, tbl, start_addr, npages); |
e465058d | 262 | } |
796e4390 MBY |
263 | |
264 | set_bit_string(tbl->it_map, index, npages); | |
820a1497 MBY |
265 | |
266 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
e465058d JM |
267 | } |
268 | ||
1b39b077 FT |
269 | static unsigned long iommu_range_alloc(struct device *dev, |
270 | struct iommu_table *tbl, | |
271 | unsigned int npages) | |
e465058d | 272 | { |
820a1497 | 273 | unsigned long flags; |
e465058d | 274 | unsigned long offset; |
1b39b077 FT |
275 | unsigned long boundary_size; |
276 | ||
277 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
278 | PAGE_SIZE) >> PAGE_SHIFT; | |
e465058d JM |
279 | |
280 | BUG_ON(npages == 0); | |
281 | ||
820a1497 MBY |
282 | spin_lock_irqsave(&tbl->it_lock, flags); |
283 | ||
1b39b077 FT |
284 | offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint, |
285 | npages, 0, boundary_size, 0); | |
e465058d | 286 | if (offset == ~0UL) { |
ff297b8c | 287 | tbl->chip_ops->tce_cache_blast(tbl); |
1b39b077 FT |
288 | |
289 | offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0, | |
290 | npages, 0, boundary_size, 0); | |
e465058d JM |
291 | if (offset == ~0UL) { |
292 | printk(KERN_WARNING "Calgary: IOMMU full.\n"); | |
820a1497 | 293 | spin_unlock_irqrestore(&tbl->it_lock, flags); |
e465058d JM |
294 | if (panic_on_overflow) |
295 | panic("Calgary: fix the allocator.\n"); | |
296 | else | |
297 | return bad_dma_address; | |
298 | } | |
299 | } | |
300 | ||
e465058d JM |
301 | tbl->it_hint = offset + npages; |
302 | BUG_ON(tbl->it_hint > tbl->it_size); | |
303 | ||
820a1497 MBY |
304 | spin_unlock_irqrestore(&tbl->it_lock, flags); |
305 | ||
e465058d JM |
306 | return offset; |
307 | } | |
308 | ||
1b39b077 FT |
309 | static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl, |
310 | void *vaddr, unsigned int npages, int direction) | |
e465058d | 311 | { |
820a1497 | 312 | unsigned long entry; |
e465058d JM |
313 | dma_addr_t ret = bad_dma_address; |
314 | ||
1b39b077 | 315 | entry = iommu_range_alloc(dev, tbl, npages); |
e465058d JM |
316 | |
317 | if (unlikely(entry == bad_dma_address)) | |
318 | goto error; | |
319 | ||
320 | /* set the return dma address */ | |
321 | ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK); | |
322 | ||
323 | /* put the TCEs in the HW table */ | |
324 | tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK, | |
325 | direction); | |
326 | ||
e465058d JM |
327 | return ret; |
328 | ||
329 | error: | |
e465058d JM |
330 | printk(KERN_WARNING "Calgary: failed to allocate %u pages in " |
331 | "iommu %p\n", npages, tbl); | |
332 | return bad_dma_address; | |
333 | } | |
334 | ||
3cc39bda | 335 | static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, |
e465058d JM |
336 | unsigned int npages) |
337 | { | |
338 | unsigned long entry; | |
796e4390 | 339 | unsigned long badbit; |
310adfdd | 340 | unsigned long badend; |
820a1497 | 341 | unsigned long flags; |
310adfdd MBY |
342 | |
343 | /* were we called with bad_dma_address? */ | |
344 | badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE); | |
345 | if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) { | |
346 | printk(KERN_ERR "Calgary: driver tried unmapping bad DMA " | |
347 | "address 0x%Lx\n", dma_addr); | |
348 | WARN_ON(1); | |
349 | return; | |
350 | } | |
e465058d JM |
351 | |
352 | entry = dma_addr >> PAGE_SHIFT; | |
353 | ||
354 | BUG_ON(entry + npages > tbl->it_size); | |
355 | ||
356 | tce_free(tbl, entry, npages); | |
357 | ||
820a1497 MBY |
358 | spin_lock_irqsave(&tbl->it_lock, flags); |
359 | ||
796e4390 MBY |
360 | badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages); |
361 | if (badbit != ~0UL) { | |
362 | if (printk_ratelimit()) | |
e465058d JM |
363 | printk(KERN_ERR "Calgary: bit is off at 0x%lx " |
364 | "tbl %p dma 0x%Lx entry 0x%lx npages %u\n", | |
796e4390 | 365 | badbit, tbl, dma_addr, entry, npages); |
e465058d JM |
366 | } |
367 | ||
1b39b077 | 368 | iommu_area_free(tbl->it_map, entry, npages); |
820a1497 MBY |
369 | |
370 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
e465058d JM |
371 | } |
372 | ||
35b6dfa0 MBY |
373 | static inline struct iommu_table *find_iommu_table(struct device *dev) |
374 | { | |
8a244590 MBY |
375 | struct pci_dev *pdev; |
376 | struct pci_bus *pbus; | |
35b6dfa0 MBY |
377 | struct iommu_table *tbl; |
378 | ||
8a244590 MBY |
379 | pdev = to_pci_dev(dev); |
380 | ||
f055a061 MFB |
381 | pbus = pdev->bus; |
382 | ||
383 | /* is the device behind a bridge? Look for the root bus */ | |
384 | while (pbus->parent) | |
385 | pbus = pbus->parent; | |
8a244590 | 386 | |
08f1c192 | 387 | tbl = pci_iommu(pbus); |
7354b075 | 388 | |
f055a061 | 389 | BUG_ON(tbl && (tbl->it_busno != pbus->number)); |
35b6dfa0 MBY |
390 | |
391 | return tbl; | |
392 | } | |
393 | ||
3cc39bda | 394 | static void calgary_unmap_sg(struct device *dev, |
e465058d JM |
395 | struct scatterlist *sglist, int nelems, int direction) |
396 | { | |
3cc39bda | 397 | struct iommu_table *tbl = find_iommu_table(dev); |
8b87d9f4 JA |
398 | struct scatterlist *s; |
399 | int i; | |
3cc39bda | 400 | |
bc3c6058 | 401 | if (!translation_enabled(tbl)) |
3cc39bda MBY |
402 | return; |
403 | ||
8b87d9f4 | 404 | for_each_sg(sglist, s, nelems, i) { |
e465058d | 405 | unsigned int npages; |
8b87d9f4 JA |
406 | dma_addr_t dma = s->dma_address; |
407 | unsigned int dmalen = s->dma_length; | |
e465058d JM |
408 | |
409 | if (dmalen == 0) | |
410 | break; | |
411 | ||
412 | npages = num_dma_pages(dma, dmalen); | |
3cc39bda | 413 | iommu_free(tbl, dma, npages); |
e465058d JM |
414 | } |
415 | } | |
416 | ||
0b11e1c6 | 417 | static int calgary_map_sg(struct device *dev, struct scatterlist *sg, |
e465058d JM |
418 | int nelems, int direction) |
419 | { | |
35b6dfa0 | 420 | struct iommu_table *tbl = find_iommu_table(dev); |
8b87d9f4 | 421 | struct scatterlist *s; |
e465058d JM |
422 | unsigned long vaddr; |
423 | unsigned int npages; | |
424 | unsigned long entry; | |
425 | int i; | |
426 | ||
8b87d9f4 | 427 | for_each_sg(sg, s, nelems, i) { |
58b053e4 | 428 | BUG_ON(!sg_page(s)); |
e465058d | 429 | |
58b053e4 | 430 | vaddr = (unsigned long) sg_virt(s); |
e465058d JM |
431 | npages = num_dma_pages(vaddr, s->length); |
432 | ||
1b39b077 | 433 | entry = iommu_range_alloc(dev, tbl, npages); |
e465058d JM |
434 | if (entry == bad_dma_address) { |
435 | /* makes sure unmap knows to stop */ | |
436 | s->dma_length = 0; | |
437 | goto error; | |
438 | } | |
439 | ||
440 | s->dma_address = (entry << PAGE_SHIFT) | s->offset; | |
441 | ||
442 | /* insert into HW table */ | |
443 | tce_build(tbl, entry, npages, vaddr & PAGE_MASK, | |
444 | direction); | |
445 | ||
446 | s->dma_length = s->length; | |
447 | } | |
448 | ||
e465058d JM |
449 | return nelems; |
450 | error: | |
3cc39bda | 451 | calgary_unmap_sg(dev, sg, nelems, direction); |
8b87d9f4 JA |
452 | for_each_sg(sg, s, nelems, i) { |
453 | sg->dma_address = bad_dma_address; | |
454 | sg->dma_length = 0; | |
e465058d | 455 | } |
e465058d JM |
456 | return 0; |
457 | } | |
458 | ||
2be62149 | 459 | static dma_addr_t calgary_map_single(struct device *dev, phys_addr_t paddr, |
e465058d JM |
460 | size_t size, int direction) |
461 | { | |
2be62149 | 462 | void *vaddr = phys_to_virt(paddr); |
e465058d JM |
463 | unsigned long uaddr; |
464 | unsigned int npages; | |
35b6dfa0 | 465 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
466 | |
467 | uaddr = (unsigned long)vaddr; | |
468 | npages = num_dma_pages(uaddr, size); | |
469 | ||
1956a96d | 470 | return iommu_alloc(dev, tbl, vaddr, npages, direction); |
e465058d JM |
471 | } |
472 | ||
0b11e1c6 | 473 | static void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle, |
e465058d JM |
474 | size_t size, int direction) |
475 | { | |
35b6dfa0 | 476 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
477 | unsigned int npages; |
478 | ||
e465058d JM |
479 | npages = num_dma_pages(dma_handle, size); |
480 | iommu_free(tbl, dma_handle, npages); | |
481 | } | |
482 | ||
0b11e1c6 | 483 | static void* calgary_alloc_coherent(struct device *dev, size_t size, |
e465058d JM |
484 | dma_addr_t *dma_handle, gfp_t flag) |
485 | { | |
486 | void *ret = NULL; | |
487 | dma_addr_t mapping; | |
488 | unsigned int npages, order; | |
35b6dfa0 | 489 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
490 | |
491 | size = PAGE_ALIGN(size); /* size rounded up to full pages */ | |
492 | npages = size >> PAGE_SHIFT; | |
493 | order = get_order(size); | |
494 | ||
495 | /* alloc enough pages (and possibly more) */ | |
496 | ret = (void *)__get_free_pages(flag, order); | |
497 | if (!ret) | |
498 | goto error; | |
499 | memset(ret, 0, size); | |
500 | ||
1956a96d AB |
501 | /* set up tces to cover the allocated range */ |
502 | mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL); | |
503 | if (mapping == bad_dma_address) | |
504 | goto free; | |
505 | *dma_handle = mapping; | |
e465058d | 506 | return ret; |
e465058d JM |
507 | free: |
508 | free_pages((unsigned long)ret, get_order(size)); | |
509 | ret = NULL; | |
510 | error: | |
511 | return ret; | |
512 | } | |
513 | ||
8d8bb39b | 514 | static struct dma_mapping_ops calgary_dma_ops = { |
e465058d JM |
515 | .alloc_coherent = calgary_alloc_coherent, |
516 | .map_single = calgary_map_single, | |
517 | .unmap_single = calgary_unmap_single, | |
518 | .map_sg = calgary_map_sg, | |
519 | .unmap_sg = calgary_unmap_sg, | |
520 | }; | |
521 | ||
b34e90b8 LV |
522 | static inline void __iomem * busno_to_bbar(unsigned char num) |
523 | { | |
524 | return bus_info[num].bbar; | |
525 | } | |
526 | ||
e465058d JM |
527 | static inline int busno_to_phbid(unsigned char num) |
528 | { | |
f38db651 | 529 | return bus_info[num].phbid; |
e465058d JM |
530 | } |
531 | ||
532 | static inline unsigned long split_queue_offset(unsigned char num) | |
533 | { | |
534 | size_t idx = busno_to_phbid(num); | |
535 | ||
536 | return split_queue_offsets[idx]; | |
537 | } | |
538 | ||
539 | static inline unsigned long tar_offset(unsigned char num) | |
540 | { | |
541 | size_t idx = busno_to_phbid(num); | |
542 | ||
543 | return tar_offsets[idx]; | |
544 | } | |
545 | ||
546 | static inline unsigned long phb_offset(unsigned char num) | |
547 | { | |
548 | size_t idx = busno_to_phbid(num); | |
549 | ||
550 | return phb_offsets[idx]; | |
551 | } | |
552 | ||
553 | static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset) | |
554 | { | |
555 | unsigned long target = ((unsigned long)bar) | offset; | |
556 | return (void __iomem*)target; | |
557 | } | |
558 | ||
8a244590 MBY |
559 | static inline int is_calioc2(unsigned short device) |
560 | { | |
561 | return (device == PCI_DEVICE_ID_IBM_CALIOC2); | |
562 | } | |
563 | ||
564 | static inline int is_calgary(unsigned short device) | |
565 | { | |
566 | return (device == PCI_DEVICE_ID_IBM_CALGARY); | |
567 | } | |
568 | ||
569 | static inline int is_cal_pci_dev(unsigned short device) | |
570 | { | |
571 | return (is_calgary(device) || is_calioc2(device)); | |
572 | } | |
573 | ||
ff297b8c | 574 | static void calgary_tce_cache_blast(struct iommu_table *tbl) |
e465058d JM |
575 | { |
576 | u64 val; | |
577 | u32 aer; | |
578 | int i = 0; | |
579 | void __iomem *bbar = tbl->bbar; | |
580 | void __iomem *target; | |
581 | ||
582 | /* disable arbitration on the bus */ | |
583 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
584 | aer = readl(target); | |
585 | writel(0, target); | |
586 | ||
587 | /* read plssr to ensure it got there */ | |
588 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET); | |
589 | val = readl(target); | |
590 | ||
591 | /* poll split queues until all DMA activity is done */ | |
592 | target = calgary_reg(bbar, split_queue_offset(tbl->it_busno)); | |
593 | do { | |
594 | val = readq(target); | |
595 | i++; | |
596 | } while ((val & 0xff) != 0xff && i < 100); | |
597 | if (i == 100) | |
598 | printk(KERN_WARNING "Calgary: PCI bus not quiesced, " | |
599 | "continuing anyway\n"); | |
600 | ||
601 | /* invalidate TCE cache */ | |
602 | target = calgary_reg(bbar, tar_offset(tbl->it_busno)); | |
603 | writeq(tbl->tar_val, target); | |
604 | ||
605 | /* enable arbitration */ | |
606 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
607 | writel(aer, target); | |
608 | (void)readl(target); /* flush */ | |
609 | } | |
610 | ||
00be3fa4 MBY |
611 | static void calioc2_tce_cache_blast(struct iommu_table *tbl) |
612 | { | |
613 | void __iomem *bbar = tbl->bbar; | |
614 | void __iomem *target; | |
615 | u64 val64; | |
616 | u32 val; | |
617 | int i = 0; | |
618 | int count = 1; | |
619 | unsigned char bus = tbl->it_busno; | |
620 | ||
621 | begin: | |
622 | printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast " | |
623 | "sequence - count %d\n", bus, count); | |
624 | ||
625 | /* 1. using the Page Migration Control reg set SoftStop */ | |
626 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
627 | val = be32_to_cpu(readl(target)); | |
628 | printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target); | |
629 | val |= PMR_SOFTSTOP; | |
630 | printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target); | |
631 | writel(cpu_to_be32(val), target); | |
632 | ||
633 | /* 2. poll split queues until all DMA activity is done */ | |
634 | printk(KERN_DEBUG "2a. starting to poll split queues\n"); | |
635 | target = calgary_reg(bbar, split_queue_offset(bus)); | |
636 | do { | |
637 | val64 = readq(target); | |
638 | i++; | |
639 | } while ((val64 & 0xff) != 0xff && i < 100); | |
640 | if (i == 100) | |
641 | printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, " | |
642 | "continuing anyway\n"); | |
643 | ||
644 | /* 3. poll Page Migration DEBUG for SoftStopFault */ | |
645 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG); | |
646 | val = be32_to_cpu(readl(target)); | |
647 | printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target); | |
648 | ||
649 | /* 4. if SoftStopFault - goto (1) */ | |
650 | if (val & PMR_SOFTSTOPFAULT) { | |
651 | if (++count < 100) | |
652 | goto begin; | |
653 | else { | |
654 | printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, " | |
655 | "aborting TCE cache flush sequence!\n"); | |
656 | return; /* pray for the best */ | |
657 | } | |
658 | } | |
659 | ||
660 | /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */ | |
661 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
662 | printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target); | |
663 | val = be32_to_cpu(readl(target)); | |
664 | printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target); | |
665 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG); | |
666 | val = be32_to_cpu(readl(target)); | |
667 | printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target); | |
668 | ||
669 | /* 6. invalidate TCE cache */ | |
670 | printk(KERN_DEBUG "6. invalidating TCE cache\n"); | |
671 | target = calgary_reg(bbar, tar_offset(bus)); | |
672 | writeq(tbl->tar_val, target); | |
673 | ||
674 | /* 7. Re-read PMCR */ | |
675 | printk(KERN_DEBUG "7a. Re-reading PMCR\n"); | |
676 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
677 | val = be32_to_cpu(readl(target)); | |
678 | printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target); | |
679 | ||
680 | /* 8. Remove HardStop */ | |
681 | printk(KERN_DEBUG "8a. removing HardStop from PMCR\n"); | |
682 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
683 | val = 0; | |
684 | printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target); | |
685 | writel(cpu_to_be32(val), target); | |
686 | val = be32_to_cpu(readl(target)); | |
687 | printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target); | |
688 | } | |
689 | ||
e465058d JM |
690 | static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start, |
691 | u64 limit) | |
692 | { | |
693 | unsigned int numpages; | |
694 | ||
695 | limit = limit | 0xfffff; | |
696 | limit++; | |
697 | ||
698 | numpages = ((limit - start) >> PAGE_SHIFT); | |
08f1c192 | 699 | iommu_range_reserve(pci_iommu(dev->bus), start, numpages); |
e465058d JM |
700 | } |
701 | ||
702 | static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev) | |
703 | { | |
704 | void __iomem *target; | |
705 | u64 low, high, sizelow; | |
706 | u64 start, limit; | |
08f1c192 | 707 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d JM |
708 | unsigned char busnum = dev->bus->number; |
709 | void __iomem *bbar = tbl->bbar; | |
710 | ||
711 | /* peripheral MEM_1 region */ | |
712 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW); | |
713 | low = be32_to_cpu(readl(target)); | |
714 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH); | |
715 | high = be32_to_cpu(readl(target)); | |
716 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE); | |
717 | sizelow = be32_to_cpu(readl(target)); | |
718 | ||
719 | start = (high << 32) | low; | |
720 | limit = sizelow; | |
721 | ||
722 | calgary_reserve_mem_region(dev, start, limit); | |
723 | } | |
724 | ||
725 | static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev) | |
726 | { | |
727 | void __iomem *target; | |
728 | u32 val32; | |
729 | u64 low, high, sizelow, sizehigh; | |
730 | u64 start, limit; | |
08f1c192 | 731 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d JM |
732 | unsigned char busnum = dev->bus->number; |
733 | void __iomem *bbar = tbl->bbar; | |
734 | ||
735 | /* is it enabled? */ | |
736 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
737 | val32 = be32_to_cpu(readl(target)); | |
738 | if (!(val32 & PHB_MEM2_ENABLE)) | |
739 | return; | |
740 | ||
741 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW); | |
742 | low = be32_to_cpu(readl(target)); | |
743 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH); | |
744 | high = be32_to_cpu(readl(target)); | |
745 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW); | |
746 | sizelow = be32_to_cpu(readl(target)); | |
747 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH); | |
748 | sizehigh = be32_to_cpu(readl(target)); | |
749 | ||
750 | start = (high << 32) | low; | |
751 | limit = (sizehigh << 32) | sizelow; | |
752 | ||
753 | calgary_reserve_mem_region(dev, start, limit); | |
754 | } | |
755 | ||
756 | /* | |
757 | * some regions of the IO address space do not get translated, so we | |
758 | * must not give devices IO addresses in those regions. The regions | |
759 | * are the 640KB-1MB region and the two PCI peripheral memory holes. | |
760 | * Reserve all of them in the IOMMU bitmap to avoid giving them out | |
761 | * later. | |
762 | */ | |
763 | static void __init calgary_reserve_regions(struct pci_dev *dev) | |
764 | { | |
765 | unsigned int npages; | |
e465058d | 766 | u64 start; |
08f1c192 | 767 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d | 768 | |
310adfdd MBY |
769 | /* reserve EMERGENCY_PAGES from bad_dma_address and up */ |
770 | iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES); | |
e465058d JM |
771 | |
772 | /* avoid the BIOS/VGA first 640KB-1MB region */ | |
e8f20414 | 773 | /* for CalIOC2 - avoid the entire first MB */ |
8a244590 MBY |
774 | if (is_calgary(dev->device)) { |
775 | start = (640 * 1024); | |
776 | npages = ((1024 - 640) * 1024) >> PAGE_SHIFT; | |
777 | } else { /* calioc2 */ | |
778 | start = 0; | |
e8f20414 | 779 | npages = (1 * 1024 * 1024) >> PAGE_SHIFT; |
8a244590 | 780 | } |
e465058d JM |
781 | iommu_range_reserve(tbl, start, npages); |
782 | ||
783 | /* reserve the two PCI peripheral memory regions in IO space */ | |
784 | calgary_reserve_peripheral_mem_1(dev); | |
785 | calgary_reserve_peripheral_mem_2(dev); | |
786 | } | |
787 | ||
788 | static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar) | |
789 | { | |
790 | u64 val64; | |
791 | u64 table_phys; | |
792 | void __iomem *target; | |
793 | int ret; | |
794 | struct iommu_table *tbl; | |
795 | ||
796 | /* build TCE tables for each PHB */ | |
797 | ret = build_tce_table(dev, bbar); | |
798 | if (ret) | |
799 | return ret; | |
800 | ||
08f1c192 | 801 | tbl = pci_iommu(dev->bus); |
f38db651 | 802 | tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space; |
95b68dec C |
803 | |
804 | if (is_kdump_kernel()) | |
805 | calgary_init_bitmap_from_tce_table(tbl); | |
806 | else | |
807 | tce_free(tbl, 0, tbl->it_size); | |
f38db651 | 808 | |
8bcf7705 MBY |
809 | if (is_calgary(dev->device)) |
810 | tbl->chip_ops = &calgary_chip_ops; | |
c3860108 MBY |
811 | else if (is_calioc2(dev->device)) |
812 | tbl->chip_ops = &calioc2_chip_ops; | |
8bcf7705 MBY |
813 | else |
814 | BUG(); | |
ff297b8c | 815 | |
e465058d JM |
816 | calgary_reserve_regions(dev); |
817 | ||
818 | /* set TARs for each PHB */ | |
819 | target = calgary_reg(bbar, tar_offset(dev->bus->number)); | |
820 | val64 = be64_to_cpu(readq(target)); | |
821 | ||
822 | /* zero out all TAR bits under sw control */ | |
823 | val64 &= ~TAR_SW_BITS; | |
e465058d | 824 | table_phys = (u64)__pa(tbl->it_base); |
8a244590 | 825 | |
e465058d JM |
826 | val64 |= table_phys; |
827 | ||
828 | BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M); | |
829 | val64 |= (u64) specified_table_size; | |
830 | ||
831 | tbl->tar_val = cpu_to_be64(val64); | |
8a244590 | 832 | |
e465058d JM |
833 | writeq(tbl->tar_val, target); |
834 | readq(target); /* flush */ | |
835 | ||
836 | return 0; | |
837 | } | |
838 | ||
b8f4fe66 | 839 | static void __init calgary_free_bus(struct pci_dev *dev) |
e465058d JM |
840 | { |
841 | u64 val64; | |
08f1c192 | 842 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d | 843 | void __iomem *target; |
b8f4fe66 | 844 | unsigned int bitmapsz; |
e465058d JM |
845 | |
846 | target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number)); | |
847 | val64 = be64_to_cpu(readq(target)); | |
848 | val64 &= ~TAR_SW_BITS; | |
849 | writeq(cpu_to_be64(val64), target); | |
850 | readq(target); /* flush */ | |
851 | ||
b8f4fe66 MBY |
852 | bitmapsz = tbl->it_size / BITS_PER_BYTE; |
853 | free_pages((unsigned long)tbl->it_map, get_order(bitmapsz)); | |
854 | tbl->it_map = NULL; | |
855 | ||
e465058d | 856 | kfree(tbl); |
08f1c192 MBY |
857 | |
858 | set_pci_iommu(dev->bus, NULL); | |
b8f4fe66 MBY |
859 | |
860 | /* Can't free bootmem allocated memory after system is up :-( */ | |
861 | bus_info[dev->bus->number].tce_space = NULL; | |
e465058d JM |
862 | } |
863 | ||
8a244590 MBY |
864 | static void calgary_dump_error_regs(struct iommu_table *tbl) |
865 | { | |
866 | void __iomem *bbar = tbl->bbar; | |
8cb32dc7 | 867 | void __iomem *target; |
ddbd41b4 | 868 | u32 csr, plssr; |
8cb32dc7 MBY |
869 | |
870 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET); | |
ddbd41b4 MBY |
871 | csr = be32_to_cpu(readl(target)); |
872 | ||
873 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET); | |
874 | plssr = be32_to_cpu(readl(target)); | |
8cb32dc7 MBY |
875 | |
876 | /* If no error, the agent ID in the CSR is not valid */ | |
877 | printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, " | |
ddbd41b4 | 878 | "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr); |
8cb32dc7 MBY |
879 | } |
880 | ||
881 | static void calioc2_dump_error_regs(struct iommu_table *tbl) | |
882 | { | |
883 | void __iomem *bbar = tbl->bbar; | |
884 | u32 csr, csmr, plssr, mck, rcstat; | |
8a244590 MBY |
885 | void __iomem *target; |
886 | unsigned long phboff = phb_offset(tbl->it_busno); | |
887 | unsigned long erroff; | |
888 | u32 errregs[7]; | |
889 | int i; | |
890 | ||
891 | /* dump CSR */ | |
892 | target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET); | |
893 | csr = be32_to_cpu(readl(target)); | |
894 | /* dump PLSSR */ | |
895 | target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET); | |
896 | plssr = be32_to_cpu(readl(target)); | |
897 | /* dump CSMR */ | |
898 | target = calgary_reg(bbar, phboff | 0x290); | |
899 | csmr = be32_to_cpu(readl(target)); | |
900 | /* dump mck */ | |
901 | target = calgary_reg(bbar, phboff | 0x800); | |
902 | mck = be32_to_cpu(readl(target)); | |
903 | ||
8cb32dc7 MBY |
904 | printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n", |
905 | tbl->it_busno); | |
906 | ||
907 | printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n", | |
908 | csr, plssr, csmr, mck); | |
8a244590 MBY |
909 | |
910 | /* dump rest of error regs */ | |
911 | printk(KERN_EMERG "Calgary: "); | |
912 | for (i = 0; i < ARRAY_SIZE(errregs); i++) { | |
7354b075 MBY |
913 | /* err regs are at 0x810 - 0x870 */ |
914 | erroff = (0x810 + (i * 0x10)); | |
8a244590 MBY |
915 | target = calgary_reg(bbar, phboff | erroff); |
916 | errregs[i] = be32_to_cpu(readl(target)); | |
917 | printk("0x%08x@0x%lx ", errregs[i], erroff); | |
918 | } | |
919 | printk("\n"); | |
8cb32dc7 MBY |
920 | |
921 | /* root complex status */ | |
922 | target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS); | |
923 | rcstat = be32_to_cpu(readl(target)); | |
924 | printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat, | |
925 | PHB_ROOT_COMPLEX_STATUS); | |
8a244590 MBY |
926 | } |
927 | ||
e465058d JM |
928 | static void calgary_watchdog(unsigned long data) |
929 | { | |
930 | struct pci_dev *dev = (struct pci_dev *)data; | |
08f1c192 | 931 | struct iommu_table *tbl = pci_iommu(dev->bus); |
e465058d JM |
932 | void __iomem *bbar = tbl->bbar; |
933 | u32 val32; | |
934 | void __iomem *target; | |
935 | ||
936 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET); | |
937 | val32 = be32_to_cpu(readl(target)); | |
938 | ||
939 | /* If no error, the agent ID in the CSR is not valid */ | |
940 | if (val32 & CSR_AGENT_MASK) { | |
8cb32dc7 | 941 | tbl->chip_ops->dump_error_regs(tbl); |
8a244590 MBY |
942 | |
943 | /* reset error */ | |
e465058d JM |
944 | writel(0, target); |
945 | ||
946 | /* Disable bus that caused the error */ | |
947 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | | |
8a244590 | 948 | PHB_CONFIG_RW_OFFSET); |
e465058d JM |
949 | val32 = be32_to_cpu(readl(target)); |
950 | val32 |= PHB_SLOT_DISABLE; | |
951 | writel(cpu_to_be32(val32), target); | |
952 | readl(target); /* flush */ | |
953 | } else { | |
954 | /* Reset the timer */ | |
955 | mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ); | |
956 | } | |
957 | } | |
958 | ||
a2b663f6 MBY |
959 | static void __init calgary_set_split_completion_timeout(void __iomem *bbar, |
960 | unsigned char busnum, unsigned long timeout) | |
cb01fc72 MBY |
961 | { |
962 | u64 val64; | |
963 | void __iomem *target; | |
58db8548 | 964 | unsigned int phb_shift = ~0; /* silence gcc */ |
cb01fc72 MBY |
965 | u64 mask; |
966 | ||
967 | switch (busno_to_phbid(busnum)) { | |
968 | case 0: phb_shift = (63 - 19); | |
969 | break; | |
970 | case 1: phb_shift = (63 - 23); | |
971 | break; | |
972 | case 2: phb_shift = (63 - 27); | |
973 | break; | |
974 | case 3: phb_shift = (63 - 35); | |
975 | break; | |
976 | default: | |
977 | BUG_ON(busno_to_phbid(busnum)); | |
978 | } | |
979 | ||
980 | target = calgary_reg(bbar, CALGARY_CONFIG_REG); | |
981 | val64 = be64_to_cpu(readq(target)); | |
982 | ||
983 | /* zero out this PHB's timer bits */ | |
984 | mask = ~(0xFUL << phb_shift); | |
985 | val64 &= mask; | |
a2b663f6 | 986 | val64 |= (timeout << phb_shift); |
cb01fc72 MBY |
987 | writeq(cpu_to_be64(val64), target); |
988 | readq(target); /* flush */ | |
989 | } | |
990 | ||
31f3dff6 | 991 | static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev) |
c3860108 MBY |
992 | { |
993 | unsigned char busnum = dev->bus->number; | |
994 | void __iomem *bbar = tbl->bbar; | |
995 | void __iomem *target; | |
996 | u32 val; | |
997 | ||
8bcf7705 MBY |
998 | /* |
999 | * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1 | |
1000 | */ | |
1001 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2); | |
1002 | val = cpu_to_be32(readl(target)); | |
1003 | val |= 0x00800000; | |
1004 | writel(cpu_to_be32(val), target); | |
c3860108 MBY |
1005 | } |
1006 | ||
31f3dff6 | 1007 | static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev) |
b8d2ea1b MBY |
1008 | { |
1009 | unsigned char busnum = dev->bus->number; | |
b8d2ea1b MBY |
1010 | |
1011 | /* | |
1012 | * Give split completion a longer timeout on bus 1 for aic94xx | |
1013 | * http://bugzilla.kernel.org/show_bug.cgi?id=7180 | |
1014 | */ | |
c3860108 | 1015 | if (is_calgary(dev->device) && (busnum == 1)) |
b8d2ea1b MBY |
1016 | calgary_set_split_completion_timeout(tbl->bbar, busnum, |
1017 | CCR_2SEC_TIMEOUT); | |
1018 | } | |
1019 | ||
e465058d JM |
1020 | static void __init calgary_enable_translation(struct pci_dev *dev) |
1021 | { | |
1022 | u32 val32; | |
1023 | unsigned char busnum; | |
1024 | void __iomem *target; | |
1025 | void __iomem *bbar; | |
1026 | struct iommu_table *tbl; | |
1027 | ||
1028 | busnum = dev->bus->number; | |
08f1c192 | 1029 | tbl = pci_iommu(dev->bus); |
e465058d JM |
1030 | bbar = tbl->bbar; |
1031 | ||
1032 | /* enable TCE in PHB Config Register */ | |
1033 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
1034 | val32 = be32_to_cpu(readl(target)); | |
1035 | val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE; | |
1036 | ||
8a244590 MBY |
1037 | printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n", |
1038 | (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ? | |
1039 | "Calgary" : "CalIOC2", busnum); | |
e465058d JM |
1040 | printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this " |
1041 | "bus.\n"); | |
1042 | ||
1043 | writel(cpu_to_be32(val32), target); | |
1044 | readl(target); /* flush */ | |
1045 | ||
1046 | init_timer(&tbl->watchdog_timer); | |
1047 | tbl->watchdog_timer.function = &calgary_watchdog; | |
1048 | tbl->watchdog_timer.data = (unsigned long)dev; | |
1049 | mod_timer(&tbl->watchdog_timer, jiffies); | |
1050 | } | |
1051 | ||
1052 | static void __init calgary_disable_translation(struct pci_dev *dev) | |
1053 | { | |
1054 | u32 val32; | |
1055 | unsigned char busnum; | |
1056 | void __iomem *target; | |
1057 | void __iomem *bbar; | |
1058 | struct iommu_table *tbl; | |
1059 | ||
1060 | busnum = dev->bus->number; | |
08f1c192 | 1061 | tbl = pci_iommu(dev->bus); |
e465058d JM |
1062 | bbar = tbl->bbar; |
1063 | ||
1064 | /* disable TCE in PHB Config Register */ | |
1065 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
1066 | val32 = be32_to_cpu(readl(target)); | |
1067 | val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE); | |
1068 | ||
70d666d6 | 1069 | printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum); |
e465058d JM |
1070 | writel(cpu_to_be32(val32), target); |
1071 | readl(target); /* flush */ | |
1072 | ||
1073 | del_timer_sync(&tbl->watchdog_timer); | |
1074 | } | |
1075 | ||
a4fc520a | 1076 | static void __init calgary_init_one_nontraslated(struct pci_dev *dev) |
e465058d | 1077 | { |
871b1700 | 1078 | pci_dev_get(dev); |
08f1c192 | 1079 | set_pci_iommu(dev->bus, NULL); |
8a244590 MBY |
1080 | |
1081 | /* is the device behind a bridge? */ | |
1082 | if (dev->bus->parent) | |
1083 | dev->bus->parent->self = dev; | |
1084 | else | |
1085 | dev->bus->self = dev; | |
e465058d JM |
1086 | } |
1087 | ||
1088 | static int __init calgary_init_one(struct pci_dev *dev) | |
1089 | { | |
e465058d | 1090 | void __iomem *bbar; |
ff297b8c | 1091 | struct iommu_table *tbl; |
e465058d JM |
1092 | int ret; |
1093 | ||
dedc9937 JM |
1094 | BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM); |
1095 | ||
eae93755 | 1096 | bbar = busno_to_bbar(dev->bus->number); |
e465058d JM |
1097 | ret = calgary_setup_tar(dev, bbar); |
1098 | if (ret) | |
eae93755 | 1099 | goto done; |
e465058d | 1100 | |
871b1700 | 1101 | pci_dev_get(dev); |
8a244590 MBY |
1102 | |
1103 | if (dev->bus->parent) { | |
1104 | if (dev->bus->parent->self) | |
1105 | printk(KERN_WARNING "Calgary: IEEEE, dev %p has " | |
1106 | "bus->parent->self!\n", dev); | |
1107 | dev->bus->parent->self = dev; | |
1108 | } else | |
1109 | dev->bus->self = dev; | |
b8d2ea1b | 1110 | |
08f1c192 | 1111 | tbl = pci_iommu(dev->bus); |
ff297b8c | 1112 | tbl->chip_ops->handle_quirks(tbl, dev); |
b8d2ea1b | 1113 | |
e465058d JM |
1114 | calgary_enable_translation(dev); |
1115 | ||
1116 | return 0; | |
1117 | ||
e465058d JM |
1118 | done: |
1119 | return ret; | |
1120 | } | |
1121 | ||
eae93755 | 1122 | static int __init calgary_locate_bbars(void) |
e465058d | 1123 | { |
eae93755 MBY |
1124 | int ret; |
1125 | int rioidx, phb, bus; | |
b34e90b8 LV |
1126 | void __iomem *bbar; |
1127 | void __iomem *target; | |
eae93755 | 1128 | unsigned long offset; |
b34e90b8 LV |
1129 | u8 start_bus, end_bus; |
1130 | u32 val; | |
1131 | ||
eae93755 MBY |
1132 | ret = -ENODATA; |
1133 | for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) { | |
1134 | struct rio_detail *rio = rio_devs[rioidx]; | |
b34e90b8 | 1135 | |
eae93755 | 1136 | if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY)) |
b34e90b8 LV |
1137 | continue; |
1138 | ||
1139 | /* map entire 1MB of Calgary config space */ | |
eae93755 MBY |
1140 | bbar = ioremap_nocache(rio->BBAR, 1024 * 1024); |
1141 | if (!bbar) | |
1142 | goto error; | |
b34e90b8 LV |
1143 | |
1144 | for (phb = 0; phb < PHBS_PER_CALGARY; phb++) { | |
eae93755 MBY |
1145 | offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET; |
1146 | target = calgary_reg(bbar, offset); | |
b34e90b8 | 1147 | |
b34e90b8 | 1148 | val = be32_to_cpu(readl(target)); |
8a244590 | 1149 | |
b34e90b8 | 1150 | start_bus = (u8)((val & 0x00FF0000) >> 16); |
eae93755 | 1151 | end_bus = (u8)((val & 0x0000FF00) >> 8); |
8a244590 MBY |
1152 | |
1153 | if (end_bus) { | |
1154 | for (bus = start_bus; bus <= end_bus; bus++) { | |
1155 | bus_info[bus].bbar = bbar; | |
1156 | bus_info[bus].phbid = phb; | |
1157 | } | |
1158 | } else { | |
1159 | bus_info[start_bus].bbar = bbar; | |
1160 | bus_info[start_bus].phbid = phb; | |
b34e90b8 LV |
1161 | } |
1162 | } | |
1163 | } | |
1164 | ||
eae93755 MBY |
1165 | return 0; |
1166 | ||
1167 | error: | |
1168 | /* scan bus_info and iounmap any bbars we previously ioremap'd */ | |
1169 | for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++) | |
1170 | if (bus_info[bus].bbar) | |
1171 | iounmap(bus_info[bus].bbar); | |
1172 | ||
1173 | return ret; | |
1174 | } | |
1175 | ||
1176 | static int __init calgary_init(void) | |
1177 | { | |
1178 | int ret; | |
1179 | struct pci_dev *dev = NULL; | |
bc3c6058 | 1180 | struct calgary_bus_info *info; |
eae93755 MBY |
1181 | |
1182 | ret = calgary_locate_bbars(); | |
1183 | if (ret) | |
1184 | return ret; | |
e465058d | 1185 | |
95b68dec C |
1186 | /* Purely for kdump kernel case */ |
1187 | if (is_kdump_kernel()) | |
1188 | get_tce_space_from_tar(); | |
1189 | ||
dedc9937 | 1190 | do { |
8a244590 | 1191 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); |
e465058d JM |
1192 | if (!dev) |
1193 | break; | |
8a244590 MBY |
1194 | if (!is_cal_pci_dev(dev->device)) |
1195 | continue; | |
bc3c6058 MBY |
1196 | |
1197 | info = &bus_info[dev->bus->number]; | |
1198 | if (info->translation_disabled) { | |
e465058d JM |
1199 | calgary_init_one_nontraslated(dev); |
1200 | continue; | |
1201 | } | |
bc3c6058 MBY |
1202 | |
1203 | if (!info->tce_space && !translate_empty_slots) | |
e465058d | 1204 | continue; |
12de257b | 1205 | |
e465058d JM |
1206 | ret = calgary_init_one(dev); |
1207 | if (ret) | |
1208 | goto error; | |
dedc9937 | 1209 | } while (1); |
e465058d | 1210 | |
1956a96d AB |
1211 | dev = NULL; |
1212 | for_each_pci_dev(dev) { | |
1213 | struct iommu_table *tbl; | |
1214 | ||
1215 | tbl = find_iommu_table(&dev->dev); | |
1216 | ||
1217 | if (translation_enabled(tbl)) | |
1218 | dev->dev.archdata.dma_ops = &calgary_dma_ops; | |
1219 | } | |
1220 | ||
e465058d JM |
1221 | return ret; |
1222 | ||
1223 | error: | |
dedc9937 | 1224 | do { |
a2b5d877 | 1225 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); |
9f2dc46d MBY |
1226 | if (!dev) |
1227 | break; | |
8a244590 MBY |
1228 | if (!is_cal_pci_dev(dev->device)) |
1229 | continue; | |
bc3c6058 MBY |
1230 | |
1231 | info = &bus_info[dev->bus->number]; | |
1232 | if (info->translation_disabled) { | |
e465058d JM |
1233 | pci_dev_put(dev); |
1234 | continue; | |
1235 | } | |
bc3c6058 | 1236 | if (!info->tce_space && !translate_empty_slots) |
e465058d | 1237 | continue; |
871b1700 | 1238 | |
e465058d | 1239 | calgary_disable_translation(dev); |
b8f4fe66 | 1240 | calgary_free_bus(dev); |
871b1700 | 1241 | pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */ |
1956a96d | 1242 | dev->dev.archdata.dma_ops = NULL; |
dedc9937 | 1243 | } while (1); |
e465058d JM |
1244 | |
1245 | return ret; | |
1246 | } | |
1247 | ||
1248 | static inline int __init determine_tce_table_size(u64 ram) | |
1249 | { | |
1250 | int ret; | |
1251 | ||
1252 | if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED) | |
1253 | return specified_table_size; | |
1254 | ||
1255 | /* | |
1256 | * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to | |
1257 | * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each | |
1258 | * larger table size has twice as many entries, so shift the | |
1259 | * max ram address by 13 to divide by 8K and then look at the | |
1260 | * order of the result to choose between 0-7. | |
1261 | */ | |
1262 | ret = get_order(ram >> 13); | |
1263 | if (ret > TCE_TABLE_SIZE_8M) | |
1264 | ret = TCE_TABLE_SIZE_8M; | |
1265 | ||
1266 | return ret; | |
1267 | } | |
1268 | ||
b34e90b8 LV |
1269 | static int __init build_detail_arrays(void) |
1270 | { | |
1271 | unsigned long ptr; | |
1272 | int i, scal_detail_size, rio_detail_size; | |
1273 | ||
1274 | if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){ | |
1275 | printk(KERN_WARNING | |
eae93755 | 1276 | "Calgary: MAX_NUMNODES too low! Defined as %d, " |
b34e90b8 LV |
1277 | "but system has %d nodes.\n", |
1278 | MAX_NUMNODES, rio_table_hdr->num_scal_dev); | |
1279 | return -ENODEV; | |
1280 | } | |
1281 | ||
1282 | switch (rio_table_hdr->version){ | |
b34e90b8 LV |
1283 | case 2: |
1284 | scal_detail_size = 11; | |
1285 | rio_detail_size = 13; | |
1286 | break; | |
1287 | case 3: | |
1288 | scal_detail_size = 12; | |
1289 | rio_detail_size = 15; | |
1290 | break; | |
eae93755 MBY |
1291 | default: |
1292 | printk(KERN_WARNING | |
1293 | "Calgary: Invalid Rio Grande Table Version: %d\n", | |
1294 | rio_table_hdr->version); | |
1295 | return -EPROTO; | |
b34e90b8 LV |
1296 | } |
1297 | ||
1298 | ptr = ((unsigned long)rio_table_hdr) + 3; | |
1299 | for (i = 0; i < rio_table_hdr->num_scal_dev; | |
1300 | i++, ptr += scal_detail_size) | |
1301 | scal_devs[i] = (struct scal_detail *)ptr; | |
1302 | ||
1303 | for (i = 0; i < rio_table_hdr->num_rio_dev; | |
1304 | i++, ptr += rio_detail_size) | |
1305 | rio_devs[i] = (struct rio_detail *)ptr; | |
1306 | ||
1307 | return 0; | |
1308 | } | |
1309 | ||
8a244590 | 1310 | static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev) |
e465058d | 1311 | { |
8a244590 | 1312 | int dev; |
e465058d | 1313 | u32 val; |
8a244590 MBY |
1314 | |
1315 | if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) { | |
1316 | /* | |
1317 | * FIXME: properly scan for devices accross the | |
1318 | * PCI-to-PCI bridge on every CalIOC2 port. | |
1319 | */ | |
1320 | return 1; | |
1321 | } | |
1322 | ||
1323 | for (dev = 1; dev < 8; dev++) { | |
1324 | val = read_pci_config(bus, dev, 0, 0); | |
1325 | if (val != 0xffffffff) | |
1326 | break; | |
1327 | } | |
1328 | return (val != 0xffffffff); | |
1329 | } | |
1330 | ||
95b68dec C |
1331 | /* |
1332 | * calgary_init_bitmap_from_tce_table(): | |
1333 | * Funtion for kdump case. In the second/kdump kernel initialize | |
1334 | * the bitmap based on the tce table entries obtained from first kernel | |
1335 | */ | |
1336 | static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl) | |
1337 | { | |
1338 | u64 *tp; | |
1339 | unsigned int index; | |
1340 | tp = ((u64 *)tbl->it_base); | |
1341 | for (index = 0 ; index < tbl->it_size; index++) { | |
1342 | if (*tp != 0x0) | |
1343 | set_bit(index, tbl->it_map); | |
1344 | tp++; | |
1345 | } | |
1346 | } | |
1347 | ||
1348 | /* | |
1349 | * get_tce_space_from_tar(): | |
1350 | * Function for kdump case. Get the tce tables from first kernel | |
1351 | * by reading the contents of the base adress register of calgary iommu | |
1352 | */ | |
9b0094f7 | 1353 | static void get_tce_space_from_tar(void) |
95b68dec C |
1354 | { |
1355 | int bus; | |
1356 | void __iomem *target; | |
1357 | unsigned long tce_space; | |
1358 | ||
1359 | for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) { | |
1360 | struct calgary_bus_info *info = &bus_info[bus]; | |
1361 | unsigned short pci_device; | |
1362 | u32 val; | |
1363 | ||
1364 | val = read_pci_config(bus, 0, 0, 0); | |
1365 | pci_device = (val & 0xFFFF0000) >> 16; | |
1366 | ||
1367 | if (!is_cal_pci_dev(pci_device)) | |
1368 | continue; | |
1369 | if (info->translation_disabled) | |
1370 | continue; | |
1371 | ||
1372 | if (calgary_bus_has_devices(bus, pci_device) || | |
1373 | translate_empty_slots) { | |
1374 | target = calgary_reg(bus_info[bus].bbar, | |
1375 | tar_offset(bus)); | |
1376 | tce_space = be64_to_cpu(readq(target)); | |
1377 | tce_space = tce_space & TAR_SW_BITS; | |
1378 | ||
1379 | tce_space = tce_space & (~specified_table_size); | |
1380 | info->tce_space = (u64 *)__va(tce_space); | |
1381 | } | |
1382 | } | |
1383 | return; | |
1384 | } | |
1385 | ||
8a244590 MBY |
1386 | void __init detect_calgary(void) |
1387 | { | |
d2105b10 | 1388 | int bus; |
e465058d | 1389 | void *tbl; |
d2105b10 | 1390 | int calgary_found = 0; |
b34e90b8 | 1391 | unsigned long ptr; |
136f1e7a | 1392 | unsigned int offset, prev_offset; |
eae93755 | 1393 | int ret; |
e465058d JM |
1394 | |
1395 | /* | |
1396 | * if the user specified iommu=off or iommu=soft or we found | |
1397 | * another HW IOMMU already, bail out. | |
1398 | */ | |
1399 | if (swiotlb || no_iommu || iommu_detected) | |
1400 | return; | |
1401 | ||
bff6547b MBY |
1402 | if (!use_calgary) |
1403 | return; | |
1404 | ||
0637a70a AK |
1405 | if (!early_pci_allowed()) |
1406 | return; | |
1407 | ||
b92cc559 MBY |
1408 | printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n"); |
1409 | ||
b34e90b8 LV |
1410 | ptr = (unsigned long)phys_to_virt(get_bios_ebda()); |
1411 | ||
1412 | rio_table_hdr = NULL; | |
136f1e7a | 1413 | prev_offset = 0; |
b34e90b8 | 1414 | offset = 0x180; |
136f1e7a IM |
1415 | /* |
1416 | * The next offset is stored in the 1st word. | |
1417 | * Only parse up until the offset increases: | |
1418 | */ | |
1419 | while (offset > prev_offset) { | |
b34e90b8 LV |
1420 | /* The block id is stored in the 2nd word */ |
1421 | if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){ | |
1422 | /* set the pointer past the offset & block id */ | |
eae93755 | 1423 | rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4); |
b34e90b8 LV |
1424 | break; |
1425 | } | |
136f1e7a | 1426 | prev_offset = offset; |
b34e90b8 LV |
1427 | offset = *((unsigned short *)(ptr + offset)); |
1428 | } | |
eae93755 | 1429 | if (!rio_table_hdr) { |
b92cc559 MBY |
1430 | printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table " |
1431 | "in EBDA - bailing!\n"); | |
b34e90b8 LV |
1432 | return; |
1433 | } | |
1434 | ||
eae93755 MBY |
1435 | ret = build_detail_arrays(); |
1436 | if (ret) { | |
b92cc559 | 1437 | printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret); |
b34e90b8 | 1438 | return; |
eae93755 | 1439 | } |
b34e90b8 | 1440 | |
95b68dec C |
1441 | specified_table_size = determine_tce_table_size((is_kdump_kernel() ? |
1442 | saved_max_pfn : max_pfn) * PAGE_SIZE); | |
e465058d | 1443 | |
d2105b10 | 1444 | for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) { |
f38db651 | 1445 | struct calgary_bus_info *info = &bus_info[bus]; |
8a244590 MBY |
1446 | unsigned short pci_device; |
1447 | u32 val; | |
1448 | ||
1449 | val = read_pci_config(bus, 0, 0, 0); | |
1450 | pci_device = (val & 0xFFFF0000) >> 16; | |
d2105b10 | 1451 | |
8a244590 | 1452 | if (!is_cal_pci_dev(pci_device)) |
e465058d | 1453 | continue; |
d2105b10 | 1454 | |
f38db651 | 1455 | if (info->translation_disabled) |
e465058d | 1456 | continue; |
f38db651 | 1457 | |
8a244590 MBY |
1458 | if (calgary_bus_has_devices(bus, pci_device) || |
1459 | translate_empty_slots) { | |
95b68dec C |
1460 | /* |
1461 | * If it is kdump kernel, find and use tce tables | |
1462 | * from first kernel, else allocate tce tables here | |
1463 | */ | |
1464 | if (!is_kdump_kernel()) { | |
1465 | tbl = alloc_tce_table(); | |
1466 | if (!tbl) | |
1467 | goto cleanup; | |
1468 | info->tce_space = tbl; | |
1469 | } | |
8a244590 | 1470 | calgary_found = 1; |
d2105b10 | 1471 | } |
e465058d JM |
1472 | } |
1473 | ||
b92cc559 MBY |
1474 | printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n", |
1475 | calgary_found ? "found" : "not found"); | |
1476 | ||
d2105b10 | 1477 | if (calgary_found) { |
e465058d JM |
1478 | iommu_detected = 1; |
1479 | calgary_detected = 1; | |
de684652 MBY |
1480 | printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n"); |
1481 | printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, " | |
1482 | "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size, | |
1483 | debugging ? "enabled" : "disabled"); | |
1956a96d AB |
1484 | |
1485 | /* swiotlb for devices that aren't behind the Calgary. */ | |
1486 | if (max_pfn > MAX_DMA32_PFN) | |
1487 | swiotlb = 1; | |
e465058d JM |
1488 | } |
1489 | return; | |
1490 | ||
1491 | cleanup: | |
f38db651 MBY |
1492 | for (--bus; bus >= 0; --bus) { |
1493 | struct calgary_bus_info *info = &bus_info[bus]; | |
1494 | ||
1495 | if (info->tce_space) | |
1496 | free_tce_table(info->tce_space); | |
1497 | } | |
e465058d JM |
1498 | } |
1499 | ||
1500 | int __init calgary_iommu_init(void) | |
1501 | { | |
1502 | int ret; | |
1503 | ||
1956a96d | 1504 | if (no_iommu || (swiotlb && !calgary_detected)) |
e465058d JM |
1505 | return -ENODEV; |
1506 | ||
1507 | if (!calgary_detected) | |
1508 | return -ENODEV; | |
1509 | ||
1510 | /* ok, we're trying to use Calgary - let's roll */ | |
1511 | printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n"); | |
1512 | ||
1513 | ret = calgary_init(); | |
1514 | if (ret) { | |
1515 | printk(KERN_ERR "PCI-DMA: Calgary init failed %d, " | |
1516 | "falling back to no_iommu\n", ret); | |
e465058d JM |
1517 | return ret; |
1518 | } | |
1519 | ||
1520 | force_iommu = 1; | |
310adfdd | 1521 | bad_dma_address = 0x0; |
1956a96d AB |
1522 | /* dma_ops is set to swiotlb or nommu */ |
1523 | if (!dma_ops) | |
1524 | dma_ops = &nommu_dma_ops; | |
e465058d JM |
1525 | |
1526 | return 0; | |
1527 | } | |
1528 | ||
1529 | static int __init calgary_parse_options(char *p) | |
1530 | { | |
1531 | unsigned int bridge; | |
1532 | size_t len; | |
1533 | char* endp; | |
1534 | ||
1535 | while (*p) { | |
1536 | if (!strncmp(p, "64k", 3)) | |
1537 | specified_table_size = TCE_TABLE_SIZE_64K; | |
1538 | else if (!strncmp(p, "128k", 4)) | |
1539 | specified_table_size = TCE_TABLE_SIZE_128K; | |
1540 | else if (!strncmp(p, "256k", 4)) | |
1541 | specified_table_size = TCE_TABLE_SIZE_256K; | |
1542 | else if (!strncmp(p, "512k", 4)) | |
1543 | specified_table_size = TCE_TABLE_SIZE_512K; | |
1544 | else if (!strncmp(p, "1M", 2)) | |
1545 | specified_table_size = TCE_TABLE_SIZE_1M; | |
1546 | else if (!strncmp(p, "2M", 2)) | |
1547 | specified_table_size = TCE_TABLE_SIZE_2M; | |
1548 | else if (!strncmp(p, "4M", 2)) | |
1549 | specified_table_size = TCE_TABLE_SIZE_4M; | |
1550 | else if (!strncmp(p, "8M", 2)) | |
1551 | specified_table_size = TCE_TABLE_SIZE_8M; | |
1552 | ||
1553 | len = strlen("translate_empty_slots"); | |
1554 | if (!strncmp(p, "translate_empty_slots", len)) | |
1555 | translate_empty_slots = 1; | |
1556 | ||
1557 | len = strlen("disable"); | |
1558 | if (!strncmp(p, "disable", len)) { | |
1559 | p += len; | |
1560 | if (*p == '=') | |
1561 | ++p; | |
1562 | if (*p == '\0') | |
1563 | break; | |
1564 | bridge = simple_strtol(p, &endp, 0); | |
1565 | if (p == endp) | |
1566 | break; | |
1567 | ||
d2105b10 | 1568 | if (bridge < MAX_PHB_BUS_NUM) { |
e465058d | 1569 | printk(KERN_INFO "Calgary: disabling " |
70d666d6 | 1570 | "translation for PHB %#x\n", bridge); |
f38db651 | 1571 | bus_info[bridge].translation_disabled = 1; |
e465058d JM |
1572 | } |
1573 | } | |
1574 | ||
1575 | p = strpbrk(p, ","); | |
1576 | if (!p) | |
1577 | break; | |
1578 | ||
1579 | p++; /* skip ',' */ | |
1580 | } | |
1581 | return 1; | |
1582 | } | |
1583 | __setup("calgary=", calgary_parse_options); | |
07877cf6 MBY |
1584 | |
1585 | static void __init calgary_fixup_one_tce_space(struct pci_dev *dev) | |
1586 | { | |
1587 | struct iommu_table *tbl; | |
1588 | unsigned int npages; | |
1589 | int i; | |
1590 | ||
08f1c192 | 1591 | tbl = pci_iommu(dev->bus); |
07877cf6 MBY |
1592 | |
1593 | for (i = 0; i < 4; i++) { | |
1594 | struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i]; | |
1595 | ||
1596 | /* Don't give out TCEs that map MEM resources */ | |
1597 | if (!(r->flags & IORESOURCE_MEM)) | |
1598 | continue; | |
1599 | ||
1600 | /* 0-based? we reserve the whole 1st MB anyway */ | |
1601 | if (!r->start) | |
1602 | continue; | |
1603 | ||
1604 | /* cover the whole region */ | |
1605 | npages = (r->end - r->start) >> PAGE_SHIFT; | |
1606 | npages++; | |
1607 | ||
07877cf6 MBY |
1608 | iommu_range_reserve(tbl, r->start, npages); |
1609 | } | |
1610 | } | |
1611 | ||
1612 | static int __init calgary_fixup_tce_spaces(void) | |
1613 | { | |
1614 | struct pci_dev *dev = NULL; | |
bc3c6058 | 1615 | struct calgary_bus_info *info; |
07877cf6 MBY |
1616 | |
1617 | if (no_iommu || swiotlb || !calgary_detected) | |
1618 | return -ENODEV; | |
1619 | ||
12de257b | 1620 | printk(KERN_DEBUG "Calgary: fixing up tce spaces\n"); |
07877cf6 MBY |
1621 | |
1622 | do { | |
1623 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); | |
1624 | if (!dev) | |
1625 | break; | |
1626 | if (!is_cal_pci_dev(dev->device)) | |
1627 | continue; | |
bc3c6058 MBY |
1628 | |
1629 | info = &bus_info[dev->bus->number]; | |
1630 | if (info->translation_disabled) | |
07877cf6 MBY |
1631 | continue; |
1632 | ||
bc3c6058 | 1633 | if (!info->tce_space) |
07877cf6 MBY |
1634 | continue; |
1635 | ||
1636 | calgary_fixup_one_tce_space(dev); | |
1637 | ||
1638 | } while (1); | |
1639 | ||
1640 | return 0; | |
1641 | } | |
1642 | ||
1643 | /* | |
1644 | * We need to be call after pcibios_assign_resources (fs_initcall level) | |
1645 | * and before device_initcall. | |
1646 | */ | |
1647 | rootfs_initcall(calgary_fixup_tce_spaces); |