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KVM: x86: add method to test PIR bitmap vector
[deliverable/linux.git] / arch / x86 / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
9611c187 8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
97222cc8
ED		 9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
edf88417 21#include <linux/kvm_host.h>
97222cc8
ED		 22#include <linux/kvm.h>
23#include <linux/mm.h>
24#include <linux/highmem.h>
25#include <linux/smp.h>
26#include <linux/hrtimer.h>
27#include <linux/io.h>
28#include <linux/module.h>
6f6d6a1a 29#include <linux/math64.h>
5a0e3ad6 30#include <linux/slab.h>
97222cc8
ED		 31#include <asm/processor.h>
32#include <asm/msr.h>
33#include <asm/page.h>
34#include <asm/current.h>
35#include <asm/apicdef.h>
60063497 36#include <linux/atomic.h>
c5cc421b 37#include <linux/jump_label.h>
5fdbf976 38#include "kvm_cache_regs.h"
97222cc8 39#include "irq.h"
229456fc 40#include "trace.h"
fc61b800 41#include "x86.h"
00b27a3e 42#include "cpuid.h"
97222cc8 43
b682b814
MT		 44#ifndef CONFIG_X86_64
45#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
46#else
47#define mod_64(x, y) ((x) % (y))
48#endif
49
97222cc8
ED		 50#define PRId64 "d"
51#define PRIx64 "llx"
52#define PRIu64 "u"
53#define PRIo64 "o"
54
55#define APIC_BUS_CYCLE_NS 1
56
57/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
58#define apic_debug(fmt, arg...)
59
60#define APIC_LVT_NUM 6
61/* 14 is the version for Xeon and Pentium 8.4.8*/
62#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
63#define LAPIC_MMIO_LENGTH (1 << 12)
64/* followed define is not in apicdef.h */
65#define APIC_SHORT_MASK 0xc0000
66#define APIC_DEST_NOSHORT 0x0
67#define APIC_DEST_MASK 0x800
68#define MAX_APIC_VECTOR 256
ecba9a52 69#define APIC_VECTORS_PER_REG 32
97222cc8 70
394457a9
NA		 71#define APIC_BROADCAST 0xFF
72#define X2APIC_BROADCAST 0xFFFFFFFFul
73
97222cc8
ED		 74#define VEC_POS(v) ((v) & (32 - 1))
75#define REG_POS(v) (((v) >> 5) << 4)
ad312c7c 76
97222cc8
ED		 77static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
78{
79 *((u32 *) (apic->regs + reg_off)) = val;
80}
81
a0c9a822
MT		 82static inline int apic_test_vector(int vec, void *bitmap)
83{
84 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
85}
86
10606919
YZ		 87bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
88{
89 struct kvm_lapic *apic = vcpu->arch.apic;
90
91 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
92 apic_test_vector(vector, apic->regs + APIC_IRR);
93}
94
97222cc8
ED		 95static inline void apic_set_vector(int vec, void *bitmap)
96{
97 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
98}
99
100static inline void apic_clear_vector(int vec, void *bitmap)
101{
102 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
103}
104
8680b94b
MT		 105static inline int __apic_test_and_set_vector(int vec, void *bitmap)
106{
107 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
108}
109
110static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
111{
112 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
113}
114
c5cc421b 115struct static_key_deferred apic_hw_disabled __read_mostly;
f8c1ea10
GN		 116struct static_key_deferred apic_sw_disabled __read_mostly;
117
97222cc8
ED		 118static inline int apic_enabled(struct kvm_lapic *apic)
119{
c48f1496 120 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
54e9818f
GN		 121}
122
97222cc8
ED		 123#define LVT_MASK \
124 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
125
126#define LINT_MASK \
127 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
128 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
129
130static inline int kvm_apic_id(struct kvm_lapic *apic)
131{
c48f1496 132 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
97222cc8
ED		 133}
134
1e08ec4a
GN		 135static void recalculate_apic_map(struct kvm *kvm)
136{
137 struct kvm_apic_map *new, *old = NULL;
138 struct kvm_vcpu *vcpu;
139 int i;
140
141 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
142
143 mutex_lock(&kvm->arch.apic_map_lock);
144
145 if (!new)
146 goto out;
147
148 new->ldr_bits = 8;
149 /* flat mode is default */
150 new->cid_shift = 8;
151 new->cid_mask = 0;
152 new->lid_mask = 0xff;
394457a9 153 new->broadcast = APIC_BROADCAST;
1e08ec4a
GN		 154
155 kvm_for_each_vcpu(i, vcpu, kvm) {
156 struct kvm_lapic *apic = vcpu->arch.apic;
1e08ec4a
GN		 157
158 if (!kvm_apic_present(vcpu))
159 continue;
160
1e08ec4a
GN		 161 if (apic_x2apic_mode(apic)) {
162 new->ldr_bits = 32;
163 new->cid_shift = 16;
45c3094a 164 new->cid_mask = new->lid_mask = 0xffff;
394457a9 165 new->broadcast = X2APIC_BROADCAST;
a3e339e1 166 } else if (kvm_apic_get_reg(apic, APIC_LDR)) {
173beedc
NA		 167 if (kvm_apic_get_reg(apic, APIC_DFR) ==
168 APIC_DFR_CLUSTER) {
169 new->cid_shift = 4;
170 new->cid_mask = 0xf;
171 new->lid_mask = 0xf;
a3e339e1
PB		 172 } else {
173 new->cid_shift = 8;
174 new->cid_mask = 0;
175 new->lid_mask = 0xff;
173beedc 176 }
1e08ec4a 177 }
a3e339e1
PB		 178
179 /*
180 * All APICs have to be configured in the same mode by an OS.
181 * We take advatage of this while building logical id loockup
182 * table. After reset APICs are in software disabled mode, so if
183 * we find apic with different setting we assume this is the mode
184 * OS wants all apics to be in; build lookup table accordingly.
185 */
186 if (kvm_apic_sw_enabled(apic))
187 break;
173beedc
NA		 188 }
189
190 kvm_for_each_vcpu(i, vcpu, kvm) {
191 struct kvm_lapic *apic = vcpu->arch.apic;
192 u16 cid, lid;
25995e5b 193 u32 ldr, aid;
1e08ec4a 194
25995e5b 195 aid = kvm_apic_id(apic);
1e08ec4a
GN		 196 ldr = kvm_apic_get_reg(apic, APIC_LDR);
197 cid = apic_cluster_id(new, ldr);
198 lid = apic_logical_id(new, ldr);
199
25995e5b
RK		 200 if (aid < ARRAY_SIZE(new->phys_map))
201 new->phys_map[aid] = apic;
202 if (lid && cid < ARRAY_SIZE(new->logical_map))
1e08ec4a
GN		 203 new->logical_map[cid][ffs(lid) - 1] = apic;
204 }
205out:
206 old = rcu_dereference_protected(kvm->arch.apic_map,
207 lockdep_is_held(&kvm->arch.apic_map_lock));
208 rcu_assign_pointer(kvm->arch.apic_map, new);
209 mutex_unlock(&kvm->arch.apic_map_lock);
210
211 if (old)
212 kfree_rcu(old, rcu);
c7c9c56c 213
3d81bc7e 214 kvm_vcpu_request_scan_ioapic(kvm);
1e08ec4a
GN		 215}
216
1e1b6c26
NA		 217static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
218{
e462755c 219 bool enabled = val & APIC_SPIV_APIC_ENABLED;
1e1b6c26
NA		 220
221 apic_set_reg(apic, APIC_SPIV, val);
e462755c
RK		 222
223 if (enabled != apic->sw_enabled) {
224 apic->sw_enabled = enabled;
225 if (enabled) {
1e1b6c26
NA		 226 static_key_slow_dec_deferred(&apic_sw_disabled);
227 recalculate_apic_map(apic->vcpu->kvm);
228 } else
229 static_key_slow_inc(&apic_sw_disabled.key);
230 }
231}
232
1e08ec4a
GN		 233static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
234{
235 apic_set_reg(apic, APIC_ID, id << 24);
236 recalculate_apic_map(apic->vcpu->kvm);
237}
238
239static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
240{
241 apic_set_reg(apic, APIC_LDR, id);
242 recalculate_apic_map(apic->vcpu->kvm);
243}
244
97222cc8
ED		 245static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
246{
c48f1496 247 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
97222cc8
ED		 248}
249
250static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
251{
c48f1496 252 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
97222cc8
ED		 253}
254
a3e06bbe
LJ		 255static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
256{
f30ebc31 257 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
a3e06bbe
LJ		 258}
259
97222cc8
ED		 260static inline int apic_lvtt_period(struct kvm_lapic *apic)
261{
f30ebc31 262 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
a3e06bbe
LJ		 263}
264
265static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
266{
f30ebc31 267 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
97222cc8
ED		 268}
269
cc6e462c
JK		 270static inline int apic_lvt_nmi_mode(u32 lvt_val)
271{
272 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
273}
274
fc61b800
GN		 275void kvm_apic_set_version(struct kvm_vcpu *vcpu)
276{
277 struct kvm_lapic *apic = vcpu->arch.apic;
278 struct kvm_cpuid_entry2 *feat;
279 u32 v = APIC_VERSION;
280
c48f1496 281 if (!kvm_vcpu_has_lapic(vcpu))
fc61b800
GN		 282 return;
283
284 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
285 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
286 v |= APIC_LVR_DIRECTED_EOI;
287 apic_set_reg(apic, APIC_LVR, v);
288}
289
f1d24831 290static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
a3e06bbe 291 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
97222cc8
ED		 292 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
293 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
294 LINT_MASK, LINT_MASK, /* LVT0-1 */
295 LVT_MASK /* LVTERR */
296};
297
298static int find_highest_vector(void *bitmap)
299{
ecba9a52
TY		 300 int vec;
301 u32 *reg;
97222cc8 302
ecba9a52
TY		 303 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
304 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
305 reg = bitmap + REG_POS(vec);
306 if (*reg)
307 return fls(*reg) - 1 + vec;
308 }
97222cc8 309
ecba9a52 310 return -1;
97222cc8
ED		 311}
312
8680b94b
MT		 313static u8 count_vectors(void *bitmap)
314{
ecba9a52
TY		 315 int vec;
316 u32 *reg;
8680b94b 317 u8 count = 0;
ecba9a52
TY		 318
319 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
320 reg = bitmap + REG_POS(vec);
321 count += hweight32(*reg);
322 }
323
8680b94b
MT		 324 return count;
325}
326
a20ed54d
YZ		 327void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
328{
329 u32 i, pir_val;
330 struct kvm_lapic *apic = vcpu->arch.apic;
331
332 for (i = 0; i <= 7; i++) {
333 pir_val = xchg(&pir[i], 0);
334 if (pir_val)
335 *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
336 }
337}
338EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
339
11f5cc05 340static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
97222cc8 341{
11f5cc05 342 apic_set_vector(vec, apic->regs + APIC_IRR);
f210f757
NA		 343 /*
344 * irr_pending must be true if any interrupt is pending; set it after
345 * APIC_IRR to avoid race with apic_clear_irr
346 */
347 apic->irr_pending = true;
97222cc8
ED		 348}
349
33e4c686 350static inline int apic_search_irr(struct kvm_lapic *apic)
97222cc8 351{
33e4c686 352 return find_highest_vector(apic->regs + APIC_IRR);
97222cc8
ED		 353}
354
355static inline int apic_find_highest_irr(struct kvm_lapic *apic)
356{
357 int result;
358
c7c9c56c
YZ		 359 /*
360 * Note that irr_pending is just a hint. It will be always
361 * true with virtual interrupt delivery enabled.
362 */
33e4c686
GN		 363 if (!apic->irr_pending)
364 return -1;
365
5a71785d 366 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
33e4c686 367 result = apic_search_irr(apic);
97222cc8
ED		 368 ASSERT(result == -1 || result >= 16);
369
370 return result;
371}
372
33e4c686
GN		 373static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
374{
56cc2406
WL		 375 struct kvm_vcpu *vcpu;
376
377 vcpu = apic->vcpu;
378
f210f757 379 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
56cc2406 380 /* try to update RVI */
f210f757 381 apic_clear_vector(vec, apic->regs + APIC_IRR);
56cc2406 382 kvm_make_request(KVM_REQ_EVENT, vcpu);
f210f757
NA		 383 } else {
384 apic->irr_pending = false;
385 apic_clear_vector(vec, apic->regs + APIC_IRR);
386 if (apic_search_irr(apic) != -1)
387 apic->irr_pending = true;
56cc2406 388 }
33e4c686
GN		 389}
390
8680b94b
MT		 391static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
392{
56cc2406
WL		 393 struct kvm_vcpu *vcpu;
394
395 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
396 return;
397
398 vcpu = apic->vcpu;
fc57ac2c 399
8680b94b 400 /*
56cc2406
WL		 401 * With APIC virtualization enabled, all caching is disabled
402 * because the processor can modify ISR under the hood. Instead
403 * just set SVI.
8680b94b 404 */
b4eef9b3 405 if (unlikely(kvm_x86_ops->hwapic_isr_update))
56cc2406
WL		 406 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
407 else {
408 ++apic->isr_count;
409 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
410 /*
411 * ISR (in service register) bit is set when injecting an interrupt.
412 * The highest vector is injected. Thus the latest bit set matches
413 * the highest bit in ISR.
414 */
415 apic->highest_isr_cache = vec;
416 }
8680b94b
MT		 417}
418
fc57ac2c
PB		 419static inline int apic_find_highest_isr(struct kvm_lapic *apic)
420{
421 int result;
422
423 /*
424 * Note that isr_count is always 1, and highest_isr_cache
425 * is always -1, with APIC virtualization enabled.
426 */
427 if (!apic->isr_count)
428 return -1;
429 if (likely(apic->highest_isr_cache != -1))
430 return apic->highest_isr_cache;
431
432 result = find_highest_vector(apic->regs + APIC_ISR);
433 ASSERT(result == -1 || result >= 16);
434
435 return result;
436}
437
8680b94b
MT		 438static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
439{
fc57ac2c
PB		 440 struct kvm_vcpu *vcpu;
441 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
442 return;
443
444 vcpu = apic->vcpu;
445
446 /*
447 * We do get here for APIC virtualization enabled if the guest
448 * uses the Hyper-V APIC enlightenment. In this case we may need
449 * to trigger a new interrupt delivery by writing the SVI field;
450 * on the other hand isr_count and highest_isr_cache are unused
451 * and must be left alone.
452 */
b4eef9b3 453 if (unlikely(kvm_x86_ops->hwapic_isr_update))
fc57ac2c
PB		 454 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
455 apic_find_highest_isr(apic));
456 else {
8680b94b 457 --apic->isr_count;
fc57ac2c
PB		 458 BUG_ON(apic->isr_count < 0);
459 apic->highest_isr_cache = -1;
460 }
8680b94b
MT		 461}
462
6e5d865c
YS		 463int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
464{
6e5d865c
YS		 465 int highest_irr;
466
33e4c686
GN		 467 /* This may race with setting of irr in __apic_accept_irq() and
468 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
469 * will cause vmexit immediately and the value will be recalculated
470 * on the next vmentry.
471 */
c48f1496 472 if (!kvm_vcpu_has_lapic(vcpu))
6e5d865c 473 return 0;
54e9818f 474 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
6e5d865c
YS		 475
476 return highest_irr;
477}
6e5d865c 478
6da7e3f6 479static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c
YZ		 480 int vector, int level, int trig_mode,
481 unsigned long *dest_map);
6da7e3f6 482
b4f2225c
YZ		 483int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
484 unsigned long *dest_map)
97222cc8 485{
ad312c7c 486 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 487
58c2dde1 488 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
b4f2225c 489 irq->level, irq->trig_mode, dest_map);
97222cc8
ED		 490}
491
ae7a2a3f
MT		 492static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
493{
494
495 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
496 sizeof(val));
497}
498
499static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
500{
501
502 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
503 sizeof(*val));
504}
505
506static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
507{
508 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
509}
510
511static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
512{
513 u8 val;
514 if (pv_eoi_get_user(vcpu, &val) < 0)
515 apic_debug("Can't read EOI MSR value: 0x%llx\n",
96893977 516 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 517 return val & 0x1;
518}
519
520static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
521{
522 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
523 apic_debug("Can't set EOI MSR value: 0x%llx\n",
96893977 524 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 525 return;
526 }
527 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
528}
529
530static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
531{
532 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
533 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
96893977 534 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 535 return;
536 }
537 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
538}
539
cf9e65b7
YZ		 540void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
541{
542 struct kvm_lapic *apic = vcpu->arch.apic;
543 int i;
544
545 for (i = 0; i < 8; i++)
546 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
547}
548
97222cc8
ED		 549static void apic_update_ppr(struct kvm_lapic *apic)
550{
3842d135 551 u32 tpr, isrv, ppr, old_ppr;
97222cc8
ED		 552 int isr;
553
c48f1496
GN		 554 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
555 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
97222cc8
ED		 556 isr = apic_find_highest_isr(apic);
557 isrv = (isr != -1) ? isr : 0;
558
559 if ((tpr & 0xf0) >= (isrv & 0xf0))
560 ppr = tpr & 0xff;
561 else
562 ppr = isrv & 0xf0;
563
564 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
565 apic, ppr, isr, isrv);
566
3842d135
AK		 567 if (old_ppr != ppr) {
568 apic_set_reg(apic, APIC_PROCPRI, ppr);
83bcacb1
AK		 569 if (ppr < old_ppr)
570 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
3842d135 571 }
97222cc8
ED		 572}
573
574static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
575{
576 apic_set_reg(apic, APIC_TASKPRI, tpr);
577 apic_update_ppr(apic);
578}
579
394457a9
NA		 580static int kvm_apic_broadcast(struct kvm_lapic *apic, u32 dest)
581{
582 return dest == (apic_x2apic_mode(apic) ?
583 X2APIC_BROADCAST : APIC_BROADCAST);
584}
585
586int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest)
97222cc8 587{
394457a9 588 return kvm_apic_id(apic) == dest || kvm_apic_broadcast(apic, dest);
97222cc8
ED		 589}
590
394457a9 591int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8
ED		 592{
593 int result = 0;
0105d1a5
GN		 594 u32 logical_id;
595
394457a9
NA		 596 if (kvm_apic_broadcast(apic, mda))
597 return 1;
598
0105d1a5 599 if (apic_x2apic_mode(apic)) {
c48f1496 600 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
0105d1a5
GN		 601 return logical_id & mda;
602 }
97222cc8 603
c48f1496 604 logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
97222cc8 605
c48f1496 606 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
97222cc8
ED		 607 case APIC_DFR_FLAT:
608 if (logical_id & mda)
609 result = 1;
610 break;
611 case APIC_DFR_CLUSTER:
612 if (((logical_id >> 4) == (mda >> 0x4))
613 && (logical_id & mda & 0xf))
614 result = 1;
615 break;
616 default:
7712de87 617 apic_debug("Bad DFR vcpu %d: %08x\n",
c48f1496 618 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
97222cc8
ED		 619 break;
620 }
621
622 return result;
623}
624
343f94fe 625int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
394457a9 626 int short_hand, unsigned int dest, int dest_mode)
97222cc8
ED		 627{
628 int result = 0;
ad312c7c 629 struct kvm_lapic *target = vcpu->arch.apic;
97222cc8
ED		 630
631 apic_debug("target %p, source %p, dest 0x%x, "
343f94fe 632 "dest_mode 0x%x, short_hand 0x%x\n",
97222cc8
ED		 633 target, source, dest, dest_mode, short_hand);
634
bd371396 635 ASSERT(target);
97222cc8
ED		 636 switch (short_hand) {
637 case APIC_DEST_NOSHORT:
343f94fe 638 if (dest_mode == 0)
97222cc8 639 /* Physical mode. */
343f94fe
GN		 640 result = kvm_apic_match_physical_addr(target, dest);
641 else
97222cc8
ED		 642 /* Logical mode. */
643 result = kvm_apic_match_logical_addr(target, dest);
644 break;
645 case APIC_DEST_SELF:
343f94fe 646 result = (target == source);
97222cc8
ED		 647 break;
648 case APIC_DEST_ALLINC:
649 result = 1;
650 break;
651 case APIC_DEST_ALLBUT:
343f94fe 652 result = (target != source);
97222cc8
ED		 653 break;
654 default:
7712de87
JK		 655 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
656 short_hand);
97222cc8
ED		 657 break;
658 }
659
660 return result;
661}
662
1e08ec4a 663bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
b4f2225c 664 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
1e08ec4a
GN		 665{
666 struct kvm_apic_map *map;
667 unsigned long bitmap = 1;
668 struct kvm_lapic **dst;
669 int i;
670 bool ret = false;
671
672 *r = -1;
673
674 if (irq->shorthand == APIC_DEST_SELF) {
b4f2225c 675 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
1e08ec4a
GN		 676 return true;
677 }
678
679 if (irq->shorthand)
680 return false;
681
682 rcu_read_lock();
683 map = rcu_dereference(kvm->arch.apic_map);
684
685 if (!map)
686 goto out;
687
394457a9
NA		 688 if (irq->dest_id == map->broadcast)
689 goto out;
690
698f9755
RK		 691 ret = true;
692
1e08ec4a 693 if (irq->dest_mode == 0) { /* physical mode */
fa834e91
RK		 694 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
695 goto out;
696
697 dst = &map->phys_map[irq->dest_id];
1e08ec4a
GN		 698 } else {
699 u32 mda = irq->dest_id << (32 - map->ldr_bits);
45c3094a
RK		 700 u16 cid = apic_cluster_id(map, mda);
701
702 if (cid >= ARRAY_SIZE(map->logical_map))
703 goto out;
1e08ec4a 704
45c3094a 705 dst = map->logical_map[cid];
1e08ec4a
GN		 706
707 bitmap = apic_logical_id(map, mda);
708
709 if (irq->delivery_mode == APIC_DM_LOWEST) {
710 int l = -1;
711 for_each_set_bit(i, &bitmap, 16) {
712 if (!dst[i])
713 continue;
714 if (l < 0)
715 l = i;
716 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
717 l = i;
718 }
719
720 bitmap = (l >= 0) ? 1 << l : 0;
721 }
722 }
723
724 for_each_set_bit(i, &bitmap, 16) {
725 if (!dst[i])
726 continue;
727 if (*r < 0)
728 *r = 0;
b4f2225c 729 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
1e08ec4a 730 }
1e08ec4a
GN		 731out:
732 rcu_read_unlock();
733 return ret;
734}
735
97222cc8
ED		 736/*
737 * Add a pending IRQ into lapic.
738 * Return 1 if successfully added and 0 if discarded.
739 */
740static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c
YZ		 741 int vector, int level, int trig_mode,
742 unsigned long *dest_map)
97222cc8 743{
6da7e3f6 744 int result = 0;
c5ec1534 745 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8 746
a183b638
PB		 747 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
748 trig_mode, vector);
97222cc8 749 switch (delivery_mode) {
97222cc8 750 case APIC_DM_LOWEST:
e1035715
GN		 751 vcpu->arch.apic_arb_prio++;
752 case APIC_DM_FIXED:
97222cc8
ED		 753 /* FIXME add logic for vcpu on reset */
754 if (unlikely(!apic_enabled(apic)))
755 break;
756
11f5cc05
JK		 757 result = 1;
758
b4f2225c
YZ		 759 if (dest_map)
760 __set_bit(vcpu->vcpu_id, dest_map);
a5d36f82 761
11f5cc05 762 if (kvm_x86_ops->deliver_posted_interrupt)
5a71785d 763 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
11f5cc05
JK		 764 else {
765 apic_set_irr(vector, apic);
5a71785d
YZ		 766
767 kvm_make_request(KVM_REQ_EVENT, vcpu);
768 kvm_vcpu_kick(vcpu);
769 }
97222cc8
ED		 770 break;
771
772 case APIC_DM_REMRD:
24d2166b
R		 773 result = 1;
774 vcpu->arch.pv.pv_unhalted = 1;
775 kvm_make_request(KVM_REQ_EVENT, vcpu);
776 kvm_vcpu_kick(vcpu);
97222cc8
ED		 777 break;
778
779 case APIC_DM_SMI:
7712de87 780 apic_debug("Ignoring guest SMI\n");
97222cc8 781 break;
3419ffc8 782
97222cc8 783 case APIC_DM_NMI:
6da7e3f6 784 result = 1;
3419ffc8 785 kvm_inject_nmi(vcpu);
26df99c6 786 kvm_vcpu_kick(vcpu);
97222cc8
ED		 787 break;
788
789 case APIC_DM_INIT:
a52315e1 790 if (!trig_mode || level) {
6da7e3f6 791 result = 1;
66450a21
JK		 792 /* assumes that there are only KVM_APIC_INIT/SIPI */
793 apic->pending_events = (1UL << KVM_APIC_INIT);
794 /* make sure pending_events is visible before sending
795 * the request */
796 smp_wmb();
3842d135 797 kvm_make_request(KVM_REQ_EVENT, vcpu);
c5ec1534
HQ		 798 kvm_vcpu_kick(vcpu);
799 } else {
1b10bf31
JK		 800 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
801 vcpu->vcpu_id);
c5ec1534 802 }
97222cc8
ED		 803 break;
804
805 case APIC_DM_STARTUP:
1b10bf31
JK		 806 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
807 vcpu->vcpu_id, vector);
66450a21
JK		 808 result = 1;
809 apic->sipi_vector = vector;
810 /* make sure sipi_vector is visible for the receiver */
811 smp_wmb();
812 set_bit(KVM_APIC_SIPI, &apic->pending_events);
813 kvm_make_request(KVM_REQ_EVENT, vcpu);
814 kvm_vcpu_kick(vcpu);
97222cc8
ED		 815 break;
816
23930f95
JK		 817 case APIC_DM_EXTINT:
818 /*
819 * Should only be called by kvm_apic_local_deliver() with LVT0,
820 * before NMI watchdog was enabled. Already handled by
821 * kvm_apic_accept_pic_intr().
822 */
823 break;
824
97222cc8
ED		 825 default:
826 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
827 delivery_mode);
828 break;
829 }
830 return result;
831}
832
e1035715 833int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
8be5453f 834{
e1035715 835 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
8be5453f
ZX		 836}
837
c7c9c56c
YZ		 838static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
839{
840 if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
841 kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
842 int trigger_mode;
843 if (apic_test_vector(vector, apic->regs + APIC_TMR))
844 trigger_mode = IOAPIC_LEVEL_TRIG;
845 else
846 trigger_mode = IOAPIC_EDGE_TRIG;
1fcc7890 847 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
c7c9c56c
YZ		 848 }
849}
850
ae7a2a3f 851static int apic_set_eoi(struct kvm_lapic *apic)
97222cc8
ED		 852{
853 int vector = apic_find_highest_isr(apic);
ae7a2a3f
MT		 854
855 trace_kvm_eoi(apic, vector);
856
97222cc8
ED		 857 /*
858 * Not every write EOI will has corresponding ISR,
859 * one example is when Kernel check timer on setup_IO_APIC
860 */
861 if (vector == -1)
ae7a2a3f 862 return vector;
97222cc8 863
8680b94b 864 apic_clear_isr(vector, apic);
97222cc8
ED		 865 apic_update_ppr(apic);
866
c7c9c56c 867 kvm_ioapic_send_eoi(apic, vector);
3842d135 868 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
ae7a2a3f 869 return vector;
97222cc8
ED		 870}
871
c7c9c56c
YZ		 872/*
873 * this interface assumes a trap-like exit, which has already finished
874 * desired side effect including vISR and vPPR update.
875 */
876void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
877{
878 struct kvm_lapic *apic = vcpu->arch.apic;
879
880 trace_kvm_eoi(apic, vector);
881
882 kvm_ioapic_send_eoi(apic, vector);
883 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
884}
885EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
886
97222cc8
ED		 887static void apic_send_ipi(struct kvm_lapic *apic)
888{
c48f1496
GN		 889 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
890 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
58c2dde1 891 struct kvm_lapic_irq irq;
97222cc8 892
58c2dde1
GN		 893 irq.vector = icr_low & APIC_VECTOR_MASK;
894 irq.delivery_mode = icr_low & APIC_MODE_MASK;
895 irq.dest_mode = icr_low & APIC_DEST_MASK;
896 irq.level = icr_low & APIC_INT_ASSERT;
897 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
898 irq.shorthand = icr_low & APIC_SHORT_MASK;
0105d1a5
GN		 899 if (apic_x2apic_mode(apic))
900 irq.dest_id = icr_high;
901 else
902 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
97222cc8 903
1000ff8d
GN		 904 trace_kvm_apic_ipi(icr_low, irq.dest_id);
905
97222cc8
ED		 906 apic_debug("icr_high 0x%x, icr_low 0x%x, "
907 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
908 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
9b5843dd 909 icr_high, icr_low, irq.shorthand, irq.dest_id,
58c2dde1
GN		 910 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
911 irq.vector);
912
b4f2225c 913 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
97222cc8
ED		 914}
915
916static u32 apic_get_tmcct(struct kvm_lapic *apic)
917{
b682b814
MT		 918 ktime_t remaining;
919 s64 ns;
9da8f4e8 920 u32 tmcct;
97222cc8
ED		 921
922 ASSERT(apic != NULL);
923
9da8f4e8 924 /* if initial count is 0, current count should also be 0 */
b963a22e
AH		 925 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
926 apic->lapic_timer.period == 0)
9da8f4e8
KP		 927 return 0;
928
ace15464 929 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
b682b814
MT		 930 if (ktime_to_ns(remaining) < 0)
931 remaining = ktime_set(0, 0);
932
d3c7b77d
MT		 933 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
934 tmcct = div64_u64(ns,
935 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 936
937 return tmcct;
938}
939
b209749f
AK		 940static void __report_tpr_access(struct kvm_lapic *apic, bool write)
941{
942 struct kvm_vcpu *vcpu = apic->vcpu;
943 struct kvm_run *run = vcpu->run;
944
a8eeb04a 945 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
5fdbf976 946 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 947 run->tpr_access.is_write = write;
948}
949
950static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
951{
952 if (apic->vcpu->arch.tpr_access_reporting)
953 __report_tpr_access(apic, write);
954}
955
97222cc8
ED		 956static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
957{
958 u32 val = 0;
959
960 if (offset >= LAPIC_MMIO_LENGTH)
961 return 0;
962
963 switch (offset) {
0105d1a5
GN		 964 case APIC_ID:
965 if (apic_x2apic_mode(apic))
966 val = kvm_apic_id(apic);
967 else
968 val = kvm_apic_id(apic) << 24;
969 break;
97222cc8 970 case APIC_ARBPRI:
7712de87 971 apic_debug("Access APIC ARBPRI register which is for P6\n");
97222cc8
ED		 972 break;
973
974 case APIC_TMCCT: /* Timer CCR */
a3e06bbe
LJ		 975 if (apic_lvtt_tscdeadline(apic))
976 return 0;
977
97222cc8
ED		 978 val = apic_get_tmcct(apic);
979 break;
4a4541a4
AK		 980 case APIC_PROCPRI:
981 apic_update_ppr(apic);
c48f1496 982 val = kvm_apic_get_reg(apic, offset);
4a4541a4 983 break;
b209749f
AK		 984 case APIC_TASKPRI:
985 report_tpr_access(apic, false);
986 /* fall thru */
97222cc8 987 default:
c48f1496 988 val = kvm_apic_get_reg(apic, offset);
97222cc8
ED		 989 break;
990 }
991
992 return val;
993}
994
d76685c4
GH		 995static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
996{
997 return container_of(dev, struct kvm_lapic, dev);
998}
999
0105d1a5
GN		 1000static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1001 void *data)
97222cc8 1002{
97222cc8
ED		 1003 unsigned char alignment = offset & 0xf;
1004 u32 result;
d5b0b5b1 1005 /* this bitmask has a bit cleared for each reserved register */
0105d1a5 1006 static const u64 rmask = 0x43ff01ffffffe70cULL;
97222cc8
ED		 1007
1008 if ((alignment + len) > 4) {
4088bb3c
GN		 1009 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1010 offset, len);
0105d1a5 1011 return 1;
97222cc8 1012 }
0105d1a5
GN		 1013
1014 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
4088bb3c
GN		 1015 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1016 offset);
0105d1a5
GN		 1017 return 1;
1018 }
1019
97222cc8
ED		 1020 result = __apic_read(apic, offset & ~0xf);
1021
229456fc
MT		 1022 trace_kvm_apic_read(offset, result);
1023
97222cc8
ED		 1024 switch (len) {
1025 case 1:
1026 case 2:
1027 case 4:
1028 memcpy(data, (char *)&result + alignment, len);
1029 break;
1030 default:
1031 printk(KERN_ERR "Local APIC read with len = %x, "
1032 "should be 1,2, or 4 instead\n", len);
1033 break;
1034 }
bda9020e 1035 return 0;
97222cc8
ED		 1036}
1037
0105d1a5
GN		 1038static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1039{
c48f1496 1040 return kvm_apic_hw_enabled(apic) &&
0105d1a5
GN		 1041 addr >= apic->base_address &&
1042 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1043}
1044
1045static int apic_mmio_read(struct kvm_io_device *this,
1046 gpa_t address, int len, void *data)
1047{
1048 struct kvm_lapic *apic = to_lapic(this);
1049 u32 offset = address - apic->base_address;
1050
1051 if (!apic_mmio_in_range(apic, address))
1052 return -EOPNOTSUPP;
1053
1054 apic_reg_read(apic, offset, len, data);
1055
1056 return 0;
1057}
1058
97222cc8
ED		 1059static void update_divide_count(struct kvm_lapic *apic)
1060{
1061 u32 tmp1, tmp2, tdcr;
1062
c48f1496 1063 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
97222cc8
ED		 1064 tmp1 = tdcr & 0xf;
1065 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 1066 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 1067
1068 apic_debug("timer divide count is 0x%x\n",
9b5843dd 1069 apic->divide_count);
97222cc8
ED		 1070}
1071
5d87db71
RK		 1072static void apic_timer_expired(struct kvm_lapic *apic)
1073{
1074 struct kvm_vcpu *vcpu = apic->vcpu;
1075 wait_queue_head_t *q = &vcpu->wq;
1076
1077 /*
1078 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1079 * vcpu_enter_guest.
1080 */
1081 if (atomic_read(&apic->lapic_timer.pending))
1082 return;
1083
1084 atomic_inc(&apic->lapic_timer.pending);
1085 /* FIXME: this code should not know anything about vcpus */
1086 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1087
1088 if (waitqueue_active(q))
1089 wake_up_interruptible(q);
1090}
1091
97222cc8
ED		 1092static void start_apic_timer(struct kvm_lapic *apic)
1093{
a3e06bbe 1094 ktime_t now;
d3c7b77d 1095 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 1096
a3e06bbe 1097 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
d5b0b5b1 1098 /* lapic timer in oneshot or periodic mode */
a3e06bbe 1099 now = apic->lapic_timer.timer.base->get_time();
c48f1496 1100 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
a3e06bbe
LJ		 1101 * APIC_BUS_CYCLE_NS * apic->divide_count;
1102
1103 if (!apic->lapic_timer.period)
1104 return;
1105 /*
1106 * Do not allow the guest to program periodic timers with small
1107 * interval, since the hrtimers are not throttled by the host
1108 * scheduler.
1109 */
1110 if (apic_lvtt_period(apic)) {
1111 s64 min_period = min_timer_period_us * 1000LL;
1112
1113 if (apic->lapic_timer.period < min_period) {
1114 pr_info_ratelimited(
1115 "kvm: vcpu %i: requested %lld ns "
1116 "lapic timer period limited to %lld ns\n",
1117 apic->vcpu->vcpu_id,
1118 apic->lapic_timer.period, min_period);
1119 apic->lapic_timer.period = min_period;
1120 }
9bc5791d 1121 }
0b975a3c 1122
a3e06bbe
LJ		 1123 hrtimer_start(&apic->lapic_timer.timer,
1124 ktime_add_ns(now, apic->lapic_timer.period),
1125 HRTIMER_MODE_ABS);
97222cc8 1126
a3e06bbe 1127 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
97222cc8
ED		 1128 PRIx64 ", "
1129 "timer initial count 0x%x, period %lldns, "
b8688d51 1130 "expire @ 0x%016" PRIx64 ".\n", __func__,
97222cc8 1131 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
c48f1496 1132 kvm_apic_get_reg(apic, APIC_TMICT),
d3c7b77d 1133 apic->lapic_timer.period,
97222cc8 1134 ktime_to_ns(ktime_add_ns(now,
d3c7b77d 1135 apic->lapic_timer.period)));
a3e06bbe
LJ		 1136 } else if (apic_lvtt_tscdeadline(apic)) {
1137 /* lapic timer in tsc deadline mode */
1138 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1139 u64 ns = 0;
1140 struct kvm_vcpu *vcpu = apic->vcpu;
cc578287 1141 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
a3e06bbe
LJ		 1142 unsigned long flags;
1143
1144 if (unlikely(!tscdeadline || !this_tsc_khz))
1145 return;
1146
1147 local_irq_save(flags);
1148
1149 now = apic->lapic_timer.timer.base->get_time();
886b470c 1150 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
a3e06bbe
LJ		 1151 if (likely(tscdeadline > guest_tsc)) {
1152 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1153 do_div(ns, this_tsc_khz);
1e0ad70c
RK		 1154 hrtimer_start(&apic->lapic_timer.timer,
1155 ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
1156 } else
1157 apic_timer_expired(apic);
a3e06bbe
LJ		 1158
1159 local_irq_restore(flags);
1160 }
97222cc8
ED		 1161}
1162
cc6e462c
JK		 1163static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1164{
c48f1496 1165 int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
cc6e462c
JK		 1166
1167 if (apic_lvt_nmi_mode(lvt0_val)) {
1168 if (!nmi_wd_enabled) {
1169 apic_debug("Receive NMI setting on APIC_LVT0 "
1170 "for cpu %d\n", apic->vcpu->vcpu_id);
1171 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1172 }
1173 } else if (nmi_wd_enabled)
1174 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1175}
1176
0105d1a5 1177static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
97222cc8 1178{
0105d1a5 1179 int ret = 0;
97222cc8 1180
0105d1a5 1181 trace_kvm_apic_write(reg, val);
97222cc8 1182
0105d1a5 1183 switch (reg) {
97222cc8 1184 case APIC_ID: /* Local APIC ID */
0105d1a5 1185 if (!apic_x2apic_mode(apic))
1e08ec4a 1186 kvm_apic_set_id(apic, val >> 24);
0105d1a5
GN		 1187 else
1188 ret = 1;
97222cc8
ED		 1189 break;
1190
1191 case APIC_TASKPRI:
b209749f 1192 report_tpr_access(apic, true);
97222cc8
ED		 1193 apic_set_tpr(apic, val & 0xff);
1194 break;
1195
1196 case APIC_EOI:
1197 apic_set_eoi(apic);
1198 break;
1199
1200 case APIC_LDR:
0105d1a5 1201 if (!apic_x2apic_mode(apic))
1e08ec4a 1202 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
0105d1a5
GN		 1203 else
1204 ret = 1;
97222cc8
ED		 1205 break;
1206
1207 case APIC_DFR:
1e08ec4a 1208 if (!apic_x2apic_mode(apic)) {
0105d1a5 1209 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1e08ec4a
GN		 1210 recalculate_apic_map(apic->vcpu->kvm);
1211 } else
0105d1a5 1212 ret = 1;
97222cc8
ED		 1213 break;
1214
fc61b800
GN		 1215 case APIC_SPIV: {
1216 u32 mask = 0x3ff;
c48f1496 1217 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
fc61b800 1218 mask |= APIC_SPIV_DIRECTED_EOI;
f8c1ea10 1219 apic_set_spiv(apic, val & mask);
97222cc8
ED		 1220 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1221 int i;
1222 u32 lvt_val;
1223
1224 for (i = 0; i < APIC_LVT_NUM; i++) {
c48f1496 1225 lvt_val = kvm_apic_get_reg(apic,
97222cc8
ED		 1226 APIC_LVTT + 0x10 * i);
1227 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1228 lvt_val | APIC_LVT_MASKED);
1229 }
d3c7b77d 1230 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 1231
1232 }
1233 break;
fc61b800 1234 }
97222cc8
ED		 1235 case APIC_ICR:
1236 /* No delay here, so we always clear the pending bit */
1237 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1238 apic_send_ipi(apic);
1239 break;
1240
1241 case APIC_ICR2:
0105d1a5
GN		 1242 if (!apic_x2apic_mode(apic))
1243 val &= 0xff000000;
1244 apic_set_reg(apic, APIC_ICR2, val);
97222cc8
ED		 1245 break;
1246
23930f95 1247 case APIC_LVT0:
cc6e462c 1248 apic_manage_nmi_watchdog(apic, val);
97222cc8
ED		 1249 case APIC_LVTTHMR:
1250 case APIC_LVTPC:
97222cc8
ED		 1251 case APIC_LVT1:
1252 case APIC_LVTERR:
1253 /* TODO: Check vector */
c48f1496 1254 if (!kvm_apic_sw_enabled(apic))
97222cc8
ED		 1255 val |= APIC_LVT_MASKED;
1256
0105d1a5
GN		 1257 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1258 apic_set_reg(apic, reg, val);
97222cc8
ED		 1259
1260 break;
1261
a323b409
RK		 1262 case APIC_LVTT: {
1263 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1264
1265 if (apic->lapic_timer.timer_mode != timer_mode) {
1266 apic->lapic_timer.timer_mode = timer_mode;
a3e06bbe 1267 hrtimer_cancel(&apic->lapic_timer.timer);
a323b409 1268 }
a3e06bbe 1269
c48f1496 1270 if (!kvm_apic_sw_enabled(apic))
a3e06bbe
LJ		 1271 val |= APIC_LVT_MASKED;
1272 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1273 apic_set_reg(apic, APIC_LVTT, val);
1274 break;
a323b409 1275 }
a3e06bbe 1276
97222cc8 1277 case APIC_TMICT:
a3e06bbe
LJ		 1278 if (apic_lvtt_tscdeadline(apic))
1279 break;
1280
d3c7b77d 1281 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 1282 apic_set_reg(apic, APIC_TMICT, val);
1283 start_apic_timer(apic);
0105d1a5 1284 break;
97222cc8
ED		 1285
1286 case APIC_TDCR:
1287 if (val & 4)
7712de87 1288 apic_debug("KVM_WRITE:TDCR %x\n", val);
97222cc8
ED		 1289 apic_set_reg(apic, APIC_TDCR, val);
1290 update_divide_count(apic);
1291 break;
1292
0105d1a5
GN		 1293 case APIC_ESR:
1294 if (apic_x2apic_mode(apic) && val != 0) {
7712de87 1295 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
0105d1a5
GN		 1296 ret = 1;
1297 }
1298 break;
1299
1300 case APIC_SELF_IPI:
1301 if (apic_x2apic_mode(apic)) {
1302 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1303 } else
1304 ret = 1;
1305 break;
97222cc8 1306 default:
0105d1a5 1307 ret = 1;
97222cc8
ED		 1308 break;
1309 }
0105d1a5
GN		 1310 if (ret)
1311 apic_debug("Local APIC Write to read-only register %x\n", reg);
1312 return ret;
1313}
1314
1315static int apic_mmio_write(struct kvm_io_device *this,
1316 gpa_t address, int len, const void *data)
1317{
1318 struct kvm_lapic *apic = to_lapic(this);
1319 unsigned int offset = address - apic->base_address;
1320 u32 val;
1321
1322 if (!apic_mmio_in_range(apic, address))
1323 return -EOPNOTSUPP;
1324
1325 /*
1326 * APIC register must be aligned on 128-bits boundary.
1327 * 32/64/128 bits registers must be accessed thru 32 bits.
1328 * Refer SDM 8.4.1
1329 */
1330 if (len != 4 || (offset & 0xf)) {
1331 /* Don't shout loud, $infamous_os would cause only noise. */
1332 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
756975bb 1333 return 0;
0105d1a5
GN		 1334 }
1335
1336 val = *(u32*)data;
1337
1338 /* too common printing */
1339 if (offset != APIC_EOI)
1340 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1341 "0x%x\n", __func__, offset, len, val);
1342
1343 apic_reg_write(apic, offset & 0xff0, val);
1344
bda9020e 1345 return 0;
97222cc8
ED		 1346}
1347
58fbbf26
KT		 1348void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1349{
c48f1496 1350 if (kvm_vcpu_has_lapic(vcpu))
58fbbf26
KT		 1351 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1352}
1353EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1354
83d4c286
YZ		 1355/* emulate APIC access in a trap manner */
1356void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1357{
1358 u32 val = 0;
1359
1360 /* hw has done the conditional check and inst decode */
1361 offset &= 0xff0;
1362
1363 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1364
1365 /* TODO: optimize to just emulate side effect w/o one more write */
1366 apic_reg_write(vcpu->arch.apic, offset, val);
1367}
1368EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1369
d589444e 1370void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 1371{
f8c1ea10
GN		 1372 struct kvm_lapic *apic = vcpu->arch.apic;
1373
ad312c7c 1374 if (!vcpu->arch.apic)
97222cc8
ED		 1375 return;
1376
f8c1ea10 1377 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1378
c5cc421b
GN		 1379 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1380 static_key_slow_dec_deferred(&apic_hw_disabled);
1381
e462755c 1382 if (!apic->sw_enabled)
f8c1ea10 1383 static_key_slow_dec_deferred(&apic_sw_disabled);
97222cc8 1384
f8c1ea10
GN		 1385 if (apic->regs)
1386 free_page((unsigned long)apic->regs);
1387
1388 kfree(apic);
97222cc8
ED		 1389}
1390
1391/*
1392 *----------------------------------------------------------------------
1393 * LAPIC interface
1394 *----------------------------------------------------------------------
1395 */
1396
a3e06bbe
LJ		 1397u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1398{
1399 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1400
c48f1496 1401 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1402 apic_lvtt_period(apic))
a3e06bbe
LJ		 1403 return 0;
1404
1405 return apic->lapic_timer.tscdeadline;
1406}
1407
1408void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1409{
1410 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1411
c48f1496 1412 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1413 apic_lvtt_period(apic))
a3e06bbe
LJ		 1414 return;
1415
1416 hrtimer_cancel(&apic->lapic_timer.timer);
1417 apic->lapic_timer.tscdeadline = data;
1418 start_apic_timer(apic);
1419}
1420
97222cc8
ED		 1421void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1422{
ad312c7c 1423 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8 1424
c48f1496 1425 if (!kvm_vcpu_has_lapic(vcpu))
97222cc8 1426 return;
54e9818f 1427
b93463aa 1428 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
c48f1496 1429 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8
ED		 1430}
1431
1432u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1433{
97222cc8
ED		 1434 u64 tpr;
1435
c48f1496 1436 if (!kvm_vcpu_has_lapic(vcpu))
97222cc8 1437 return 0;
54e9818f 1438
c48f1496 1439 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
97222cc8
ED		 1440
1441 return (tpr & 0xf0) >> 4;
1442}
1443
1444void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1445{
8d14695f 1446 u64 old_value = vcpu->arch.apic_base;
ad312c7c 1447 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1448
1449 if (!apic) {
1450 value |= MSR_IA32_APICBASE_BSP;
ad312c7c 1451 vcpu->arch.apic_base = value;
97222cc8
ED		 1452 return;
1453 }
c5af89b6 1454
e66d2ae7
JK		 1455 if (!kvm_vcpu_is_bsp(apic->vcpu))
1456 value &= ~MSR_IA32_APICBASE_BSP;
1457 vcpu->arch.apic_base = value;
1458
c5cc421b 1459 /* update jump label if enable bit changes */
0dce7cd6 1460 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
c5cc421b
GN		 1461 if (value & MSR_IA32_APICBASE_ENABLE)
1462 static_key_slow_dec_deferred(&apic_hw_disabled);
1463 else
1464 static_key_slow_inc(&apic_hw_disabled.key);
1e08ec4a 1465 recalculate_apic_map(vcpu->kvm);
c5cc421b
GN		 1466 }
1467
8d14695f
YZ		 1468 if ((old_value ^ value) & X2APIC_ENABLE) {
1469 if (value & X2APIC_ENABLE) {
1470 u32 id = kvm_apic_id(apic);
1471 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1472 kvm_apic_set_ldr(apic, ldr);
1473 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1474 } else
1475 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
0105d1a5 1476 }
8d14695f 1477
ad312c7c 1478 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 1479 MSR_IA32_APICBASE_BASE;
1480
db324fe6
NA		 1481 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1482 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1483 pr_warn_once("APIC base relocation is unsupported by KVM");
1484
97222cc8
ED		 1485 /* with FSB delivery interrupt, we can restart APIC functionality */
1486 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
ad312c7c 1487 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1488
1489}
1490
c5ec1534 1491void kvm_lapic_reset(struct kvm_vcpu *vcpu)
97222cc8
ED		 1492{
1493 struct kvm_lapic *apic;
1494 int i;
1495
b8688d51 1496 apic_debug("%s\n", __func__);
97222cc8
ED		 1497
1498 ASSERT(vcpu);
ad312c7c 1499 apic = vcpu->arch.apic;
97222cc8
ED		 1500 ASSERT(apic != NULL);
1501
1502 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 1503 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1504
1e08ec4a 1505 kvm_apic_set_id(apic, vcpu->vcpu_id);
fc61b800 1506 kvm_apic_set_version(apic->vcpu);
97222cc8
ED		 1507
1508 for (i = 0; i < APIC_LVT_NUM; i++)
1509 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
a323b409 1510 apic->lapic_timer.timer_mode = 0;
40487c68
QH		 1511 apic_set_reg(apic, APIC_LVT0,
1512 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
97222cc8
ED		 1513
1514 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
f8c1ea10 1515 apic_set_spiv(apic, 0xff);
97222cc8 1516 apic_set_reg(apic, APIC_TASKPRI, 0);
1e08ec4a 1517 kvm_apic_set_ldr(apic, 0);
97222cc8
ED		 1518 apic_set_reg(apic, APIC_ESR, 0);
1519 apic_set_reg(apic, APIC_ICR, 0);
1520 apic_set_reg(apic, APIC_ICR2, 0);
1521 apic_set_reg(apic, APIC_TDCR, 0);
1522 apic_set_reg(apic, APIC_TMICT, 0);
1523 for (i = 0; i < 8; i++) {
1524 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1525 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1526 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1527 }
c7c9c56c
YZ		 1528 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1529 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
8680b94b 1530 apic->highest_isr_cache = -1;
b33ac88b 1531 update_divide_count(apic);
d3c7b77d 1532 atomic_set(&apic->lapic_timer.pending, 0);
c5af89b6 1533 if (kvm_vcpu_is_bsp(vcpu))
5dbc8f3f
GN		 1534 kvm_lapic_set_base(vcpu,
1535 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
ae7a2a3f 1536 vcpu->arch.pv_eoi.msr_val = 0;
97222cc8
ED		 1537 apic_update_ppr(apic);
1538
e1035715 1539 vcpu->arch.apic_arb_prio = 0;
41383771 1540 vcpu->arch.apic_attention = 0;
e1035715 1541
98eff52a 1542 apic_debug("%s: vcpu=%p, id=%d, base_msr="
b8688d51 1543 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
97222cc8 1544 vcpu, kvm_apic_id(apic),
ad312c7c 1545 vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1546}
1547
97222cc8
ED		 1548/*
1549 *----------------------------------------------------------------------
1550 * timer interface
1551 *----------------------------------------------------------------------
1552 */
1b9778da 1553
2a6eac96 1554static bool lapic_is_periodic(struct kvm_lapic *apic)
97222cc8 1555{
d3c7b77d 1556 return apic_lvtt_period(apic);
97222cc8
ED		 1557}
1558
3d80840d
MT		 1559int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1560{
54e9818f 1561 struct kvm_lapic *apic = vcpu->arch.apic;
3d80840d 1562
c48f1496 1563 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
54e9818f
GN		 1564 apic_lvt_enabled(apic, APIC_LVTT))
1565 return atomic_read(&apic->lapic_timer.pending);
3d80840d
MT		 1566
1567 return 0;
1568}
1569
89342082 1570int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 1571{
c48f1496 1572 u32 reg = kvm_apic_get_reg(apic, lvt_type);
23930f95 1573 int vector, mode, trig_mode;
23930f95 1574
c48f1496 1575 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 1576 vector = reg & APIC_VECTOR_MASK;
1577 mode = reg & APIC_MODE_MASK;
1578 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
b4f2225c
YZ		 1579 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1580 NULL);
23930f95
JK		 1581 }
1582 return 0;
1583}
1b9778da 1584
8fdb2351 1585void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 1586{
8fdb2351
JK		 1587 struct kvm_lapic *apic = vcpu->arch.apic;
1588
1589 if (apic)
1590 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 1591}
1592
d76685c4
GH		 1593static const struct kvm_io_device_ops apic_mmio_ops = {
1594 .read = apic_mmio_read,
1595 .write = apic_mmio_write,
d76685c4
GH		 1596};
1597
e9d90d47
AK		 1598static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1599{
1600 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2a6eac96 1601 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
e9d90d47 1602
5d87db71 1603 apic_timer_expired(apic);
e9d90d47 1604
2a6eac96 1605 if (lapic_is_periodic(apic)) {
e9d90d47
AK		 1606 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1607 return HRTIMER_RESTART;
1608 } else
1609 return HRTIMER_NORESTART;
1610}
1611
97222cc8
ED		 1612int kvm_create_lapic(struct kvm_vcpu *vcpu)
1613{
1614 struct kvm_lapic *apic;
1615
1616 ASSERT(vcpu != NULL);
1617 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1618
1619 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1620 if (!apic)
1621 goto nomem;
1622
ad312c7c 1623 vcpu->arch.apic = apic;
97222cc8 1624
afc20184
TY		 1625 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1626 if (!apic->regs) {
97222cc8
ED		 1627 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1628 vcpu->vcpu_id);
d589444e 1629 goto nomem_free_apic;
97222cc8 1630 }
97222cc8
ED		 1631 apic->vcpu = vcpu;
1632
d3c7b77d
MT		 1633 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1634 HRTIMER_MODE_ABS);
e9d90d47 1635 apic->lapic_timer.timer.function = apic_timer_fn;
d3c7b77d 1636
c5cc421b
GN		 1637 /*
1638 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1639 * thinking that APIC satet has changed.
1640 */
1641 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
6aed64a8
GN		 1642 kvm_lapic_set_base(vcpu,
1643 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
97222cc8 1644
f8c1ea10 1645 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
c5ec1534 1646 kvm_lapic_reset(vcpu);
d76685c4 1647 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
97222cc8
ED		 1648
1649 return 0;
d589444e
RR		 1650nomem_free_apic:
1651 kfree(apic);
97222cc8 1652nomem:
97222cc8
ED		 1653 return -ENOMEM;
1654}
97222cc8
ED		 1655
1656int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1657{
ad312c7c 1658 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1659 int highest_irr;
1660
c48f1496 1661 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
97222cc8
ED		 1662 return -1;
1663
6e5d865c 1664 apic_update_ppr(apic);
97222cc8
ED		 1665 highest_irr = apic_find_highest_irr(apic);
1666 if ((highest_irr == -1) ||
c48f1496 1667 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
97222cc8
ED		 1668 return -1;
1669 return highest_irr;
1670}
1671
40487c68
QH		 1672int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1673{
c48f1496 1674 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 1675 int r = 0;
1676
c48f1496 1677 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
e7dca5c0
CL		 1678 r = 1;
1679 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1680 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1681 r = 1;
40487c68
QH		 1682 return r;
1683}
1684
1b9778da
ED		 1685void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1686{
ad312c7c 1687 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 1688
c48f1496 1689 if (!kvm_vcpu_has_lapic(vcpu))
54e9818f
GN		 1690 return;
1691
1692 if (atomic_read(&apic->lapic_timer.pending) > 0) {
f1ed0450 1693 kvm_apic_local_deliver(apic, APIC_LVTT);
fae0ba21
NA		 1694 if (apic_lvtt_tscdeadline(apic))
1695 apic->lapic_timer.tscdeadline = 0;
f1ed0450 1696 atomic_set(&apic->lapic_timer.pending, 0);
1b9778da
ED		 1697 }
1698}
1699
97222cc8
ED		 1700int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1701{
1702 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 1703 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1704
1705 if (vector == -1)
1706 return -1;
1707
56cc2406
WL		 1708 /*
1709 * We get here even with APIC virtualization enabled, if doing
1710 * nested virtualization and L1 runs with the "acknowledge interrupt
1711 * on exit" mode. Then we cannot inject the interrupt via RVI,
1712 * because the process would deliver it through the IDT.
1713 */
1714
8680b94b 1715 apic_set_isr(vector, apic);
97222cc8
ED		 1716 apic_update_ppr(apic);
1717 apic_clear_irr(vector, apic);
1718 return vector;
1719}
96ad2cc6 1720
64eb0620
GN		 1721void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1722 struct kvm_lapic_state *s)
96ad2cc6 1723{
ad312c7c 1724 struct kvm_lapic *apic = vcpu->arch.apic;
96ad2cc6 1725
5dbc8f3f 1726 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
64eb0620
GN		 1727 /* set SPIV separately to get count of SW disabled APICs right */
1728 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1729 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1e08ec4a
GN		 1730 /* call kvm_apic_set_id() to put apic into apic_map */
1731 kvm_apic_set_id(apic, kvm_apic_id(apic));
fc61b800
GN		 1732 kvm_apic_set_version(vcpu);
1733
96ad2cc6 1734 apic_update_ppr(apic);
d3c7b77d 1735 hrtimer_cancel(&apic->lapic_timer.timer);
96ad2cc6
ED		 1736 update_divide_count(apic);
1737 start_apic_timer(apic);
6e24a6ef 1738 apic->irr_pending = true;
c7c9c56c
YZ		 1739 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
1740 1 : count_vectors(apic->regs + APIC_ISR);
8680b94b 1741 apic->highest_isr_cache = -1;
4114c27d
WW		 1742 if (kvm_x86_ops->hwapic_irr_update)
1743 kvm_x86_ops->hwapic_irr_update(vcpu,
1744 apic_find_highest_irr(apic));
b4eef9b3
TC		 1745 if (unlikely(kvm_x86_ops->hwapic_isr_update))
1746 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1747 apic_find_highest_isr(apic));
3842d135 1748 kvm_make_request(KVM_REQ_EVENT, vcpu);
10606919 1749 kvm_rtc_eoi_tracking_restore_one(vcpu);
96ad2cc6 1750}
a3d7f85f 1751
2f52d58c 1752void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 1753{
a3d7f85f
ED		 1754 struct hrtimer *timer;
1755
c48f1496 1756 if (!kvm_vcpu_has_lapic(vcpu))
a3d7f85f
ED		 1757 return;
1758
54e9818f 1759 timer = &vcpu->arch.apic->lapic_timer.timer;
a3d7f85f 1760 if (hrtimer_cancel(timer))
beb20d52 1761 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
a3d7f85f 1762}
b93463aa 1763
ae7a2a3f
MT		 1764/*
1765 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1766 *
1767 * Detect whether guest triggered PV EOI since the
1768 * last entry. If yes, set EOI on guests's behalf.
1769 * Clear PV EOI in guest memory in any case.
1770 */
1771static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1772 struct kvm_lapic *apic)
1773{
1774 bool pending;
1775 int vector;
1776 /*
1777 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1778 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1779 *
1780 * KVM_APIC_PV_EOI_PENDING is unset:
1781 * -> host disabled PV EOI.
1782 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1783 * -> host enabled PV EOI, guest did not execute EOI yet.
1784 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1785 * -> host enabled PV EOI, guest executed EOI.
1786 */
1787 BUG_ON(!pv_eoi_enabled(vcpu));
1788 pending = pv_eoi_get_pending(vcpu);
1789 /*
1790 * Clear pending bit in any case: it will be set again on vmentry.
1791 * While this might not be ideal from performance point of view,
1792 * this makes sure pv eoi is only enabled when we know it's safe.
1793 */
1794 pv_eoi_clr_pending(vcpu);
1795 if (pending)
1796 return;
1797 vector = apic_set_eoi(apic);
1798 trace_kvm_pv_eoi(apic, vector);
1799}
1800
b93463aa
AK		 1801void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1802{
1803 u32 data;
b93463aa 1804
ae7a2a3f
MT		 1805 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1806 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1807
41383771 1808 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 1809 return;
1810
fda4e2e8
AH		 1811 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1812 sizeof(u32));
b93463aa
AK		 1813
1814 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1815}
1816
ae7a2a3f
MT		 1817/*
1818 * apic_sync_pv_eoi_to_guest - called before vmentry
1819 *
1820 * Detect whether it's safe to enable PV EOI and
1821 * if yes do so.
1822 */
1823static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1824 struct kvm_lapic *apic)
1825{
1826 if (!pv_eoi_enabled(vcpu) ||
1827 /* IRR set or many bits in ISR: could be nested. */
1828 apic->irr_pending ||
1829 /* Cache not set: could be safe but we don't bother. */
1830 apic->highest_isr_cache == -1 ||
1831 /* Need EOI to update ioapic. */
1832 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1833 /*
1834 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1835 * so we need not do anything here.
1836 */
1837 return;
1838 }
1839
1840 pv_eoi_set_pending(apic->vcpu);
1841}
1842
b93463aa
AK		 1843void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1844{
1845 u32 data, tpr;
1846 int max_irr, max_isr;
ae7a2a3f 1847 struct kvm_lapic *apic = vcpu->arch.apic;
b93463aa 1848
ae7a2a3f
MT		 1849 apic_sync_pv_eoi_to_guest(vcpu, apic);
1850
41383771 1851 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 1852 return;
1853
c48f1496 1854 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
b93463aa
AK		 1855 max_irr = apic_find_highest_irr(apic);
1856 if (max_irr < 0)
1857 max_irr = 0;
1858 max_isr = apic_find_highest_isr(apic);
1859 if (max_isr < 0)
1860 max_isr = 0;
1861 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1862
fda4e2e8
AH		 1863 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1864 sizeof(u32));
b93463aa
AK		 1865}
1866
fda4e2e8 1867int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
b93463aa 1868{
fda4e2e8
AH		 1869 if (vapic_addr) {
1870 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1871 &vcpu->arch.apic->vapic_cache,
1872 vapic_addr, sizeof(u32)))
1873 return -EINVAL;
41383771 1874 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8 1875 } else {
41383771 1876 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8
AH		 1877 }
1878
1879 vcpu->arch.apic->vapic_addr = vapic_addr;
1880 return 0;
b93463aa 1881}
0105d1a5
GN		 1882
1883int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1884{
1885 struct kvm_lapic *apic = vcpu->arch.apic;
1886 u32 reg = (msr - APIC_BASE_MSR) << 4;
1887
1888 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1889 return 1;
1890
c69d3d9b
NA		 1891 if (reg == APIC_ICR2)
1892 return 1;
1893
0105d1a5 1894 /* if this is ICR write vector before command */
decdc283 1895 if (reg == APIC_ICR)
0105d1a5
GN		 1896 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1897 return apic_reg_write(apic, reg, (u32)data);
1898}
1899
1900int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1901{
1902 struct kvm_lapic *apic = vcpu->arch.apic;
1903 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1904
1905 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1906 return 1;
1907
c69d3d9b
NA		 1908 if (reg == APIC_DFR || reg == APIC_ICR2) {
1909 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
1910 reg);
1911 return 1;
1912 }
1913
0105d1a5
GN		 1914 if (apic_reg_read(apic, reg, 4, &low))
1915 return 1;
decdc283 1916 if (reg == APIC_ICR)
0105d1a5
GN		 1917 apic_reg_read(apic, APIC_ICR2, 4, &high);
1918
1919 *data = (((u64)high) << 32) | low;
1920
1921 return 0;
1922}
10388a07
GN		 1923
1924int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1925{
1926 struct kvm_lapic *apic = vcpu->arch.apic;
1927
c48f1496 1928 if (!kvm_vcpu_has_lapic(vcpu))
10388a07
GN		 1929 return 1;
1930
1931 /* if this is ICR write vector before command */
1932 if (reg == APIC_ICR)
1933 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1934 return apic_reg_write(apic, reg, (u32)data);
1935}
1936
1937int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1938{
1939 struct kvm_lapic *apic = vcpu->arch.apic;
1940 u32 low, high = 0;
1941
c48f1496 1942 if (!kvm_vcpu_has_lapic(vcpu))
10388a07
GN		 1943 return 1;
1944
1945 if (apic_reg_read(apic, reg, 4, &low))
1946 return 1;
1947 if (reg == APIC_ICR)
1948 apic_reg_read(apic, APIC_ICR2, 4, &high);
1949
1950 *data = (((u64)high) << 32) | low;
1951
1952 return 0;
1953}
ae7a2a3f
MT		 1954
1955int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1956{
1957 u64 addr = data & ~KVM_MSR_ENABLED;
1958 if (!IS_ALIGNED(addr, 4))
1959 return 1;
1960
1961 vcpu->arch.pv_eoi.msr_val = data;
1962 if (!pv_eoi_enabled(vcpu))
1963 return 0;
1964 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
8f964525 1965 addr, sizeof(u8));
ae7a2a3f 1966}
c5cc421b 1967
66450a21
JK		 1968void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
1969{
1970 struct kvm_lapic *apic = vcpu->arch.apic;
2b4a273b 1971 u8 sipi_vector;
299018f4 1972 unsigned long pe;
66450a21 1973
299018f4 1974 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
66450a21
JK		 1975 return;
1976
299018f4
GN		 1977 pe = xchg(&apic->pending_events, 0);
1978
1979 if (test_bit(KVM_APIC_INIT, &pe)) {
66450a21
JK		 1980 kvm_lapic_reset(vcpu);
1981 kvm_vcpu_reset(vcpu);
1982 if (kvm_vcpu_is_bsp(apic->vcpu))
1983 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1984 else
1985 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
1986 }
299018f4 1987 if (test_bit(KVM_APIC_SIPI, &pe) &&
66450a21
JK		 1988 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
1989 /* evaluate pending_events before reading the vector */
1990 smp_rmb();
1991 sipi_vector = apic->sipi_vector;
98eff52a 1992 apic_debug("vcpu %d received sipi with vector # %x\n",
66450a21
JK		 1993 vcpu->vcpu_id, sipi_vector);
1994 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
1995 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1996 }
1997}
1998
c5cc421b
GN		 1999void kvm_lapic_init(void)
2000{
2001 /* do not patch jump label more than once per second */
2002 jump_label_rate_limit(&apic_hw_disabled, HZ);
f8c1ea10 2003 jump_label_rate_limit(&apic_sw_disabled, HZ);
c5cc421b 2004}
Linux kernel - Deliverables
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