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x86: TSC deadline definitions
[deliverable/linux.git] / arch / x86 / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
9611c187 8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
97222cc8
ED		 9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
edf88417 21#include <linux/kvm_host.h>
97222cc8
ED		 22#include <linux/kvm.h>
23#include <linux/mm.h>
24#include <linux/highmem.h>
25#include <linux/smp.h>
26#include <linux/hrtimer.h>
27#include <linux/io.h>
28#include <linux/module.h>
6f6d6a1a 29#include <linux/math64.h>
5a0e3ad6 30#include <linux/slab.h>
97222cc8
ED		 31#include <asm/processor.h>
32#include <asm/msr.h>
33#include <asm/page.h>
34#include <asm/current.h>
35#include <asm/apicdef.h>
60063497 36#include <linux/atomic.h>
5fdbf976 37#include "kvm_cache_regs.h"
97222cc8 38#include "irq.h"
229456fc 39#include "trace.h"
fc61b800 40#include "x86.h"
97222cc8 41
b682b814
MT		 42#ifndef CONFIG_X86_64
43#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
44#else
45#define mod_64(x, y) ((x) % (y))
46#endif
47
97222cc8
ED		 48#define PRId64 "d"
49#define PRIx64 "llx"
50#define PRIu64 "u"
51#define PRIo64 "o"
52
53#define APIC_BUS_CYCLE_NS 1
54
55/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
56#define apic_debug(fmt, arg...)
57
58#define APIC_LVT_NUM 6
59/* 14 is the version for Xeon and Pentium 8.4.8*/
60#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
61#define LAPIC_MMIO_LENGTH (1 << 12)
62/* followed define is not in apicdef.h */
63#define APIC_SHORT_MASK 0xc0000
64#define APIC_DEST_NOSHORT 0x0
65#define APIC_DEST_MASK 0x800
66#define MAX_APIC_VECTOR 256
67
68#define VEC_POS(v) ((v) & (32 - 1))
69#define REG_POS(v) (((v) >> 5) << 4)
ad312c7c 70
9bc5791d
JK		 71static unsigned int min_timer_period_us = 500;
72module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
73
97222cc8
ED		 74static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
75{
76 return *((u32 *) (apic->regs + reg_off));
77}
78
79static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
80{
81 *((u32 *) (apic->regs + reg_off)) = val;
82}
83
84static inline int apic_test_and_set_vector(int vec, void *bitmap)
85{
86 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
87}
88
89static inline int apic_test_and_clear_vector(int vec, void *bitmap)
90{
91 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
92}
93
94static inline void apic_set_vector(int vec, void *bitmap)
95{
96 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
97}
98
99static inline void apic_clear_vector(int vec, void *bitmap)
100{
101 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
102}
103
104static inline int apic_hw_enabled(struct kvm_lapic *apic)
105{
ad312c7c 106 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
97222cc8
ED		 107}
108
109static inline int apic_sw_enabled(struct kvm_lapic *apic)
110{
111 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
112}
113
114static inline int apic_enabled(struct kvm_lapic *apic)
115{
116 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
117}
118
119#define LVT_MASK \
120 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
121
122#define LINT_MASK \
123 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
124 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
125
126static inline int kvm_apic_id(struct kvm_lapic *apic)
127{
128 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
129}
130
131static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
132{
133 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
134}
135
136static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
137{
138 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
139}
140
141static inline int apic_lvtt_period(struct kvm_lapic *apic)
142{
143 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
144}
145
cc6e462c
JK		 146static inline int apic_lvt_nmi_mode(u32 lvt_val)
147{
148 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
149}
150
fc61b800
GN		 151void kvm_apic_set_version(struct kvm_vcpu *vcpu)
152{
153 struct kvm_lapic *apic = vcpu->arch.apic;
154 struct kvm_cpuid_entry2 *feat;
155 u32 v = APIC_VERSION;
156
157 if (!irqchip_in_kernel(vcpu->kvm))
158 return;
159
160 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
161 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
162 v |= APIC_LVR_DIRECTED_EOI;
163 apic_set_reg(apic, APIC_LVR, v);
164}
165
0105d1a5
GN		 166static inline int apic_x2apic_mode(struct kvm_lapic *apic)
167{
168 return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
169}
170
97222cc8
ED		 171static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
172 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
173 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
174 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
175 LINT_MASK, LINT_MASK, /* LVT0-1 */
176 LVT_MASK /* LVTERR */
177};
178
179static int find_highest_vector(void *bitmap)
180{
181 u32 *word = bitmap;
182 int word_offset = MAX_APIC_VECTOR >> 5;
183
184 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
185 continue;
186
187 if (likely(!word_offset && !word[0]))
188 return -1;
189 else
190 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
191}
192
193static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
194{
33e4c686 195 apic->irr_pending = true;
97222cc8
ED		 196 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
197}
198
33e4c686 199static inline int apic_search_irr(struct kvm_lapic *apic)
97222cc8 200{
33e4c686 201 return find_highest_vector(apic->regs + APIC_IRR);
97222cc8
ED		 202}
203
204static inline int apic_find_highest_irr(struct kvm_lapic *apic)
205{
206 int result;
207
33e4c686
GN		 208 if (!apic->irr_pending)
209 return -1;
210
211 result = apic_search_irr(apic);
97222cc8
ED		 212 ASSERT(result == -1 || result >= 16);
213
214 return result;
215}
216
33e4c686
GN		 217static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
218{
219 apic->irr_pending = false;
220 apic_clear_vector(vec, apic->regs + APIC_IRR);
221 if (apic_search_irr(apic) != -1)
222 apic->irr_pending = true;
223}
224
6e5d865c
YS		 225int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
226{
ad312c7c 227 struct kvm_lapic *apic = vcpu->arch.apic;
6e5d865c
YS		 228 int highest_irr;
229
33e4c686
GN		 230 /* This may race with setting of irr in __apic_accept_irq() and
231 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
232 * will cause vmexit immediately and the value will be recalculated
233 * on the next vmentry.
234 */
6e5d865c
YS		 235 if (!apic)
236 return 0;
237 highest_irr = apic_find_highest_irr(apic);
238
239 return highest_irr;
240}
6e5d865c 241
6da7e3f6
GN		 242static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
243 int vector, int level, int trig_mode);
244
58c2dde1 245int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
97222cc8 246{
ad312c7c 247 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 248
58c2dde1
GN		 249 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
250 irq->level, irq->trig_mode);
97222cc8
ED		 251}
252
253static inline int apic_find_highest_isr(struct kvm_lapic *apic)
254{
255 int result;
256
257 result = find_highest_vector(apic->regs + APIC_ISR);
258 ASSERT(result == -1 || result >= 16);
259
260 return result;
261}
262
263static void apic_update_ppr(struct kvm_lapic *apic)
264{
3842d135 265 u32 tpr, isrv, ppr, old_ppr;
97222cc8
ED		 266 int isr;
267
3842d135 268 old_ppr = apic_get_reg(apic, APIC_PROCPRI);
97222cc8
ED		 269 tpr = apic_get_reg(apic, APIC_TASKPRI);
270 isr = apic_find_highest_isr(apic);
271 isrv = (isr != -1) ? isr : 0;
272
273 if ((tpr & 0xf0) >= (isrv & 0xf0))
274 ppr = tpr & 0xff;
275 else
276 ppr = isrv & 0xf0;
277
278 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
279 apic, ppr, isr, isrv);
280
3842d135
AK		 281 if (old_ppr != ppr) {
282 apic_set_reg(apic, APIC_PROCPRI, ppr);
83bcacb1
AK		 283 if (ppr < old_ppr)
284 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
3842d135 285 }
97222cc8
ED		 286}
287
288static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
289{
290 apic_set_reg(apic, APIC_TASKPRI, tpr);
291 apic_update_ppr(apic);
292}
293
294int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
295{
343f94fe 296 return dest == 0xff || kvm_apic_id(apic) == dest;
97222cc8
ED		 297}
298
299int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
300{
301 int result = 0;
0105d1a5
GN		 302 u32 logical_id;
303
304 if (apic_x2apic_mode(apic)) {
305 logical_id = apic_get_reg(apic, APIC_LDR);
306 return logical_id & mda;
307 }
97222cc8
ED		 308
309 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
310
311 switch (apic_get_reg(apic, APIC_DFR)) {
312 case APIC_DFR_FLAT:
313 if (logical_id & mda)
314 result = 1;
315 break;
316 case APIC_DFR_CLUSTER:
317 if (((logical_id >> 4) == (mda >> 0x4))
318 && (logical_id & mda & 0xf))
319 result = 1;
320 break;
321 default:
7712de87
JK		 322 apic_debug("Bad DFR vcpu %d: %08x\n",
323 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
97222cc8
ED		 324 break;
325 }
326
327 return result;
328}
329
343f94fe 330int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
97222cc8
ED		 331 int short_hand, int dest, int dest_mode)
332{
333 int result = 0;
ad312c7c 334 struct kvm_lapic *target = vcpu->arch.apic;
97222cc8
ED		 335
336 apic_debug("target %p, source %p, dest 0x%x, "
343f94fe 337 "dest_mode 0x%x, short_hand 0x%x\n",
97222cc8
ED		 338 target, source, dest, dest_mode, short_hand);
339
bd371396 340 ASSERT(target);
97222cc8
ED		 341 switch (short_hand) {
342 case APIC_DEST_NOSHORT:
343f94fe 343 if (dest_mode == 0)
97222cc8 344 /* Physical mode. */
343f94fe
GN		 345 result = kvm_apic_match_physical_addr(target, dest);
346 else
97222cc8
ED		 347 /* Logical mode. */
348 result = kvm_apic_match_logical_addr(target, dest);
349 break;
350 case APIC_DEST_SELF:
343f94fe 351 result = (target == source);
97222cc8
ED		 352 break;
353 case APIC_DEST_ALLINC:
354 result = 1;
355 break;
356 case APIC_DEST_ALLBUT:
343f94fe 357 result = (target != source);
97222cc8
ED		 358 break;
359 default:
7712de87
JK		 360 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
361 short_hand);
97222cc8
ED		 362 break;
363 }
364
365 return result;
366}
367
368/*
369 * Add a pending IRQ into lapic.
370 * Return 1 if successfully added and 0 if discarded.
371 */
372static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
373 int vector, int level, int trig_mode)
374{
6da7e3f6 375 int result = 0;
c5ec1534 376 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8
ED		 377
378 switch (delivery_mode) {
97222cc8 379 case APIC_DM_LOWEST:
e1035715
GN		 380 vcpu->arch.apic_arb_prio++;
381 case APIC_DM_FIXED:
97222cc8
ED		 382 /* FIXME add logic for vcpu on reset */
383 if (unlikely(!apic_enabled(apic)))
384 break;
385
a5d36f82
AK		 386 if (trig_mode) {
387 apic_debug("level trig mode for vector %d", vector);
388 apic_set_vector(vector, apic->regs + APIC_TMR);
389 } else
390 apic_clear_vector(vector, apic->regs + APIC_TMR);
391
6da7e3f6 392 result = !apic_test_and_set_irr(vector, apic);
1000ff8d 393 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
4da74896 394 trig_mode, vector, !result);
6da7e3f6
GN		 395 if (!result) {
396 if (trig_mode)
397 apic_debug("level trig mode repeatedly for "
398 "vector %d", vector);
97222cc8
ED		 399 break;
400 }
401
3842d135 402 kvm_make_request(KVM_REQ_EVENT, vcpu);
d7690175 403 kvm_vcpu_kick(vcpu);
97222cc8
ED		 404 break;
405
406 case APIC_DM_REMRD:
7712de87 407 apic_debug("Ignoring delivery mode 3\n");
97222cc8
ED		 408 break;
409
410 case APIC_DM_SMI:
7712de87 411 apic_debug("Ignoring guest SMI\n");
97222cc8 412 break;
3419ffc8 413
97222cc8 414 case APIC_DM_NMI:
6da7e3f6 415 result = 1;
3419ffc8 416 kvm_inject_nmi(vcpu);
26df99c6 417 kvm_vcpu_kick(vcpu);
97222cc8
ED		 418 break;
419
420 case APIC_DM_INIT:
c5ec1534 421 if (level) {
6da7e3f6 422 result = 1;
a4535290 423 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
3842d135 424 kvm_make_request(KVM_REQ_EVENT, vcpu);
c5ec1534
HQ		 425 kvm_vcpu_kick(vcpu);
426 } else {
1b10bf31
JK		 427 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
428 vcpu->vcpu_id);
c5ec1534 429 }
97222cc8
ED		 430 break;
431
432 case APIC_DM_STARTUP:
1b10bf31
JK		 433 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
434 vcpu->vcpu_id, vector);
a4535290 435 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6da7e3f6 436 result = 1;
ad312c7c 437 vcpu->arch.sipi_vector = vector;
a4535290 438 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
3842d135 439 kvm_make_request(KVM_REQ_EVENT, vcpu);
d7690175 440 kvm_vcpu_kick(vcpu);
c5ec1534 441 }
97222cc8
ED		 442 break;
443
23930f95
JK		 444 case APIC_DM_EXTINT:
445 /*
446 * Should only be called by kvm_apic_local_deliver() with LVT0,
447 * before NMI watchdog was enabled. Already handled by
448 * kvm_apic_accept_pic_intr().
449 */
450 break;
451
97222cc8
ED		 452 default:
453 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
454 delivery_mode);
455 break;
456 }
457 return result;
458}
459
e1035715 460int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
8be5453f 461{
e1035715 462 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
8be5453f
ZX		 463}
464
97222cc8
ED		 465static void apic_set_eoi(struct kvm_lapic *apic)
466{
467 int vector = apic_find_highest_isr(apic);
f5244726 468 int trigger_mode;
97222cc8
ED		 469 /*
470 * Not every write EOI will has corresponding ISR,
471 * one example is when Kernel check timer on setup_IO_APIC
472 */
473 if (vector == -1)
474 return;
475
476 apic_clear_vector(vector, apic->regs + APIC_ISR);
477 apic_update_ppr(apic);
478
479 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
f5244726
MT		 480 trigger_mode = IOAPIC_LEVEL_TRIG;
481 else
482 trigger_mode = IOAPIC_EDGE_TRIG;
eba0226b 483 if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI))
fc61b800 484 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
3842d135 485 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
97222cc8
ED		 486}
487
488static void apic_send_ipi(struct kvm_lapic *apic)
489{
490 u32 icr_low = apic_get_reg(apic, APIC_ICR);
491 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
58c2dde1 492 struct kvm_lapic_irq irq;
97222cc8 493
58c2dde1
GN		 494 irq.vector = icr_low & APIC_VECTOR_MASK;
495 irq.delivery_mode = icr_low & APIC_MODE_MASK;
496 irq.dest_mode = icr_low & APIC_DEST_MASK;
497 irq.level = icr_low & APIC_INT_ASSERT;
498 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
499 irq.shorthand = icr_low & APIC_SHORT_MASK;
0105d1a5
GN		 500 if (apic_x2apic_mode(apic))
501 irq.dest_id = icr_high;
502 else
503 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
97222cc8 504
1000ff8d
GN		 505 trace_kvm_apic_ipi(icr_low, irq.dest_id);
506
97222cc8
ED		 507 apic_debug("icr_high 0x%x, icr_low 0x%x, "
508 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
509 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
9b5843dd 510 icr_high, icr_low, irq.shorthand, irq.dest_id,
58c2dde1
GN		 511 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
512 irq.vector);
513
514 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
97222cc8
ED		 515}
516
517static u32 apic_get_tmcct(struct kvm_lapic *apic)
518{
b682b814
MT		 519 ktime_t remaining;
520 s64 ns;
9da8f4e8 521 u32 tmcct;
97222cc8
ED		 522
523 ASSERT(apic != NULL);
524
9da8f4e8 525 /* if initial count is 0, current count should also be 0 */
b682b814 526 if (apic_get_reg(apic, APIC_TMICT) == 0)
9da8f4e8
KP		 527 return 0;
528
ace15464 529 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
b682b814
MT		 530 if (ktime_to_ns(remaining) < 0)
531 remaining = ktime_set(0, 0);
532
d3c7b77d
MT		 533 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
534 tmcct = div64_u64(ns,
535 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 536
537 return tmcct;
538}
539
b209749f
AK		 540static void __report_tpr_access(struct kvm_lapic *apic, bool write)
541{
542 struct kvm_vcpu *vcpu = apic->vcpu;
543 struct kvm_run *run = vcpu->run;
544
a8eeb04a 545 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
5fdbf976 546 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 547 run->tpr_access.is_write = write;
548}
549
550static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
551{
552 if (apic->vcpu->arch.tpr_access_reporting)
553 __report_tpr_access(apic, write);
554}
555
97222cc8
ED		 556static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
557{
558 u32 val = 0;
559
560 if (offset >= LAPIC_MMIO_LENGTH)
561 return 0;
562
563 switch (offset) {
0105d1a5
GN		 564 case APIC_ID:
565 if (apic_x2apic_mode(apic))
566 val = kvm_apic_id(apic);
567 else
568 val = kvm_apic_id(apic) << 24;
569 break;
97222cc8 570 case APIC_ARBPRI:
7712de87 571 apic_debug("Access APIC ARBPRI register which is for P6\n");
97222cc8
ED		 572 break;
573
574 case APIC_TMCCT: /* Timer CCR */
575 val = apic_get_tmcct(apic);
576 break;
577
b209749f
AK		 578 case APIC_TASKPRI:
579 report_tpr_access(apic, false);
580 /* fall thru */
97222cc8 581 default:
6e5d865c 582 apic_update_ppr(apic);
97222cc8
ED		 583 val = apic_get_reg(apic, offset);
584 break;
585 }
586
587 return val;
588}
589
d76685c4
GH		 590static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
591{
592 return container_of(dev, struct kvm_lapic, dev);
593}
594
0105d1a5
GN		 595static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
596 void *data)
97222cc8 597{
97222cc8
ED		 598 unsigned char alignment = offset & 0xf;
599 u32 result;
0105d1a5
GN		 600 /* this bitmask has a bit cleared for each reserver register */
601 static const u64 rmask = 0x43ff01ffffffe70cULL;
97222cc8
ED		 602
603 if ((alignment + len) > 4) {
4088bb3c
GN		 604 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
605 offset, len);
0105d1a5 606 return 1;
97222cc8 607 }
0105d1a5
GN		 608
609 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
4088bb3c
GN		 610 apic_debug("KVM_APIC_READ: read reserved register %x\n",
611 offset);
0105d1a5
GN		 612 return 1;
613 }
614
97222cc8
ED		 615 result = __apic_read(apic, offset & ~0xf);
616
229456fc
MT		 617 trace_kvm_apic_read(offset, result);
618
97222cc8
ED		 619 switch (len) {
620 case 1:
621 case 2:
622 case 4:
623 memcpy(data, (char *)&result + alignment, len);
624 break;
625 default:
626 printk(KERN_ERR "Local APIC read with len = %x, "
627 "should be 1,2, or 4 instead\n", len);
628 break;
629 }
bda9020e 630 return 0;
97222cc8
ED		 631}
632
0105d1a5
GN		 633static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
634{
635 return apic_hw_enabled(apic) &&
636 addr >= apic->base_address &&
637 addr < apic->base_address + LAPIC_MMIO_LENGTH;
638}
639
640static int apic_mmio_read(struct kvm_io_device *this,
641 gpa_t address, int len, void *data)
642{
643 struct kvm_lapic *apic = to_lapic(this);
644 u32 offset = address - apic->base_address;
645
646 if (!apic_mmio_in_range(apic, address))
647 return -EOPNOTSUPP;
648
649 apic_reg_read(apic, offset, len, data);
650
651 return 0;
652}
653
97222cc8
ED		 654static void update_divide_count(struct kvm_lapic *apic)
655{
656 u32 tmp1, tmp2, tdcr;
657
658 tdcr = apic_get_reg(apic, APIC_TDCR);
659 tmp1 = tdcr & 0xf;
660 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 661 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 662
663 apic_debug("timer divide count is 0x%x\n",
9b5843dd 664 apic->divide_count);
97222cc8
ED		 665}
666
667static void start_apic_timer(struct kvm_lapic *apic)
668{
d3c7b77d 669 ktime_t now = apic->lapic_timer.timer.base->get_time();
97222cc8 670
b2d83cfa 671 apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT) *
d3c7b77d
MT		 672 APIC_BUS_CYCLE_NS * apic->divide_count;
673 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 674
d3c7b77d 675 if (!apic->lapic_timer.period)
0b975a3c 676 return;
1444885a
MT		 677 /*
678 * Do not allow the guest to program periodic timers with small
679 * interval, since the hrtimers are not throttled by the host
680 * scheduler.
681 */
682 if (apic_lvtt_period(apic)) {
9bc5791d
JK		 683 s64 min_period = min_timer_period_us * 1000LL;
684
685 if (apic->lapic_timer.period < min_period) {
686 pr_info_ratelimited(
687 "kvm: vcpu %i: requested %lld ns "
688 "lapic timer period limited to %lld ns\n",
689 apic->vcpu->vcpu_id, apic->lapic_timer.period,
690 min_period);
691 apic->lapic_timer.period = min_period;
692 }
1444885a 693 }
0b975a3c 694
d3c7b77d
MT		 695 hrtimer_start(&apic->lapic_timer.timer,
696 ktime_add_ns(now, apic->lapic_timer.period),
97222cc8
ED		 697 HRTIMER_MODE_ABS);
698
699 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
700 PRIx64 ", "
701 "timer initial count 0x%x, period %lldns, "
b8688d51 702 "expire @ 0x%016" PRIx64 ".\n", __func__,
97222cc8
ED		 703 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
704 apic_get_reg(apic, APIC_TMICT),
d3c7b77d 705 apic->lapic_timer.period,
97222cc8 706 ktime_to_ns(ktime_add_ns(now,
d3c7b77d 707 apic->lapic_timer.period)));
97222cc8
ED		 708}
709
cc6e462c
JK		 710static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
711{
712 int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
713
714 if (apic_lvt_nmi_mode(lvt0_val)) {
715 if (!nmi_wd_enabled) {
716 apic_debug("Receive NMI setting on APIC_LVT0 "
717 "for cpu %d\n", apic->vcpu->vcpu_id);
718 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
719 }
720 } else if (nmi_wd_enabled)
721 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
722}
723
0105d1a5 724static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
97222cc8 725{
0105d1a5 726 int ret = 0;
97222cc8 727
0105d1a5 728 trace_kvm_apic_write(reg, val);
97222cc8 729
0105d1a5 730 switch (reg) {
97222cc8 731 case APIC_ID: /* Local APIC ID */
0105d1a5
GN		 732 if (!apic_x2apic_mode(apic))
733 apic_set_reg(apic, APIC_ID, val);
734 else
735 ret = 1;
97222cc8
ED		 736 break;
737
738 case APIC_TASKPRI:
b209749f 739 report_tpr_access(apic, true);
97222cc8
ED		 740 apic_set_tpr(apic, val & 0xff);
741 break;
742
743 case APIC_EOI:
744 apic_set_eoi(apic);
745 break;
746
747 case APIC_LDR:
0105d1a5
GN		 748 if (!apic_x2apic_mode(apic))
749 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
750 else
751 ret = 1;
97222cc8
ED		 752 break;
753
754 case APIC_DFR:
0105d1a5
GN		 755 if (!apic_x2apic_mode(apic))
756 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
757 else
758 ret = 1;
97222cc8
ED		 759 break;
760
fc61b800
GN		 761 case APIC_SPIV: {
762 u32 mask = 0x3ff;
763 if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
764 mask |= APIC_SPIV_DIRECTED_EOI;
765 apic_set_reg(apic, APIC_SPIV, val & mask);
97222cc8
ED		 766 if (!(val & APIC_SPIV_APIC_ENABLED)) {
767 int i;
768 u32 lvt_val;
769
770 for (i = 0; i < APIC_LVT_NUM; i++) {
771 lvt_val = apic_get_reg(apic,
772 APIC_LVTT + 0x10 * i);
773 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
774 lvt_val | APIC_LVT_MASKED);
775 }
d3c7b77d 776 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 777
778 }
779 break;
fc61b800 780 }
97222cc8
ED		 781 case APIC_ICR:
782 /* No delay here, so we always clear the pending bit */
783 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
784 apic_send_ipi(apic);
785 break;
786
787 case APIC_ICR2:
0105d1a5
GN		 788 if (!apic_x2apic_mode(apic))
789 val &= 0xff000000;
790 apic_set_reg(apic, APIC_ICR2, val);
97222cc8
ED		 791 break;
792
23930f95 793 case APIC_LVT0:
cc6e462c 794 apic_manage_nmi_watchdog(apic, val);
97222cc8
ED		 795 case APIC_LVTT:
796 case APIC_LVTTHMR:
797 case APIC_LVTPC:
97222cc8
ED		 798 case APIC_LVT1:
799 case APIC_LVTERR:
800 /* TODO: Check vector */
801 if (!apic_sw_enabled(apic))
802 val |= APIC_LVT_MASKED;
803
0105d1a5
GN		 804 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
805 apic_set_reg(apic, reg, val);
97222cc8
ED		 806
807 break;
808
809 case APIC_TMICT:
d3c7b77d 810 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 811 apic_set_reg(apic, APIC_TMICT, val);
812 start_apic_timer(apic);
0105d1a5 813 break;
97222cc8
ED		 814
815 case APIC_TDCR:
816 if (val & 4)
7712de87 817 apic_debug("KVM_WRITE:TDCR %x\n", val);
97222cc8
ED		 818 apic_set_reg(apic, APIC_TDCR, val);
819 update_divide_count(apic);
820 break;
821
0105d1a5
GN		 822 case APIC_ESR:
823 if (apic_x2apic_mode(apic) && val != 0) {
7712de87 824 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
0105d1a5
GN		 825 ret = 1;
826 }
827 break;
828
829 case APIC_SELF_IPI:
830 if (apic_x2apic_mode(apic)) {
831 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
832 } else
833 ret = 1;
834 break;
97222cc8 835 default:
0105d1a5 836 ret = 1;
97222cc8
ED		 837 break;
838 }
0105d1a5
GN		 839 if (ret)
840 apic_debug("Local APIC Write to read-only register %x\n", reg);
841 return ret;
842}
843
844static int apic_mmio_write(struct kvm_io_device *this,
845 gpa_t address, int len, const void *data)
846{
847 struct kvm_lapic *apic = to_lapic(this);
848 unsigned int offset = address - apic->base_address;
849 u32 val;
850
851 if (!apic_mmio_in_range(apic, address))
852 return -EOPNOTSUPP;
853
854 /*
855 * APIC register must be aligned on 128-bits boundary.
856 * 32/64/128 bits registers must be accessed thru 32 bits.
857 * Refer SDM 8.4.1
858 */
859 if (len != 4 || (offset & 0xf)) {
860 /* Don't shout loud, $infamous_os would cause only noise. */
861 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
756975bb 862 return 0;
0105d1a5
GN		 863 }
864
865 val = *(u32*)data;
866
867 /* too common printing */
868 if (offset != APIC_EOI)
869 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
870 "0x%x\n", __func__, offset, len, val);
871
872 apic_reg_write(apic, offset & 0xff0, val);
873
bda9020e 874 return 0;
97222cc8
ED		 875}
876
58fbbf26
KT		 877void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
878{
879 struct kvm_lapic *apic = vcpu->arch.apic;
880
881 if (apic)
882 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
883}
884EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
885
d589444e 886void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 887{
ad312c7c 888 if (!vcpu->arch.apic)
97222cc8
ED		 889 return;
890
d3c7b77d 891 hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
97222cc8 892
afc20184
TY		 893 if (vcpu->arch.apic->regs)
894 free_page((unsigned long)vcpu->arch.apic->regs);
97222cc8 895
ad312c7c 896 kfree(vcpu->arch.apic);
97222cc8
ED		 897}
898
899/*
900 *----------------------------------------------------------------------
901 * LAPIC interface
902 *----------------------------------------------------------------------
903 */
904
905void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
906{
ad312c7c 907 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 908
909 if (!apic)
910 return;
b93463aa
AK		 911 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
912 | (apic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8
ED		 913}
914
915u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
916{
ad312c7c 917 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 918 u64 tpr;
919
920 if (!apic)
921 return 0;
922 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
923
924 return (tpr & 0xf0) >> 4;
925}
926
927void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
928{
ad312c7c 929 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 930
931 if (!apic) {
932 value |= MSR_IA32_APICBASE_BSP;
ad312c7c 933 vcpu->arch.apic_base = value;
97222cc8
ED		 934 return;
935 }
c5af89b6
GN		 936
937 if (!kvm_vcpu_is_bsp(apic->vcpu))
97222cc8
ED		 938 value &= ~MSR_IA32_APICBASE_BSP;
939
ad312c7c 940 vcpu->arch.apic_base = value;
0105d1a5
GN		 941 if (apic_x2apic_mode(apic)) {
942 u32 id = kvm_apic_id(apic);
943 u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
944 apic_set_reg(apic, APIC_LDR, ldr);
945 }
ad312c7c 946 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 947 MSR_IA32_APICBASE_BASE;
948
949 /* with FSB delivery interrupt, we can restart APIC functionality */
950 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
ad312c7c 951 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 952
953}
954
c5ec1534 955void kvm_lapic_reset(struct kvm_vcpu *vcpu)
97222cc8
ED		 956{
957 struct kvm_lapic *apic;
958 int i;
959
b8688d51 960 apic_debug("%s\n", __func__);
97222cc8
ED		 961
962 ASSERT(vcpu);
ad312c7c 963 apic = vcpu->arch.apic;
97222cc8
ED		 964 ASSERT(apic != NULL);
965
966 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 967 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 968
969 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
fc61b800 970 kvm_apic_set_version(apic->vcpu);
97222cc8
ED		 971
972 for (i = 0; i < APIC_LVT_NUM; i++)
973 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
40487c68
QH		 974 apic_set_reg(apic, APIC_LVT0,
975 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
97222cc8
ED		 976
977 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
978 apic_set_reg(apic, APIC_SPIV, 0xff);
979 apic_set_reg(apic, APIC_TASKPRI, 0);
980 apic_set_reg(apic, APIC_LDR, 0);
981 apic_set_reg(apic, APIC_ESR, 0);
982 apic_set_reg(apic, APIC_ICR, 0);
983 apic_set_reg(apic, APIC_ICR2, 0);
984 apic_set_reg(apic, APIC_TDCR, 0);
985 apic_set_reg(apic, APIC_TMICT, 0);
986 for (i = 0; i < 8; i++) {
987 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
988 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
989 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
990 }
33e4c686 991 apic->irr_pending = false;
b33ac88b 992 update_divide_count(apic);
d3c7b77d 993 atomic_set(&apic->lapic_timer.pending, 0);
c5af89b6 994 if (kvm_vcpu_is_bsp(vcpu))
ad312c7c 995 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
97222cc8
ED		 996 apic_update_ppr(apic);
997
e1035715
GN		 998 vcpu->arch.apic_arb_prio = 0;
999
97222cc8 1000 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
b8688d51 1001 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
97222cc8 1002 vcpu, kvm_apic_id(apic),
ad312c7c 1003 vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1004}
1005
343f94fe 1006bool kvm_apic_present(struct kvm_vcpu *vcpu)
97222cc8 1007{
343f94fe
GN		 1008 return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
1009}
97222cc8 1010
343f94fe
GN		 1011int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
1012{
1013 return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
97222cc8
ED		 1014}
1015
1016/*
1017 *----------------------------------------------------------------------
1018 * timer interface
1019 *----------------------------------------------------------------------
1020 */
1b9778da 1021
d3c7b77d 1022static bool lapic_is_periodic(struct kvm_timer *ktimer)
97222cc8 1023{
d3c7b77d
MT		 1024 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
1025 lapic_timer);
1026 return apic_lvtt_period(apic);
97222cc8
ED		 1027}
1028
3d80840d
MT		 1029int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1030{
1031 struct kvm_lapic *lapic = vcpu->arch.apic;
1032
54aaacee 1033 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
d3c7b77d 1034 return atomic_read(&lapic->lapic_timer.pending);
3d80840d
MT		 1035
1036 return 0;
1037}
1038
8fdb2351 1039static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 1040{
8fdb2351 1041 u32 reg = apic_get_reg(apic, lvt_type);
23930f95 1042 int vector, mode, trig_mode;
23930f95 1043
8fdb2351 1044 if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 1045 vector = reg & APIC_VECTOR_MASK;
1046 mode = reg & APIC_MODE_MASK;
1047 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1048 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
1049 }
1050 return 0;
1051}
1b9778da 1052
8fdb2351 1053void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 1054{
8fdb2351
JK		 1055 struct kvm_lapic *apic = vcpu->arch.apic;
1056
1057 if (apic)
1058 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 1059}
1060
386eb6e8 1061static struct kvm_timer_ops lapic_timer_ops = {
d3c7b77d
MT		 1062 .is_periodic = lapic_is_periodic,
1063};
97222cc8 1064
d76685c4
GH		 1065static const struct kvm_io_device_ops apic_mmio_ops = {
1066 .read = apic_mmio_read,
1067 .write = apic_mmio_write,
d76685c4
GH		 1068};
1069
97222cc8
ED		 1070int kvm_create_lapic(struct kvm_vcpu *vcpu)
1071{
1072 struct kvm_lapic *apic;
1073
1074 ASSERT(vcpu != NULL);
1075 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1076
1077 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1078 if (!apic)
1079 goto nomem;
1080
ad312c7c 1081 vcpu->arch.apic = apic;
97222cc8 1082
afc20184
TY		 1083 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1084 if (!apic->regs) {
97222cc8
ED		 1085 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1086 vcpu->vcpu_id);
d589444e 1087 goto nomem_free_apic;
97222cc8 1088 }
97222cc8
ED		 1089 apic->vcpu = vcpu;
1090
d3c7b77d
MT		 1091 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1092 HRTIMER_MODE_ABS);
1093 apic->lapic_timer.timer.function = kvm_timer_fn;
1094 apic->lapic_timer.t_ops = &lapic_timer_ops;
1095 apic->lapic_timer.kvm = vcpu->kvm;
1ed0ce00 1096 apic->lapic_timer.vcpu = vcpu;
d3c7b77d 1097
97222cc8 1098 apic->base_address = APIC_DEFAULT_PHYS_BASE;
ad312c7c 1099 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
97222cc8 1100
c5ec1534 1101 kvm_lapic_reset(vcpu);
d76685c4 1102 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
97222cc8
ED		 1103
1104 return 0;
d589444e
RR		 1105nomem_free_apic:
1106 kfree(apic);
97222cc8 1107nomem:
97222cc8
ED		 1108 return -ENOMEM;
1109}
97222cc8
ED		 1110
1111int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1112{
ad312c7c 1113 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1114 int highest_irr;
1115
1116 if (!apic || !apic_enabled(apic))
1117 return -1;
1118
6e5d865c 1119 apic_update_ppr(apic);
97222cc8
ED		 1120 highest_irr = apic_find_highest_irr(apic);
1121 if ((highest_irr == -1) ||
1122 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1123 return -1;
1124 return highest_irr;
1125}
1126
40487c68
QH		 1127int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1128{
ad312c7c 1129 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 1130 int r = 0;
1131
e7dca5c0
CL		 1132 if (!apic_hw_enabled(vcpu->arch.apic))
1133 r = 1;
1134 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1135 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1136 r = 1;
40487c68
QH		 1137 return r;
1138}
1139
1b9778da
ED		 1140void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1141{
ad312c7c 1142 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 1143
d3c7b77d 1144 if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
8fdb2351 1145 if (kvm_apic_local_deliver(apic, APIC_LVTT))
d3c7b77d 1146 atomic_dec(&apic->lapic_timer.pending);
1b9778da
ED		 1147 }
1148}
1149
97222cc8
ED		 1150int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1151{
1152 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 1153 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1154
1155 if (vector == -1)
1156 return -1;
1157
1158 apic_set_vector(vector, apic->regs + APIC_ISR);
1159 apic_update_ppr(apic);
1160 apic_clear_irr(vector, apic);
1161 return vector;
1162}
96ad2cc6
ED		 1163
1164void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1165{
ad312c7c 1166 struct kvm_lapic *apic = vcpu->arch.apic;
96ad2cc6 1167
ad312c7c 1168 apic->base_address = vcpu->arch.apic_base &
96ad2cc6 1169 MSR_IA32_APICBASE_BASE;
fc61b800
GN		 1170 kvm_apic_set_version(vcpu);
1171
96ad2cc6 1172 apic_update_ppr(apic);
d3c7b77d 1173 hrtimer_cancel(&apic->lapic_timer.timer);
96ad2cc6
ED		 1174 update_divide_count(apic);
1175 start_apic_timer(apic);
6e24a6ef 1176 apic->irr_pending = true;
3842d135 1177 kvm_make_request(KVM_REQ_EVENT, vcpu);
96ad2cc6 1178}
a3d7f85f 1179
2f52d58c 1180void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 1181{
ad312c7c 1182 struct kvm_lapic *apic = vcpu->arch.apic;
a3d7f85f
ED		 1183 struct hrtimer *timer;
1184
1185 if (!apic)
1186 return;
1187
d3c7b77d 1188 timer = &apic->lapic_timer.timer;
a3d7f85f 1189 if (hrtimer_cancel(timer))
beb20d52 1190 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
a3d7f85f 1191}
b93463aa
AK		 1192
1193void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1194{
1195 u32 data;
1196 void *vapic;
1197
1198 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1199 return;
1200
1201 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1202 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1203 kunmap_atomic(vapic, KM_USER0);
1204
1205 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1206}
1207
1208void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1209{
1210 u32 data, tpr;
1211 int max_irr, max_isr;
1212 struct kvm_lapic *apic;
1213 void *vapic;
1214
1215 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1216 return;
1217
1218 apic = vcpu->arch.apic;
1219 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1220 max_irr = apic_find_highest_irr(apic);
1221 if (max_irr < 0)
1222 max_irr = 0;
1223 max_isr = apic_find_highest_isr(apic);
1224 if (max_isr < 0)
1225 max_isr = 0;
1226 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1227
1228 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1229 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1230 kunmap_atomic(vapic, KM_USER0);
1231}
1232
1233void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1234{
1235 if (!irqchip_in_kernel(vcpu->kvm))
1236 return;
1237
1238 vcpu->arch.apic->vapic_addr = vapic_addr;
1239}
0105d1a5
GN		 1240
1241int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1242{
1243 struct kvm_lapic *apic = vcpu->arch.apic;
1244 u32 reg = (msr - APIC_BASE_MSR) << 4;
1245
1246 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1247 return 1;
1248
1249 /* if this is ICR write vector before command */
1250 if (msr == 0x830)
1251 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1252 return apic_reg_write(apic, reg, (u32)data);
1253}
1254
1255int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1256{
1257 struct kvm_lapic *apic = vcpu->arch.apic;
1258 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1259
1260 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1261 return 1;
1262
1263 if (apic_reg_read(apic, reg, 4, &low))
1264 return 1;
1265 if (msr == 0x830)
1266 apic_reg_read(apic, APIC_ICR2, 4, &high);
1267
1268 *data = (((u64)high) << 32) | low;
1269
1270 return 0;
1271}
10388a07
GN		 1272
1273int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1274{
1275 struct kvm_lapic *apic = vcpu->arch.apic;
1276
1277 if (!irqchip_in_kernel(vcpu->kvm))
1278 return 1;
1279
1280 /* if this is ICR write vector before command */
1281 if (reg == APIC_ICR)
1282 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1283 return apic_reg_write(apic, reg, (u32)data);
1284}
1285
1286int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1287{
1288 struct kvm_lapic *apic = vcpu->arch.apic;
1289 u32 low, high = 0;
1290
1291 if (!irqchip_in_kernel(vcpu->kvm))
1292 return 1;
1293
1294 if (apic_reg_read(apic, reg, 4, &low))
1295 return 1;
1296 if (reg == APIC_ICR)
1297 apic_reg_read(apic, APIC_ICR2, 4, &high);
1298
1299 *data = (((u64)high) << 32) | low;
1300
1301 return 0;
1302}
Linux kernel - Deliverables
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