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KVM: Clean up and extend rate-limited output
[deliverable/linux.git] / arch / x86 / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
9611c187 8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
97222cc8
ED		 9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
edf88417 21#include <linux/kvm_host.h>
97222cc8
ED		 22#include <linux/kvm.h>
23#include <linux/mm.h>
24#include <linux/highmem.h>
25#include <linux/smp.h>
26#include <linux/hrtimer.h>
27#include <linux/io.h>
28#include <linux/module.h>
6f6d6a1a 29#include <linux/math64.h>
5a0e3ad6 30#include <linux/slab.h>
97222cc8
ED		 31#include <asm/processor.h>
32#include <asm/msr.h>
33#include <asm/page.h>
34#include <asm/current.h>
35#include <asm/apicdef.h>
60063497 36#include <linux/atomic.h>
5fdbf976 37#include "kvm_cache_regs.h"
97222cc8 38#include "irq.h"
229456fc 39#include "trace.h"
fc61b800 40#include "x86.h"
97222cc8 41
b682b814
MT		 42#ifndef CONFIG_X86_64
43#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
44#else
45#define mod_64(x, y) ((x) % (y))
46#endif
47
97222cc8
ED		 48#define PRId64 "d"
49#define PRIx64 "llx"
50#define PRIu64 "u"
51#define PRIo64 "o"
52
53#define APIC_BUS_CYCLE_NS 1
54
55/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
56#define apic_debug(fmt, arg...)
57
58#define APIC_LVT_NUM 6
59/* 14 is the version for Xeon and Pentium 8.4.8*/
60#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
61#define LAPIC_MMIO_LENGTH (1 << 12)
62/* followed define is not in apicdef.h */
63#define APIC_SHORT_MASK 0xc0000
64#define APIC_DEST_NOSHORT 0x0
65#define APIC_DEST_MASK 0x800
66#define MAX_APIC_VECTOR 256
67
68#define VEC_POS(v) ((v) & (32 - 1))
69#define REG_POS(v) (((v) >> 5) << 4)
ad312c7c 70
97222cc8
ED		 71static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
72{
73 return *((u32 *) (apic->regs + reg_off));
74}
75
76static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
77{
78 *((u32 *) (apic->regs + reg_off)) = val;
79}
80
81static inline int apic_test_and_set_vector(int vec, void *bitmap)
82{
83 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
84}
85
86static inline int apic_test_and_clear_vector(int vec, void *bitmap)
87{
88 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
89}
90
91static inline void apic_set_vector(int vec, void *bitmap)
92{
93 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
94}
95
96static inline void apic_clear_vector(int vec, void *bitmap)
97{
98 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
99}
100
101static inline int apic_hw_enabled(struct kvm_lapic *apic)
102{
ad312c7c 103 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
97222cc8
ED		 104}
105
106static inline int apic_sw_enabled(struct kvm_lapic *apic)
107{
108 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
109}
110
111static inline int apic_enabled(struct kvm_lapic *apic)
112{
113 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
114}
115
116#define LVT_MASK \
117 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
118
119#define LINT_MASK \
120 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
121 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
122
123static inline int kvm_apic_id(struct kvm_lapic *apic)
124{
125 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
126}
127
128static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
129{
130 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
131}
132
133static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
134{
135 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
136}
137
138static inline int apic_lvtt_period(struct kvm_lapic *apic)
139{
140 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
141}
142
cc6e462c
JK		 143static inline int apic_lvt_nmi_mode(u32 lvt_val)
144{
145 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
146}
147
fc61b800
GN		 148void kvm_apic_set_version(struct kvm_vcpu *vcpu)
149{
150 struct kvm_lapic *apic = vcpu->arch.apic;
151 struct kvm_cpuid_entry2 *feat;
152 u32 v = APIC_VERSION;
153
154 if (!irqchip_in_kernel(vcpu->kvm))
155 return;
156
157 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
158 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
159 v |= APIC_LVR_DIRECTED_EOI;
160 apic_set_reg(apic, APIC_LVR, v);
161}
162
0105d1a5
GN		 163static inline int apic_x2apic_mode(struct kvm_lapic *apic)
164{
165 return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
166}
167
97222cc8
ED		 168static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
169 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
170 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
171 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
172 LINT_MASK, LINT_MASK, /* LVT0-1 */
173 LVT_MASK /* LVTERR */
174};
175
176static int find_highest_vector(void *bitmap)
177{
178 u32 *word = bitmap;
179 int word_offset = MAX_APIC_VECTOR >> 5;
180
181 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
182 continue;
183
184 if (likely(!word_offset && !word[0]))
185 return -1;
186 else
187 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
188}
189
190static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
191{
33e4c686 192 apic->irr_pending = true;
97222cc8
ED		 193 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
194}
195
33e4c686 196static inline int apic_search_irr(struct kvm_lapic *apic)
97222cc8 197{
33e4c686 198 return find_highest_vector(apic->regs + APIC_IRR);
97222cc8
ED		 199}
200
201static inline int apic_find_highest_irr(struct kvm_lapic *apic)
202{
203 int result;
204
33e4c686
GN		 205 if (!apic->irr_pending)
206 return -1;
207
208 result = apic_search_irr(apic);
97222cc8
ED		 209 ASSERT(result == -1 || result >= 16);
210
211 return result;
212}
213
33e4c686
GN		 214static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
215{
216 apic->irr_pending = false;
217 apic_clear_vector(vec, apic->regs + APIC_IRR);
218 if (apic_search_irr(apic) != -1)
219 apic->irr_pending = true;
220}
221
6e5d865c
YS		 222int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
223{
ad312c7c 224 struct kvm_lapic *apic = vcpu->arch.apic;
6e5d865c
YS		 225 int highest_irr;
226
33e4c686
GN		 227 /* This may race with setting of irr in __apic_accept_irq() and
228 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
229 * will cause vmexit immediately and the value will be recalculated
230 * on the next vmentry.
231 */
6e5d865c
YS		 232 if (!apic)
233 return 0;
234 highest_irr = apic_find_highest_irr(apic);
235
236 return highest_irr;
237}
6e5d865c 238
6da7e3f6
GN		 239static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
240 int vector, int level, int trig_mode);
241
58c2dde1 242int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
97222cc8 243{
ad312c7c 244 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 245
58c2dde1
GN		 246 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
247 irq->level, irq->trig_mode);
97222cc8
ED		 248}
249
250static inline int apic_find_highest_isr(struct kvm_lapic *apic)
251{
252 int result;
253
254 result = find_highest_vector(apic->regs + APIC_ISR);
255 ASSERT(result == -1 || result >= 16);
256
257 return result;
258}
259
260static void apic_update_ppr(struct kvm_lapic *apic)
261{
3842d135 262 u32 tpr, isrv, ppr, old_ppr;
97222cc8
ED		 263 int isr;
264
3842d135 265 old_ppr = apic_get_reg(apic, APIC_PROCPRI);
97222cc8
ED		 266 tpr = apic_get_reg(apic, APIC_TASKPRI);
267 isr = apic_find_highest_isr(apic);
268 isrv = (isr != -1) ? isr : 0;
269
270 if ((tpr & 0xf0) >= (isrv & 0xf0))
271 ppr = tpr & 0xff;
272 else
273 ppr = isrv & 0xf0;
274
275 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
276 apic, ppr, isr, isrv);
277
3842d135
AK		 278 if (old_ppr != ppr) {
279 apic_set_reg(apic, APIC_PROCPRI, ppr);
83bcacb1
AK		 280 if (ppr < old_ppr)
281 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
3842d135 282 }
97222cc8
ED		 283}
284
285static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
286{
287 apic_set_reg(apic, APIC_TASKPRI, tpr);
288 apic_update_ppr(apic);
289}
290
291int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
292{
343f94fe 293 return dest == 0xff || kvm_apic_id(apic) == dest;
97222cc8
ED		 294}
295
296int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
297{
298 int result = 0;
0105d1a5
GN		 299 u32 logical_id;
300
301 if (apic_x2apic_mode(apic)) {
302 logical_id = apic_get_reg(apic, APIC_LDR);
303 return logical_id & mda;
304 }
97222cc8
ED		 305
306 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
307
308 switch (apic_get_reg(apic, APIC_DFR)) {
309 case APIC_DFR_FLAT:
310 if (logical_id & mda)
311 result = 1;
312 break;
313 case APIC_DFR_CLUSTER:
314 if (((logical_id >> 4) == (mda >> 0x4))
315 && (logical_id & mda & 0xf))
316 result = 1;
317 break;
318 default:
7712de87
JK		 319 apic_debug("Bad DFR vcpu %d: %08x\n",
320 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
97222cc8
ED		 321 break;
322 }
323
324 return result;
325}
326
343f94fe 327int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
97222cc8
ED		 328 int short_hand, int dest, int dest_mode)
329{
330 int result = 0;
ad312c7c 331 struct kvm_lapic *target = vcpu->arch.apic;
97222cc8
ED		 332
333 apic_debug("target %p, source %p, dest 0x%x, "
343f94fe 334 "dest_mode 0x%x, short_hand 0x%x\n",
97222cc8
ED		 335 target, source, dest, dest_mode, short_hand);
336
bd371396 337 ASSERT(target);
97222cc8
ED		 338 switch (short_hand) {
339 case APIC_DEST_NOSHORT:
343f94fe 340 if (dest_mode == 0)
97222cc8 341 /* Physical mode. */
343f94fe
GN		 342 result = kvm_apic_match_physical_addr(target, dest);
343 else
97222cc8
ED		 344 /* Logical mode. */
345 result = kvm_apic_match_logical_addr(target, dest);
346 break;
347 case APIC_DEST_SELF:
343f94fe 348 result = (target == source);
97222cc8
ED		 349 break;
350 case APIC_DEST_ALLINC:
351 result = 1;
352 break;
353 case APIC_DEST_ALLBUT:
343f94fe 354 result = (target != source);
97222cc8
ED		 355 break;
356 default:
7712de87
JK		 357 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
358 short_hand);
97222cc8
ED		 359 break;
360 }
361
362 return result;
363}
364
365/*
366 * Add a pending IRQ into lapic.
367 * Return 1 if successfully added and 0 if discarded.
368 */
369static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
370 int vector, int level, int trig_mode)
371{
6da7e3f6 372 int result = 0;
c5ec1534 373 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8
ED		 374
375 switch (delivery_mode) {
97222cc8 376 case APIC_DM_LOWEST:
e1035715
GN		 377 vcpu->arch.apic_arb_prio++;
378 case APIC_DM_FIXED:
97222cc8
ED		 379 /* FIXME add logic for vcpu on reset */
380 if (unlikely(!apic_enabled(apic)))
381 break;
382
a5d36f82
AK		 383 if (trig_mode) {
384 apic_debug("level trig mode for vector %d", vector);
385 apic_set_vector(vector, apic->regs + APIC_TMR);
386 } else
387 apic_clear_vector(vector, apic->regs + APIC_TMR);
388
6da7e3f6 389 result = !apic_test_and_set_irr(vector, apic);
1000ff8d 390 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
4da74896 391 trig_mode, vector, !result);
6da7e3f6
GN		 392 if (!result) {
393 if (trig_mode)
394 apic_debug("level trig mode repeatedly for "
395 "vector %d", vector);
97222cc8
ED		 396 break;
397 }
398
3842d135 399 kvm_make_request(KVM_REQ_EVENT, vcpu);
d7690175 400 kvm_vcpu_kick(vcpu);
97222cc8
ED		 401 break;
402
403 case APIC_DM_REMRD:
7712de87 404 apic_debug("Ignoring delivery mode 3\n");
97222cc8
ED		 405 break;
406
407 case APIC_DM_SMI:
7712de87 408 apic_debug("Ignoring guest SMI\n");
97222cc8 409 break;
3419ffc8 410
97222cc8 411 case APIC_DM_NMI:
6da7e3f6 412 result = 1;
3419ffc8 413 kvm_inject_nmi(vcpu);
26df99c6 414 kvm_vcpu_kick(vcpu);
97222cc8
ED		 415 break;
416
417 case APIC_DM_INIT:
c5ec1534 418 if (level) {
6da7e3f6 419 result = 1;
a4535290 420 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
3842d135 421 kvm_make_request(KVM_REQ_EVENT, vcpu);
c5ec1534
HQ		 422 kvm_vcpu_kick(vcpu);
423 } else {
1b10bf31
JK		 424 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
425 vcpu->vcpu_id);
c5ec1534 426 }
97222cc8
ED		 427 break;
428
429 case APIC_DM_STARTUP:
1b10bf31
JK		 430 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
431 vcpu->vcpu_id, vector);
a4535290 432 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6da7e3f6 433 result = 1;
ad312c7c 434 vcpu->arch.sipi_vector = vector;
a4535290 435 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
3842d135 436 kvm_make_request(KVM_REQ_EVENT, vcpu);
d7690175 437 kvm_vcpu_kick(vcpu);
c5ec1534 438 }
97222cc8
ED		 439 break;
440
23930f95
JK		 441 case APIC_DM_EXTINT:
442 /*
443 * Should only be called by kvm_apic_local_deliver() with LVT0,
444 * before NMI watchdog was enabled. Already handled by
445 * kvm_apic_accept_pic_intr().
446 */
447 break;
448
97222cc8
ED		 449 default:
450 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
451 delivery_mode);
452 break;
453 }
454 return result;
455}
456
e1035715 457int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
8be5453f 458{
e1035715 459 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
8be5453f
ZX		 460}
461
97222cc8
ED		 462static void apic_set_eoi(struct kvm_lapic *apic)
463{
464 int vector = apic_find_highest_isr(apic);
f5244726 465 int trigger_mode;
97222cc8
ED		 466 /*
467 * Not every write EOI will has corresponding ISR,
468 * one example is when Kernel check timer on setup_IO_APIC
469 */
470 if (vector == -1)
471 return;
472
473 apic_clear_vector(vector, apic->regs + APIC_ISR);
474 apic_update_ppr(apic);
475
476 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
f5244726
MT		 477 trigger_mode = IOAPIC_LEVEL_TRIG;
478 else
479 trigger_mode = IOAPIC_EDGE_TRIG;
eba0226b 480 if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI))
fc61b800 481 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
3842d135 482 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
97222cc8
ED		 483}
484
485static void apic_send_ipi(struct kvm_lapic *apic)
486{
487 u32 icr_low = apic_get_reg(apic, APIC_ICR);
488 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
58c2dde1 489 struct kvm_lapic_irq irq;
97222cc8 490
58c2dde1
GN		 491 irq.vector = icr_low & APIC_VECTOR_MASK;
492 irq.delivery_mode = icr_low & APIC_MODE_MASK;
493 irq.dest_mode = icr_low & APIC_DEST_MASK;
494 irq.level = icr_low & APIC_INT_ASSERT;
495 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
496 irq.shorthand = icr_low & APIC_SHORT_MASK;
0105d1a5
GN		 497 if (apic_x2apic_mode(apic))
498 irq.dest_id = icr_high;
499 else
500 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
97222cc8 501
1000ff8d
GN		 502 trace_kvm_apic_ipi(icr_low, irq.dest_id);
503
97222cc8
ED		 504 apic_debug("icr_high 0x%x, icr_low 0x%x, "
505 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
506 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
9b5843dd 507 icr_high, icr_low, irq.shorthand, irq.dest_id,
58c2dde1
GN		 508 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
509 irq.vector);
510
511 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
97222cc8
ED		 512}
513
514static u32 apic_get_tmcct(struct kvm_lapic *apic)
515{
b682b814
MT		 516 ktime_t remaining;
517 s64 ns;
9da8f4e8 518 u32 tmcct;
97222cc8
ED		 519
520 ASSERT(apic != NULL);
521
9da8f4e8 522 /* if initial count is 0, current count should also be 0 */
b682b814 523 if (apic_get_reg(apic, APIC_TMICT) == 0)
9da8f4e8
KP		 524 return 0;
525
ace15464 526 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
b682b814
MT		 527 if (ktime_to_ns(remaining) < 0)
528 remaining = ktime_set(0, 0);
529
d3c7b77d
MT		 530 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
531 tmcct = div64_u64(ns,
532 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 533
534 return tmcct;
535}
536
b209749f
AK		 537static void __report_tpr_access(struct kvm_lapic *apic, bool write)
538{
539 struct kvm_vcpu *vcpu = apic->vcpu;
540 struct kvm_run *run = vcpu->run;
541
a8eeb04a 542 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
5fdbf976 543 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 544 run->tpr_access.is_write = write;
545}
546
547static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
548{
549 if (apic->vcpu->arch.tpr_access_reporting)
550 __report_tpr_access(apic, write);
551}
552
97222cc8
ED		 553static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
554{
555 u32 val = 0;
556
557 if (offset >= LAPIC_MMIO_LENGTH)
558 return 0;
559
560 switch (offset) {
0105d1a5
GN		 561 case APIC_ID:
562 if (apic_x2apic_mode(apic))
563 val = kvm_apic_id(apic);
564 else
565 val = kvm_apic_id(apic) << 24;
566 break;
97222cc8 567 case APIC_ARBPRI:
7712de87 568 apic_debug("Access APIC ARBPRI register which is for P6\n");
97222cc8
ED		 569 break;
570
571 case APIC_TMCCT: /* Timer CCR */
572 val = apic_get_tmcct(apic);
573 break;
574
b209749f
AK		 575 case APIC_TASKPRI:
576 report_tpr_access(apic, false);
577 /* fall thru */
97222cc8 578 default:
6e5d865c 579 apic_update_ppr(apic);
97222cc8
ED		 580 val = apic_get_reg(apic, offset);
581 break;
582 }
583
584 return val;
585}
586
d76685c4
GH		 587static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
588{
589 return container_of(dev, struct kvm_lapic, dev);
590}
591
0105d1a5
GN		 592static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
593 void *data)
97222cc8 594{
97222cc8
ED		 595 unsigned char alignment = offset & 0xf;
596 u32 result;
0105d1a5
GN		 597 /* this bitmask has a bit cleared for each reserver register */
598 static const u64 rmask = 0x43ff01ffffffe70cULL;
97222cc8
ED		 599
600 if ((alignment + len) > 4) {
4088bb3c
GN		 601 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
602 offset, len);
0105d1a5 603 return 1;
97222cc8 604 }
0105d1a5
GN		 605
606 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
4088bb3c
GN		 607 apic_debug("KVM_APIC_READ: read reserved register %x\n",
608 offset);
0105d1a5
GN		 609 return 1;
610 }
611
97222cc8
ED		 612 result = __apic_read(apic, offset & ~0xf);
613
229456fc
MT		 614 trace_kvm_apic_read(offset, result);
615
97222cc8
ED		 616 switch (len) {
617 case 1:
618 case 2:
619 case 4:
620 memcpy(data, (char *)&result + alignment, len);
621 break;
622 default:
623 printk(KERN_ERR "Local APIC read with len = %x, "
624 "should be 1,2, or 4 instead\n", len);
625 break;
626 }
bda9020e 627 return 0;
97222cc8
ED		 628}
629
0105d1a5
GN		 630static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
631{
632 return apic_hw_enabled(apic) &&
633 addr >= apic->base_address &&
634 addr < apic->base_address + LAPIC_MMIO_LENGTH;
635}
636
637static int apic_mmio_read(struct kvm_io_device *this,
638 gpa_t address, int len, void *data)
639{
640 struct kvm_lapic *apic = to_lapic(this);
641 u32 offset = address - apic->base_address;
642
643 if (!apic_mmio_in_range(apic, address))
644 return -EOPNOTSUPP;
645
646 apic_reg_read(apic, offset, len, data);
647
648 return 0;
649}
650
97222cc8
ED		 651static void update_divide_count(struct kvm_lapic *apic)
652{
653 u32 tmp1, tmp2, tdcr;
654
655 tdcr = apic_get_reg(apic, APIC_TDCR);
656 tmp1 = tdcr & 0xf;
657 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 658 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 659
660 apic_debug("timer divide count is 0x%x\n",
9b5843dd 661 apic->divide_count);
97222cc8
ED		 662}
663
664static void start_apic_timer(struct kvm_lapic *apic)
665{
d3c7b77d 666 ktime_t now = apic->lapic_timer.timer.base->get_time();
97222cc8 667
b2d83cfa 668 apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT) *
d3c7b77d
MT		 669 APIC_BUS_CYCLE_NS * apic->divide_count;
670 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 671
d3c7b77d 672 if (!apic->lapic_timer.period)
0b975a3c 673 return;
1444885a
MT		 674 /*
675 * Do not allow the guest to program periodic timers with small
676 * interval, since the hrtimers are not throttled by the host
677 * scheduler.
678 */
679 if (apic_lvtt_period(apic)) {
680 if (apic->lapic_timer.period < NSEC_PER_MSEC/2)
681 apic->lapic_timer.period = NSEC_PER_MSEC/2;
682 }
0b975a3c 683
d3c7b77d
MT		 684 hrtimer_start(&apic->lapic_timer.timer,
685 ktime_add_ns(now, apic->lapic_timer.period),
97222cc8
ED		 686 HRTIMER_MODE_ABS);
687
688 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
689 PRIx64 ", "
690 "timer initial count 0x%x, period %lldns, "
b8688d51 691 "expire @ 0x%016" PRIx64 ".\n", __func__,
97222cc8
ED		 692 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
693 apic_get_reg(apic, APIC_TMICT),
d3c7b77d 694 apic->lapic_timer.period,
97222cc8 695 ktime_to_ns(ktime_add_ns(now,
d3c7b77d 696 apic->lapic_timer.period)));
97222cc8
ED		 697}
698
cc6e462c
JK		 699static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
700{
701 int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
702
703 if (apic_lvt_nmi_mode(lvt0_val)) {
704 if (!nmi_wd_enabled) {
705 apic_debug("Receive NMI setting on APIC_LVT0 "
706 "for cpu %d\n", apic->vcpu->vcpu_id);
707 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
708 }
709 } else if (nmi_wd_enabled)
710 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
711}
712
0105d1a5 713static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
97222cc8 714{
0105d1a5 715 int ret = 0;
97222cc8 716
0105d1a5 717 trace_kvm_apic_write(reg, val);
97222cc8 718
0105d1a5 719 switch (reg) {
97222cc8 720 case APIC_ID: /* Local APIC ID */
0105d1a5
GN		 721 if (!apic_x2apic_mode(apic))
722 apic_set_reg(apic, APIC_ID, val);
723 else
724 ret = 1;
97222cc8
ED		 725 break;
726
727 case APIC_TASKPRI:
b209749f 728 report_tpr_access(apic, true);
97222cc8
ED		 729 apic_set_tpr(apic, val & 0xff);
730 break;
731
732 case APIC_EOI:
733 apic_set_eoi(apic);
734 break;
735
736 case APIC_LDR:
0105d1a5
GN		 737 if (!apic_x2apic_mode(apic))
738 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
739 else
740 ret = 1;
97222cc8
ED		 741 break;
742
743 case APIC_DFR:
0105d1a5
GN		 744 if (!apic_x2apic_mode(apic))
745 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
746 else
747 ret = 1;
97222cc8
ED		 748 break;
749
fc61b800
GN		 750 case APIC_SPIV: {
751 u32 mask = 0x3ff;
752 if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
753 mask |= APIC_SPIV_DIRECTED_EOI;
754 apic_set_reg(apic, APIC_SPIV, val & mask);
97222cc8
ED		 755 if (!(val & APIC_SPIV_APIC_ENABLED)) {
756 int i;
757 u32 lvt_val;
758
759 for (i = 0; i < APIC_LVT_NUM; i++) {
760 lvt_val = apic_get_reg(apic,
761 APIC_LVTT + 0x10 * i);
762 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
763 lvt_val | APIC_LVT_MASKED);
764 }
d3c7b77d 765 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 766
767 }
768 break;
fc61b800 769 }
97222cc8
ED		 770 case APIC_ICR:
771 /* No delay here, so we always clear the pending bit */
772 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
773 apic_send_ipi(apic);
774 break;
775
776 case APIC_ICR2:
0105d1a5
GN		 777 if (!apic_x2apic_mode(apic))
778 val &= 0xff000000;
779 apic_set_reg(apic, APIC_ICR2, val);
97222cc8
ED		 780 break;
781
23930f95 782 case APIC_LVT0:
cc6e462c 783 apic_manage_nmi_watchdog(apic, val);
97222cc8
ED		 784 case APIC_LVTT:
785 case APIC_LVTTHMR:
786 case APIC_LVTPC:
97222cc8
ED		 787 case APIC_LVT1:
788 case APIC_LVTERR:
789 /* TODO: Check vector */
790 if (!apic_sw_enabled(apic))
791 val |= APIC_LVT_MASKED;
792
0105d1a5
GN		 793 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
794 apic_set_reg(apic, reg, val);
97222cc8
ED		 795
796 break;
797
798 case APIC_TMICT:
d3c7b77d 799 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 800 apic_set_reg(apic, APIC_TMICT, val);
801 start_apic_timer(apic);
0105d1a5 802 break;
97222cc8
ED		 803
804 case APIC_TDCR:
805 if (val & 4)
7712de87 806 apic_debug("KVM_WRITE:TDCR %x\n", val);
97222cc8
ED		 807 apic_set_reg(apic, APIC_TDCR, val);
808 update_divide_count(apic);
809 break;
810
0105d1a5
GN		 811 case APIC_ESR:
812 if (apic_x2apic_mode(apic) && val != 0) {
7712de87 813 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
0105d1a5
GN		 814 ret = 1;
815 }
816 break;
817
818 case APIC_SELF_IPI:
819 if (apic_x2apic_mode(apic)) {
820 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
821 } else
822 ret = 1;
823 break;
97222cc8 824 default:
0105d1a5 825 ret = 1;
97222cc8
ED		 826 break;
827 }
0105d1a5
GN		 828 if (ret)
829 apic_debug("Local APIC Write to read-only register %x\n", reg);
830 return ret;
831}
832
833static int apic_mmio_write(struct kvm_io_device *this,
834 gpa_t address, int len, const void *data)
835{
836 struct kvm_lapic *apic = to_lapic(this);
837 unsigned int offset = address - apic->base_address;
838 u32 val;
839
840 if (!apic_mmio_in_range(apic, address))
841 return -EOPNOTSUPP;
842
843 /*
844 * APIC register must be aligned on 128-bits boundary.
845 * 32/64/128 bits registers must be accessed thru 32 bits.
846 * Refer SDM 8.4.1
847 */
848 if (len != 4 || (offset & 0xf)) {
849 /* Don't shout loud, $infamous_os would cause only noise. */
850 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
756975bb 851 return 0;
0105d1a5
GN		 852 }
853
854 val = *(u32*)data;
855
856 /* too common printing */
857 if (offset != APIC_EOI)
858 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
859 "0x%x\n", __func__, offset, len, val);
860
861 apic_reg_write(apic, offset & 0xff0, val);
862
bda9020e 863 return 0;
97222cc8
ED		 864}
865
58fbbf26
KT		 866void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
867{
868 struct kvm_lapic *apic = vcpu->arch.apic;
869
870 if (apic)
871 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
872}
873EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
874
d589444e 875void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 876{
ad312c7c 877 if (!vcpu->arch.apic)
97222cc8
ED		 878 return;
879
d3c7b77d 880 hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
97222cc8 881
afc20184
TY		 882 if (vcpu->arch.apic->regs)
883 free_page((unsigned long)vcpu->arch.apic->regs);
97222cc8 884
ad312c7c 885 kfree(vcpu->arch.apic);
97222cc8
ED		 886}
887
888/*
889 *----------------------------------------------------------------------
890 * LAPIC interface
891 *----------------------------------------------------------------------
892 */
893
894void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
895{
ad312c7c 896 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 897
898 if (!apic)
899 return;
b93463aa
AK		 900 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
901 | (apic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8
ED		 902}
903
904u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
905{
ad312c7c 906 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 907 u64 tpr;
908
909 if (!apic)
910 return 0;
911 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
912
913 return (tpr & 0xf0) >> 4;
914}
915
916void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
917{
ad312c7c 918 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 919
920 if (!apic) {
921 value |= MSR_IA32_APICBASE_BSP;
ad312c7c 922 vcpu->arch.apic_base = value;
97222cc8
ED		 923 return;
924 }
c5af89b6
GN		 925
926 if (!kvm_vcpu_is_bsp(apic->vcpu))
97222cc8
ED		 927 value &= ~MSR_IA32_APICBASE_BSP;
928
ad312c7c 929 vcpu->arch.apic_base = value;
0105d1a5
GN		 930 if (apic_x2apic_mode(apic)) {
931 u32 id = kvm_apic_id(apic);
932 u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
933 apic_set_reg(apic, APIC_LDR, ldr);
934 }
ad312c7c 935 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 936 MSR_IA32_APICBASE_BASE;
937
938 /* with FSB delivery interrupt, we can restart APIC functionality */
939 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
ad312c7c 940 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 941
942}
943
c5ec1534 944void kvm_lapic_reset(struct kvm_vcpu *vcpu)
97222cc8
ED		 945{
946 struct kvm_lapic *apic;
947 int i;
948
b8688d51 949 apic_debug("%s\n", __func__);
97222cc8
ED		 950
951 ASSERT(vcpu);
ad312c7c 952 apic = vcpu->arch.apic;
97222cc8
ED		 953 ASSERT(apic != NULL);
954
955 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 956 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 957
958 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
fc61b800 959 kvm_apic_set_version(apic->vcpu);
97222cc8
ED		 960
961 for (i = 0; i < APIC_LVT_NUM; i++)
962 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
40487c68
QH		 963 apic_set_reg(apic, APIC_LVT0,
964 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
97222cc8
ED		 965
966 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
967 apic_set_reg(apic, APIC_SPIV, 0xff);
968 apic_set_reg(apic, APIC_TASKPRI, 0);
969 apic_set_reg(apic, APIC_LDR, 0);
970 apic_set_reg(apic, APIC_ESR, 0);
971 apic_set_reg(apic, APIC_ICR, 0);
972 apic_set_reg(apic, APIC_ICR2, 0);
973 apic_set_reg(apic, APIC_TDCR, 0);
974 apic_set_reg(apic, APIC_TMICT, 0);
975 for (i = 0; i < 8; i++) {
976 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
977 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
978 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
979 }
33e4c686 980 apic->irr_pending = false;
b33ac88b 981 update_divide_count(apic);
d3c7b77d 982 atomic_set(&apic->lapic_timer.pending, 0);
c5af89b6 983 if (kvm_vcpu_is_bsp(vcpu))
ad312c7c 984 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
97222cc8
ED		 985 apic_update_ppr(apic);
986
e1035715
GN		 987 vcpu->arch.apic_arb_prio = 0;
988
97222cc8 989 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
b8688d51 990 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
97222cc8 991 vcpu, kvm_apic_id(apic),
ad312c7c 992 vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 993}
994
343f94fe 995bool kvm_apic_present(struct kvm_vcpu *vcpu)
97222cc8 996{
343f94fe
GN		 997 return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
998}
97222cc8 999
343f94fe
GN		 1000int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
1001{
1002 return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
97222cc8
ED		 1003}
1004
1005/*
1006 *----------------------------------------------------------------------
1007 * timer interface
1008 *----------------------------------------------------------------------
1009 */
1b9778da 1010
d3c7b77d 1011static bool lapic_is_periodic(struct kvm_timer *ktimer)
97222cc8 1012{
d3c7b77d
MT		 1013 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
1014 lapic_timer);
1015 return apic_lvtt_period(apic);
97222cc8
ED		 1016}
1017
3d80840d
MT		 1018int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1019{
1020 struct kvm_lapic *lapic = vcpu->arch.apic;
1021
54aaacee 1022 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
d3c7b77d 1023 return atomic_read(&lapic->lapic_timer.pending);
3d80840d
MT		 1024
1025 return 0;
1026}
1027
8fdb2351 1028static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 1029{
8fdb2351 1030 u32 reg = apic_get_reg(apic, lvt_type);
23930f95 1031 int vector, mode, trig_mode;
23930f95 1032
8fdb2351 1033 if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 1034 vector = reg & APIC_VECTOR_MASK;
1035 mode = reg & APIC_MODE_MASK;
1036 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1037 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
1038 }
1039 return 0;
1040}
1b9778da 1041
8fdb2351 1042void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 1043{
8fdb2351
JK		 1044 struct kvm_lapic *apic = vcpu->arch.apic;
1045
1046 if (apic)
1047 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 1048}
1049
386eb6e8 1050static struct kvm_timer_ops lapic_timer_ops = {
d3c7b77d
MT		 1051 .is_periodic = lapic_is_periodic,
1052};
97222cc8 1053
d76685c4
GH		 1054static const struct kvm_io_device_ops apic_mmio_ops = {
1055 .read = apic_mmio_read,
1056 .write = apic_mmio_write,
d76685c4
GH		 1057};
1058
97222cc8
ED		 1059int kvm_create_lapic(struct kvm_vcpu *vcpu)
1060{
1061 struct kvm_lapic *apic;
1062
1063 ASSERT(vcpu != NULL);
1064 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1065
1066 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1067 if (!apic)
1068 goto nomem;
1069
ad312c7c 1070 vcpu->arch.apic = apic;
97222cc8 1071
afc20184
TY		 1072 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1073 if (!apic->regs) {
97222cc8
ED		 1074 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1075 vcpu->vcpu_id);
d589444e 1076 goto nomem_free_apic;
97222cc8 1077 }
97222cc8
ED		 1078 apic->vcpu = vcpu;
1079
d3c7b77d
MT		 1080 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1081 HRTIMER_MODE_ABS);
1082 apic->lapic_timer.timer.function = kvm_timer_fn;
1083 apic->lapic_timer.t_ops = &lapic_timer_ops;
1084 apic->lapic_timer.kvm = vcpu->kvm;
1ed0ce00 1085 apic->lapic_timer.vcpu = vcpu;
d3c7b77d 1086
97222cc8 1087 apic->base_address = APIC_DEFAULT_PHYS_BASE;
ad312c7c 1088 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
97222cc8 1089
c5ec1534 1090 kvm_lapic_reset(vcpu);
d76685c4 1091 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
97222cc8
ED		 1092
1093 return 0;
d589444e
RR		 1094nomem_free_apic:
1095 kfree(apic);
97222cc8 1096nomem:
97222cc8
ED		 1097 return -ENOMEM;
1098}
97222cc8
ED		 1099
1100int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1101{
ad312c7c 1102 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1103 int highest_irr;
1104
1105 if (!apic || !apic_enabled(apic))
1106 return -1;
1107
6e5d865c 1108 apic_update_ppr(apic);
97222cc8
ED		 1109 highest_irr = apic_find_highest_irr(apic);
1110 if ((highest_irr == -1) ||
1111 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1112 return -1;
1113 return highest_irr;
1114}
1115
40487c68
QH		 1116int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1117{
ad312c7c 1118 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 1119 int r = 0;
1120
e7dca5c0
CL		 1121 if (!apic_hw_enabled(vcpu->arch.apic))
1122 r = 1;
1123 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1124 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1125 r = 1;
40487c68
QH		 1126 return r;
1127}
1128
1b9778da
ED		 1129void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1130{
ad312c7c 1131 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 1132
d3c7b77d 1133 if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
8fdb2351 1134 if (kvm_apic_local_deliver(apic, APIC_LVTT))
d3c7b77d 1135 atomic_dec(&apic->lapic_timer.pending);
1b9778da
ED		 1136 }
1137}
1138
97222cc8
ED		 1139int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1140{
1141 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 1142 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1143
1144 if (vector == -1)
1145 return -1;
1146
1147 apic_set_vector(vector, apic->regs + APIC_ISR);
1148 apic_update_ppr(apic);
1149 apic_clear_irr(vector, apic);
1150 return vector;
1151}
96ad2cc6
ED		 1152
1153void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1154{
ad312c7c 1155 struct kvm_lapic *apic = vcpu->arch.apic;
96ad2cc6 1156
ad312c7c 1157 apic->base_address = vcpu->arch.apic_base &
96ad2cc6 1158 MSR_IA32_APICBASE_BASE;
fc61b800
GN		 1159 kvm_apic_set_version(vcpu);
1160
96ad2cc6 1161 apic_update_ppr(apic);
d3c7b77d 1162 hrtimer_cancel(&apic->lapic_timer.timer);
96ad2cc6
ED		 1163 update_divide_count(apic);
1164 start_apic_timer(apic);
6e24a6ef 1165 apic->irr_pending = true;
3842d135 1166 kvm_make_request(KVM_REQ_EVENT, vcpu);
96ad2cc6 1167}
a3d7f85f 1168
2f52d58c 1169void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 1170{
ad312c7c 1171 struct kvm_lapic *apic = vcpu->arch.apic;
a3d7f85f
ED		 1172 struct hrtimer *timer;
1173
1174 if (!apic)
1175 return;
1176
d3c7b77d 1177 timer = &apic->lapic_timer.timer;
a3d7f85f 1178 if (hrtimer_cancel(timer))
beb20d52 1179 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
a3d7f85f 1180}
b93463aa
AK		 1181
1182void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1183{
1184 u32 data;
1185 void *vapic;
1186
1187 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1188 return;
1189
1190 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1191 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1192 kunmap_atomic(vapic, KM_USER0);
1193
1194 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1195}
1196
1197void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1198{
1199 u32 data, tpr;
1200 int max_irr, max_isr;
1201 struct kvm_lapic *apic;
1202 void *vapic;
1203
1204 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1205 return;
1206
1207 apic = vcpu->arch.apic;
1208 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1209 max_irr = apic_find_highest_irr(apic);
1210 if (max_irr < 0)
1211 max_irr = 0;
1212 max_isr = apic_find_highest_isr(apic);
1213 if (max_isr < 0)
1214 max_isr = 0;
1215 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1216
1217 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1218 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1219 kunmap_atomic(vapic, KM_USER0);
1220}
1221
1222void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1223{
1224 if (!irqchip_in_kernel(vcpu->kvm))
1225 return;
1226
1227 vcpu->arch.apic->vapic_addr = vapic_addr;
1228}
0105d1a5
GN		 1229
1230int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1231{
1232 struct kvm_lapic *apic = vcpu->arch.apic;
1233 u32 reg = (msr - APIC_BASE_MSR) << 4;
1234
1235 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1236 return 1;
1237
1238 /* if this is ICR write vector before command */
1239 if (msr == 0x830)
1240 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1241 return apic_reg_write(apic, reg, (u32)data);
1242}
1243
1244int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1245{
1246 struct kvm_lapic *apic = vcpu->arch.apic;
1247 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1248
1249 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1250 return 1;
1251
1252 if (apic_reg_read(apic, reg, 4, &low))
1253 return 1;
1254 if (msr == 0x830)
1255 apic_reg_read(apic, APIC_ICR2, 4, &high);
1256
1257 *data = (((u64)high) << 32) | low;
1258
1259 return 0;
1260}
10388a07
GN		 1261
1262int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1263{
1264 struct kvm_lapic *apic = vcpu->arch.apic;
1265
1266 if (!irqchip_in_kernel(vcpu->kvm))
1267 return 1;
1268
1269 /* if this is ICR write vector before command */
1270 if (reg == APIC_ICR)
1271 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1272 return apic_reg_write(apic, reg, (u32)data);
1273}
1274
1275int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1276{
1277 struct kvm_lapic *apic = vcpu->arch.apic;
1278 u32 low, high = 0;
1279
1280 if (!irqchip_in_kernel(vcpu->kvm))
1281 return 1;
1282
1283 if (apic_reg_read(apic, reg, 4, &low))
1284 return 1;
1285 if (reg == APIC_ICR)
1286 apic_reg_read(apic, APIC_ICR2, 4, &high);
1287
1288 *data = (((u64)high) << 32) | low;
1289
1290 return 0;
1291}
Linux kernel - Deliverables
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