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KVM: x86: Fix reserved x2apic registers
[deliverable/linux.git] / arch / x86 / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
9611c187 8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
97222cc8
ED		 9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
edf88417 21#include <linux/kvm_host.h>
97222cc8
ED		 22#include <linux/kvm.h>
23#include <linux/mm.h>
24#include <linux/highmem.h>
25#include <linux/smp.h>
26#include <linux/hrtimer.h>
27#include <linux/io.h>
28#include <linux/module.h>
6f6d6a1a 29#include <linux/math64.h>
5a0e3ad6 30#include <linux/slab.h>
97222cc8
ED		 31#include <asm/processor.h>
32#include <asm/msr.h>
33#include <asm/page.h>
34#include <asm/current.h>
35#include <asm/apicdef.h>
60063497 36#include <linux/atomic.h>
c5cc421b 37#include <linux/jump_label.h>
5fdbf976 38#include "kvm_cache_regs.h"
97222cc8 39#include "irq.h"
229456fc 40#include "trace.h"
fc61b800 41#include "x86.h"
00b27a3e 42#include "cpuid.h"
97222cc8 43
b682b814
MT		 44#ifndef CONFIG_X86_64
45#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
46#else
47#define mod_64(x, y) ((x) % (y))
48#endif
49
97222cc8
ED		 50#define PRId64 "d"
51#define PRIx64 "llx"
52#define PRIu64 "u"
53#define PRIo64 "o"
54
55#define APIC_BUS_CYCLE_NS 1
56
57/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
58#define apic_debug(fmt, arg...)
59
60#define APIC_LVT_NUM 6
61/* 14 is the version for Xeon and Pentium 8.4.8*/
62#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
63#define LAPIC_MMIO_LENGTH (1 << 12)
64/* followed define is not in apicdef.h */
65#define APIC_SHORT_MASK 0xc0000
66#define APIC_DEST_NOSHORT 0x0
67#define APIC_DEST_MASK 0x800
68#define MAX_APIC_VECTOR 256
ecba9a52 69#define APIC_VECTORS_PER_REG 32
97222cc8 70
394457a9
NA		 71#define APIC_BROADCAST 0xFF
72#define X2APIC_BROADCAST 0xFFFFFFFFul
73
97222cc8
ED		 74#define VEC_POS(v) ((v) & (32 - 1))
75#define REG_POS(v) (((v) >> 5) << 4)
ad312c7c 76
97222cc8
ED		 77static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
78{
79 *((u32 *) (apic->regs + reg_off)) = val;
80}
81
a0c9a822
MT		 82static inline int apic_test_vector(int vec, void *bitmap)
83{
84 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
85}
86
10606919
YZ		 87bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
88{
89 struct kvm_lapic *apic = vcpu->arch.apic;
90
91 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
92 apic_test_vector(vector, apic->regs + APIC_IRR);
93}
94
97222cc8
ED		 95static inline void apic_set_vector(int vec, void *bitmap)
96{
97 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
98}
99
100static inline void apic_clear_vector(int vec, void *bitmap)
101{
102 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
103}
104
8680b94b
MT		 105static inline int __apic_test_and_set_vector(int vec, void *bitmap)
106{
107 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
108}
109
110static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
111{
112 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
113}
114
c5cc421b 115struct static_key_deferred apic_hw_disabled __read_mostly;
f8c1ea10
GN		 116struct static_key_deferred apic_sw_disabled __read_mostly;
117
97222cc8
ED		 118static inline int apic_enabled(struct kvm_lapic *apic)
119{
c48f1496 120 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
54e9818f
GN		 121}
122
97222cc8
ED		 123#define LVT_MASK \
124 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
125
126#define LINT_MASK \
127 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
128 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
129
130static inline int kvm_apic_id(struct kvm_lapic *apic)
131{
c48f1496 132 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
97222cc8
ED		 133}
134
17d68b76
GN		 135#define KVM_X2APIC_CID_BITS 0
136
1e08ec4a
GN		 137static void recalculate_apic_map(struct kvm *kvm)
138{
139 struct kvm_apic_map *new, *old = NULL;
140 struct kvm_vcpu *vcpu;
141 int i;
142
143 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
144
145 mutex_lock(&kvm->arch.apic_map_lock);
146
147 if (!new)
148 goto out;
149
150 new->ldr_bits = 8;
151 /* flat mode is default */
152 new->cid_shift = 8;
153 new->cid_mask = 0;
154 new->lid_mask = 0xff;
394457a9 155 new->broadcast = APIC_BROADCAST;
1e08ec4a
GN		 156
157 kvm_for_each_vcpu(i, vcpu, kvm) {
158 struct kvm_lapic *apic = vcpu->arch.apic;
1e08ec4a
GN		 159
160 if (!kvm_apic_present(vcpu))
161 continue;
162
1e08ec4a
GN		 163 if (apic_x2apic_mode(apic)) {
164 new->ldr_bits = 32;
165 new->cid_shift = 16;
17d68b76
GN		 166 new->cid_mask = (1 << KVM_X2APIC_CID_BITS) - 1;
167 new->lid_mask = 0xffff;
394457a9 168 new->broadcast = X2APIC_BROADCAST;
a3e339e1 169 } else if (kvm_apic_get_reg(apic, APIC_LDR)) {
173beedc
NA		 170 if (kvm_apic_get_reg(apic, APIC_DFR) ==
171 APIC_DFR_CLUSTER) {
172 new->cid_shift = 4;
173 new->cid_mask = 0xf;
174 new->lid_mask = 0xf;
a3e339e1
PB		 175 } else {
176 new->cid_shift = 8;
177 new->cid_mask = 0;
178 new->lid_mask = 0xff;
173beedc 179 }
1e08ec4a 180 }
a3e339e1
PB		 181
182 /*
183 * All APICs have to be configured in the same mode by an OS.
184 * We take advatage of this while building logical id loockup
185 * table. After reset APICs are in software disabled mode, so if
186 * we find apic with different setting we assume this is the mode
187 * OS wants all apics to be in; build lookup table accordingly.
188 */
189 if (kvm_apic_sw_enabled(apic))
190 break;
173beedc
NA		 191 }
192
193 kvm_for_each_vcpu(i, vcpu, kvm) {
194 struct kvm_lapic *apic = vcpu->arch.apic;
195 u16 cid, lid;
196 u32 ldr;
1e08ec4a
GN		 197
198 new->phys_map[kvm_apic_id(apic)] = apic;
199
200 ldr = kvm_apic_get_reg(apic, APIC_LDR);
201 cid = apic_cluster_id(new, ldr);
202 lid = apic_logical_id(new, ldr);
203
204 if (lid)
205 new->logical_map[cid][ffs(lid) - 1] = apic;
206 }
207out:
208 old = rcu_dereference_protected(kvm->arch.apic_map,
209 lockdep_is_held(&kvm->arch.apic_map_lock));
210 rcu_assign_pointer(kvm->arch.apic_map, new);
211 mutex_unlock(&kvm->arch.apic_map_lock);
212
213 if (old)
214 kfree_rcu(old, rcu);
c7c9c56c 215
3d81bc7e 216 kvm_vcpu_request_scan_ioapic(kvm);
1e08ec4a
GN		 217}
218
1e1b6c26
NA		 219static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
220{
e462755c 221 bool enabled = val & APIC_SPIV_APIC_ENABLED;
1e1b6c26
NA		 222
223 apic_set_reg(apic, APIC_SPIV, val);
e462755c
RK		 224
225 if (enabled != apic->sw_enabled) {
226 apic->sw_enabled = enabled;
227 if (enabled) {
1e1b6c26
NA		 228 static_key_slow_dec_deferred(&apic_sw_disabled);
229 recalculate_apic_map(apic->vcpu->kvm);
230 } else
231 static_key_slow_inc(&apic_sw_disabled.key);
232 }
233}
234
1e08ec4a
GN		 235static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
236{
237 apic_set_reg(apic, APIC_ID, id << 24);
238 recalculate_apic_map(apic->vcpu->kvm);
239}
240
241static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
242{
243 apic_set_reg(apic, APIC_LDR, id);
244 recalculate_apic_map(apic->vcpu->kvm);
245}
246
97222cc8
ED		 247static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
248{
c48f1496 249 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
97222cc8
ED		 250}
251
252static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
253{
c48f1496 254 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
97222cc8
ED		 255}
256
a3e06bbe
LJ		 257static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
258{
f30ebc31 259 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
a3e06bbe
LJ		 260}
261
97222cc8
ED		 262static inline int apic_lvtt_period(struct kvm_lapic *apic)
263{
f30ebc31 264 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
a3e06bbe
LJ		 265}
266
267static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
268{
f30ebc31 269 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
97222cc8
ED		 270}
271
cc6e462c
JK		 272static inline int apic_lvt_nmi_mode(u32 lvt_val)
273{
274 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
275}
276
fc61b800
GN		 277void kvm_apic_set_version(struct kvm_vcpu *vcpu)
278{
279 struct kvm_lapic *apic = vcpu->arch.apic;
280 struct kvm_cpuid_entry2 *feat;
281 u32 v = APIC_VERSION;
282
c48f1496 283 if (!kvm_vcpu_has_lapic(vcpu))
fc61b800
GN		 284 return;
285
286 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
287 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
288 v |= APIC_LVR_DIRECTED_EOI;
289 apic_set_reg(apic, APIC_LVR, v);
290}
291
f1d24831 292static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
a3e06bbe 293 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
97222cc8
ED		 294 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
295 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
296 LINT_MASK, LINT_MASK, /* LVT0-1 */
297 LVT_MASK /* LVTERR */
298};
299
300static int find_highest_vector(void *bitmap)
301{
ecba9a52
TY		 302 int vec;
303 u32 *reg;
97222cc8 304
ecba9a52
TY		 305 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
306 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
307 reg = bitmap + REG_POS(vec);
308 if (*reg)
309 return fls(*reg) - 1 + vec;
310 }
97222cc8 311
ecba9a52 312 return -1;
97222cc8
ED		 313}
314
8680b94b
MT		 315static u8 count_vectors(void *bitmap)
316{
ecba9a52
TY		 317 int vec;
318 u32 *reg;
8680b94b 319 u8 count = 0;
ecba9a52
TY		 320
321 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
322 reg = bitmap + REG_POS(vec);
323 count += hweight32(*reg);
324 }
325
8680b94b
MT		 326 return count;
327}
328
a20ed54d
YZ		 329void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
330{
331 u32 i, pir_val;
332 struct kvm_lapic *apic = vcpu->arch.apic;
333
334 for (i = 0; i <= 7; i++) {
335 pir_val = xchg(&pir[i], 0);
336 if (pir_val)
337 *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
338 }
339}
340EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
341
11f5cc05 342static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
97222cc8 343{
11f5cc05 344 apic_set_vector(vec, apic->regs + APIC_IRR);
f210f757
NA		 345 /*
346 * irr_pending must be true if any interrupt is pending; set it after
347 * APIC_IRR to avoid race with apic_clear_irr
348 */
349 apic->irr_pending = true;
97222cc8
ED		 350}
351
33e4c686 352static inline int apic_search_irr(struct kvm_lapic *apic)
97222cc8 353{
33e4c686 354 return find_highest_vector(apic->regs + APIC_IRR);
97222cc8
ED		 355}
356
357static inline int apic_find_highest_irr(struct kvm_lapic *apic)
358{
359 int result;
360
c7c9c56c
YZ		 361 /*
362 * Note that irr_pending is just a hint. It will be always
363 * true with virtual interrupt delivery enabled.
364 */
33e4c686
GN		 365 if (!apic->irr_pending)
366 return -1;
367
5a71785d 368 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
33e4c686 369 result = apic_search_irr(apic);
97222cc8
ED		 370 ASSERT(result == -1 || result >= 16);
371
372 return result;
373}
374
33e4c686
GN		 375static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
376{
56cc2406
WL		 377 struct kvm_vcpu *vcpu;
378
379 vcpu = apic->vcpu;
380
f210f757 381 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
56cc2406 382 /* try to update RVI */
f210f757 383 apic_clear_vector(vec, apic->regs + APIC_IRR);
56cc2406 384 kvm_make_request(KVM_REQ_EVENT, vcpu);
f210f757
NA		 385 } else {
386 apic->irr_pending = false;
387 apic_clear_vector(vec, apic->regs + APIC_IRR);
388 if (apic_search_irr(apic) != -1)
389 apic->irr_pending = true;
56cc2406 390 }
33e4c686
GN		 391}
392
8680b94b
MT		 393static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
394{
56cc2406
WL		 395 struct kvm_vcpu *vcpu;
396
397 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
398 return;
399
400 vcpu = apic->vcpu;
fc57ac2c 401
8680b94b 402 /*
56cc2406
WL		 403 * With APIC virtualization enabled, all caching is disabled
404 * because the processor can modify ISR under the hood. Instead
405 * just set SVI.
8680b94b 406 */
56cc2406
WL		 407 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
408 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
409 else {
410 ++apic->isr_count;
411 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
412 /*
413 * ISR (in service register) bit is set when injecting an interrupt.
414 * The highest vector is injected. Thus the latest bit set matches
415 * the highest bit in ISR.
416 */
417 apic->highest_isr_cache = vec;
418 }
8680b94b
MT		 419}
420
fc57ac2c
PB		 421static inline int apic_find_highest_isr(struct kvm_lapic *apic)
422{
423 int result;
424
425 /*
426 * Note that isr_count is always 1, and highest_isr_cache
427 * is always -1, with APIC virtualization enabled.
428 */
429 if (!apic->isr_count)
430 return -1;
431 if (likely(apic->highest_isr_cache != -1))
432 return apic->highest_isr_cache;
433
434 result = find_highest_vector(apic->regs + APIC_ISR);
435 ASSERT(result == -1 || result >= 16);
436
437 return result;
438}
439
8680b94b
MT		 440static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
441{
fc57ac2c
PB		 442 struct kvm_vcpu *vcpu;
443 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
444 return;
445
446 vcpu = apic->vcpu;
447
448 /*
449 * We do get here for APIC virtualization enabled if the guest
450 * uses the Hyper-V APIC enlightenment. In this case we may need
451 * to trigger a new interrupt delivery by writing the SVI field;
452 * on the other hand isr_count and highest_isr_cache are unused
453 * and must be left alone.
454 */
455 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
456 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
457 apic_find_highest_isr(apic));
458 else {
8680b94b 459 --apic->isr_count;
fc57ac2c
PB		 460 BUG_ON(apic->isr_count < 0);
461 apic->highest_isr_cache = -1;
462 }
8680b94b
MT		 463}
464
6e5d865c
YS		 465int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
466{
6e5d865c
YS		 467 int highest_irr;
468
33e4c686
GN		 469 /* This may race with setting of irr in __apic_accept_irq() and
470 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
471 * will cause vmexit immediately and the value will be recalculated
472 * on the next vmentry.
473 */
c48f1496 474 if (!kvm_vcpu_has_lapic(vcpu))
6e5d865c 475 return 0;
54e9818f 476 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
6e5d865c
YS		 477
478 return highest_irr;
479}
6e5d865c 480
6da7e3f6 481static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c
YZ		 482 int vector, int level, int trig_mode,
483 unsigned long *dest_map);
6da7e3f6 484
b4f2225c
YZ		 485int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
486 unsigned long *dest_map)
97222cc8 487{
ad312c7c 488 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 489
58c2dde1 490 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
b4f2225c 491 irq->level, irq->trig_mode, dest_map);
97222cc8
ED		 492}
493
ae7a2a3f
MT		 494static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
495{
496
497 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
498 sizeof(val));
499}
500
501static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
502{
503
504 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
505 sizeof(*val));
506}
507
508static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
509{
510 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
511}
512
513static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
514{
515 u8 val;
516 if (pv_eoi_get_user(vcpu, &val) < 0)
517 apic_debug("Can't read EOI MSR value: 0x%llx\n",
96893977 518 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 519 return val & 0x1;
520}
521
522static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
523{
524 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
525 apic_debug("Can't set EOI MSR value: 0x%llx\n",
96893977 526 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 527 return;
528 }
529 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
530}
531
532static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
533{
534 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
535 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
96893977 536 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 537 return;
538 }
539 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
540}
541
cf9e65b7
YZ		 542void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
543{
544 struct kvm_lapic *apic = vcpu->arch.apic;
545 int i;
546
547 for (i = 0; i < 8; i++)
548 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
549}
550
97222cc8
ED		 551static void apic_update_ppr(struct kvm_lapic *apic)
552{
3842d135 553 u32 tpr, isrv, ppr, old_ppr;
97222cc8
ED		 554 int isr;
555
c48f1496
GN		 556 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
557 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
97222cc8
ED		 558 isr = apic_find_highest_isr(apic);
559 isrv = (isr != -1) ? isr : 0;
560
561 if ((tpr & 0xf0) >= (isrv & 0xf0))
562 ppr = tpr & 0xff;
563 else
564 ppr = isrv & 0xf0;
565
566 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
567 apic, ppr, isr, isrv);
568
3842d135
AK		 569 if (old_ppr != ppr) {
570 apic_set_reg(apic, APIC_PROCPRI, ppr);
83bcacb1
AK		 571 if (ppr < old_ppr)
572 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
3842d135 573 }
97222cc8
ED		 574}
575
576static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
577{
578 apic_set_reg(apic, APIC_TASKPRI, tpr);
579 apic_update_ppr(apic);
580}
581
394457a9
NA		 582static int kvm_apic_broadcast(struct kvm_lapic *apic, u32 dest)
583{
584 return dest == (apic_x2apic_mode(apic) ?
585 X2APIC_BROADCAST : APIC_BROADCAST);
586}
587
588int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest)
97222cc8 589{
394457a9 590 return kvm_apic_id(apic) == dest || kvm_apic_broadcast(apic, dest);
97222cc8
ED		 591}
592
394457a9 593int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8
ED		 594{
595 int result = 0;
0105d1a5
GN		 596 u32 logical_id;
597
394457a9
NA		 598 if (kvm_apic_broadcast(apic, mda))
599 return 1;
600
0105d1a5 601 if (apic_x2apic_mode(apic)) {
c48f1496 602 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
0105d1a5
GN		 603 return logical_id & mda;
604 }
97222cc8 605
c48f1496 606 logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
97222cc8 607
c48f1496 608 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
97222cc8
ED		 609 case APIC_DFR_FLAT:
610 if (logical_id & mda)
611 result = 1;
612 break;
613 case APIC_DFR_CLUSTER:
614 if (((logical_id >> 4) == (mda >> 0x4))
615 && (logical_id & mda & 0xf))
616 result = 1;
617 break;
618 default:
7712de87 619 apic_debug("Bad DFR vcpu %d: %08x\n",
c48f1496 620 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
97222cc8
ED		 621 break;
622 }
623
624 return result;
625}
626
343f94fe 627int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
394457a9 628 int short_hand, unsigned int dest, int dest_mode)
97222cc8
ED		 629{
630 int result = 0;
ad312c7c 631 struct kvm_lapic *target = vcpu->arch.apic;
97222cc8
ED		 632
633 apic_debug("target %p, source %p, dest 0x%x, "
343f94fe 634 "dest_mode 0x%x, short_hand 0x%x\n",
97222cc8
ED		 635 target, source, dest, dest_mode, short_hand);
636
bd371396 637 ASSERT(target);
97222cc8
ED		 638 switch (short_hand) {
639 case APIC_DEST_NOSHORT:
343f94fe 640 if (dest_mode == 0)
97222cc8 641 /* Physical mode. */
343f94fe
GN		 642 result = kvm_apic_match_physical_addr(target, dest);
643 else
97222cc8
ED		 644 /* Logical mode. */
645 result = kvm_apic_match_logical_addr(target, dest);
646 break;
647 case APIC_DEST_SELF:
343f94fe 648 result = (target == source);
97222cc8
ED		 649 break;
650 case APIC_DEST_ALLINC:
651 result = 1;
652 break;
653 case APIC_DEST_ALLBUT:
343f94fe 654 result = (target != source);
97222cc8
ED		 655 break;
656 default:
7712de87
JK		 657 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
658 short_hand);
97222cc8
ED		 659 break;
660 }
661
662 return result;
663}
664
1e08ec4a 665bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
b4f2225c 666 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
1e08ec4a
GN		 667{
668 struct kvm_apic_map *map;
669 unsigned long bitmap = 1;
670 struct kvm_lapic **dst;
671 int i;
672 bool ret = false;
673
674 *r = -1;
675
676 if (irq->shorthand == APIC_DEST_SELF) {
b4f2225c 677 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
1e08ec4a
GN		 678 return true;
679 }
680
681 if (irq->shorthand)
682 return false;
683
684 rcu_read_lock();
685 map = rcu_dereference(kvm->arch.apic_map);
686
687 if (!map)
688 goto out;
689
394457a9
NA		 690 if (irq->dest_id == map->broadcast)
691 goto out;
692
1e08ec4a 693 if (irq->dest_mode == 0) { /* physical mode */
394457a9 694 if (irq->delivery_mode == APIC_DM_LOWEST)
1e08ec4a
GN		 695 goto out;
696 dst = &map->phys_map[irq->dest_id & 0xff];
697 } else {
698 u32 mda = irq->dest_id << (32 - map->ldr_bits);
699
700 dst = map->logical_map[apic_cluster_id(map, mda)];
701
702 bitmap = apic_logical_id(map, mda);
703
704 if (irq->delivery_mode == APIC_DM_LOWEST) {
705 int l = -1;
706 for_each_set_bit(i, &bitmap, 16) {
707 if (!dst[i])
708 continue;
709 if (l < 0)
710 l = i;
711 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
712 l = i;
713 }
714
715 bitmap = (l >= 0) ? 1 << l : 0;
716 }
717 }
718
719 for_each_set_bit(i, &bitmap, 16) {
720 if (!dst[i])
721 continue;
722 if (*r < 0)
723 *r = 0;
b4f2225c 724 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
1e08ec4a
GN		 725 }
726
727 ret = true;
728out:
729 rcu_read_unlock();
730 return ret;
731}
732
97222cc8
ED		 733/*
734 * Add a pending IRQ into lapic.
735 * Return 1 if successfully added and 0 if discarded.
736 */
737static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c
YZ		 738 int vector, int level, int trig_mode,
739 unsigned long *dest_map)
97222cc8 740{
6da7e3f6 741 int result = 0;
c5ec1534 742 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8 743
a183b638
PB		 744 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
745 trig_mode, vector);
97222cc8 746 switch (delivery_mode) {
97222cc8 747 case APIC_DM_LOWEST:
e1035715
GN		 748 vcpu->arch.apic_arb_prio++;
749 case APIC_DM_FIXED:
97222cc8
ED		 750 /* FIXME add logic for vcpu on reset */
751 if (unlikely(!apic_enabled(apic)))
752 break;
753
11f5cc05
JK		 754 result = 1;
755
b4f2225c
YZ		 756 if (dest_map)
757 __set_bit(vcpu->vcpu_id, dest_map);
a5d36f82 758
11f5cc05 759 if (kvm_x86_ops->deliver_posted_interrupt)
5a71785d 760 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
11f5cc05
JK		 761 else {
762 apic_set_irr(vector, apic);
5a71785d
YZ		 763
764 kvm_make_request(KVM_REQ_EVENT, vcpu);
765 kvm_vcpu_kick(vcpu);
766 }
97222cc8
ED		 767 break;
768
769 case APIC_DM_REMRD:
24d2166b
R		 770 result = 1;
771 vcpu->arch.pv.pv_unhalted = 1;
772 kvm_make_request(KVM_REQ_EVENT, vcpu);
773 kvm_vcpu_kick(vcpu);
97222cc8
ED		 774 break;
775
776 case APIC_DM_SMI:
7712de87 777 apic_debug("Ignoring guest SMI\n");
97222cc8 778 break;
3419ffc8 779
97222cc8 780 case APIC_DM_NMI:
6da7e3f6 781 result = 1;
3419ffc8 782 kvm_inject_nmi(vcpu);
26df99c6 783 kvm_vcpu_kick(vcpu);
97222cc8
ED		 784 break;
785
786 case APIC_DM_INIT:
a52315e1 787 if (!trig_mode || level) {
6da7e3f6 788 result = 1;
66450a21
JK		 789 /* assumes that there are only KVM_APIC_INIT/SIPI */
790 apic->pending_events = (1UL << KVM_APIC_INIT);
791 /* make sure pending_events is visible before sending
792 * the request */
793 smp_wmb();
3842d135 794 kvm_make_request(KVM_REQ_EVENT, vcpu);
c5ec1534
HQ		 795 kvm_vcpu_kick(vcpu);
796 } else {
1b10bf31
JK		 797 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
798 vcpu->vcpu_id);
c5ec1534 799 }
97222cc8
ED		 800 break;
801
802 case APIC_DM_STARTUP:
1b10bf31
JK		 803 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
804 vcpu->vcpu_id, vector);
66450a21
JK		 805 result = 1;
806 apic->sipi_vector = vector;
807 /* make sure sipi_vector is visible for the receiver */
808 smp_wmb();
809 set_bit(KVM_APIC_SIPI, &apic->pending_events);
810 kvm_make_request(KVM_REQ_EVENT, vcpu);
811 kvm_vcpu_kick(vcpu);
97222cc8
ED		 812 break;
813
23930f95
JK		 814 case APIC_DM_EXTINT:
815 /*
816 * Should only be called by kvm_apic_local_deliver() with LVT0,
817 * before NMI watchdog was enabled. Already handled by
818 * kvm_apic_accept_pic_intr().
819 */
820 break;
821
97222cc8
ED		 822 default:
823 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
824 delivery_mode);
825 break;
826 }
827 return result;
828}
829
e1035715 830int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
8be5453f 831{
e1035715 832 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
8be5453f
ZX		 833}
834
c7c9c56c
YZ		 835static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
836{
837 if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
838 kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
839 int trigger_mode;
840 if (apic_test_vector(vector, apic->regs + APIC_TMR))
841 trigger_mode = IOAPIC_LEVEL_TRIG;
842 else
843 trigger_mode = IOAPIC_EDGE_TRIG;
1fcc7890 844 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
c7c9c56c
YZ		 845 }
846}
847
ae7a2a3f 848static int apic_set_eoi(struct kvm_lapic *apic)
97222cc8
ED		 849{
850 int vector = apic_find_highest_isr(apic);
ae7a2a3f
MT		 851
852 trace_kvm_eoi(apic, vector);
853
97222cc8
ED		 854 /*
855 * Not every write EOI will has corresponding ISR,
856 * one example is when Kernel check timer on setup_IO_APIC
857 */
858 if (vector == -1)
ae7a2a3f 859 return vector;
97222cc8 860
8680b94b 861 apic_clear_isr(vector, apic);
97222cc8
ED		 862 apic_update_ppr(apic);
863
c7c9c56c 864 kvm_ioapic_send_eoi(apic, vector);
3842d135 865 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
ae7a2a3f 866 return vector;
97222cc8
ED		 867}
868
c7c9c56c
YZ		 869/*
870 * this interface assumes a trap-like exit, which has already finished
871 * desired side effect including vISR and vPPR update.
872 */
873void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
874{
875 struct kvm_lapic *apic = vcpu->arch.apic;
876
877 trace_kvm_eoi(apic, vector);
878
879 kvm_ioapic_send_eoi(apic, vector);
880 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
881}
882EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
883
97222cc8
ED		 884static void apic_send_ipi(struct kvm_lapic *apic)
885{
c48f1496
GN		 886 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
887 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
58c2dde1 888 struct kvm_lapic_irq irq;
97222cc8 889
58c2dde1
GN		 890 irq.vector = icr_low & APIC_VECTOR_MASK;
891 irq.delivery_mode = icr_low & APIC_MODE_MASK;
892 irq.dest_mode = icr_low & APIC_DEST_MASK;
893 irq.level = icr_low & APIC_INT_ASSERT;
894 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
895 irq.shorthand = icr_low & APIC_SHORT_MASK;
0105d1a5
GN		 896 if (apic_x2apic_mode(apic))
897 irq.dest_id = icr_high;
898 else
899 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
97222cc8 900
1000ff8d
GN		 901 trace_kvm_apic_ipi(icr_low, irq.dest_id);
902
97222cc8
ED		 903 apic_debug("icr_high 0x%x, icr_low 0x%x, "
904 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
905 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
9b5843dd 906 icr_high, icr_low, irq.shorthand, irq.dest_id,
58c2dde1
GN		 907 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
908 irq.vector);
909
b4f2225c 910 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
97222cc8
ED		 911}
912
913static u32 apic_get_tmcct(struct kvm_lapic *apic)
914{
b682b814
MT		 915 ktime_t remaining;
916 s64 ns;
9da8f4e8 917 u32 tmcct;
97222cc8
ED		 918
919 ASSERT(apic != NULL);
920
9da8f4e8 921 /* if initial count is 0, current count should also be 0 */
b963a22e
AH		 922 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
923 apic->lapic_timer.period == 0)
9da8f4e8
KP		 924 return 0;
925
ace15464 926 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
b682b814
MT		 927 if (ktime_to_ns(remaining) < 0)
928 remaining = ktime_set(0, 0);
929
d3c7b77d
MT		 930 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
931 tmcct = div64_u64(ns,
932 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 933
934 return tmcct;
935}
936
b209749f
AK		 937static void __report_tpr_access(struct kvm_lapic *apic, bool write)
938{
939 struct kvm_vcpu *vcpu = apic->vcpu;
940 struct kvm_run *run = vcpu->run;
941
a8eeb04a 942 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
5fdbf976 943 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 944 run->tpr_access.is_write = write;
945}
946
947static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
948{
949 if (apic->vcpu->arch.tpr_access_reporting)
950 __report_tpr_access(apic, write);
951}
952
97222cc8
ED		 953static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
954{
955 u32 val = 0;
956
957 if (offset >= LAPIC_MMIO_LENGTH)
958 return 0;
959
960 switch (offset) {
0105d1a5
GN		 961 case APIC_ID:
962 if (apic_x2apic_mode(apic))
963 val = kvm_apic_id(apic);
964 else
965 val = kvm_apic_id(apic) << 24;
966 break;
97222cc8 967 case APIC_ARBPRI:
7712de87 968 apic_debug("Access APIC ARBPRI register which is for P6\n");
97222cc8
ED		 969 break;
970
971 case APIC_TMCCT: /* Timer CCR */
a3e06bbe
LJ		 972 if (apic_lvtt_tscdeadline(apic))
973 return 0;
974
97222cc8
ED		 975 val = apic_get_tmcct(apic);
976 break;
4a4541a4
AK		 977 case APIC_PROCPRI:
978 apic_update_ppr(apic);
c48f1496 979 val = kvm_apic_get_reg(apic, offset);
4a4541a4 980 break;
b209749f
AK		 981 case APIC_TASKPRI:
982 report_tpr_access(apic, false);
983 /* fall thru */
97222cc8 984 default:
c48f1496 985 val = kvm_apic_get_reg(apic, offset);
97222cc8
ED		 986 break;
987 }
988
989 return val;
990}
991
d76685c4
GH		 992static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
993{
994 return container_of(dev, struct kvm_lapic, dev);
995}
996
0105d1a5
GN		 997static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
998 void *data)
97222cc8 999{
97222cc8
ED		 1000 unsigned char alignment = offset & 0xf;
1001 u32 result;
d5b0b5b1 1002 /* this bitmask has a bit cleared for each reserved register */
0105d1a5 1003 static const u64 rmask = 0x43ff01ffffffe70cULL;
97222cc8
ED		 1004
1005 if ((alignment + len) > 4) {
4088bb3c
GN		 1006 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1007 offset, len);
0105d1a5 1008 return 1;
97222cc8 1009 }
0105d1a5
GN		 1010
1011 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
4088bb3c
GN		 1012 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1013 offset);
0105d1a5
GN		 1014 return 1;
1015 }
1016
97222cc8
ED		 1017 result = __apic_read(apic, offset & ~0xf);
1018
229456fc
MT		 1019 trace_kvm_apic_read(offset, result);
1020
97222cc8
ED		 1021 switch (len) {
1022 case 1:
1023 case 2:
1024 case 4:
1025 memcpy(data, (char *)&result + alignment, len);
1026 break;
1027 default:
1028 printk(KERN_ERR "Local APIC read with len = %x, "
1029 "should be 1,2, or 4 instead\n", len);
1030 break;
1031 }
bda9020e 1032 return 0;
97222cc8
ED		 1033}
1034
0105d1a5
GN		 1035static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1036{
c48f1496 1037 return kvm_apic_hw_enabled(apic) &&
0105d1a5
GN		 1038 addr >= apic->base_address &&
1039 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1040}
1041
1042static int apic_mmio_read(struct kvm_io_device *this,
1043 gpa_t address, int len, void *data)
1044{
1045 struct kvm_lapic *apic = to_lapic(this);
1046 u32 offset = address - apic->base_address;
1047
1048 if (!apic_mmio_in_range(apic, address))
1049 return -EOPNOTSUPP;
1050
1051 apic_reg_read(apic, offset, len, data);
1052
1053 return 0;
1054}
1055
97222cc8
ED		 1056static void update_divide_count(struct kvm_lapic *apic)
1057{
1058 u32 tmp1, tmp2, tdcr;
1059
c48f1496 1060 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
97222cc8
ED		 1061 tmp1 = tdcr & 0xf;
1062 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 1063 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 1064
1065 apic_debug("timer divide count is 0x%x\n",
9b5843dd 1066 apic->divide_count);
97222cc8
ED		 1067}
1068
5d87db71
RK		 1069static void apic_timer_expired(struct kvm_lapic *apic)
1070{
1071 struct kvm_vcpu *vcpu = apic->vcpu;
1072 wait_queue_head_t *q = &vcpu->wq;
1073
1074 /*
1075 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1076 * vcpu_enter_guest.
1077 */
1078 if (atomic_read(&apic->lapic_timer.pending))
1079 return;
1080
1081 atomic_inc(&apic->lapic_timer.pending);
1082 /* FIXME: this code should not know anything about vcpus */
1083 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1084
1085 if (waitqueue_active(q))
1086 wake_up_interruptible(q);
1087}
1088
97222cc8
ED		 1089static void start_apic_timer(struct kvm_lapic *apic)
1090{
a3e06bbe 1091 ktime_t now;
d3c7b77d 1092 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 1093
a3e06bbe 1094 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
d5b0b5b1 1095 /* lapic timer in oneshot or periodic mode */
a3e06bbe 1096 now = apic->lapic_timer.timer.base->get_time();
c48f1496 1097 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
a3e06bbe
LJ		 1098 * APIC_BUS_CYCLE_NS * apic->divide_count;
1099
1100 if (!apic->lapic_timer.period)
1101 return;
1102 /*
1103 * Do not allow the guest to program periodic timers with small
1104 * interval, since the hrtimers are not throttled by the host
1105 * scheduler.
1106 */
1107 if (apic_lvtt_period(apic)) {
1108 s64 min_period = min_timer_period_us * 1000LL;
1109
1110 if (apic->lapic_timer.period < min_period) {
1111 pr_info_ratelimited(
1112 "kvm: vcpu %i: requested %lld ns "
1113 "lapic timer period limited to %lld ns\n",
1114 apic->vcpu->vcpu_id,
1115 apic->lapic_timer.period, min_period);
1116 apic->lapic_timer.period = min_period;
1117 }
9bc5791d 1118 }
0b975a3c 1119
a3e06bbe
LJ		 1120 hrtimer_start(&apic->lapic_timer.timer,
1121 ktime_add_ns(now, apic->lapic_timer.period),
1122 HRTIMER_MODE_ABS);
97222cc8 1123
a3e06bbe 1124 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
97222cc8
ED		 1125 PRIx64 ", "
1126 "timer initial count 0x%x, period %lldns, "
b8688d51 1127 "expire @ 0x%016" PRIx64 ".\n", __func__,
97222cc8 1128 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
c48f1496 1129 kvm_apic_get_reg(apic, APIC_TMICT),
d3c7b77d 1130 apic->lapic_timer.period,
97222cc8 1131 ktime_to_ns(ktime_add_ns(now,
d3c7b77d 1132 apic->lapic_timer.period)));
a3e06bbe
LJ		 1133 } else if (apic_lvtt_tscdeadline(apic)) {
1134 /* lapic timer in tsc deadline mode */
1135 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1136 u64 ns = 0;
1137 struct kvm_vcpu *vcpu = apic->vcpu;
cc578287 1138 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
a3e06bbe
LJ		 1139 unsigned long flags;
1140
1141 if (unlikely(!tscdeadline || !this_tsc_khz))
1142 return;
1143
1144 local_irq_save(flags);
1145
1146 now = apic->lapic_timer.timer.base->get_time();
886b470c 1147 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
a3e06bbe
LJ		 1148 if (likely(tscdeadline > guest_tsc)) {
1149 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1150 do_div(ns, this_tsc_khz);
1e0ad70c
RK		 1151 hrtimer_start(&apic->lapic_timer.timer,
1152 ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
1153 } else
1154 apic_timer_expired(apic);
a3e06bbe
LJ		 1155
1156 local_irq_restore(flags);
1157 }
97222cc8
ED		 1158}
1159
cc6e462c
JK		 1160static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1161{
c48f1496 1162 int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
cc6e462c
JK		 1163
1164 if (apic_lvt_nmi_mode(lvt0_val)) {
1165 if (!nmi_wd_enabled) {
1166 apic_debug("Receive NMI setting on APIC_LVT0 "
1167 "for cpu %d\n", apic->vcpu->vcpu_id);
1168 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1169 }
1170 } else if (nmi_wd_enabled)
1171 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1172}
1173
0105d1a5 1174static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
97222cc8 1175{
0105d1a5 1176 int ret = 0;
97222cc8 1177
0105d1a5 1178 trace_kvm_apic_write(reg, val);
97222cc8 1179
0105d1a5 1180 switch (reg) {
97222cc8 1181 case APIC_ID: /* Local APIC ID */
0105d1a5 1182 if (!apic_x2apic_mode(apic))
1e08ec4a 1183 kvm_apic_set_id(apic, val >> 24);
0105d1a5
GN		 1184 else
1185 ret = 1;
97222cc8
ED		 1186 break;
1187
1188 case APIC_TASKPRI:
b209749f 1189 report_tpr_access(apic, true);
97222cc8
ED		 1190 apic_set_tpr(apic, val & 0xff);
1191 break;
1192
1193 case APIC_EOI:
1194 apic_set_eoi(apic);
1195 break;
1196
1197 case APIC_LDR:
0105d1a5 1198 if (!apic_x2apic_mode(apic))
1e08ec4a 1199 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
0105d1a5
GN		 1200 else
1201 ret = 1;
97222cc8
ED		 1202 break;
1203
1204 case APIC_DFR:
1e08ec4a 1205 if (!apic_x2apic_mode(apic)) {
0105d1a5 1206 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1e08ec4a
GN		 1207 recalculate_apic_map(apic->vcpu->kvm);
1208 } else
0105d1a5 1209 ret = 1;
97222cc8
ED		 1210 break;
1211
fc61b800
GN		 1212 case APIC_SPIV: {
1213 u32 mask = 0x3ff;
c48f1496 1214 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
fc61b800 1215 mask |= APIC_SPIV_DIRECTED_EOI;
f8c1ea10 1216 apic_set_spiv(apic, val & mask);
97222cc8
ED		 1217 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1218 int i;
1219 u32 lvt_val;
1220
1221 for (i = 0; i < APIC_LVT_NUM; i++) {
c48f1496 1222 lvt_val = kvm_apic_get_reg(apic,
97222cc8
ED		 1223 APIC_LVTT + 0x10 * i);
1224 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1225 lvt_val | APIC_LVT_MASKED);
1226 }
d3c7b77d 1227 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 1228
1229 }
1230 break;
fc61b800 1231 }
97222cc8
ED		 1232 case APIC_ICR:
1233 /* No delay here, so we always clear the pending bit */
1234 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1235 apic_send_ipi(apic);
1236 break;
1237
1238 case APIC_ICR2:
0105d1a5
GN		 1239 if (!apic_x2apic_mode(apic))
1240 val &= 0xff000000;
1241 apic_set_reg(apic, APIC_ICR2, val);
97222cc8
ED		 1242 break;
1243
23930f95 1244 case APIC_LVT0:
cc6e462c 1245 apic_manage_nmi_watchdog(apic, val);
97222cc8
ED		 1246 case APIC_LVTTHMR:
1247 case APIC_LVTPC:
97222cc8
ED		 1248 case APIC_LVT1:
1249 case APIC_LVTERR:
1250 /* TODO: Check vector */
c48f1496 1251 if (!kvm_apic_sw_enabled(apic))
97222cc8
ED		 1252 val |= APIC_LVT_MASKED;
1253
0105d1a5
GN		 1254 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1255 apic_set_reg(apic, reg, val);
97222cc8
ED		 1256
1257 break;
1258
a323b409
RK		 1259 case APIC_LVTT: {
1260 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1261
1262 if (apic->lapic_timer.timer_mode != timer_mode) {
1263 apic->lapic_timer.timer_mode = timer_mode;
a3e06bbe 1264 hrtimer_cancel(&apic->lapic_timer.timer);
a323b409 1265 }
a3e06bbe 1266
c48f1496 1267 if (!kvm_apic_sw_enabled(apic))
a3e06bbe
LJ		 1268 val |= APIC_LVT_MASKED;
1269 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1270 apic_set_reg(apic, APIC_LVTT, val);
1271 break;
a323b409 1272 }
a3e06bbe 1273
97222cc8 1274 case APIC_TMICT:
a3e06bbe
LJ		 1275 if (apic_lvtt_tscdeadline(apic))
1276 break;
1277
d3c7b77d 1278 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 1279 apic_set_reg(apic, APIC_TMICT, val);
1280 start_apic_timer(apic);
0105d1a5 1281 break;
97222cc8
ED		 1282
1283 case APIC_TDCR:
1284 if (val & 4)
7712de87 1285 apic_debug("KVM_WRITE:TDCR %x\n", val);
97222cc8
ED		 1286 apic_set_reg(apic, APIC_TDCR, val);
1287 update_divide_count(apic);
1288 break;
1289
0105d1a5
GN		 1290 case APIC_ESR:
1291 if (apic_x2apic_mode(apic) && val != 0) {
7712de87 1292 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
0105d1a5
GN		 1293 ret = 1;
1294 }
1295 break;
1296
1297 case APIC_SELF_IPI:
1298 if (apic_x2apic_mode(apic)) {
1299 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1300 } else
1301 ret = 1;
1302 break;
97222cc8 1303 default:
0105d1a5 1304 ret = 1;
97222cc8
ED		 1305 break;
1306 }
0105d1a5
GN		 1307 if (ret)
1308 apic_debug("Local APIC Write to read-only register %x\n", reg);
1309 return ret;
1310}
1311
1312static int apic_mmio_write(struct kvm_io_device *this,
1313 gpa_t address, int len, const void *data)
1314{
1315 struct kvm_lapic *apic = to_lapic(this);
1316 unsigned int offset = address - apic->base_address;
1317 u32 val;
1318
1319 if (!apic_mmio_in_range(apic, address))
1320 return -EOPNOTSUPP;
1321
1322 /*
1323 * APIC register must be aligned on 128-bits boundary.
1324 * 32/64/128 bits registers must be accessed thru 32 bits.
1325 * Refer SDM 8.4.1
1326 */
1327 if (len != 4 || (offset & 0xf)) {
1328 /* Don't shout loud, $infamous_os would cause only noise. */
1329 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
756975bb 1330 return 0;
0105d1a5
GN		 1331 }
1332
1333 val = *(u32*)data;
1334
1335 /* too common printing */
1336 if (offset != APIC_EOI)
1337 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1338 "0x%x\n", __func__, offset, len, val);
1339
1340 apic_reg_write(apic, offset & 0xff0, val);
1341
bda9020e 1342 return 0;
97222cc8
ED		 1343}
1344
58fbbf26
KT		 1345void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1346{
c48f1496 1347 if (kvm_vcpu_has_lapic(vcpu))
58fbbf26
KT		 1348 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1349}
1350EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1351
83d4c286
YZ		 1352/* emulate APIC access in a trap manner */
1353void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1354{
1355 u32 val = 0;
1356
1357 /* hw has done the conditional check and inst decode */
1358 offset &= 0xff0;
1359
1360 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1361
1362 /* TODO: optimize to just emulate side effect w/o one more write */
1363 apic_reg_write(vcpu->arch.apic, offset, val);
1364}
1365EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1366
d589444e 1367void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 1368{
f8c1ea10
GN		 1369 struct kvm_lapic *apic = vcpu->arch.apic;
1370
ad312c7c 1371 if (!vcpu->arch.apic)
97222cc8
ED		 1372 return;
1373
f8c1ea10 1374 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1375
c5cc421b
GN		 1376 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1377 static_key_slow_dec_deferred(&apic_hw_disabled);
1378
e462755c 1379 if (!apic->sw_enabled)
f8c1ea10 1380 static_key_slow_dec_deferred(&apic_sw_disabled);
97222cc8 1381
f8c1ea10
GN		 1382 if (apic->regs)
1383 free_page((unsigned long)apic->regs);
1384
1385 kfree(apic);
97222cc8
ED		 1386}
1387
1388/*
1389 *----------------------------------------------------------------------
1390 * LAPIC interface
1391 *----------------------------------------------------------------------
1392 */
1393
a3e06bbe
LJ		 1394u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1395{
1396 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1397
c48f1496 1398 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1399 apic_lvtt_period(apic))
a3e06bbe
LJ		 1400 return 0;
1401
1402 return apic->lapic_timer.tscdeadline;
1403}
1404
1405void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1406{
1407 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1408
c48f1496 1409 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1410 apic_lvtt_period(apic))
a3e06bbe
LJ		 1411 return;
1412
1413 hrtimer_cancel(&apic->lapic_timer.timer);
1414 apic->lapic_timer.tscdeadline = data;
1415 start_apic_timer(apic);
1416}
1417
97222cc8
ED		 1418void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1419{
ad312c7c 1420 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8 1421
c48f1496 1422 if (!kvm_vcpu_has_lapic(vcpu))
97222cc8 1423 return;
54e9818f 1424
b93463aa 1425 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
c48f1496 1426 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8
ED		 1427}
1428
1429u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1430{
97222cc8
ED		 1431 u64 tpr;
1432
c48f1496 1433 if (!kvm_vcpu_has_lapic(vcpu))
97222cc8 1434 return 0;
54e9818f 1435
c48f1496 1436 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
97222cc8
ED		 1437
1438 return (tpr & 0xf0) >> 4;
1439}
1440
1441void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1442{
8d14695f 1443 u64 old_value = vcpu->arch.apic_base;
ad312c7c 1444 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1445
1446 if (!apic) {
1447 value |= MSR_IA32_APICBASE_BSP;
ad312c7c 1448 vcpu->arch.apic_base = value;
97222cc8
ED		 1449 return;
1450 }
c5af89b6 1451
e66d2ae7
JK		 1452 if (!kvm_vcpu_is_bsp(apic->vcpu))
1453 value &= ~MSR_IA32_APICBASE_BSP;
1454 vcpu->arch.apic_base = value;
1455
c5cc421b 1456 /* update jump label if enable bit changes */
0dce7cd6 1457 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
c5cc421b
GN		 1458 if (value & MSR_IA32_APICBASE_ENABLE)
1459 static_key_slow_dec_deferred(&apic_hw_disabled);
1460 else
1461 static_key_slow_inc(&apic_hw_disabled.key);
1e08ec4a 1462 recalculate_apic_map(vcpu->kvm);
c5cc421b
GN		 1463 }
1464
8d14695f
YZ		 1465 if ((old_value ^ value) & X2APIC_ENABLE) {
1466 if (value & X2APIC_ENABLE) {
1467 u32 id = kvm_apic_id(apic);
1468 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1469 kvm_apic_set_ldr(apic, ldr);
1470 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1471 } else
1472 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
0105d1a5 1473 }
8d14695f 1474
ad312c7c 1475 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 1476 MSR_IA32_APICBASE_BASE;
1477
db324fe6
NA		 1478 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1479 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1480 pr_warn_once("APIC base relocation is unsupported by KVM");
1481
97222cc8
ED		 1482 /* with FSB delivery interrupt, we can restart APIC functionality */
1483 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
ad312c7c 1484 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1485
1486}
1487
c5ec1534 1488void kvm_lapic_reset(struct kvm_vcpu *vcpu)
97222cc8
ED		 1489{
1490 struct kvm_lapic *apic;
1491 int i;
1492
b8688d51 1493 apic_debug("%s\n", __func__);
97222cc8
ED		 1494
1495 ASSERT(vcpu);
ad312c7c 1496 apic = vcpu->arch.apic;
97222cc8
ED		 1497 ASSERT(apic != NULL);
1498
1499 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 1500 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1501
1e08ec4a 1502 kvm_apic_set_id(apic, vcpu->vcpu_id);
fc61b800 1503 kvm_apic_set_version(apic->vcpu);
97222cc8
ED		 1504
1505 for (i = 0; i < APIC_LVT_NUM; i++)
1506 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
a323b409 1507 apic->lapic_timer.timer_mode = 0;
40487c68
QH		 1508 apic_set_reg(apic, APIC_LVT0,
1509 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
97222cc8
ED		 1510
1511 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
f8c1ea10 1512 apic_set_spiv(apic, 0xff);
97222cc8 1513 apic_set_reg(apic, APIC_TASKPRI, 0);
1e08ec4a 1514 kvm_apic_set_ldr(apic, 0);
97222cc8
ED		 1515 apic_set_reg(apic, APIC_ESR, 0);
1516 apic_set_reg(apic, APIC_ICR, 0);
1517 apic_set_reg(apic, APIC_ICR2, 0);
1518 apic_set_reg(apic, APIC_TDCR, 0);
1519 apic_set_reg(apic, APIC_TMICT, 0);
1520 for (i = 0; i < 8; i++) {
1521 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1522 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1523 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1524 }
c7c9c56c
YZ		 1525 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1526 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
8680b94b 1527 apic->highest_isr_cache = -1;
b33ac88b 1528 update_divide_count(apic);
d3c7b77d 1529 atomic_set(&apic->lapic_timer.pending, 0);
c5af89b6 1530 if (kvm_vcpu_is_bsp(vcpu))
5dbc8f3f
GN		 1531 kvm_lapic_set_base(vcpu,
1532 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
ae7a2a3f 1533 vcpu->arch.pv_eoi.msr_val = 0;
97222cc8
ED		 1534 apic_update_ppr(apic);
1535
e1035715 1536 vcpu->arch.apic_arb_prio = 0;
41383771 1537 vcpu->arch.apic_attention = 0;
e1035715 1538
98eff52a 1539 apic_debug("%s: vcpu=%p, id=%d, base_msr="
b8688d51 1540 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
97222cc8 1541 vcpu, kvm_apic_id(apic),
ad312c7c 1542 vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1543}
1544
97222cc8
ED		 1545/*
1546 *----------------------------------------------------------------------
1547 * timer interface
1548 *----------------------------------------------------------------------
1549 */
1b9778da 1550
2a6eac96 1551static bool lapic_is_periodic(struct kvm_lapic *apic)
97222cc8 1552{
d3c7b77d 1553 return apic_lvtt_period(apic);
97222cc8
ED		 1554}
1555
3d80840d
MT		 1556int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1557{
54e9818f 1558 struct kvm_lapic *apic = vcpu->arch.apic;
3d80840d 1559
c48f1496 1560 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
54e9818f
GN		 1561 apic_lvt_enabled(apic, APIC_LVTT))
1562 return atomic_read(&apic->lapic_timer.pending);
3d80840d
MT		 1563
1564 return 0;
1565}
1566
89342082 1567int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 1568{
c48f1496 1569 u32 reg = kvm_apic_get_reg(apic, lvt_type);
23930f95 1570 int vector, mode, trig_mode;
23930f95 1571
c48f1496 1572 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 1573 vector = reg & APIC_VECTOR_MASK;
1574 mode = reg & APIC_MODE_MASK;
1575 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
b4f2225c
YZ		 1576 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1577 NULL);
23930f95
JK		 1578 }
1579 return 0;
1580}
1b9778da 1581
8fdb2351 1582void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 1583{
8fdb2351
JK		 1584 struct kvm_lapic *apic = vcpu->arch.apic;
1585
1586 if (apic)
1587 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 1588}
1589
d76685c4
GH		 1590static const struct kvm_io_device_ops apic_mmio_ops = {
1591 .read = apic_mmio_read,
1592 .write = apic_mmio_write,
d76685c4
GH		 1593};
1594
e9d90d47
AK		 1595static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1596{
1597 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2a6eac96 1598 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
e9d90d47 1599
5d87db71 1600 apic_timer_expired(apic);
e9d90d47 1601
2a6eac96 1602 if (lapic_is_periodic(apic)) {
e9d90d47
AK		 1603 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1604 return HRTIMER_RESTART;
1605 } else
1606 return HRTIMER_NORESTART;
1607}
1608
97222cc8
ED		 1609int kvm_create_lapic(struct kvm_vcpu *vcpu)
1610{
1611 struct kvm_lapic *apic;
1612
1613 ASSERT(vcpu != NULL);
1614 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1615
1616 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1617 if (!apic)
1618 goto nomem;
1619
ad312c7c 1620 vcpu->arch.apic = apic;
97222cc8 1621
afc20184
TY		 1622 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1623 if (!apic->regs) {
97222cc8
ED		 1624 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1625 vcpu->vcpu_id);
d589444e 1626 goto nomem_free_apic;
97222cc8 1627 }
97222cc8
ED		 1628 apic->vcpu = vcpu;
1629
d3c7b77d
MT		 1630 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1631 HRTIMER_MODE_ABS);
e9d90d47 1632 apic->lapic_timer.timer.function = apic_timer_fn;
d3c7b77d 1633
c5cc421b
GN		 1634 /*
1635 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1636 * thinking that APIC satet has changed.
1637 */
1638 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
6aed64a8
GN		 1639 kvm_lapic_set_base(vcpu,
1640 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
97222cc8 1641
f8c1ea10 1642 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
c5ec1534 1643 kvm_lapic_reset(vcpu);
d76685c4 1644 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
97222cc8
ED		 1645
1646 return 0;
d589444e
RR		 1647nomem_free_apic:
1648 kfree(apic);
97222cc8 1649nomem:
97222cc8
ED		 1650 return -ENOMEM;
1651}
97222cc8
ED		 1652
1653int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1654{
ad312c7c 1655 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1656 int highest_irr;
1657
c48f1496 1658 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
97222cc8
ED		 1659 return -1;
1660
6e5d865c 1661 apic_update_ppr(apic);
97222cc8
ED		 1662 highest_irr = apic_find_highest_irr(apic);
1663 if ((highest_irr == -1) ||
c48f1496 1664 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
97222cc8
ED		 1665 return -1;
1666 return highest_irr;
1667}
1668
40487c68
QH		 1669int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1670{
c48f1496 1671 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 1672 int r = 0;
1673
c48f1496 1674 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
e7dca5c0
CL		 1675 r = 1;
1676 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1677 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1678 r = 1;
40487c68
QH		 1679 return r;
1680}
1681
1b9778da
ED		 1682void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1683{
ad312c7c 1684 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 1685
c48f1496 1686 if (!kvm_vcpu_has_lapic(vcpu))
54e9818f
GN		 1687 return;
1688
1689 if (atomic_read(&apic->lapic_timer.pending) > 0) {
f1ed0450 1690 kvm_apic_local_deliver(apic, APIC_LVTT);
fae0ba21
NA		 1691 if (apic_lvtt_tscdeadline(apic))
1692 apic->lapic_timer.tscdeadline = 0;
f1ed0450 1693 atomic_set(&apic->lapic_timer.pending, 0);
1b9778da
ED		 1694 }
1695}
1696
97222cc8
ED		 1697int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1698{
1699 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 1700 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1701
1702 if (vector == -1)
1703 return -1;
1704
56cc2406
WL		 1705 /*
1706 * We get here even with APIC virtualization enabled, if doing
1707 * nested virtualization and L1 runs with the "acknowledge interrupt
1708 * on exit" mode. Then we cannot inject the interrupt via RVI,
1709 * because the process would deliver it through the IDT.
1710 */
1711
8680b94b 1712 apic_set_isr(vector, apic);
97222cc8
ED		 1713 apic_update_ppr(apic);
1714 apic_clear_irr(vector, apic);
1715 return vector;
1716}
96ad2cc6 1717
64eb0620
GN		 1718void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1719 struct kvm_lapic_state *s)
96ad2cc6 1720{
ad312c7c 1721 struct kvm_lapic *apic = vcpu->arch.apic;
96ad2cc6 1722
5dbc8f3f 1723 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
64eb0620
GN		 1724 /* set SPIV separately to get count of SW disabled APICs right */
1725 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1726 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1e08ec4a
GN		 1727 /* call kvm_apic_set_id() to put apic into apic_map */
1728 kvm_apic_set_id(apic, kvm_apic_id(apic));
fc61b800
GN		 1729 kvm_apic_set_version(vcpu);
1730
96ad2cc6 1731 apic_update_ppr(apic);
d3c7b77d 1732 hrtimer_cancel(&apic->lapic_timer.timer);
96ad2cc6
ED		 1733 update_divide_count(apic);
1734 start_apic_timer(apic);
6e24a6ef 1735 apic->irr_pending = true;
c7c9c56c
YZ		 1736 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
1737 1 : count_vectors(apic->regs + APIC_ISR);
8680b94b 1738 apic->highest_isr_cache = -1;
4114c27d
WW		 1739 if (kvm_x86_ops->hwapic_irr_update)
1740 kvm_x86_ops->hwapic_irr_update(vcpu,
1741 apic_find_highest_irr(apic));
c7c9c56c 1742 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic));
3842d135 1743 kvm_make_request(KVM_REQ_EVENT, vcpu);
10606919 1744 kvm_rtc_eoi_tracking_restore_one(vcpu);
96ad2cc6 1745}
a3d7f85f 1746
2f52d58c 1747void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 1748{
a3d7f85f
ED		 1749 struct hrtimer *timer;
1750
c48f1496 1751 if (!kvm_vcpu_has_lapic(vcpu))
a3d7f85f
ED		 1752 return;
1753
54e9818f 1754 timer = &vcpu->arch.apic->lapic_timer.timer;
a3d7f85f 1755 if (hrtimer_cancel(timer))
beb20d52 1756 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
a3d7f85f 1757}
b93463aa 1758
ae7a2a3f
MT		 1759/*
1760 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1761 *
1762 * Detect whether guest triggered PV EOI since the
1763 * last entry. If yes, set EOI on guests's behalf.
1764 * Clear PV EOI in guest memory in any case.
1765 */
1766static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1767 struct kvm_lapic *apic)
1768{
1769 bool pending;
1770 int vector;
1771 /*
1772 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1773 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1774 *
1775 * KVM_APIC_PV_EOI_PENDING is unset:
1776 * -> host disabled PV EOI.
1777 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1778 * -> host enabled PV EOI, guest did not execute EOI yet.
1779 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1780 * -> host enabled PV EOI, guest executed EOI.
1781 */
1782 BUG_ON(!pv_eoi_enabled(vcpu));
1783 pending = pv_eoi_get_pending(vcpu);
1784 /*
1785 * Clear pending bit in any case: it will be set again on vmentry.
1786 * While this might not be ideal from performance point of view,
1787 * this makes sure pv eoi is only enabled when we know it's safe.
1788 */
1789 pv_eoi_clr_pending(vcpu);
1790 if (pending)
1791 return;
1792 vector = apic_set_eoi(apic);
1793 trace_kvm_pv_eoi(apic, vector);
1794}
1795
b93463aa
AK		 1796void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1797{
1798 u32 data;
b93463aa 1799
ae7a2a3f
MT		 1800 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1801 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1802
41383771 1803 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 1804 return;
1805
fda4e2e8
AH		 1806 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1807 sizeof(u32));
b93463aa
AK		 1808
1809 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1810}
1811
ae7a2a3f
MT		 1812/*
1813 * apic_sync_pv_eoi_to_guest - called before vmentry
1814 *
1815 * Detect whether it's safe to enable PV EOI and
1816 * if yes do so.
1817 */
1818static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1819 struct kvm_lapic *apic)
1820{
1821 if (!pv_eoi_enabled(vcpu) ||
1822 /* IRR set or many bits in ISR: could be nested. */
1823 apic->irr_pending ||
1824 /* Cache not set: could be safe but we don't bother. */
1825 apic->highest_isr_cache == -1 ||
1826 /* Need EOI to update ioapic. */
1827 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1828 /*
1829 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1830 * so we need not do anything here.
1831 */
1832 return;
1833 }
1834
1835 pv_eoi_set_pending(apic->vcpu);
1836}
1837
b93463aa
AK		 1838void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1839{
1840 u32 data, tpr;
1841 int max_irr, max_isr;
ae7a2a3f 1842 struct kvm_lapic *apic = vcpu->arch.apic;
b93463aa 1843
ae7a2a3f
MT		 1844 apic_sync_pv_eoi_to_guest(vcpu, apic);
1845
41383771 1846 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 1847 return;
1848
c48f1496 1849 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
b93463aa
AK		 1850 max_irr = apic_find_highest_irr(apic);
1851 if (max_irr < 0)
1852 max_irr = 0;
1853 max_isr = apic_find_highest_isr(apic);
1854 if (max_isr < 0)
1855 max_isr = 0;
1856 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1857
fda4e2e8
AH		 1858 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1859 sizeof(u32));
b93463aa
AK		 1860}
1861
fda4e2e8 1862int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
b93463aa 1863{
fda4e2e8
AH		 1864 if (vapic_addr) {
1865 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1866 &vcpu->arch.apic->vapic_cache,
1867 vapic_addr, sizeof(u32)))
1868 return -EINVAL;
41383771 1869 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8 1870 } else {
41383771 1871 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8
AH		 1872 }
1873
1874 vcpu->arch.apic->vapic_addr = vapic_addr;
1875 return 0;
b93463aa 1876}
0105d1a5
GN		 1877
1878int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1879{
1880 struct kvm_lapic *apic = vcpu->arch.apic;
1881 u32 reg = (msr - APIC_BASE_MSR) << 4;
1882
1883 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1884 return 1;
1885
c69d3d9b
NA		 1886 if (reg == APIC_ICR2)
1887 return 1;
1888
0105d1a5
GN		 1889 /* if this is ICR write vector before command */
1890 if (msr == 0x830)
1891 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1892 return apic_reg_write(apic, reg, (u32)data);
1893}
1894
1895int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1896{
1897 struct kvm_lapic *apic = vcpu->arch.apic;
1898 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1899
1900 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1901 return 1;
1902
c69d3d9b
NA		 1903 if (reg == APIC_DFR || reg == APIC_ICR2) {
1904 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
1905 reg);
1906 return 1;
1907 }
1908
0105d1a5
GN		 1909 if (apic_reg_read(apic, reg, 4, &low))
1910 return 1;
1911 if (msr == 0x830)
1912 apic_reg_read(apic, APIC_ICR2, 4, &high);
1913
1914 *data = (((u64)high) << 32) | low;
1915
1916 return 0;
1917}
10388a07
GN		 1918
1919int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1920{
1921 struct kvm_lapic *apic = vcpu->arch.apic;
1922
c48f1496 1923 if (!kvm_vcpu_has_lapic(vcpu))
10388a07
GN		 1924 return 1;
1925
1926 /* if this is ICR write vector before command */
1927 if (reg == APIC_ICR)
1928 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1929 return apic_reg_write(apic, reg, (u32)data);
1930}
1931
1932int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1933{
1934 struct kvm_lapic *apic = vcpu->arch.apic;
1935 u32 low, high = 0;
1936
c48f1496 1937 if (!kvm_vcpu_has_lapic(vcpu))
10388a07
GN		 1938 return 1;
1939
1940 if (apic_reg_read(apic, reg, 4, &low))
1941 return 1;
1942 if (reg == APIC_ICR)
1943 apic_reg_read(apic, APIC_ICR2, 4, &high);
1944
1945 *data = (((u64)high) << 32) | low;
1946
1947 return 0;
1948}
ae7a2a3f
MT		 1949
1950int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1951{
1952 u64 addr = data & ~KVM_MSR_ENABLED;
1953 if (!IS_ALIGNED(addr, 4))
1954 return 1;
1955
1956 vcpu->arch.pv_eoi.msr_val = data;
1957 if (!pv_eoi_enabled(vcpu))
1958 return 0;
1959 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
8f964525 1960 addr, sizeof(u8));
ae7a2a3f 1961}
c5cc421b 1962
66450a21
JK		 1963void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
1964{
1965 struct kvm_lapic *apic = vcpu->arch.apic;
2b4a273b 1966 u8 sipi_vector;
299018f4 1967 unsigned long pe;
66450a21 1968
299018f4 1969 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
66450a21
JK		 1970 return;
1971
299018f4
GN		 1972 pe = xchg(&apic->pending_events, 0);
1973
1974 if (test_bit(KVM_APIC_INIT, &pe)) {
66450a21
JK		 1975 kvm_lapic_reset(vcpu);
1976 kvm_vcpu_reset(vcpu);
1977 if (kvm_vcpu_is_bsp(apic->vcpu))
1978 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1979 else
1980 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
1981 }
299018f4 1982 if (test_bit(KVM_APIC_SIPI, &pe) &&
66450a21
JK		 1983 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
1984 /* evaluate pending_events before reading the vector */
1985 smp_rmb();
1986 sipi_vector = apic->sipi_vector;
98eff52a 1987 apic_debug("vcpu %d received sipi with vector # %x\n",
66450a21
JK		 1988 vcpu->vcpu_id, sipi_vector);
1989 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
1990 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1991 }
1992}
1993
c5cc421b
GN		 1994void kvm_lapic_init(void)
1995{
1996 /* do not patch jump label more than once per second */
1997 jump_label_rate_limit(&apic_hw_disabled, HZ);
f8c1ea10 1998 jump_label_rate_limit(&apic_sw_disabled, HZ);
c5cc421b 1999}
Linux kernel - Deliverables
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