Commit | Line | Data |
---|---|---|
97222cc8 ED |
1 | |
2 | /* | |
3 | * Local APIC virtualization | |
4 | * | |
5 | * Copyright (C) 2006 Qumranet, Inc. | |
6 | * Copyright (C) 2007 Novell | |
7 | * Copyright (C) 2007 Intel | |
9611c187 | 8 | * Copyright 2009 Red Hat, Inc. and/or its affiliates. |
97222cc8 ED |
9 | * |
10 | * Authors: | |
11 | * Dor Laor <dor.laor@qumranet.com> | |
12 | * Gregory Haskins <ghaskins@novell.com> | |
13 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
14 | * | |
15 | * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | */ | |
20 | ||
edf88417 | 21 | #include <linux/kvm_host.h> |
97222cc8 ED |
22 | #include <linux/kvm.h> |
23 | #include <linux/mm.h> | |
24 | #include <linux/highmem.h> | |
25 | #include <linux/smp.h> | |
26 | #include <linux/hrtimer.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/module.h> | |
6f6d6a1a | 29 | #include <linux/math64.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
97222cc8 ED |
31 | #include <asm/processor.h> |
32 | #include <asm/msr.h> | |
33 | #include <asm/page.h> | |
34 | #include <asm/current.h> | |
35 | #include <asm/apicdef.h> | |
d0659d94 | 36 | #include <asm/delay.h> |
60063497 | 37 | #include <linux/atomic.h> |
c5cc421b | 38 | #include <linux/jump_label.h> |
5fdbf976 | 39 | #include "kvm_cache_regs.h" |
97222cc8 | 40 | #include "irq.h" |
229456fc | 41 | #include "trace.h" |
fc61b800 | 42 | #include "x86.h" |
00b27a3e | 43 | #include "cpuid.h" |
97222cc8 | 44 | |
b682b814 MT |
45 | #ifndef CONFIG_X86_64 |
46 | #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) | |
47 | #else | |
48 | #define mod_64(x, y) ((x) % (y)) | |
49 | #endif | |
50 | ||
97222cc8 ED |
51 | #define PRId64 "d" |
52 | #define PRIx64 "llx" | |
53 | #define PRIu64 "u" | |
54 | #define PRIo64 "o" | |
55 | ||
56 | #define APIC_BUS_CYCLE_NS 1 | |
57 | ||
58 | /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ | |
59 | #define apic_debug(fmt, arg...) | |
60 | ||
61 | #define APIC_LVT_NUM 6 | |
62 | /* 14 is the version for Xeon and Pentium 8.4.8*/ | |
63 | #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16)) | |
64 | #define LAPIC_MMIO_LENGTH (1 << 12) | |
65 | /* followed define is not in apicdef.h */ | |
66 | #define APIC_SHORT_MASK 0xc0000 | |
67 | #define APIC_DEST_NOSHORT 0x0 | |
68 | #define APIC_DEST_MASK 0x800 | |
69 | #define MAX_APIC_VECTOR 256 | |
ecba9a52 | 70 | #define APIC_VECTORS_PER_REG 32 |
97222cc8 | 71 | |
394457a9 NA |
72 | #define APIC_BROADCAST 0xFF |
73 | #define X2APIC_BROADCAST 0xFFFFFFFFul | |
74 | ||
97222cc8 ED |
75 | #define VEC_POS(v) ((v) & (32 - 1)) |
76 | #define REG_POS(v) (((v) >> 5) << 4) | |
ad312c7c | 77 | |
97222cc8 ED |
78 | static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) |
79 | { | |
80 | *((u32 *) (apic->regs + reg_off)) = val; | |
81 | } | |
82 | ||
a0c9a822 MT |
83 | static inline int apic_test_vector(int vec, void *bitmap) |
84 | { | |
85 | return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
86 | } | |
87 | ||
10606919 YZ |
88 | bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector) |
89 | { | |
90 | struct kvm_lapic *apic = vcpu->arch.apic; | |
91 | ||
92 | return apic_test_vector(vector, apic->regs + APIC_ISR) || | |
93 | apic_test_vector(vector, apic->regs + APIC_IRR); | |
94 | } | |
95 | ||
97222cc8 ED |
96 | static inline void apic_set_vector(int vec, void *bitmap) |
97 | { | |
98 | set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
99 | } | |
100 | ||
101 | static inline void apic_clear_vector(int vec, void *bitmap) | |
102 | { | |
103 | clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
104 | } | |
105 | ||
8680b94b MT |
106 | static inline int __apic_test_and_set_vector(int vec, void *bitmap) |
107 | { | |
108 | return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
109 | } | |
110 | ||
111 | static inline int __apic_test_and_clear_vector(int vec, void *bitmap) | |
112 | { | |
113 | return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
114 | } | |
115 | ||
c5cc421b | 116 | struct static_key_deferred apic_hw_disabled __read_mostly; |
f8c1ea10 GN |
117 | struct static_key_deferred apic_sw_disabled __read_mostly; |
118 | ||
97222cc8 ED |
119 | static inline int apic_enabled(struct kvm_lapic *apic) |
120 | { | |
c48f1496 | 121 | return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic); |
54e9818f GN |
122 | } |
123 | ||
97222cc8 ED |
124 | #define LVT_MASK \ |
125 | (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) | |
126 | ||
127 | #define LINT_MASK \ | |
128 | (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ | |
129 | APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) | |
130 | ||
131 | static inline int kvm_apic_id(struct kvm_lapic *apic) | |
132 | { | |
c48f1496 | 133 | return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff; |
97222cc8 ED |
134 | } |
135 | ||
1e08ec4a GN |
136 | static void recalculate_apic_map(struct kvm *kvm) |
137 | { | |
138 | struct kvm_apic_map *new, *old = NULL; | |
139 | struct kvm_vcpu *vcpu; | |
140 | int i; | |
141 | ||
142 | new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL); | |
143 | ||
144 | mutex_lock(&kvm->arch.apic_map_lock); | |
145 | ||
146 | if (!new) | |
147 | goto out; | |
148 | ||
149 | new->ldr_bits = 8; | |
150 | /* flat mode is default */ | |
151 | new->cid_shift = 8; | |
152 | new->cid_mask = 0; | |
153 | new->lid_mask = 0xff; | |
394457a9 | 154 | new->broadcast = APIC_BROADCAST; |
1e08ec4a GN |
155 | |
156 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
157 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1e08ec4a GN |
158 | |
159 | if (!kvm_apic_present(vcpu)) | |
160 | continue; | |
161 | ||
1e08ec4a GN |
162 | if (apic_x2apic_mode(apic)) { |
163 | new->ldr_bits = 32; | |
164 | new->cid_shift = 16; | |
45c3094a | 165 | new->cid_mask = new->lid_mask = 0xffff; |
394457a9 | 166 | new->broadcast = X2APIC_BROADCAST; |
a3e339e1 | 167 | } else if (kvm_apic_get_reg(apic, APIC_LDR)) { |
173beedc NA |
168 | if (kvm_apic_get_reg(apic, APIC_DFR) == |
169 | APIC_DFR_CLUSTER) { | |
170 | new->cid_shift = 4; | |
171 | new->cid_mask = 0xf; | |
172 | new->lid_mask = 0xf; | |
a3e339e1 PB |
173 | } else { |
174 | new->cid_shift = 8; | |
175 | new->cid_mask = 0; | |
176 | new->lid_mask = 0xff; | |
173beedc | 177 | } |
1e08ec4a | 178 | } |
a3e339e1 PB |
179 | |
180 | /* | |
181 | * All APICs have to be configured in the same mode by an OS. | |
182 | * We take advatage of this while building logical id loockup | |
183 | * table. After reset APICs are in software disabled mode, so if | |
184 | * we find apic with different setting we assume this is the mode | |
185 | * OS wants all apics to be in; build lookup table accordingly. | |
186 | */ | |
187 | if (kvm_apic_sw_enabled(apic)) | |
188 | break; | |
173beedc NA |
189 | } |
190 | ||
191 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
192 | struct kvm_lapic *apic = vcpu->arch.apic; | |
193 | u16 cid, lid; | |
25995e5b | 194 | u32 ldr, aid; |
1e08ec4a | 195 | |
25995e5b | 196 | aid = kvm_apic_id(apic); |
1e08ec4a GN |
197 | ldr = kvm_apic_get_reg(apic, APIC_LDR); |
198 | cid = apic_cluster_id(new, ldr); | |
199 | lid = apic_logical_id(new, ldr); | |
200 | ||
25995e5b RK |
201 | if (aid < ARRAY_SIZE(new->phys_map)) |
202 | new->phys_map[aid] = apic; | |
203 | if (lid && cid < ARRAY_SIZE(new->logical_map)) | |
1e08ec4a GN |
204 | new->logical_map[cid][ffs(lid) - 1] = apic; |
205 | } | |
206 | out: | |
207 | old = rcu_dereference_protected(kvm->arch.apic_map, | |
208 | lockdep_is_held(&kvm->arch.apic_map_lock)); | |
209 | rcu_assign_pointer(kvm->arch.apic_map, new); | |
210 | mutex_unlock(&kvm->arch.apic_map_lock); | |
211 | ||
212 | if (old) | |
213 | kfree_rcu(old, rcu); | |
c7c9c56c | 214 | |
3d81bc7e | 215 | kvm_vcpu_request_scan_ioapic(kvm); |
1e08ec4a GN |
216 | } |
217 | ||
1e1b6c26 NA |
218 | static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val) |
219 | { | |
e462755c | 220 | bool enabled = val & APIC_SPIV_APIC_ENABLED; |
1e1b6c26 NA |
221 | |
222 | apic_set_reg(apic, APIC_SPIV, val); | |
e462755c RK |
223 | |
224 | if (enabled != apic->sw_enabled) { | |
225 | apic->sw_enabled = enabled; | |
226 | if (enabled) { | |
1e1b6c26 NA |
227 | static_key_slow_dec_deferred(&apic_sw_disabled); |
228 | recalculate_apic_map(apic->vcpu->kvm); | |
229 | } else | |
230 | static_key_slow_inc(&apic_sw_disabled.key); | |
231 | } | |
232 | } | |
233 | ||
1e08ec4a GN |
234 | static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id) |
235 | { | |
236 | apic_set_reg(apic, APIC_ID, id << 24); | |
237 | recalculate_apic_map(apic->vcpu->kvm); | |
238 | } | |
239 | ||
240 | static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id) | |
241 | { | |
242 | apic_set_reg(apic, APIC_LDR, id); | |
243 | recalculate_apic_map(apic->vcpu->kvm); | |
244 | } | |
245 | ||
97222cc8 ED |
246 | static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) |
247 | { | |
c48f1496 | 248 | return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); |
97222cc8 ED |
249 | } |
250 | ||
251 | static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) | |
252 | { | |
c48f1496 | 253 | return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; |
97222cc8 ED |
254 | } |
255 | ||
a3e06bbe LJ |
256 | static inline int apic_lvtt_oneshot(struct kvm_lapic *apic) |
257 | { | |
f30ebc31 | 258 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT; |
a3e06bbe LJ |
259 | } |
260 | ||
97222cc8 ED |
261 | static inline int apic_lvtt_period(struct kvm_lapic *apic) |
262 | { | |
f30ebc31 | 263 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC; |
a3e06bbe LJ |
264 | } |
265 | ||
266 | static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic) | |
267 | { | |
f30ebc31 | 268 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE; |
97222cc8 ED |
269 | } |
270 | ||
cc6e462c JK |
271 | static inline int apic_lvt_nmi_mode(u32 lvt_val) |
272 | { | |
273 | return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI; | |
274 | } | |
275 | ||
fc61b800 GN |
276 | void kvm_apic_set_version(struct kvm_vcpu *vcpu) |
277 | { | |
278 | struct kvm_lapic *apic = vcpu->arch.apic; | |
279 | struct kvm_cpuid_entry2 *feat; | |
280 | u32 v = APIC_VERSION; | |
281 | ||
c48f1496 | 282 | if (!kvm_vcpu_has_lapic(vcpu)) |
fc61b800 GN |
283 | return; |
284 | ||
285 | feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0); | |
286 | if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31)))) | |
287 | v |= APIC_LVR_DIRECTED_EOI; | |
288 | apic_set_reg(apic, APIC_LVR, v); | |
289 | } | |
290 | ||
f1d24831 | 291 | static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = { |
a3e06bbe | 292 | LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */ |
97222cc8 ED |
293 | LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ |
294 | LVT_MASK | APIC_MODE_MASK, /* LVTPC */ | |
295 | LINT_MASK, LINT_MASK, /* LVT0-1 */ | |
296 | LVT_MASK /* LVTERR */ | |
297 | }; | |
298 | ||
299 | static int find_highest_vector(void *bitmap) | |
300 | { | |
ecba9a52 TY |
301 | int vec; |
302 | u32 *reg; | |
97222cc8 | 303 | |
ecba9a52 TY |
304 | for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; |
305 | vec >= 0; vec -= APIC_VECTORS_PER_REG) { | |
306 | reg = bitmap + REG_POS(vec); | |
307 | if (*reg) | |
308 | return fls(*reg) - 1 + vec; | |
309 | } | |
97222cc8 | 310 | |
ecba9a52 | 311 | return -1; |
97222cc8 ED |
312 | } |
313 | ||
8680b94b MT |
314 | static u8 count_vectors(void *bitmap) |
315 | { | |
ecba9a52 TY |
316 | int vec; |
317 | u32 *reg; | |
8680b94b | 318 | u8 count = 0; |
ecba9a52 TY |
319 | |
320 | for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) { | |
321 | reg = bitmap + REG_POS(vec); | |
322 | count += hweight32(*reg); | |
323 | } | |
324 | ||
8680b94b MT |
325 | return count; |
326 | } | |
327 | ||
a20ed54d YZ |
328 | void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir) |
329 | { | |
330 | u32 i, pir_val; | |
331 | struct kvm_lapic *apic = vcpu->arch.apic; | |
332 | ||
333 | for (i = 0; i <= 7; i++) { | |
334 | pir_val = xchg(&pir[i], 0); | |
335 | if (pir_val) | |
336 | *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val; | |
337 | } | |
338 | } | |
339 | EXPORT_SYMBOL_GPL(kvm_apic_update_irr); | |
340 | ||
11f5cc05 | 341 | static inline void apic_set_irr(int vec, struct kvm_lapic *apic) |
97222cc8 | 342 | { |
11f5cc05 | 343 | apic_set_vector(vec, apic->regs + APIC_IRR); |
f210f757 NA |
344 | /* |
345 | * irr_pending must be true if any interrupt is pending; set it after | |
346 | * APIC_IRR to avoid race with apic_clear_irr | |
347 | */ | |
348 | apic->irr_pending = true; | |
97222cc8 ED |
349 | } |
350 | ||
33e4c686 | 351 | static inline int apic_search_irr(struct kvm_lapic *apic) |
97222cc8 | 352 | { |
33e4c686 | 353 | return find_highest_vector(apic->regs + APIC_IRR); |
97222cc8 ED |
354 | } |
355 | ||
356 | static inline int apic_find_highest_irr(struct kvm_lapic *apic) | |
357 | { | |
358 | int result; | |
359 | ||
c7c9c56c YZ |
360 | /* |
361 | * Note that irr_pending is just a hint. It will be always | |
362 | * true with virtual interrupt delivery enabled. | |
363 | */ | |
33e4c686 GN |
364 | if (!apic->irr_pending) |
365 | return -1; | |
366 | ||
5a71785d | 367 | kvm_x86_ops->sync_pir_to_irr(apic->vcpu); |
33e4c686 | 368 | result = apic_search_irr(apic); |
97222cc8 ED |
369 | ASSERT(result == -1 || result >= 16); |
370 | ||
371 | return result; | |
372 | } | |
373 | ||
33e4c686 GN |
374 | static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) |
375 | { | |
56cc2406 WL |
376 | struct kvm_vcpu *vcpu; |
377 | ||
378 | vcpu = apic->vcpu; | |
379 | ||
f210f757 | 380 | if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) { |
56cc2406 | 381 | /* try to update RVI */ |
f210f757 | 382 | apic_clear_vector(vec, apic->regs + APIC_IRR); |
56cc2406 | 383 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f210f757 NA |
384 | } else { |
385 | apic->irr_pending = false; | |
386 | apic_clear_vector(vec, apic->regs + APIC_IRR); | |
387 | if (apic_search_irr(apic) != -1) | |
388 | apic->irr_pending = true; | |
56cc2406 | 389 | } |
33e4c686 GN |
390 | } |
391 | ||
8680b94b MT |
392 | static inline void apic_set_isr(int vec, struct kvm_lapic *apic) |
393 | { | |
56cc2406 WL |
394 | struct kvm_vcpu *vcpu; |
395 | ||
396 | if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) | |
397 | return; | |
398 | ||
399 | vcpu = apic->vcpu; | |
fc57ac2c | 400 | |
8680b94b | 401 | /* |
56cc2406 WL |
402 | * With APIC virtualization enabled, all caching is disabled |
403 | * because the processor can modify ISR under the hood. Instead | |
404 | * just set SVI. | |
8680b94b | 405 | */ |
b4eef9b3 | 406 | if (unlikely(kvm_x86_ops->hwapic_isr_update)) |
56cc2406 WL |
407 | kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec); |
408 | else { | |
409 | ++apic->isr_count; | |
410 | BUG_ON(apic->isr_count > MAX_APIC_VECTOR); | |
411 | /* | |
412 | * ISR (in service register) bit is set when injecting an interrupt. | |
413 | * The highest vector is injected. Thus the latest bit set matches | |
414 | * the highest bit in ISR. | |
415 | */ | |
416 | apic->highest_isr_cache = vec; | |
417 | } | |
8680b94b MT |
418 | } |
419 | ||
fc57ac2c PB |
420 | static inline int apic_find_highest_isr(struct kvm_lapic *apic) |
421 | { | |
422 | int result; | |
423 | ||
424 | /* | |
425 | * Note that isr_count is always 1, and highest_isr_cache | |
426 | * is always -1, with APIC virtualization enabled. | |
427 | */ | |
428 | if (!apic->isr_count) | |
429 | return -1; | |
430 | if (likely(apic->highest_isr_cache != -1)) | |
431 | return apic->highest_isr_cache; | |
432 | ||
433 | result = find_highest_vector(apic->regs + APIC_ISR); | |
434 | ASSERT(result == -1 || result >= 16); | |
435 | ||
436 | return result; | |
437 | } | |
438 | ||
8680b94b MT |
439 | static inline void apic_clear_isr(int vec, struct kvm_lapic *apic) |
440 | { | |
fc57ac2c PB |
441 | struct kvm_vcpu *vcpu; |
442 | if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) | |
443 | return; | |
444 | ||
445 | vcpu = apic->vcpu; | |
446 | ||
447 | /* | |
448 | * We do get here for APIC virtualization enabled if the guest | |
449 | * uses the Hyper-V APIC enlightenment. In this case we may need | |
450 | * to trigger a new interrupt delivery by writing the SVI field; | |
451 | * on the other hand isr_count and highest_isr_cache are unused | |
452 | * and must be left alone. | |
453 | */ | |
b4eef9b3 | 454 | if (unlikely(kvm_x86_ops->hwapic_isr_update)) |
fc57ac2c PB |
455 | kvm_x86_ops->hwapic_isr_update(vcpu->kvm, |
456 | apic_find_highest_isr(apic)); | |
457 | else { | |
8680b94b | 458 | --apic->isr_count; |
fc57ac2c PB |
459 | BUG_ON(apic->isr_count < 0); |
460 | apic->highest_isr_cache = -1; | |
461 | } | |
8680b94b MT |
462 | } |
463 | ||
6e5d865c YS |
464 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) |
465 | { | |
6e5d865c YS |
466 | int highest_irr; |
467 | ||
33e4c686 GN |
468 | /* This may race with setting of irr in __apic_accept_irq() and |
469 | * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq | |
470 | * will cause vmexit immediately and the value will be recalculated | |
471 | * on the next vmentry. | |
472 | */ | |
c48f1496 | 473 | if (!kvm_vcpu_has_lapic(vcpu)) |
6e5d865c | 474 | return 0; |
54e9818f | 475 | highest_irr = apic_find_highest_irr(vcpu->arch.apic); |
6e5d865c YS |
476 | |
477 | return highest_irr; | |
478 | } | |
6e5d865c | 479 | |
6da7e3f6 | 480 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, |
b4f2225c YZ |
481 | int vector, int level, int trig_mode, |
482 | unsigned long *dest_map); | |
6da7e3f6 | 483 | |
b4f2225c YZ |
484 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, |
485 | unsigned long *dest_map) | |
97222cc8 | 486 | { |
ad312c7c | 487 | struct kvm_lapic *apic = vcpu->arch.apic; |
8be5453f | 488 | |
58c2dde1 | 489 | return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, |
b4f2225c | 490 | irq->level, irq->trig_mode, dest_map); |
97222cc8 ED |
491 | } |
492 | ||
ae7a2a3f MT |
493 | static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val) |
494 | { | |
495 | ||
496 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val, | |
497 | sizeof(val)); | |
498 | } | |
499 | ||
500 | static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val) | |
501 | { | |
502 | ||
503 | return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val, | |
504 | sizeof(*val)); | |
505 | } | |
506 | ||
507 | static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu) | |
508 | { | |
509 | return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED; | |
510 | } | |
511 | ||
512 | static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu) | |
513 | { | |
514 | u8 val; | |
515 | if (pv_eoi_get_user(vcpu, &val) < 0) | |
516 | apic_debug("Can't read EOI MSR value: 0x%llx\n", | |
96893977 | 517 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
518 | return val & 0x1; |
519 | } | |
520 | ||
521 | static void pv_eoi_set_pending(struct kvm_vcpu *vcpu) | |
522 | { | |
523 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) { | |
524 | apic_debug("Can't set EOI MSR value: 0x%llx\n", | |
96893977 | 525 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
526 | return; |
527 | } | |
528 | __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
529 | } | |
530 | ||
531 | static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu) | |
532 | { | |
533 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) { | |
534 | apic_debug("Can't clear EOI MSR value: 0x%llx\n", | |
96893977 | 535 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
536 | return; |
537 | } | |
538 | __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
539 | } | |
540 | ||
cf9e65b7 YZ |
541 | void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr) |
542 | { | |
543 | struct kvm_lapic *apic = vcpu->arch.apic; | |
544 | int i; | |
545 | ||
546 | for (i = 0; i < 8; i++) | |
547 | apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]); | |
548 | } | |
549 | ||
97222cc8 ED |
550 | static void apic_update_ppr(struct kvm_lapic *apic) |
551 | { | |
3842d135 | 552 | u32 tpr, isrv, ppr, old_ppr; |
97222cc8 ED |
553 | int isr; |
554 | ||
c48f1496 GN |
555 | old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI); |
556 | tpr = kvm_apic_get_reg(apic, APIC_TASKPRI); | |
97222cc8 ED |
557 | isr = apic_find_highest_isr(apic); |
558 | isrv = (isr != -1) ? isr : 0; | |
559 | ||
560 | if ((tpr & 0xf0) >= (isrv & 0xf0)) | |
561 | ppr = tpr & 0xff; | |
562 | else | |
563 | ppr = isrv & 0xf0; | |
564 | ||
565 | apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x", | |
566 | apic, ppr, isr, isrv); | |
567 | ||
3842d135 AK |
568 | if (old_ppr != ppr) { |
569 | apic_set_reg(apic, APIC_PROCPRI, ppr); | |
83bcacb1 AK |
570 | if (ppr < old_ppr) |
571 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); | |
3842d135 | 572 | } |
97222cc8 ED |
573 | } |
574 | ||
575 | static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) | |
576 | { | |
577 | apic_set_reg(apic, APIC_TASKPRI, tpr); | |
578 | apic_update_ppr(apic); | |
579 | } | |
580 | ||
394457a9 NA |
581 | static int kvm_apic_broadcast(struct kvm_lapic *apic, u32 dest) |
582 | { | |
583 | return dest == (apic_x2apic_mode(apic) ? | |
584 | X2APIC_BROADCAST : APIC_BROADCAST); | |
585 | } | |
586 | ||
587 | int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest) | |
97222cc8 | 588 | { |
394457a9 | 589 | return kvm_apic_id(apic) == dest || kvm_apic_broadcast(apic, dest); |
97222cc8 ED |
590 | } |
591 | ||
394457a9 | 592 | int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda) |
97222cc8 ED |
593 | { |
594 | int result = 0; | |
0105d1a5 GN |
595 | u32 logical_id; |
596 | ||
394457a9 NA |
597 | if (kvm_apic_broadcast(apic, mda)) |
598 | return 1; | |
599 | ||
0105d1a5 | 600 | if (apic_x2apic_mode(apic)) { |
c48f1496 | 601 | logical_id = kvm_apic_get_reg(apic, APIC_LDR); |
0105d1a5 GN |
602 | return logical_id & mda; |
603 | } | |
97222cc8 | 604 | |
c48f1496 | 605 | logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR)); |
97222cc8 | 606 | |
c48f1496 | 607 | switch (kvm_apic_get_reg(apic, APIC_DFR)) { |
97222cc8 ED |
608 | case APIC_DFR_FLAT: |
609 | if (logical_id & mda) | |
610 | result = 1; | |
611 | break; | |
612 | case APIC_DFR_CLUSTER: | |
613 | if (((logical_id >> 4) == (mda >> 0x4)) | |
614 | && (logical_id & mda & 0xf)) | |
615 | result = 1; | |
616 | break; | |
617 | default: | |
7712de87 | 618 | apic_debug("Bad DFR vcpu %d: %08x\n", |
c48f1496 | 619 | apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR)); |
97222cc8 ED |
620 | break; |
621 | } | |
622 | ||
623 | return result; | |
624 | } | |
625 | ||
343f94fe | 626 | int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, |
394457a9 | 627 | int short_hand, unsigned int dest, int dest_mode) |
97222cc8 ED |
628 | { |
629 | int result = 0; | |
ad312c7c | 630 | struct kvm_lapic *target = vcpu->arch.apic; |
97222cc8 ED |
631 | |
632 | apic_debug("target %p, source %p, dest 0x%x, " | |
343f94fe | 633 | "dest_mode 0x%x, short_hand 0x%x\n", |
97222cc8 ED |
634 | target, source, dest, dest_mode, short_hand); |
635 | ||
bd371396 | 636 | ASSERT(target); |
97222cc8 ED |
637 | switch (short_hand) { |
638 | case APIC_DEST_NOSHORT: | |
343f94fe | 639 | if (dest_mode == 0) |
97222cc8 | 640 | /* Physical mode. */ |
343f94fe GN |
641 | result = kvm_apic_match_physical_addr(target, dest); |
642 | else | |
97222cc8 ED |
643 | /* Logical mode. */ |
644 | result = kvm_apic_match_logical_addr(target, dest); | |
645 | break; | |
646 | case APIC_DEST_SELF: | |
343f94fe | 647 | result = (target == source); |
97222cc8 ED |
648 | break; |
649 | case APIC_DEST_ALLINC: | |
650 | result = 1; | |
651 | break; | |
652 | case APIC_DEST_ALLBUT: | |
343f94fe | 653 | result = (target != source); |
97222cc8 ED |
654 | break; |
655 | default: | |
7712de87 JK |
656 | apic_debug("kvm: apic: Bad dest shorthand value %x\n", |
657 | short_hand); | |
97222cc8 ED |
658 | break; |
659 | } | |
660 | ||
661 | return result; | |
662 | } | |
663 | ||
1e08ec4a | 664 | bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, |
b4f2225c | 665 | struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map) |
1e08ec4a GN |
666 | { |
667 | struct kvm_apic_map *map; | |
668 | unsigned long bitmap = 1; | |
669 | struct kvm_lapic **dst; | |
670 | int i; | |
671 | bool ret = false; | |
672 | ||
673 | *r = -1; | |
674 | ||
675 | if (irq->shorthand == APIC_DEST_SELF) { | |
b4f2225c | 676 | *r = kvm_apic_set_irq(src->vcpu, irq, dest_map); |
1e08ec4a GN |
677 | return true; |
678 | } | |
679 | ||
680 | if (irq->shorthand) | |
681 | return false; | |
682 | ||
683 | rcu_read_lock(); | |
684 | map = rcu_dereference(kvm->arch.apic_map); | |
685 | ||
686 | if (!map) | |
687 | goto out; | |
688 | ||
394457a9 NA |
689 | if (irq->dest_id == map->broadcast) |
690 | goto out; | |
691 | ||
698f9755 RK |
692 | ret = true; |
693 | ||
1e08ec4a | 694 | if (irq->dest_mode == 0) { /* physical mode */ |
fa834e91 RK |
695 | if (irq->dest_id >= ARRAY_SIZE(map->phys_map)) |
696 | goto out; | |
697 | ||
698 | dst = &map->phys_map[irq->dest_id]; | |
1e08ec4a GN |
699 | } else { |
700 | u32 mda = irq->dest_id << (32 - map->ldr_bits); | |
45c3094a RK |
701 | u16 cid = apic_cluster_id(map, mda); |
702 | ||
703 | if (cid >= ARRAY_SIZE(map->logical_map)) | |
704 | goto out; | |
1e08ec4a | 705 | |
45c3094a | 706 | dst = map->logical_map[cid]; |
1e08ec4a GN |
707 | |
708 | bitmap = apic_logical_id(map, mda); | |
709 | ||
710 | if (irq->delivery_mode == APIC_DM_LOWEST) { | |
711 | int l = -1; | |
712 | for_each_set_bit(i, &bitmap, 16) { | |
713 | if (!dst[i]) | |
714 | continue; | |
715 | if (l < 0) | |
716 | l = i; | |
717 | else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0) | |
718 | l = i; | |
719 | } | |
720 | ||
721 | bitmap = (l >= 0) ? 1 << l : 0; | |
722 | } | |
723 | } | |
724 | ||
725 | for_each_set_bit(i, &bitmap, 16) { | |
726 | if (!dst[i]) | |
727 | continue; | |
728 | if (*r < 0) | |
729 | *r = 0; | |
b4f2225c | 730 | *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map); |
1e08ec4a | 731 | } |
1e08ec4a GN |
732 | out: |
733 | rcu_read_unlock(); | |
734 | return ret; | |
735 | } | |
736 | ||
97222cc8 ED |
737 | /* |
738 | * Add a pending IRQ into lapic. | |
739 | * Return 1 if successfully added and 0 if discarded. | |
740 | */ | |
741 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, | |
b4f2225c YZ |
742 | int vector, int level, int trig_mode, |
743 | unsigned long *dest_map) | |
97222cc8 | 744 | { |
6da7e3f6 | 745 | int result = 0; |
c5ec1534 | 746 | struct kvm_vcpu *vcpu = apic->vcpu; |
97222cc8 | 747 | |
a183b638 PB |
748 | trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode, |
749 | trig_mode, vector); | |
97222cc8 | 750 | switch (delivery_mode) { |
97222cc8 | 751 | case APIC_DM_LOWEST: |
e1035715 GN |
752 | vcpu->arch.apic_arb_prio++; |
753 | case APIC_DM_FIXED: | |
97222cc8 ED |
754 | /* FIXME add logic for vcpu on reset */ |
755 | if (unlikely(!apic_enabled(apic))) | |
756 | break; | |
757 | ||
11f5cc05 JK |
758 | result = 1; |
759 | ||
b4f2225c YZ |
760 | if (dest_map) |
761 | __set_bit(vcpu->vcpu_id, dest_map); | |
a5d36f82 | 762 | |
11f5cc05 | 763 | if (kvm_x86_ops->deliver_posted_interrupt) |
5a71785d | 764 | kvm_x86_ops->deliver_posted_interrupt(vcpu, vector); |
11f5cc05 JK |
765 | else { |
766 | apic_set_irr(vector, apic); | |
5a71785d YZ |
767 | |
768 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
769 | kvm_vcpu_kick(vcpu); | |
770 | } | |
97222cc8 ED |
771 | break; |
772 | ||
773 | case APIC_DM_REMRD: | |
24d2166b R |
774 | result = 1; |
775 | vcpu->arch.pv.pv_unhalted = 1; | |
776 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
777 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
778 | break; |
779 | ||
780 | case APIC_DM_SMI: | |
7712de87 | 781 | apic_debug("Ignoring guest SMI\n"); |
97222cc8 | 782 | break; |
3419ffc8 | 783 | |
97222cc8 | 784 | case APIC_DM_NMI: |
6da7e3f6 | 785 | result = 1; |
3419ffc8 | 786 | kvm_inject_nmi(vcpu); |
26df99c6 | 787 | kvm_vcpu_kick(vcpu); |
97222cc8 ED |
788 | break; |
789 | ||
790 | case APIC_DM_INIT: | |
a52315e1 | 791 | if (!trig_mode || level) { |
6da7e3f6 | 792 | result = 1; |
66450a21 JK |
793 | /* assumes that there are only KVM_APIC_INIT/SIPI */ |
794 | apic->pending_events = (1UL << KVM_APIC_INIT); | |
795 | /* make sure pending_events is visible before sending | |
796 | * the request */ | |
797 | smp_wmb(); | |
3842d135 | 798 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
c5ec1534 HQ |
799 | kvm_vcpu_kick(vcpu); |
800 | } else { | |
1b10bf31 JK |
801 | apic_debug("Ignoring de-assert INIT to vcpu %d\n", |
802 | vcpu->vcpu_id); | |
c5ec1534 | 803 | } |
97222cc8 ED |
804 | break; |
805 | ||
806 | case APIC_DM_STARTUP: | |
1b10bf31 JK |
807 | apic_debug("SIPI to vcpu %d vector 0x%02x\n", |
808 | vcpu->vcpu_id, vector); | |
66450a21 JK |
809 | result = 1; |
810 | apic->sipi_vector = vector; | |
811 | /* make sure sipi_vector is visible for the receiver */ | |
812 | smp_wmb(); | |
813 | set_bit(KVM_APIC_SIPI, &apic->pending_events); | |
814 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
815 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
816 | break; |
817 | ||
23930f95 JK |
818 | case APIC_DM_EXTINT: |
819 | /* | |
820 | * Should only be called by kvm_apic_local_deliver() with LVT0, | |
821 | * before NMI watchdog was enabled. Already handled by | |
822 | * kvm_apic_accept_pic_intr(). | |
823 | */ | |
824 | break; | |
825 | ||
97222cc8 ED |
826 | default: |
827 | printk(KERN_ERR "TODO: unsupported delivery mode %x\n", | |
828 | delivery_mode); | |
829 | break; | |
830 | } | |
831 | return result; | |
832 | } | |
833 | ||
e1035715 | 834 | int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2) |
8be5453f | 835 | { |
e1035715 | 836 | return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; |
8be5453f ZX |
837 | } |
838 | ||
c7c9c56c YZ |
839 | static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector) |
840 | { | |
841 | if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) && | |
842 | kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) { | |
843 | int trigger_mode; | |
844 | if (apic_test_vector(vector, apic->regs + APIC_TMR)) | |
845 | trigger_mode = IOAPIC_LEVEL_TRIG; | |
846 | else | |
847 | trigger_mode = IOAPIC_EDGE_TRIG; | |
1fcc7890 | 848 | kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); |
c7c9c56c YZ |
849 | } |
850 | } | |
851 | ||
ae7a2a3f | 852 | static int apic_set_eoi(struct kvm_lapic *apic) |
97222cc8 ED |
853 | { |
854 | int vector = apic_find_highest_isr(apic); | |
ae7a2a3f MT |
855 | |
856 | trace_kvm_eoi(apic, vector); | |
857 | ||
97222cc8 ED |
858 | /* |
859 | * Not every write EOI will has corresponding ISR, | |
860 | * one example is when Kernel check timer on setup_IO_APIC | |
861 | */ | |
862 | if (vector == -1) | |
ae7a2a3f | 863 | return vector; |
97222cc8 | 864 | |
8680b94b | 865 | apic_clear_isr(vector, apic); |
97222cc8 ED |
866 | apic_update_ppr(apic); |
867 | ||
c7c9c56c | 868 | kvm_ioapic_send_eoi(apic, vector); |
3842d135 | 869 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); |
ae7a2a3f | 870 | return vector; |
97222cc8 ED |
871 | } |
872 | ||
c7c9c56c YZ |
873 | /* |
874 | * this interface assumes a trap-like exit, which has already finished | |
875 | * desired side effect including vISR and vPPR update. | |
876 | */ | |
877 | void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector) | |
878 | { | |
879 | struct kvm_lapic *apic = vcpu->arch.apic; | |
880 | ||
881 | trace_kvm_eoi(apic, vector); | |
882 | ||
883 | kvm_ioapic_send_eoi(apic, vector); | |
884 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); | |
885 | } | |
886 | EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated); | |
887 | ||
97222cc8 ED |
888 | static void apic_send_ipi(struct kvm_lapic *apic) |
889 | { | |
c48f1496 GN |
890 | u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR); |
891 | u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2); | |
58c2dde1 | 892 | struct kvm_lapic_irq irq; |
97222cc8 | 893 | |
58c2dde1 GN |
894 | irq.vector = icr_low & APIC_VECTOR_MASK; |
895 | irq.delivery_mode = icr_low & APIC_MODE_MASK; | |
896 | irq.dest_mode = icr_low & APIC_DEST_MASK; | |
897 | irq.level = icr_low & APIC_INT_ASSERT; | |
898 | irq.trig_mode = icr_low & APIC_INT_LEVELTRIG; | |
899 | irq.shorthand = icr_low & APIC_SHORT_MASK; | |
0105d1a5 GN |
900 | if (apic_x2apic_mode(apic)) |
901 | irq.dest_id = icr_high; | |
902 | else | |
903 | irq.dest_id = GET_APIC_DEST_FIELD(icr_high); | |
97222cc8 | 904 | |
1000ff8d GN |
905 | trace_kvm_apic_ipi(icr_low, irq.dest_id); |
906 | ||
97222cc8 ED |
907 | apic_debug("icr_high 0x%x, icr_low 0x%x, " |
908 | "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, " | |
909 | "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n", | |
9b5843dd | 910 | icr_high, icr_low, irq.shorthand, irq.dest_id, |
58c2dde1 GN |
911 | irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode, |
912 | irq.vector); | |
913 | ||
b4f2225c | 914 | kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); |
97222cc8 ED |
915 | } |
916 | ||
917 | static u32 apic_get_tmcct(struct kvm_lapic *apic) | |
918 | { | |
b682b814 MT |
919 | ktime_t remaining; |
920 | s64 ns; | |
9da8f4e8 | 921 | u32 tmcct; |
97222cc8 ED |
922 | |
923 | ASSERT(apic != NULL); | |
924 | ||
9da8f4e8 | 925 | /* if initial count is 0, current count should also be 0 */ |
b963a22e AH |
926 | if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 || |
927 | apic->lapic_timer.period == 0) | |
9da8f4e8 KP |
928 | return 0; |
929 | ||
ace15464 | 930 | remaining = hrtimer_get_remaining(&apic->lapic_timer.timer); |
b682b814 MT |
931 | if (ktime_to_ns(remaining) < 0) |
932 | remaining = ktime_set(0, 0); | |
933 | ||
d3c7b77d MT |
934 | ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); |
935 | tmcct = div64_u64(ns, | |
936 | (APIC_BUS_CYCLE_NS * apic->divide_count)); | |
97222cc8 ED |
937 | |
938 | return tmcct; | |
939 | } | |
940 | ||
b209749f AK |
941 | static void __report_tpr_access(struct kvm_lapic *apic, bool write) |
942 | { | |
943 | struct kvm_vcpu *vcpu = apic->vcpu; | |
944 | struct kvm_run *run = vcpu->run; | |
945 | ||
a8eeb04a | 946 | kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu); |
5fdbf976 | 947 | run->tpr_access.rip = kvm_rip_read(vcpu); |
b209749f AK |
948 | run->tpr_access.is_write = write; |
949 | } | |
950 | ||
951 | static inline void report_tpr_access(struct kvm_lapic *apic, bool write) | |
952 | { | |
953 | if (apic->vcpu->arch.tpr_access_reporting) | |
954 | __report_tpr_access(apic, write); | |
955 | } | |
956 | ||
97222cc8 ED |
957 | static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) |
958 | { | |
959 | u32 val = 0; | |
960 | ||
961 | if (offset >= LAPIC_MMIO_LENGTH) | |
962 | return 0; | |
963 | ||
964 | switch (offset) { | |
0105d1a5 GN |
965 | case APIC_ID: |
966 | if (apic_x2apic_mode(apic)) | |
967 | val = kvm_apic_id(apic); | |
968 | else | |
969 | val = kvm_apic_id(apic) << 24; | |
970 | break; | |
97222cc8 | 971 | case APIC_ARBPRI: |
7712de87 | 972 | apic_debug("Access APIC ARBPRI register which is for P6\n"); |
97222cc8 ED |
973 | break; |
974 | ||
975 | case APIC_TMCCT: /* Timer CCR */ | |
a3e06bbe LJ |
976 | if (apic_lvtt_tscdeadline(apic)) |
977 | return 0; | |
978 | ||
97222cc8 ED |
979 | val = apic_get_tmcct(apic); |
980 | break; | |
4a4541a4 AK |
981 | case APIC_PROCPRI: |
982 | apic_update_ppr(apic); | |
c48f1496 | 983 | val = kvm_apic_get_reg(apic, offset); |
4a4541a4 | 984 | break; |
b209749f AK |
985 | case APIC_TASKPRI: |
986 | report_tpr_access(apic, false); | |
987 | /* fall thru */ | |
97222cc8 | 988 | default: |
c48f1496 | 989 | val = kvm_apic_get_reg(apic, offset); |
97222cc8 ED |
990 | break; |
991 | } | |
992 | ||
993 | return val; | |
994 | } | |
995 | ||
d76685c4 GH |
996 | static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev) |
997 | { | |
998 | return container_of(dev, struct kvm_lapic, dev); | |
999 | } | |
1000 | ||
0105d1a5 GN |
1001 | static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len, |
1002 | void *data) | |
97222cc8 | 1003 | { |
97222cc8 ED |
1004 | unsigned char alignment = offset & 0xf; |
1005 | u32 result; | |
d5b0b5b1 | 1006 | /* this bitmask has a bit cleared for each reserved register */ |
0105d1a5 | 1007 | static const u64 rmask = 0x43ff01ffffffe70cULL; |
97222cc8 ED |
1008 | |
1009 | if ((alignment + len) > 4) { | |
4088bb3c GN |
1010 | apic_debug("KVM_APIC_READ: alignment error %x %d\n", |
1011 | offset, len); | |
0105d1a5 | 1012 | return 1; |
97222cc8 | 1013 | } |
0105d1a5 GN |
1014 | |
1015 | if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) { | |
4088bb3c GN |
1016 | apic_debug("KVM_APIC_READ: read reserved register %x\n", |
1017 | offset); | |
0105d1a5 GN |
1018 | return 1; |
1019 | } | |
1020 | ||
97222cc8 ED |
1021 | result = __apic_read(apic, offset & ~0xf); |
1022 | ||
229456fc MT |
1023 | trace_kvm_apic_read(offset, result); |
1024 | ||
97222cc8 ED |
1025 | switch (len) { |
1026 | case 1: | |
1027 | case 2: | |
1028 | case 4: | |
1029 | memcpy(data, (char *)&result + alignment, len); | |
1030 | break; | |
1031 | default: | |
1032 | printk(KERN_ERR "Local APIC read with len = %x, " | |
1033 | "should be 1,2, or 4 instead\n", len); | |
1034 | break; | |
1035 | } | |
bda9020e | 1036 | return 0; |
97222cc8 ED |
1037 | } |
1038 | ||
0105d1a5 GN |
1039 | static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) |
1040 | { | |
c48f1496 | 1041 | return kvm_apic_hw_enabled(apic) && |
0105d1a5 GN |
1042 | addr >= apic->base_address && |
1043 | addr < apic->base_address + LAPIC_MMIO_LENGTH; | |
1044 | } | |
1045 | ||
1046 | static int apic_mmio_read(struct kvm_io_device *this, | |
1047 | gpa_t address, int len, void *data) | |
1048 | { | |
1049 | struct kvm_lapic *apic = to_lapic(this); | |
1050 | u32 offset = address - apic->base_address; | |
1051 | ||
1052 | if (!apic_mmio_in_range(apic, address)) | |
1053 | return -EOPNOTSUPP; | |
1054 | ||
1055 | apic_reg_read(apic, offset, len, data); | |
1056 | ||
1057 | return 0; | |
1058 | } | |
1059 | ||
97222cc8 ED |
1060 | static void update_divide_count(struct kvm_lapic *apic) |
1061 | { | |
1062 | u32 tmp1, tmp2, tdcr; | |
1063 | ||
c48f1496 | 1064 | tdcr = kvm_apic_get_reg(apic, APIC_TDCR); |
97222cc8 ED |
1065 | tmp1 = tdcr & 0xf; |
1066 | tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; | |
d3c7b77d | 1067 | apic->divide_count = 0x1 << (tmp2 & 0x7); |
97222cc8 ED |
1068 | |
1069 | apic_debug("timer divide count is 0x%x\n", | |
9b5843dd | 1070 | apic->divide_count); |
97222cc8 ED |
1071 | } |
1072 | ||
5d87db71 RK |
1073 | static void apic_timer_expired(struct kvm_lapic *apic) |
1074 | { | |
1075 | struct kvm_vcpu *vcpu = apic->vcpu; | |
1076 | wait_queue_head_t *q = &vcpu->wq; | |
d0659d94 | 1077 | struct kvm_timer *ktimer = &apic->lapic_timer; |
5d87db71 RK |
1078 | |
1079 | /* | |
1080 | * Note: KVM_REQ_PENDING_TIMER is implicitly checked in | |
1081 | * vcpu_enter_guest. | |
1082 | */ | |
1083 | if (atomic_read(&apic->lapic_timer.pending)) | |
1084 | return; | |
1085 | ||
1086 | atomic_inc(&apic->lapic_timer.pending); | |
1087 | /* FIXME: this code should not know anything about vcpus */ | |
1088 | kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); | |
1089 | ||
1090 | if (waitqueue_active(q)) | |
1091 | wake_up_interruptible(q); | |
d0659d94 MT |
1092 | |
1093 | if (apic_lvtt_tscdeadline(apic)) | |
1094 | ktimer->expired_tscdeadline = ktimer->tscdeadline; | |
1095 | } | |
1096 | ||
1097 | /* | |
1098 | * On APICv, this test will cause a busy wait | |
1099 | * during a higher-priority task. | |
1100 | */ | |
1101 | ||
1102 | static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu) | |
1103 | { | |
1104 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1105 | u32 reg = kvm_apic_get_reg(apic, APIC_LVTT); | |
1106 | ||
1107 | if (kvm_apic_hw_enabled(apic)) { | |
1108 | int vec = reg & APIC_VECTOR_MASK; | |
1109 | ||
1110 | if (kvm_x86_ops->test_posted_interrupt) | |
1111 | return kvm_x86_ops->test_posted_interrupt(vcpu, vec); | |
1112 | else { | |
1113 | if (apic_test_vector(vec, apic->regs + APIC_ISR)) | |
1114 | return true; | |
1115 | } | |
1116 | } | |
1117 | return false; | |
1118 | } | |
1119 | ||
1120 | void wait_lapic_expire(struct kvm_vcpu *vcpu) | |
1121 | { | |
1122 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1123 | u64 guest_tsc, tsc_deadline; | |
1124 | ||
1125 | if (!kvm_vcpu_has_lapic(vcpu)) | |
1126 | return; | |
1127 | ||
1128 | if (apic->lapic_timer.expired_tscdeadline == 0) | |
1129 | return; | |
1130 | ||
1131 | if (!lapic_timer_int_injected(vcpu)) | |
1132 | return; | |
1133 | ||
1134 | tsc_deadline = apic->lapic_timer.expired_tscdeadline; | |
1135 | apic->lapic_timer.expired_tscdeadline = 0; | |
1136 | guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc()); | |
6c19b753 | 1137 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline); |
d0659d94 MT |
1138 | |
1139 | /* __delay is delay_tsc whenever the hardware has TSC, thus always. */ | |
1140 | if (guest_tsc < tsc_deadline) | |
1141 | __delay(tsc_deadline - guest_tsc); | |
5d87db71 RK |
1142 | } |
1143 | ||
97222cc8 ED |
1144 | static void start_apic_timer(struct kvm_lapic *apic) |
1145 | { | |
a3e06bbe | 1146 | ktime_t now; |
d0659d94 | 1147 | |
d3c7b77d | 1148 | atomic_set(&apic->lapic_timer.pending, 0); |
0b975a3c | 1149 | |
a3e06bbe | 1150 | if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) { |
d5b0b5b1 | 1151 | /* lapic timer in oneshot or periodic mode */ |
a3e06bbe | 1152 | now = apic->lapic_timer.timer.base->get_time(); |
c48f1496 | 1153 | apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT) |
a3e06bbe LJ |
1154 | * APIC_BUS_CYCLE_NS * apic->divide_count; |
1155 | ||
1156 | if (!apic->lapic_timer.period) | |
1157 | return; | |
1158 | /* | |
1159 | * Do not allow the guest to program periodic timers with small | |
1160 | * interval, since the hrtimers are not throttled by the host | |
1161 | * scheduler. | |
1162 | */ | |
1163 | if (apic_lvtt_period(apic)) { | |
1164 | s64 min_period = min_timer_period_us * 1000LL; | |
1165 | ||
1166 | if (apic->lapic_timer.period < min_period) { | |
1167 | pr_info_ratelimited( | |
1168 | "kvm: vcpu %i: requested %lld ns " | |
1169 | "lapic timer period limited to %lld ns\n", | |
1170 | apic->vcpu->vcpu_id, | |
1171 | apic->lapic_timer.period, min_period); | |
1172 | apic->lapic_timer.period = min_period; | |
1173 | } | |
9bc5791d | 1174 | } |
0b975a3c | 1175 | |
a3e06bbe LJ |
1176 | hrtimer_start(&apic->lapic_timer.timer, |
1177 | ktime_add_ns(now, apic->lapic_timer.period), | |
1178 | HRTIMER_MODE_ABS); | |
97222cc8 | 1179 | |
a3e06bbe | 1180 | apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016" |
97222cc8 ED |
1181 | PRIx64 ", " |
1182 | "timer initial count 0x%x, period %lldns, " | |
b8688d51 | 1183 | "expire @ 0x%016" PRIx64 ".\n", __func__, |
97222cc8 | 1184 | APIC_BUS_CYCLE_NS, ktime_to_ns(now), |
c48f1496 | 1185 | kvm_apic_get_reg(apic, APIC_TMICT), |
d3c7b77d | 1186 | apic->lapic_timer.period, |
97222cc8 | 1187 | ktime_to_ns(ktime_add_ns(now, |
d3c7b77d | 1188 | apic->lapic_timer.period))); |
a3e06bbe LJ |
1189 | } else if (apic_lvtt_tscdeadline(apic)) { |
1190 | /* lapic timer in tsc deadline mode */ | |
1191 | u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline; | |
1192 | u64 ns = 0; | |
d0659d94 | 1193 | ktime_t expire; |
a3e06bbe | 1194 | struct kvm_vcpu *vcpu = apic->vcpu; |
cc578287 | 1195 | unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz; |
a3e06bbe LJ |
1196 | unsigned long flags; |
1197 | ||
1198 | if (unlikely(!tscdeadline || !this_tsc_khz)) | |
1199 | return; | |
1200 | ||
1201 | local_irq_save(flags); | |
1202 | ||
1203 | now = apic->lapic_timer.timer.base->get_time(); | |
886b470c | 1204 | guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc()); |
a3e06bbe LJ |
1205 | if (likely(tscdeadline > guest_tsc)) { |
1206 | ns = (tscdeadline - guest_tsc) * 1000000ULL; | |
1207 | do_div(ns, this_tsc_khz); | |
d0659d94 MT |
1208 | expire = ktime_add_ns(now, ns); |
1209 | expire = ktime_sub_ns(expire, lapic_timer_advance_ns); | |
1e0ad70c | 1210 | hrtimer_start(&apic->lapic_timer.timer, |
d0659d94 | 1211 | expire, HRTIMER_MODE_ABS); |
1e0ad70c RK |
1212 | } else |
1213 | apic_timer_expired(apic); | |
a3e06bbe LJ |
1214 | |
1215 | local_irq_restore(flags); | |
1216 | } | |
97222cc8 ED |
1217 | } |
1218 | ||
cc6e462c JK |
1219 | static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) |
1220 | { | |
c48f1496 | 1221 | int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0)); |
cc6e462c JK |
1222 | |
1223 | if (apic_lvt_nmi_mode(lvt0_val)) { | |
1224 | if (!nmi_wd_enabled) { | |
1225 | apic_debug("Receive NMI setting on APIC_LVT0 " | |
1226 | "for cpu %d\n", apic->vcpu->vcpu_id); | |
1227 | apic->vcpu->kvm->arch.vapics_in_nmi_mode++; | |
1228 | } | |
1229 | } else if (nmi_wd_enabled) | |
1230 | apic->vcpu->kvm->arch.vapics_in_nmi_mode--; | |
1231 | } | |
1232 | ||
0105d1a5 | 1233 | static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) |
97222cc8 | 1234 | { |
0105d1a5 | 1235 | int ret = 0; |
97222cc8 | 1236 | |
0105d1a5 | 1237 | trace_kvm_apic_write(reg, val); |
97222cc8 | 1238 | |
0105d1a5 | 1239 | switch (reg) { |
97222cc8 | 1240 | case APIC_ID: /* Local APIC ID */ |
0105d1a5 | 1241 | if (!apic_x2apic_mode(apic)) |
1e08ec4a | 1242 | kvm_apic_set_id(apic, val >> 24); |
0105d1a5 GN |
1243 | else |
1244 | ret = 1; | |
97222cc8 ED |
1245 | break; |
1246 | ||
1247 | case APIC_TASKPRI: | |
b209749f | 1248 | report_tpr_access(apic, true); |
97222cc8 ED |
1249 | apic_set_tpr(apic, val & 0xff); |
1250 | break; | |
1251 | ||
1252 | case APIC_EOI: | |
1253 | apic_set_eoi(apic); | |
1254 | break; | |
1255 | ||
1256 | case APIC_LDR: | |
0105d1a5 | 1257 | if (!apic_x2apic_mode(apic)) |
1e08ec4a | 1258 | kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); |
0105d1a5 GN |
1259 | else |
1260 | ret = 1; | |
97222cc8 ED |
1261 | break; |
1262 | ||
1263 | case APIC_DFR: | |
1e08ec4a | 1264 | if (!apic_x2apic_mode(apic)) { |
0105d1a5 | 1265 | apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); |
1e08ec4a GN |
1266 | recalculate_apic_map(apic->vcpu->kvm); |
1267 | } else | |
0105d1a5 | 1268 | ret = 1; |
97222cc8 ED |
1269 | break; |
1270 | ||
fc61b800 GN |
1271 | case APIC_SPIV: { |
1272 | u32 mask = 0x3ff; | |
c48f1496 | 1273 | if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) |
fc61b800 | 1274 | mask |= APIC_SPIV_DIRECTED_EOI; |
f8c1ea10 | 1275 | apic_set_spiv(apic, val & mask); |
97222cc8 ED |
1276 | if (!(val & APIC_SPIV_APIC_ENABLED)) { |
1277 | int i; | |
1278 | u32 lvt_val; | |
1279 | ||
1280 | for (i = 0; i < APIC_LVT_NUM; i++) { | |
c48f1496 | 1281 | lvt_val = kvm_apic_get_reg(apic, |
97222cc8 ED |
1282 | APIC_LVTT + 0x10 * i); |
1283 | apic_set_reg(apic, APIC_LVTT + 0x10 * i, | |
1284 | lvt_val | APIC_LVT_MASKED); | |
1285 | } | |
d3c7b77d | 1286 | atomic_set(&apic->lapic_timer.pending, 0); |
97222cc8 ED |
1287 | |
1288 | } | |
1289 | break; | |
fc61b800 | 1290 | } |
97222cc8 ED |
1291 | case APIC_ICR: |
1292 | /* No delay here, so we always clear the pending bit */ | |
1293 | apic_set_reg(apic, APIC_ICR, val & ~(1 << 12)); | |
1294 | apic_send_ipi(apic); | |
1295 | break; | |
1296 | ||
1297 | case APIC_ICR2: | |
0105d1a5 GN |
1298 | if (!apic_x2apic_mode(apic)) |
1299 | val &= 0xff000000; | |
1300 | apic_set_reg(apic, APIC_ICR2, val); | |
97222cc8 ED |
1301 | break; |
1302 | ||
23930f95 | 1303 | case APIC_LVT0: |
cc6e462c | 1304 | apic_manage_nmi_watchdog(apic, val); |
97222cc8 ED |
1305 | case APIC_LVTTHMR: |
1306 | case APIC_LVTPC: | |
97222cc8 ED |
1307 | case APIC_LVT1: |
1308 | case APIC_LVTERR: | |
1309 | /* TODO: Check vector */ | |
c48f1496 | 1310 | if (!kvm_apic_sw_enabled(apic)) |
97222cc8 ED |
1311 | val |= APIC_LVT_MASKED; |
1312 | ||
0105d1a5 GN |
1313 | val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4]; |
1314 | apic_set_reg(apic, reg, val); | |
97222cc8 ED |
1315 | |
1316 | break; | |
1317 | ||
a323b409 RK |
1318 | case APIC_LVTT: { |
1319 | u32 timer_mode = val & apic->lapic_timer.timer_mode_mask; | |
1320 | ||
1321 | if (apic->lapic_timer.timer_mode != timer_mode) { | |
1322 | apic->lapic_timer.timer_mode = timer_mode; | |
a3e06bbe | 1323 | hrtimer_cancel(&apic->lapic_timer.timer); |
a323b409 | 1324 | } |
a3e06bbe | 1325 | |
c48f1496 | 1326 | if (!kvm_apic_sw_enabled(apic)) |
a3e06bbe LJ |
1327 | val |= APIC_LVT_MASKED; |
1328 | val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); | |
1329 | apic_set_reg(apic, APIC_LVTT, val); | |
1330 | break; | |
a323b409 | 1331 | } |
a3e06bbe | 1332 | |
97222cc8 | 1333 | case APIC_TMICT: |
a3e06bbe LJ |
1334 | if (apic_lvtt_tscdeadline(apic)) |
1335 | break; | |
1336 | ||
d3c7b77d | 1337 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 ED |
1338 | apic_set_reg(apic, APIC_TMICT, val); |
1339 | start_apic_timer(apic); | |
0105d1a5 | 1340 | break; |
97222cc8 ED |
1341 | |
1342 | case APIC_TDCR: | |
1343 | if (val & 4) | |
7712de87 | 1344 | apic_debug("KVM_WRITE:TDCR %x\n", val); |
97222cc8 ED |
1345 | apic_set_reg(apic, APIC_TDCR, val); |
1346 | update_divide_count(apic); | |
1347 | break; | |
1348 | ||
0105d1a5 GN |
1349 | case APIC_ESR: |
1350 | if (apic_x2apic_mode(apic) && val != 0) { | |
7712de87 | 1351 | apic_debug("KVM_WRITE:ESR not zero %x\n", val); |
0105d1a5 GN |
1352 | ret = 1; |
1353 | } | |
1354 | break; | |
1355 | ||
1356 | case APIC_SELF_IPI: | |
1357 | if (apic_x2apic_mode(apic)) { | |
1358 | apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff)); | |
1359 | } else | |
1360 | ret = 1; | |
1361 | break; | |
97222cc8 | 1362 | default: |
0105d1a5 | 1363 | ret = 1; |
97222cc8 ED |
1364 | break; |
1365 | } | |
0105d1a5 GN |
1366 | if (ret) |
1367 | apic_debug("Local APIC Write to read-only register %x\n", reg); | |
1368 | return ret; | |
1369 | } | |
1370 | ||
1371 | static int apic_mmio_write(struct kvm_io_device *this, | |
1372 | gpa_t address, int len, const void *data) | |
1373 | { | |
1374 | struct kvm_lapic *apic = to_lapic(this); | |
1375 | unsigned int offset = address - apic->base_address; | |
1376 | u32 val; | |
1377 | ||
1378 | if (!apic_mmio_in_range(apic, address)) | |
1379 | return -EOPNOTSUPP; | |
1380 | ||
1381 | /* | |
1382 | * APIC register must be aligned on 128-bits boundary. | |
1383 | * 32/64/128 bits registers must be accessed thru 32 bits. | |
1384 | * Refer SDM 8.4.1 | |
1385 | */ | |
1386 | if (len != 4 || (offset & 0xf)) { | |
1387 | /* Don't shout loud, $infamous_os would cause only noise. */ | |
1388 | apic_debug("apic write: bad size=%d %lx\n", len, (long)address); | |
756975bb | 1389 | return 0; |
0105d1a5 GN |
1390 | } |
1391 | ||
1392 | val = *(u32*)data; | |
1393 | ||
1394 | /* too common printing */ | |
1395 | if (offset != APIC_EOI) | |
1396 | apic_debug("%s: offset 0x%x with length 0x%x, and value is " | |
1397 | "0x%x\n", __func__, offset, len, val); | |
1398 | ||
1399 | apic_reg_write(apic, offset & 0xff0, val); | |
1400 | ||
bda9020e | 1401 | return 0; |
97222cc8 ED |
1402 | } |
1403 | ||
58fbbf26 KT |
1404 | void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu) |
1405 | { | |
c48f1496 | 1406 | if (kvm_vcpu_has_lapic(vcpu)) |
58fbbf26 KT |
1407 | apic_reg_write(vcpu->arch.apic, APIC_EOI, 0); |
1408 | } | |
1409 | EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi); | |
1410 | ||
83d4c286 YZ |
1411 | /* emulate APIC access in a trap manner */ |
1412 | void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset) | |
1413 | { | |
1414 | u32 val = 0; | |
1415 | ||
1416 | /* hw has done the conditional check and inst decode */ | |
1417 | offset &= 0xff0; | |
1418 | ||
1419 | apic_reg_read(vcpu->arch.apic, offset, 4, &val); | |
1420 | ||
1421 | /* TODO: optimize to just emulate side effect w/o one more write */ | |
1422 | apic_reg_write(vcpu->arch.apic, offset, val); | |
1423 | } | |
1424 | EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode); | |
1425 | ||
d589444e | 1426 | void kvm_free_lapic(struct kvm_vcpu *vcpu) |
97222cc8 | 1427 | { |
f8c1ea10 GN |
1428 | struct kvm_lapic *apic = vcpu->arch.apic; |
1429 | ||
ad312c7c | 1430 | if (!vcpu->arch.apic) |
97222cc8 ED |
1431 | return; |
1432 | ||
f8c1ea10 | 1433 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 1434 | |
c5cc421b GN |
1435 | if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) |
1436 | static_key_slow_dec_deferred(&apic_hw_disabled); | |
1437 | ||
e462755c | 1438 | if (!apic->sw_enabled) |
f8c1ea10 | 1439 | static_key_slow_dec_deferred(&apic_sw_disabled); |
97222cc8 | 1440 | |
f8c1ea10 GN |
1441 | if (apic->regs) |
1442 | free_page((unsigned long)apic->regs); | |
1443 | ||
1444 | kfree(apic); | |
97222cc8 ED |
1445 | } |
1446 | ||
1447 | /* | |
1448 | *---------------------------------------------------------------------- | |
1449 | * LAPIC interface | |
1450 | *---------------------------------------------------------------------- | |
1451 | */ | |
1452 | ||
a3e06bbe LJ |
1453 | u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu) |
1454 | { | |
1455 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 1456 | |
c48f1496 | 1457 | if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) || |
54e9818f | 1458 | apic_lvtt_period(apic)) |
a3e06bbe LJ |
1459 | return 0; |
1460 | ||
1461 | return apic->lapic_timer.tscdeadline; | |
1462 | } | |
1463 | ||
1464 | void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) | |
1465 | { | |
1466 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 1467 | |
c48f1496 | 1468 | if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) || |
54e9818f | 1469 | apic_lvtt_period(apic)) |
a3e06bbe LJ |
1470 | return; |
1471 | ||
1472 | hrtimer_cancel(&apic->lapic_timer.timer); | |
1473 | apic->lapic_timer.tscdeadline = data; | |
1474 | start_apic_timer(apic); | |
1475 | } | |
1476 | ||
97222cc8 ED |
1477 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) |
1478 | { | |
ad312c7c | 1479 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 | 1480 | |
c48f1496 | 1481 | if (!kvm_vcpu_has_lapic(vcpu)) |
97222cc8 | 1482 | return; |
54e9818f | 1483 | |
b93463aa | 1484 | apic_set_tpr(apic, ((cr8 & 0x0f) << 4) |
c48f1496 | 1485 | | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4)); |
97222cc8 ED |
1486 | } |
1487 | ||
1488 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) | |
1489 | { | |
97222cc8 ED |
1490 | u64 tpr; |
1491 | ||
c48f1496 | 1492 | if (!kvm_vcpu_has_lapic(vcpu)) |
97222cc8 | 1493 | return 0; |
54e9818f | 1494 | |
c48f1496 | 1495 | tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI); |
97222cc8 ED |
1496 | |
1497 | return (tpr & 0xf0) >> 4; | |
1498 | } | |
1499 | ||
1500 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) | |
1501 | { | |
8d14695f | 1502 | u64 old_value = vcpu->arch.apic_base; |
ad312c7c | 1503 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1504 | |
1505 | if (!apic) { | |
1506 | value |= MSR_IA32_APICBASE_BSP; | |
ad312c7c | 1507 | vcpu->arch.apic_base = value; |
97222cc8 ED |
1508 | return; |
1509 | } | |
c5af89b6 | 1510 | |
e66d2ae7 JK |
1511 | if (!kvm_vcpu_is_bsp(apic->vcpu)) |
1512 | value &= ~MSR_IA32_APICBASE_BSP; | |
1513 | vcpu->arch.apic_base = value; | |
1514 | ||
c5cc421b | 1515 | /* update jump label if enable bit changes */ |
0dce7cd6 | 1516 | if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) { |
c5cc421b GN |
1517 | if (value & MSR_IA32_APICBASE_ENABLE) |
1518 | static_key_slow_dec_deferred(&apic_hw_disabled); | |
1519 | else | |
1520 | static_key_slow_inc(&apic_hw_disabled.key); | |
1e08ec4a | 1521 | recalculate_apic_map(vcpu->kvm); |
c5cc421b GN |
1522 | } |
1523 | ||
8d14695f YZ |
1524 | if ((old_value ^ value) & X2APIC_ENABLE) { |
1525 | if (value & X2APIC_ENABLE) { | |
1526 | u32 id = kvm_apic_id(apic); | |
1527 | u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf)); | |
1528 | kvm_apic_set_ldr(apic, ldr); | |
1529 | kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true); | |
1530 | } else | |
1531 | kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false); | |
0105d1a5 | 1532 | } |
8d14695f | 1533 | |
ad312c7c | 1534 | apic->base_address = apic->vcpu->arch.apic_base & |
97222cc8 ED |
1535 | MSR_IA32_APICBASE_BASE; |
1536 | ||
db324fe6 NA |
1537 | if ((value & MSR_IA32_APICBASE_ENABLE) && |
1538 | apic->base_address != APIC_DEFAULT_PHYS_BASE) | |
1539 | pr_warn_once("APIC base relocation is unsupported by KVM"); | |
1540 | ||
97222cc8 ED |
1541 | /* with FSB delivery interrupt, we can restart APIC functionality */ |
1542 | apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is " | |
ad312c7c | 1543 | "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
1544 | |
1545 | } | |
1546 | ||
c5ec1534 | 1547 | void kvm_lapic_reset(struct kvm_vcpu *vcpu) |
97222cc8 ED |
1548 | { |
1549 | struct kvm_lapic *apic; | |
1550 | int i; | |
1551 | ||
b8688d51 | 1552 | apic_debug("%s\n", __func__); |
97222cc8 ED |
1553 | |
1554 | ASSERT(vcpu); | |
ad312c7c | 1555 | apic = vcpu->arch.apic; |
97222cc8 ED |
1556 | ASSERT(apic != NULL); |
1557 | ||
1558 | /* Stop the timer in case it's a reset to an active apic */ | |
d3c7b77d | 1559 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 1560 | |
1e08ec4a | 1561 | kvm_apic_set_id(apic, vcpu->vcpu_id); |
fc61b800 | 1562 | kvm_apic_set_version(apic->vcpu); |
97222cc8 ED |
1563 | |
1564 | for (i = 0; i < APIC_LVT_NUM; i++) | |
1565 | apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); | |
a323b409 | 1566 | apic->lapic_timer.timer_mode = 0; |
40487c68 QH |
1567 | apic_set_reg(apic, APIC_LVT0, |
1568 | SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); | |
97222cc8 ED |
1569 | |
1570 | apic_set_reg(apic, APIC_DFR, 0xffffffffU); | |
f8c1ea10 | 1571 | apic_set_spiv(apic, 0xff); |
97222cc8 | 1572 | apic_set_reg(apic, APIC_TASKPRI, 0); |
1e08ec4a | 1573 | kvm_apic_set_ldr(apic, 0); |
97222cc8 ED |
1574 | apic_set_reg(apic, APIC_ESR, 0); |
1575 | apic_set_reg(apic, APIC_ICR, 0); | |
1576 | apic_set_reg(apic, APIC_ICR2, 0); | |
1577 | apic_set_reg(apic, APIC_TDCR, 0); | |
1578 | apic_set_reg(apic, APIC_TMICT, 0); | |
1579 | for (i = 0; i < 8; i++) { | |
1580 | apic_set_reg(apic, APIC_IRR + 0x10 * i, 0); | |
1581 | apic_set_reg(apic, APIC_ISR + 0x10 * i, 0); | |
1582 | apic_set_reg(apic, APIC_TMR + 0x10 * i, 0); | |
1583 | } | |
c7c9c56c YZ |
1584 | apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm); |
1585 | apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm); | |
8680b94b | 1586 | apic->highest_isr_cache = -1; |
b33ac88b | 1587 | update_divide_count(apic); |
d3c7b77d | 1588 | atomic_set(&apic->lapic_timer.pending, 0); |
c5af89b6 | 1589 | if (kvm_vcpu_is_bsp(vcpu)) |
5dbc8f3f GN |
1590 | kvm_lapic_set_base(vcpu, |
1591 | vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP); | |
ae7a2a3f | 1592 | vcpu->arch.pv_eoi.msr_val = 0; |
97222cc8 ED |
1593 | apic_update_ppr(apic); |
1594 | ||
e1035715 | 1595 | vcpu->arch.apic_arb_prio = 0; |
41383771 | 1596 | vcpu->arch.apic_attention = 0; |
e1035715 | 1597 | |
98eff52a | 1598 | apic_debug("%s: vcpu=%p, id=%d, base_msr=" |
b8688d51 | 1599 | "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__, |
97222cc8 | 1600 | vcpu, kvm_apic_id(apic), |
ad312c7c | 1601 | vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
1602 | } |
1603 | ||
97222cc8 ED |
1604 | /* |
1605 | *---------------------------------------------------------------------- | |
1606 | * timer interface | |
1607 | *---------------------------------------------------------------------- | |
1608 | */ | |
1b9778da | 1609 | |
2a6eac96 | 1610 | static bool lapic_is_periodic(struct kvm_lapic *apic) |
97222cc8 | 1611 | { |
d3c7b77d | 1612 | return apic_lvtt_period(apic); |
97222cc8 ED |
1613 | } |
1614 | ||
3d80840d MT |
1615 | int apic_has_pending_timer(struct kvm_vcpu *vcpu) |
1616 | { | |
54e9818f | 1617 | struct kvm_lapic *apic = vcpu->arch.apic; |
3d80840d | 1618 | |
c48f1496 | 1619 | if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) && |
54e9818f GN |
1620 | apic_lvt_enabled(apic, APIC_LVTT)) |
1621 | return atomic_read(&apic->lapic_timer.pending); | |
3d80840d MT |
1622 | |
1623 | return 0; | |
1624 | } | |
1625 | ||
89342082 | 1626 | int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) |
1b9778da | 1627 | { |
c48f1496 | 1628 | u32 reg = kvm_apic_get_reg(apic, lvt_type); |
23930f95 | 1629 | int vector, mode, trig_mode; |
23930f95 | 1630 | |
c48f1496 | 1631 | if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { |
23930f95 JK |
1632 | vector = reg & APIC_VECTOR_MASK; |
1633 | mode = reg & APIC_MODE_MASK; | |
1634 | trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; | |
b4f2225c YZ |
1635 | return __apic_accept_irq(apic, mode, vector, 1, trig_mode, |
1636 | NULL); | |
23930f95 JK |
1637 | } |
1638 | return 0; | |
1639 | } | |
1b9778da | 1640 | |
8fdb2351 | 1641 | void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu) |
23930f95 | 1642 | { |
8fdb2351 JK |
1643 | struct kvm_lapic *apic = vcpu->arch.apic; |
1644 | ||
1645 | if (apic) | |
1646 | kvm_apic_local_deliver(apic, APIC_LVT0); | |
1b9778da ED |
1647 | } |
1648 | ||
d76685c4 GH |
1649 | static const struct kvm_io_device_ops apic_mmio_ops = { |
1650 | .read = apic_mmio_read, | |
1651 | .write = apic_mmio_write, | |
d76685c4 GH |
1652 | }; |
1653 | ||
e9d90d47 AK |
1654 | static enum hrtimer_restart apic_timer_fn(struct hrtimer *data) |
1655 | { | |
1656 | struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer); | |
2a6eac96 | 1657 | struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer); |
e9d90d47 | 1658 | |
5d87db71 | 1659 | apic_timer_expired(apic); |
e9d90d47 | 1660 | |
2a6eac96 | 1661 | if (lapic_is_periodic(apic)) { |
e9d90d47 AK |
1662 | hrtimer_add_expires_ns(&ktimer->timer, ktimer->period); |
1663 | return HRTIMER_RESTART; | |
1664 | } else | |
1665 | return HRTIMER_NORESTART; | |
1666 | } | |
1667 | ||
97222cc8 ED |
1668 | int kvm_create_lapic(struct kvm_vcpu *vcpu) |
1669 | { | |
1670 | struct kvm_lapic *apic; | |
1671 | ||
1672 | ASSERT(vcpu != NULL); | |
1673 | apic_debug("apic_init %d\n", vcpu->vcpu_id); | |
1674 | ||
1675 | apic = kzalloc(sizeof(*apic), GFP_KERNEL); | |
1676 | if (!apic) | |
1677 | goto nomem; | |
1678 | ||
ad312c7c | 1679 | vcpu->arch.apic = apic; |
97222cc8 | 1680 | |
afc20184 TY |
1681 | apic->regs = (void *)get_zeroed_page(GFP_KERNEL); |
1682 | if (!apic->regs) { | |
97222cc8 ED |
1683 | printk(KERN_ERR "malloc apic regs error for vcpu %x\n", |
1684 | vcpu->vcpu_id); | |
d589444e | 1685 | goto nomem_free_apic; |
97222cc8 | 1686 | } |
97222cc8 ED |
1687 | apic->vcpu = vcpu; |
1688 | ||
d3c7b77d MT |
1689 | hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, |
1690 | HRTIMER_MODE_ABS); | |
e9d90d47 | 1691 | apic->lapic_timer.timer.function = apic_timer_fn; |
d3c7b77d | 1692 | |
c5cc421b GN |
1693 | /* |
1694 | * APIC is created enabled. This will prevent kvm_lapic_set_base from | |
1695 | * thinking that APIC satet has changed. | |
1696 | */ | |
1697 | vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; | |
6aed64a8 GN |
1698 | kvm_lapic_set_base(vcpu, |
1699 | APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE); | |
97222cc8 | 1700 | |
f8c1ea10 | 1701 | static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */ |
c5ec1534 | 1702 | kvm_lapic_reset(vcpu); |
d76685c4 | 1703 | kvm_iodevice_init(&apic->dev, &apic_mmio_ops); |
97222cc8 ED |
1704 | |
1705 | return 0; | |
d589444e RR |
1706 | nomem_free_apic: |
1707 | kfree(apic); | |
97222cc8 | 1708 | nomem: |
97222cc8 ED |
1709 | return -ENOMEM; |
1710 | } | |
97222cc8 ED |
1711 | |
1712 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) | |
1713 | { | |
ad312c7c | 1714 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1715 | int highest_irr; |
1716 | ||
c48f1496 | 1717 | if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic)) |
97222cc8 ED |
1718 | return -1; |
1719 | ||
6e5d865c | 1720 | apic_update_ppr(apic); |
97222cc8 ED |
1721 | highest_irr = apic_find_highest_irr(apic); |
1722 | if ((highest_irr == -1) || | |
c48f1496 | 1723 | ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI))) |
97222cc8 ED |
1724 | return -1; |
1725 | return highest_irr; | |
1726 | } | |
1727 | ||
40487c68 QH |
1728 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) |
1729 | { | |
c48f1496 | 1730 | u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0); |
40487c68 QH |
1731 | int r = 0; |
1732 | ||
c48f1496 | 1733 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
e7dca5c0 CL |
1734 | r = 1; |
1735 | if ((lvt0 & APIC_LVT_MASKED) == 0 && | |
1736 | GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) | |
1737 | r = 1; | |
40487c68 QH |
1738 | return r; |
1739 | } | |
1740 | ||
1b9778da ED |
1741 | void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) |
1742 | { | |
ad312c7c | 1743 | struct kvm_lapic *apic = vcpu->arch.apic; |
1b9778da | 1744 | |
c48f1496 | 1745 | if (!kvm_vcpu_has_lapic(vcpu)) |
54e9818f GN |
1746 | return; |
1747 | ||
1748 | if (atomic_read(&apic->lapic_timer.pending) > 0) { | |
f1ed0450 | 1749 | kvm_apic_local_deliver(apic, APIC_LVTT); |
fae0ba21 NA |
1750 | if (apic_lvtt_tscdeadline(apic)) |
1751 | apic->lapic_timer.tscdeadline = 0; | |
f1ed0450 | 1752 | atomic_set(&apic->lapic_timer.pending, 0); |
1b9778da ED |
1753 | } |
1754 | } | |
1755 | ||
97222cc8 ED |
1756 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) |
1757 | { | |
1758 | int vector = kvm_apic_has_interrupt(vcpu); | |
ad312c7c | 1759 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1760 | |
1761 | if (vector == -1) | |
1762 | return -1; | |
1763 | ||
56cc2406 WL |
1764 | /* |
1765 | * We get here even with APIC virtualization enabled, if doing | |
1766 | * nested virtualization and L1 runs with the "acknowledge interrupt | |
1767 | * on exit" mode. Then we cannot inject the interrupt via RVI, | |
1768 | * because the process would deliver it through the IDT. | |
1769 | */ | |
1770 | ||
8680b94b | 1771 | apic_set_isr(vector, apic); |
97222cc8 ED |
1772 | apic_update_ppr(apic); |
1773 | apic_clear_irr(vector, apic); | |
1774 | return vector; | |
1775 | } | |
96ad2cc6 | 1776 | |
64eb0620 GN |
1777 | void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu, |
1778 | struct kvm_lapic_state *s) | |
96ad2cc6 | 1779 | { |
ad312c7c | 1780 | struct kvm_lapic *apic = vcpu->arch.apic; |
96ad2cc6 | 1781 | |
5dbc8f3f | 1782 | kvm_lapic_set_base(vcpu, vcpu->arch.apic_base); |
64eb0620 GN |
1783 | /* set SPIV separately to get count of SW disabled APICs right */ |
1784 | apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); | |
1785 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); | |
1e08ec4a GN |
1786 | /* call kvm_apic_set_id() to put apic into apic_map */ |
1787 | kvm_apic_set_id(apic, kvm_apic_id(apic)); | |
fc61b800 GN |
1788 | kvm_apic_set_version(vcpu); |
1789 | ||
96ad2cc6 | 1790 | apic_update_ppr(apic); |
d3c7b77d | 1791 | hrtimer_cancel(&apic->lapic_timer.timer); |
96ad2cc6 ED |
1792 | update_divide_count(apic); |
1793 | start_apic_timer(apic); | |
6e24a6ef | 1794 | apic->irr_pending = true; |
c7c9c56c YZ |
1795 | apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ? |
1796 | 1 : count_vectors(apic->regs + APIC_ISR); | |
8680b94b | 1797 | apic->highest_isr_cache = -1; |
4114c27d WW |
1798 | if (kvm_x86_ops->hwapic_irr_update) |
1799 | kvm_x86_ops->hwapic_irr_update(vcpu, | |
1800 | apic_find_highest_irr(apic)); | |
b4eef9b3 TC |
1801 | if (unlikely(kvm_x86_ops->hwapic_isr_update)) |
1802 | kvm_x86_ops->hwapic_isr_update(vcpu->kvm, | |
1803 | apic_find_highest_isr(apic)); | |
3842d135 | 1804 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
10606919 | 1805 | kvm_rtc_eoi_tracking_restore_one(vcpu); |
96ad2cc6 | 1806 | } |
a3d7f85f | 1807 | |
2f52d58c | 1808 | void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) |
a3d7f85f | 1809 | { |
a3d7f85f ED |
1810 | struct hrtimer *timer; |
1811 | ||
c48f1496 | 1812 | if (!kvm_vcpu_has_lapic(vcpu)) |
a3d7f85f ED |
1813 | return; |
1814 | ||
54e9818f | 1815 | timer = &vcpu->arch.apic->lapic_timer.timer; |
a3d7f85f | 1816 | if (hrtimer_cancel(timer)) |
beb20d52 | 1817 | hrtimer_start_expires(timer, HRTIMER_MODE_ABS); |
a3d7f85f | 1818 | } |
b93463aa | 1819 | |
ae7a2a3f MT |
1820 | /* |
1821 | * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt | |
1822 | * | |
1823 | * Detect whether guest triggered PV EOI since the | |
1824 | * last entry. If yes, set EOI on guests's behalf. | |
1825 | * Clear PV EOI in guest memory in any case. | |
1826 | */ | |
1827 | static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu, | |
1828 | struct kvm_lapic *apic) | |
1829 | { | |
1830 | bool pending; | |
1831 | int vector; | |
1832 | /* | |
1833 | * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host | |
1834 | * and KVM_PV_EOI_ENABLED in guest memory as follows: | |
1835 | * | |
1836 | * KVM_APIC_PV_EOI_PENDING is unset: | |
1837 | * -> host disabled PV EOI. | |
1838 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set: | |
1839 | * -> host enabled PV EOI, guest did not execute EOI yet. | |
1840 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset: | |
1841 | * -> host enabled PV EOI, guest executed EOI. | |
1842 | */ | |
1843 | BUG_ON(!pv_eoi_enabled(vcpu)); | |
1844 | pending = pv_eoi_get_pending(vcpu); | |
1845 | /* | |
1846 | * Clear pending bit in any case: it will be set again on vmentry. | |
1847 | * While this might not be ideal from performance point of view, | |
1848 | * this makes sure pv eoi is only enabled when we know it's safe. | |
1849 | */ | |
1850 | pv_eoi_clr_pending(vcpu); | |
1851 | if (pending) | |
1852 | return; | |
1853 | vector = apic_set_eoi(apic); | |
1854 | trace_kvm_pv_eoi(apic, vector); | |
1855 | } | |
1856 | ||
b93463aa AK |
1857 | void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) |
1858 | { | |
1859 | u32 data; | |
b93463aa | 1860 | |
ae7a2a3f MT |
1861 | if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention)) |
1862 | apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); | |
1863 | ||
41383771 | 1864 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
1865 | return; |
1866 | ||
fda4e2e8 AH |
1867 | kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, |
1868 | sizeof(u32)); | |
b93463aa AK |
1869 | |
1870 | apic_set_tpr(vcpu->arch.apic, data & 0xff); | |
1871 | } | |
1872 | ||
ae7a2a3f MT |
1873 | /* |
1874 | * apic_sync_pv_eoi_to_guest - called before vmentry | |
1875 | * | |
1876 | * Detect whether it's safe to enable PV EOI and | |
1877 | * if yes do so. | |
1878 | */ | |
1879 | static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu, | |
1880 | struct kvm_lapic *apic) | |
1881 | { | |
1882 | if (!pv_eoi_enabled(vcpu) || | |
1883 | /* IRR set or many bits in ISR: could be nested. */ | |
1884 | apic->irr_pending || | |
1885 | /* Cache not set: could be safe but we don't bother. */ | |
1886 | apic->highest_isr_cache == -1 || | |
1887 | /* Need EOI to update ioapic. */ | |
1888 | kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) { | |
1889 | /* | |
1890 | * PV EOI was disabled by apic_sync_pv_eoi_from_guest | |
1891 | * so we need not do anything here. | |
1892 | */ | |
1893 | return; | |
1894 | } | |
1895 | ||
1896 | pv_eoi_set_pending(apic->vcpu); | |
1897 | } | |
1898 | ||
b93463aa AK |
1899 | void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) |
1900 | { | |
1901 | u32 data, tpr; | |
1902 | int max_irr, max_isr; | |
ae7a2a3f | 1903 | struct kvm_lapic *apic = vcpu->arch.apic; |
b93463aa | 1904 | |
ae7a2a3f MT |
1905 | apic_sync_pv_eoi_to_guest(vcpu, apic); |
1906 | ||
41383771 | 1907 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
1908 | return; |
1909 | ||
c48f1496 | 1910 | tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff; |
b93463aa AK |
1911 | max_irr = apic_find_highest_irr(apic); |
1912 | if (max_irr < 0) | |
1913 | max_irr = 0; | |
1914 | max_isr = apic_find_highest_isr(apic); | |
1915 | if (max_isr < 0) | |
1916 | max_isr = 0; | |
1917 | data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); | |
1918 | ||
fda4e2e8 AH |
1919 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, |
1920 | sizeof(u32)); | |
b93463aa AK |
1921 | } |
1922 | ||
fda4e2e8 | 1923 | int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) |
b93463aa | 1924 | { |
fda4e2e8 AH |
1925 | if (vapic_addr) { |
1926 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, | |
1927 | &vcpu->arch.apic->vapic_cache, | |
1928 | vapic_addr, sizeof(u32))) | |
1929 | return -EINVAL; | |
41383771 | 1930 | __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); |
fda4e2e8 | 1931 | } else { |
41383771 | 1932 | __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); |
fda4e2e8 AH |
1933 | } |
1934 | ||
1935 | vcpu->arch.apic->vapic_addr = vapic_addr; | |
1936 | return 0; | |
b93463aa | 1937 | } |
0105d1a5 GN |
1938 | |
1939 | int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1940 | { | |
1941 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1942 | u32 reg = (msr - APIC_BASE_MSR) << 4; | |
1943 | ||
1944 | if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic)) | |
1945 | return 1; | |
1946 | ||
c69d3d9b NA |
1947 | if (reg == APIC_ICR2) |
1948 | return 1; | |
1949 | ||
0105d1a5 | 1950 | /* if this is ICR write vector before command */ |
decdc283 | 1951 | if (reg == APIC_ICR) |
0105d1a5 GN |
1952 | apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); |
1953 | return apic_reg_write(apic, reg, (u32)data); | |
1954 | } | |
1955 | ||
1956 | int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data) | |
1957 | { | |
1958 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1959 | u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0; | |
1960 | ||
1961 | if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic)) | |
1962 | return 1; | |
1963 | ||
c69d3d9b NA |
1964 | if (reg == APIC_DFR || reg == APIC_ICR2) { |
1965 | apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n", | |
1966 | reg); | |
1967 | return 1; | |
1968 | } | |
1969 | ||
0105d1a5 GN |
1970 | if (apic_reg_read(apic, reg, 4, &low)) |
1971 | return 1; | |
decdc283 | 1972 | if (reg == APIC_ICR) |
0105d1a5 GN |
1973 | apic_reg_read(apic, APIC_ICR2, 4, &high); |
1974 | ||
1975 | *data = (((u64)high) << 32) | low; | |
1976 | ||
1977 | return 0; | |
1978 | } | |
10388a07 GN |
1979 | |
1980 | int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) | |
1981 | { | |
1982 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1983 | ||
c48f1496 | 1984 | if (!kvm_vcpu_has_lapic(vcpu)) |
10388a07 GN |
1985 | return 1; |
1986 | ||
1987 | /* if this is ICR write vector before command */ | |
1988 | if (reg == APIC_ICR) | |
1989 | apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); | |
1990 | return apic_reg_write(apic, reg, (u32)data); | |
1991 | } | |
1992 | ||
1993 | int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data) | |
1994 | { | |
1995 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1996 | u32 low, high = 0; | |
1997 | ||
c48f1496 | 1998 | if (!kvm_vcpu_has_lapic(vcpu)) |
10388a07 GN |
1999 | return 1; |
2000 | ||
2001 | if (apic_reg_read(apic, reg, 4, &low)) | |
2002 | return 1; | |
2003 | if (reg == APIC_ICR) | |
2004 | apic_reg_read(apic, APIC_ICR2, 4, &high); | |
2005 | ||
2006 | *data = (((u64)high) << 32) | low; | |
2007 | ||
2008 | return 0; | |
2009 | } | |
ae7a2a3f MT |
2010 | |
2011 | int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data) | |
2012 | { | |
2013 | u64 addr = data & ~KVM_MSR_ENABLED; | |
2014 | if (!IS_ALIGNED(addr, 4)) | |
2015 | return 1; | |
2016 | ||
2017 | vcpu->arch.pv_eoi.msr_val = data; | |
2018 | if (!pv_eoi_enabled(vcpu)) | |
2019 | return 0; | |
2020 | return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data, | |
8f964525 | 2021 | addr, sizeof(u8)); |
ae7a2a3f | 2022 | } |
c5cc421b | 2023 | |
66450a21 JK |
2024 | void kvm_apic_accept_events(struct kvm_vcpu *vcpu) |
2025 | { | |
2026 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2b4a273b | 2027 | u8 sipi_vector; |
299018f4 | 2028 | unsigned long pe; |
66450a21 | 2029 | |
299018f4 | 2030 | if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events) |
66450a21 JK |
2031 | return; |
2032 | ||
299018f4 GN |
2033 | pe = xchg(&apic->pending_events, 0); |
2034 | ||
2035 | if (test_bit(KVM_APIC_INIT, &pe)) { | |
66450a21 JK |
2036 | kvm_lapic_reset(vcpu); |
2037 | kvm_vcpu_reset(vcpu); | |
2038 | if (kvm_vcpu_is_bsp(apic->vcpu)) | |
2039 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
2040 | else | |
2041 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
2042 | } | |
299018f4 | 2043 | if (test_bit(KVM_APIC_SIPI, &pe) && |
66450a21 JK |
2044 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { |
2045 | /* evaluate pending_events before reading the vector */ | |
2046 | smp_rmb(); | |
2047 | sipi_vector = apic->sipi_vector; | |
98eff52a | 2048 | apic_debug("vcpu %d received sipi with vector # %x\n", |
66450a21 JK |
2049 | vcpu->vcpu_id, sipi_vector); |
2050 | kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector); | |
2051 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
2052 | } | |
2053 | } | |
2054 | ||
c5cc421b GN |
2055 | void kvm_lapic_init(void) |
2056 | { | |
2057 | /* do not patch jump label more than once per second */ | |
2058 | jump_label_rate_limit(&apic_hw_disabled, HZ); | |
f8c1ea10 | 2059 | jump_label_rate_limit(&apic_sw_disabled, HZ); |
c5cc421b | 2060 | } |