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KVM: MMU: remove call to kvm_mmu_pte_write from walk_addr
[deliverable/linux.git] / arch / x86 / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 *
9 * Authors:
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
13 *
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 */
19
edf88417 20#include <linux/kvm_host.h>
97222cc8
ED		 21#include <linux/kvm.h>
22#include <linux/mm.h>
23#include <linux/highmem.h>
24#include <linux/smp.h>
25#include <linux/hrtimer.h>
26#include <linux/io.h>
27#include <linux/module.h>
6f6d6a1a 28#include <linux/math64.h>
97222cc8
ED		 29#include <asm/processor.h>
30#include <asm/msr.h>
31#include <asm/page.h>
32#include <asm/current.h>
33#include <asm/apicdef.h>
34#include <asm/atomic.h>
5fdbf976 35#include "kvm_cache_regs.h"
97222cc8
ED		 36#include "irq.h"
37
b682b814
MT		 38#ifndef CONFIG_X86_64
39#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
40#else
41#define mod_64(x, y) ((x) % (y))
42#endif
43
97222cc8
ED		 44#define PRId64 "d"
45#define PRIx64 "llx"
46#define PRIu64 "u"
47#define PRIo64 "o"
48
49#define APIC_BUS_CYCLE_NS 1
50
51/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
52#define apic_debug(fmt, arg...)
53
54#define APIC_LVT_NUM 6
55/* 14 is the version for Xeon and Pentium 8.4.8*/
56#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
57#define LAPIC_MMIO_LENGTH (1 << 12)
58/* followed define is not in apicdef.h */
59#define APIC_SHORT_MASK 0xc0000
60#define APIC_DEST_NOSHORT 0x0
61#define APIC_DEST_MASK 0x800
62#define MAX_APIC_VECTOR 256
63
64#define VEC_POS(v) ((v) & (32 - 1))
65#define REG_POS(v) (((v) >> 5) << 4)
ad312c7c 66
97222cc8
ED		 67static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
68{
69 return *((u32 *) (apic->regs + reg_off));
70}
71
72static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
73{
74 *((u32 *) (apic->regs + reg_off)) = val;
75}
76
77static inline int apic_test_and_set_vector(int vec, void *bitmap)
78{
79 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
80}
81
82static inline int apic_test_and_clear_vector(int vec, void *bitmap)
83{
84 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
85}
86
87static inline void apic_set_vector(int vec, void *bitmap)
88{
89 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
90}
91
92static inline void apic_clear_vector(int vec, void *bitmap)
93{
94 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
95}
96
97static inline int apic_hw_enabled(struct kvm_lapic *apic)
98{
ad312c7c 99 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
97222cc8
ED		 100}
101
102static inline int apic_sw_enabled(struct kvm_lapic *apic)
103{
104 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
105}
106
107static inline int apic_enabled(struct kvm_lapic *apic)
108{
109 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
110}
111
112#define LVT_MASK \
113 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
114
115#define LINT_MASK \
116 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
117 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
118
119static inline int kvm_apic_id(struct kvm_lapic *apic)
120{
121 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
122}
123
124static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
125{
126 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
127}
128
129static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
130{
131 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
132}
133
134static inline int apic_lvtt_period(struct kvm_lapic *apic)
135{
136 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
137}
138
cc6e462c
JK		 139static inline int apic_lvt_nmi_mode(u32 lvt_val)
140{
141 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
142}
143
97222cc8
ED		 144static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
145 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
146 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
147 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
148 LINT_MASK, LINT_MASK, /* LVT0-1 */
149 LVT_MASK /* LVTERR */
150};
151
152static int find_highest_vector(void *bitmap)
153{
154 u32 *word = bitmap;
155 int word_offset = MAX_APIC_VECTOR >> 5;
156
157 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
158 continue;
159
160 if (likely(!word_offset && !word[0]))
161 return -1;
162 else
163 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
164}
165
166static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
167{
168 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
169}
170
171static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
172{
173 apic_clear_vector(vec, apic->regs + APIC_IRR);
174}
175
176static inline int apic_find_highest_irr(struct kvm_lapic *apic)
177{
178 int result;
179
180 result = find_highest_vector(apic->regs + APIC_IRR);
181 ASSERT(result == -1 || result >= 16);
182
183 return result;
184}
185
6e5d865c
YS		 186int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
187{
ad312c7c 188 struct kvm_lapic *apic = vcpu->arch.apic;
6e5d865c
YS		 189 int highest_irr;
190
191 if (!apic)
192 return 0;
193 highest_irr = apic_find_highest_irr(apic);
194
195 return highest_irr;
196}
197EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
198
8be5453f 199int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 trig)
97222cc8 200{
ad312c7c 201 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 202
97222cc8
ED		 203 if (!apic_test_and_set_irr(vec, apic)) {
204 /* a new pending irq is set in IRR */
205 if (trig)
206 apic_set_vector(vec, apic->regs + APIC_TMR);
207 else
208 apic_clear_vector(vec, apic->regs + APIC_TMR);
209 kvm_vcpu_kick(apic->vcpu);
210 return 1;
211 }
212 return 0;
213}
214
215static inline int apic_find_highest_isr(struct kvm_lapic *apic)
216{
217 int result;
218
219 result = find_highest_vector(apic->regs + APIC_ISR);
220 ASSERT(result == -1 || result >= 16);
221
222 return result;
223}
224
225static void apic_update_ppr(struct kvm_lapic *apic)
226{
227 u32 tpr, isrv, ppr;
228 int isr;
229
230 tpr = apic_get_reg(apic, APIC_TASKPRI);
231 isr = apic_find_highest_isr(apic);
232 isrv = (isr != -1) ? isr : 0;
233
234 if ((tpr & 0xf0) >= (isrv & 0xf0))
235 ppr = tpr & 0xff;
236 else
237 ppr = isrv & 0xf0;
238
239 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
240 apic, ppr, isr, isrv);
241
242 apic_set_reg(apic, APIC_PROCPRI, ppr);
243}
244
245static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
246{
247 apic_set_reg(apic, APIC_TASKPRI, tpr);
248 apic_update_ppr(apic);
249}
250
251int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
252{
253 return kvm_apic_id(apic) == dest;
254}
255
256int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
257{
258 int result = 0;
259 u8 logical_id;
260
261 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
262
263 switch (apic_get_reg(apic, APIC_DFR)) {
264 case APIC_DFR_FLAT:
265 if (logical_id & mda)
266 result = 1;
267 break;
268 case APIC_DFR_CLUSTER:
269 if (((logical_id >> 4) == (mda >> 0x4))
270 && (logical_id & mda & 0xf))
271 result = 1;
272 break;
273 default:
274 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
275 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
276 break;
277 }
278
279 return result;
280}
281
282static int apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
283 int short_hand, int dest, int dest_mode)
284{
285 int result = 0;
ad312c7c 286 struct kvm_lapic *target = vcpu->arch.apic;
97222cc8
ED		 287
288 apic_debug("target %p, source %p, dest 0x%x, "
289 "dest_mode 0x%x, short_hand 0x%x",
290 target, source, dest, dest_mode, short_hand);
291
292 ASSERT(!target);
293 switch (short_hand) {
294 case APIC_DEST_NOSHORT:
295 if (dest_mode == 0) {
296 /* Physical mode. */
297 if ((dest == 0xFF) || (dest == kvm_apic_id(target)))
298 result = 1;
299 } else
300 /* Logical mode. */
301 result = kvm_apic_match_logical_addr(target, dest);
302 break;
303 case APIC_DEST_SELF:
304 if (target == source)
305 result = 1;
306 break;
307 case APIC_DEST_ALLINC:
308 result = 1;
309 break;
310 case APIC_DEST_ALLBUT:
311 if (target != source)
312 result = 1;
313 break;
314 default:
315 printk(KERN_WARNING "Bad dest shorthand value %x\n",
316 short_hand);
317 break;
318 }
319
320 return result;
321}
322
323/*
324 * Add a pending IRQ into lapic.
325 * Return 1 if successfully added and 0 if discarded.
326 */
327static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
328 int vector, int level, int trig_mode)
329{
c5ec1534
HQ		 330 int orig_irr, result = 0;
331 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8
ED		 332
333 switch (delivery_mode) {
334 case APIC_DM_FIXED:
335 case APIC_DM_LOWEST:
336 /* FIXME add logic for vcpu on reset */
337 if (unlikely(!apic_enabled(apic)))
338 break;
339
1b9778da
ED		 340 orig_irr = apic_test_and_set_irr(vector, apic);
341 if (orig_irr && trig_mode) {
97222cc8
ED		 342 apic_debug("level trig mode repeatedly for vector %d",
343 vector);
344 break;
345 }
346
347 if (trig_mode) {
348 apic_debug("level trig mode for vector %d", vector);
349 apic_set_vector(vector, apic->regs + APIC_TMR);
350 } else
351 apic_clear_vector(vector, apic->regs + APIC_TMR);
352
d7690175 353 kvm_vcpu_kick(vcpu);
97222cc8 354
1b9778da 355 result = (orig_irr == 0);
97222cc8
ED		 356 break;
357
358 case APIC_DM_REMRD:
359 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
360 break;
361
362 case APIC_DM_SMI:
363 printk(KERN_DEBUG "Ignoring guest SMI\n");
364 break;
3419ffc8 365
97222cc8 366 case APIC_DM_NMI:
3419ffc8 367 kvm_inject_nmi(vcpu);
26df99c6 368 kvm_vcpu_kick(vcpu);
97222cc8
ED		 369 break;
370
371 case APIC_DM_INIT:
c5ec1534 372 if (level) {
a4535290 373 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
c5ec1534
HQ		 374 printk(KERN_DEBUG
375 "INIT on a runnable vcpu %d\n",
376 vcpu->vcpu_id);
a4535290 377 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
c5ec1534
HQ		 378 kvm_vcpu_kick(vcpu);
379 } else {
1b10bf31
JK		 380 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
381 vcpu->vcpu_id);
c5ec1534 382 }
97222cc8
ED		 383 break;
384
385 case APIC_DM_STARTUP:
1b10bf31
JK		 386 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
387 vcpu->vcpu_id, vector);
a4535290 388 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
ad312c7c 389 vcpu->arch.sipi_vector = vector;
a4535290 390 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
d7690175 391 kvm_vcpu_kick(vcpu);
c5ec1534 392 }
97222cc8
ED		 393 break;
394
23930f95
JK		 395 case APIC_DM_EXTINT:
396 /*
397 * Should only be called by kvm_apic_local_deliver() with LVT0,
398 * before NMI watchdog was enabled. Already handled by
399 * kvm_apic_accept_pic_intr().
400 */
401 break;
402
97222cc8
ED		 403 default:
404 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
405 delivery_mode);
406 break;
407 }
408 return result;
409}
410
8be5453f 411static struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector,
110c2fae 412 unsigned long *bitmap)
97222cc8 413{
932f72ad
HQ		 414 int last;
415 int next;
e4d47f40 416 struct kvm_lapic *apic = NULL;
932f72ad 417
bfc6d222 418 last = kvm->arch.round_robin_prev_vcpu;
932f72ad
HQ		 419 next = last;
420
421 do {
422 if (++next == KVM_MAX_VCPUS)
423 next = 0;
110c2fae 424 if (kvm->vcpus[next] == NULL || !test_bit(next, bitmap))
932f72ad 425 continue;
ad312c7c 426 apic = kvm->vcpus[next]->arch.apic;
932f72ad
HQ		 427 if (apic && apic_enabled(apic))
428 break;
429 apic = NULL;
430 } while (next != last);
bfc6d222 431 kvm->arch.round_robin_prev_vcpu = next;
932f72ad 432
e4d47f40
QH		 433 if (!apic)
434 printk(KERN_DEBUG "vcpu not ready for apic_round_robin\n");
97222cc8 435
932f72ad 436 return apic;
97222cc8
ED		 437}
438
8be5453f 439struct kvm_vcpu *kvm_get_lowest_prio_vcpu(struct kvm *kvm, u8 vector,
110c2fae 440 unsigned long *bitmap)
8be5453f
ZX		 441{
442 struct kvm_lapic *apic;
443
444 apic = kvm_apic_round_robin(kvm, vector, bitmap);
445 if (apic)
446 return apic->vcpu;
447 return NULL;
448}
449
97222cc8
ED		 450static void apic_set_eoi(struct kvm_lapic *apic)
451{
452 int vector = apic_find_highest_isr(apic);
f5244726 453 int trigger_mode;
97222cc8
ED		 454 /*
455 * Not every write EOI will has corresponding ISR,
456 * one example is when Kernel check timer on setup_IO_APIC
457 */
458 if (vector == -1)
459 return;
460
461 apic_clear_vector(vector, apic->regs + APIC_ISR);
462 apic_update_ppr(apic);
463
464 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
f5244726
MT		 465 trigger_mode = IOAPIC_LEVEL_TRIG;
466 else
467 trigger_mode = IOAPIC_EDGE_TRIG;
468 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
97222cc8
ED		 469}
470
471static void apic_send_ipi(struct kvm_lapic *apic)
472{
473 u32 icr_low = apic_get_reg(apic, APIC_ICR);
474 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
475
476 unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
477 unsigned int short_hand = icr_low & APIC_SHORT_MASK;
478 unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
479 unsigned int level = icr_low & APIC_INT_ASSERT;
480 unsigned int dest_mode = icr_low & APIC_DEST_MASK;
481 unsigned int delivery_mode = icr_low & APIC_MODE_MASK;
482 unsigned int vector = icr_low & APIC_VECTOR_MASK;
483
8be5453f 484 struct kvm_vcpu *target;
97222cc8 485 struct kvm_vcpu *vcpu;
bfd349d0 486 DECLARE_BITMAP(lpr_map, KVM_MAX_VCPUS);
97222cc8
ED		 487 int i;
488
bfd349d0 489 bitmap_zero(lpr_map, KVM_MAX_VCPUS);
97222cc8
ED		 490 apic_debug("icr_high 0x%x, icr_low 0x%x, "
491 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
492 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
493 icr_high, icr_low, short_hand, dest,
494 trig_mode, level, dest_mode, delivery_mode, vector);
495
496 for (i = 0; i < KVM_MAX_VCPUS; i++) {
497 vcpu = apic->vcpu->kvm->vcpus[i];
498 if (!vcpu)
499 continue;
500
ad312c7c 501 if (vcpu->arch.apic &&
97222cc8
ED		 502 apic_match_dest(vcpu, apic, short_hand, dest, dest_mode)) {
503 if (delivery_mode == APIC_DM_LOWEST)
bfd349d0 504 __set_bit(vcpu->vcpu_id, lpr_map);
97222cc8 505 else
ad312c7c 506 __apic_accept_irq(vcpu->arch.apic, delivery_mode,
97222cc8
ED		 507 vector, level, trig_mode);
508 }
509 }
510
511 if (delivery_mode == APIC_DM_LOWEST) {
bfd349d0 512 target = kvm_get_lowest_prio_vcpu(vcpu->kvm, vector, lpr_map);
97222cc8 513 if (target != NULL)
ad312c7c 514 __apic_accept_irq(target->arch.apic, delivery_mode,
97222cc8
ED		 515 vector, level, trig_mode);
516 }
517}
518
519static u32 apic_get_tmcct(struct kvm_lapic *apic)
520{
b682b814
MT		 521 ktime_t remaining;
522 s64 ns;
9da8f4e8 523 u32 tmcct;
97222cc8
ED		 524
525 ASSERT(apic != NULL);
526
9da8f4e8 527 /* if initial count is 0, current count should also be 0 */
b682b814 528 if (apic_get_reg(apic, APIC_TMICT) == 0)
9da8f4e8
KP		 529 return 0;
530
d3c7b77d 531 remaining = hrtimer_expires_remaining(&apic->lapic_timer.timer);
b682b814
MT		 532 if (ktime_to_ns(remaining) < 0)
533 remaining = ktime_set(0, 0);
534
d3c7b77d
MT		 535 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
536 tmcct = div64_u64(ns,
537 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 538
539 return tmcct;
540}
541
b209749f
AK		 542static void __report_tpr_access(struct kvm_lapic *apic, bool write)
543{
544 struct kvm_vcpu *vcpu = apic->vcpu;
545 struct kvm_run *run = vcpu->run;
546
547 set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
5fdbf976 548 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 549 run->tpr_access.is_write = write;
550}
551
552static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
553{
554 if (apic->vcpu->arch.tpr_access_reporting)
555 __report_tpr_access(apic, write);
556}
557
97222cc8
ED		 558static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
559{
560 u32 val = 0;
561
c7bf23ba
JR		 562 KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
563
97222cc8
ED		 564 if (offset >= LAPIC_MMIO_LENGTH)
565 return 0;
566
567 switch (offset) {
568 case APIC_ARBPRI:
569 printk(KERN_WARNING "Access APIC ARBPRI register "
570 "which is for P6\n");
571 break;
572
573 case APIC_TMCCT: /* Timer CCR */
574 val = apic_get_tmcct(apic);
575 break;
576
b209749f
AK		 577 case APIC_TASKPRI:
578 report_tpr_access(apic, false);
579 /* fall thru */
97222cc8 580 default:
6e5d865c 581 apic_update_ppr(apic);
97222cc8
ED		 582 val = apic_get_reg(apic, offset);
583 break;
584 }
585
586 return val;
587}
588
589static void apic_mmio_read(struct kvm_io_device *this,
590 gpa_t address, int len, void *data)
591{
592 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
593 unsigned int offset = address - apic->base_address;
594 unsigned char alignment = offset & 0xf;
595 u32 result;
596
597 if ((alignment + len) > 4) {
598 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
599 (unsigned long)address, len);
600 return;
601 }
602 result = __apic_read(apic, offset & ~0xf);
603
604 switch (len) {
605 case 1:
606 case 2:
607 case 4:
608 memcpy(data, (char *)&result + alignment, len);
609 break;
610 default:
611 printk(KERN_ERR "Local APIC read with len = %x, "
612 "should be 1,2, or 4 instead\n", len);
613 break;
614 }
615}
616
617static void update_divide_count(struct kvm_lapic *apic)
618{
619 u32 tmp1, tmp2, tdcr;
620
621 tdcr = apic_get_reg(apic, APIC_TDCR);
622 tmp1 = tdcr & 0xf;
623 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 624 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 625
626 apic_debug("timer divide count is 0x%x\n",
d3c7b77d 627 apic->lapic_timer.divide_count);
97222cc8
ED		 628}
629
630static void start_apic_timer(struct kvm_lapic *apic)
631{
d3c7b77d 632 ktime_t now = apic->lapic_timer.timer.base->get_time();
97222cc8 633
d3c7b77d
MT		 634 apic->lapic_timer.period = apic_get_reg(apic, APIC_TMICT) *
635 APIC_BUS_CYCLE_NS * apic->divide_count;
636 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 637
d3c7b77d 638 if (!apic->lapic_timer.period)
0b975a3c
AK		 639 return;
640
d3c7b77d
MT		 641 hrtimer_start(&apic->lapic_timer.timer,
642 ktime_add_ns(now, apic->lapic_timer.period),
97222cc8
ED		 643 HRTIMER_MODE_ABS);
644
645 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
646 PRIx64 ", "
647 "timer initial count 0x%x, period %lldns, "
b8688d51 648 "expire @ 0x%016" PRIx64 ".\n", __func__,
97222cc8
ED		 649 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
650 apic_get_reg(apic, APIC_TMICT),
d3c7b77d 651 apic->lapic_timer.period,
97222cc8 652 ktime_to_ns(ktime_add_ns(now,
d3c7b77d 653 apic->lapic_timer.period)));
97222cc8
ED		 654}
655
cc6e462c
JK		 656static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
657{
658 int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
659
660 if (apic_lvt_nmi_mode(lvt0_val)) {
661 if (!nmi_wd_enabled) {
662 apic_debug("Receive NMI setting on APIC_LVT0 "
663 "for cpu %d\n", apic->vcpu->vcpu_id);
664 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
665 }
666 } else if (nmi_wd_enabled)
667 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
668}
669
97222cc8
ED		 670static void apic_mmio_write(struct kvm_io_device *this,
671 gpa_t address, int len, const void *data)
672{
673 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
674 unsigned int offset = address - apic->base_address;
675 unsigned char alignment = offset & 0xf;
676 u32 val;
677
678 /*
679 * APIC register must be aligned on 128-bits boundary.
680 * 32/64/128 bits registers must be accessed thru 32 bits.
681 * Refer SDM 8.4.1
682 */
683 if (len != 4 || alignment) {
1b10bf31
JK		 684 /* Don't shout loud, $infamous_os would cause only noise. */
685 apic_debug("apic write: bad size=%d %lx\n",
686 len, (long)address);
97222cc8
ED		 687 return;
688 }
689
690 val = *(u32 *) data;
691
692 /* too common printing */
693 if (offset != APIC_EOI)
694 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
b8688d51 695 "0x%x\n", __func__, offset, len, val);
97222cc8
ED		 696
697 offset &= 0xff0;
698
c7bf23ba
JR		 699 KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
700
97222cc8
ED		 701 switch (offset) {
702 case APIC_ID: /* Local APIC ID */
703 apic_set_reg(apic, APIC_ID, val);
704 break;
705
706 case APIC_TASKPRI:
b209749f 707 report_tpr_access(apic, true);
97222cc8
ED		 708 apic_set_tpr(apic, val & 0xff);
709 break;
710
711 case APIC_EOI:
712 apic_set_eoi(apic);
713 break;
714
715 case APIC_LDR:
716 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
717 break;
718
719 case APIC_DFR:
720 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
721 break;
722
723 case APIC_SPIV:
724 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
725 if (!(val & APIC_SPIV_APIC_ENABLED)) {
726 int i;
727 u32 lvt_val;
728
729 for (i = 0; i < APIC_LVT_NUM; i++) {
730 lvt_val = apic_get_reg(apic,
731 APIC_LVTT + 0x10 * i);
732 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
733 lvt_val | APIC_LVT_MASKED);
734 }
d3c7b77d 735 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 736
737 }
738 break;
739
740 case APIC_ICR:
741 /* No delay here, so we always clear the pending bit */
742 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
743 apic_send_ipi(apic);
744 break;
745
746 case APIC_ICR2:
747 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
748 break;
749
23930f95 750 case APIC_LVT0:
cc6e462c 751 apic_manage_nmi_watchdog(apic, val);
97222cc8
ED		 752 case APIC_LVTT:
753 case APIC_LVTTHMR:
754 case APIC_LVTPC:
97222cc8
ED		 755 case APIC_LVT1:
756 case APIC_LVTERR:
757 /* TODO: Check vector */
758 if (!apic_sw_enabled(apic))
759 val |= APIC_LVT_MASKED;
760
761 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
762 apic_set_reg(apic, offset, val);
763
764 break;
765
766 case APIC_TMICT:
d3c7b77d 767 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 768 apic_set_reg(apic, APIC_TMICT, val);
769 start_apic_timer(apic);
770 return;
771
772 case APIC_TDCR:
773 if (val & 4)
774 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
775 apic_set_reg(apic, APIC_TDCR, val);
776 update_divide_count(apic);
777 break;
778
779 default:
780 apic_debug("Local APIC Write to read-only register %x\n",
781 offset);
782 break;
783 }
784
785}
786
92760499
LV		 787static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr,
788 int len, int size)
97222cc8
ED		 789{
790 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
791 int ret = 0;
792
793
794 if (apic_hw_enabled(apic) &&
795 (addr >= apic->base_address) &&
796 (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
797 ret = 1;
798
799 return ret;
800}
801
d589444e 802void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 803{
ad312c7c 804 if (!vcpu->arch.apic)
97222cc8
ED		 805 return;
806
d3c7b77d 807 hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
97222cc8 808
ad312c7c
ZX		 809 if (vcpu->arch.apic->regs_page)
810 __free_page(vcpu->arch.apic->regs_page);
97222cc8 811
ad312c7c 812 kfree(vcpu->arch.apic);
97222cc8
ED		 813}
814
815/*
816 *----------------------------------------------------------------------
817 * LAPIC interface
818 *----------------------------------------------------------------------
819 */
820
821void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
822{
ad312c7c 823 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 824
825 if (!apic)
826 return;
b93463aa
AK		 827 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
828 | (apic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8 829}
ec7cf690 830EXPORT_SYMBOL_GPL(kvm_lapic_set_tpr);
97222cc8
ED		 831
832u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
833{
ad312c7c 834 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 835 u64 tpr;
836
837 if (!apic)
838 return 0;
839 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
840
841 return (tpr & 0xf0) >> 4;
842}
6e5d865c 843EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
97222cc8
ED		 844
845void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
846{
ad312c7c 847 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 848
849 if (!apic) {
850 value |= MSR_IA32_APICBASE_BSP;
ad312c7c 851 vcpu->arch.apic_base = value;
97222cc8
ED		 852 return;
853 }
854 if (apic->vcpu->vcpu_id)
855 value &= ~MSR_IA32_APICBASE_BSP;
856
ad312c7c
ZX		 857 vcpu->arch.apic_base = value;
858 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 859 MSR_IA32_APICBASE_BASE;
860
861 /* with FSB delivery interrupt, we can restart APIC functionality */
862 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
ad312c7c 863 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 864
865}
866
867u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
868{
ad312c7c 869 return vcpu->arch.apic_base;
97222cc8
ED		 870}
871EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
872
c5ec1534 873void kvm_lapic_reset(struct kvm_vcpu *vcpu)
97222cc8
ED		 874{
875 struct kvm_lapic *apic;
876 int i;
877
b8688d51 878 apic_debug("%s\n", __func__);
97222cc8
ED		 879
880 ASSERT(vcpu);
ad312c7c 881 apic = vcpu->arch.apic;
97222cc8
ED		 882 ASSERT(apic != NULL);
883
884 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 885 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 886
887 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
888 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
889
890 for (i = 0; i < APIC_LVT_NUM; i++)
891 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
40487c68
QH		 892 apic_set_reg(apic, APIC_LVT0,
893 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
97222cc8
ED		 894
895 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
896 apic_set_reg(apic, APIC_SPIV, 0xff);
897 apic_set_reg(apic, APIC_TASKPRI, 0);
898 apic_set_reg(apic, APIC_LDR, 0);
899 apic_set_reg(apic, APIC_ESR, 0);
900 apic_set_reg(apic, APIC_ICR, 0);
901 apic_set_reg(apic, APIC_ICR2, 0);
902 apic_set_reg(apic, APIC_TDCR, 0);
903 apic_set_reg(apic, APIC_TMICT, 0);
904 for (i = 0; i < 8; i++) {
905 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
906 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
907 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
908 }
b33ac88b 909 update_divide_count(apic);
d3c7b77d 910 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8 911 if (vcpu->vcpu_id == 0)
ad312c7c 912 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
97222cc8
ED		 913 apic_update_ppr(apic);
914
915 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
b8688d51 916 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
97222cc8 917 vcpu, kvm_apic_id(apic),
ad312c7c 918 vcpu->arch.apic_base, apic->base_address);
97222cc8 919}
c5ec1534 920EXPORT_SYMBOL_GPL(kvm_lapic_reset);
97222cc8
ED		 921
922int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
923{
ad312c7c 924 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 925 int ret = 0;
926
927 if (!apic)
928 return 0;
929 ret = apic_enabled(apic);
930
931 return ret;
932}
6e5d865c 933EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
97222cc8
ED		 934
935/*
936 *----------------------------------------------------------------------
937 * timer interface
938 *----------------------------------------------------------------------
939 */
1b9778da 940
d3c7b77d 941static bool lapic_is_periodic(struct kvm_timer *ktimer)
97222cc8 942{
d3c7b77d
MT		 943 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
944 lapic_timer);
945 return apic_lvtt_period(apic);
97222cc8
ED		 946}
947
3d80840d
MT		 948int apic_has_pending_timer(struct kvm_vcpu *vcpu)
949{
950 struct kvm_lapic *lapic = vcpu->arch.apic;
951
54aaacee 952 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
d3c7b77d 953 return atomic_read(&lapic->lapic_timer.pending);
3d80840d
MT		 954
955 return 0;
956}
957
8fdb2351 958static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 959{
8fdb2351 960 u32 reg = apic_get_reg(apic, lvt_type);
23930f95 961 int vector, mode, trig_mode;
23930f95 962
8fdb2351 963 if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 964 vector = reg & APIC_VECTOR_MASK;
965 mode = reg & APIC_MODE_MASK;
966 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
967 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
968 }
969 return 0;
970}
1b9778da 971
8fdb2351 972void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 973{
8fdb2351
JK		 974 struct kvm_lapic *apic = vcpu->arch.apic;
975
976 if (apic)
977 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 978}
979
d3c7b77d
MT		 980struct kvm_timer_ops lapic_timer_ops = {
981 .is_periodic = lapic_is_periodic,
982};
97222cc8
ED		 983
984int kvm_create_lapic(struct kvm_vcpu *vcpu)
985{
986 struct kvm_lapic *apic;
987
988 ASSERT(vcpu != NULL);
989 apic_debug("apic_init %d\n", vcpu->vcpu_id);
990
991 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
992 if (!apic)
993 goto nomem;
994
ad312c7c 995 vcpu->arch.apic = apic;
97222cc8
ED		 996
997 apic->regs_page = alloc_page(GFP_KERNEL);
998 if (apic->regs_page == NULL) {
999 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1000 vcpu->vcpu_id);
d589444e 1001 goto nomem_free_apic;
97222cc8
ED		 1002 }
1003 apic->regs = page_address(apic->regs_page);
1004 memset(apic->regs, 0, PAGE_SIZE);
1005 apic->vcpu = vcpu;
1006
d3c7b77d
MT		 1007 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1008 HRTIMER_MODE_ABS);
1009 apic->lapic_timer.timer.function = kvm_timer_fn;
1010 apic->lapic_timer.t_ops = &lapic_timer_ops;
1011 apic->lapic_timer.kvm = vcpu->kvm;
1012 apic->lapic_timer.vcpu_id = vcpu->vcpu_id;
1013
97222cc8 1014 apic->base_address = APIC_DEFAULT_PHYS_BASE;
ad312c7c 1015 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
97222cc8 1016
c5ec1534 1017 kvm_lapic_reset(vcpu);
97222cc8
ED		 1018 apic->dev.read = apic_mmio_read;
1019 apic->dev.write = apic_mmio_write;
1020 apic->dev.in_range = apic_mmio_range;
1021 apic->dev.private = apic;
1022
1023 return 0;
d589444e
RR		 1024nomem_free_apic:
1025 kfree(apic);
97222cc8 1026nomem:
97222cc8
ED		 1027 return -ENOMEM;
1028}
1029EXPORT_SYMBOL_GPL(kvm_create_lapic);
1030
1031int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1032{
ad312c7c 1033 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1034 int highest_irr;
1035
1036 if (!apic || !apic_enabled(apic))
1037 return -1;
1038
6e5d865c 1039 apic_update_ppr(apic);
97222cc8
ED		 1040 highest_irr = apic_find_highest_irr(apic);
1041 if ((highest_irr == -1) ||
1042 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1043 return -1;
1044 return highest_irr;
1045}
1046
40487c68
QH		 1047int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1048{
ad312c7c 1049 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 1050 int r = 0;
1051
1052 if (vcpu->vcpu_id == 0) {
ad312c7c 1053 if (!apic_hw_enabled(vcpu->arch.apic))
40487c68
QH		 1054 r = 1;
1055 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1056 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1057 r = 1;
1058 }
1059 return r;
1060}
1061
1b9778da
ED		 1062void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1063{
ad312c7c 1064 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 1065
d3c7b77d 1066 if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
8fdb2351 1067 if (kvm_apic_local_deliver(apic, APIC_LVTT))
d3c7b77d 1068 atomic_dec(&apic->lapic_timer.pending);
1b9778da
ED		 1069 }
1070}
1071
97222cc8
ED		 1072int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1073{
1074 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 1075 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1076
1077 if (vector == -1)
1078 return -1;
1079
1080 apic_set_vector(vector, apic->regs + APIC_ISR);
1081 apic_update_ppr(apic);
1082 apic_clear_irr(vector, apic);
1083 return vector;
1084}
96ad2cc6
ED		 1085
1086void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1087{
ad312c7c 1088 struct kvm_lapic *apic = vcpu->arch.apic;
96ad2cc6 1089
ad312c7c 1090 apic->base_address = vcpu->arch.apic_base &
96ad2cc6
ED		 1091 MSR_IA32_APICBASE_BASE;
1092 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1093 apic_update_ppr(apic);
d3c7b77d 1094 hrtimer_cancel(&apic->lapic_timer.timer);
96ad2cc6
ED		 1095 update_divide_count(apic);
1096 start_apic_timer(apic);
1097}
a3d7f85f 1098
2f52d58c 1099void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 1100{
ad312c7c 1101 struct kvm_lapic *apic = vcpu->arch.apic;
a3d7f85f
ED		 1102 struct hrtimer *timer;
1103
1104 if (!apic)
1105 return;
1106
d3c7b77d 1107 timer = &apic->lapic_timer.timer;
a3d7f85f 1108 if (hrtimer_cancel(timer))
beb20d52 1109 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
a3d7f85f 1110}
b93463aa
AK		 1111
1112void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1113{
1114 u32 data;
1115 void *vapic;
1116
1117 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1118 return;
1119
1120 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1121 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1122 kunmap_atomic(vapic, KM_USER0);
1123
1124 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1125}
1126
1127void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1128{
1129 u32 data, tpr;
1130 int max_irr, max_isr;
1131 struct kvm_lapic *apic;
1132 void *vapic;
1133
1134 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1135 return;
1136
1137 apic = vcpu->arch.apic;
1138 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1139 max_irr = apic_find_highest_irr(apic);
1140 if (max_irr < 0)
1141 max_irr = 0;
1142 max_isr = apic_find_highest_isr(apic);
1143 if (max_isr < 0)
1144 max_isr = 0;
1145 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1146
1147 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1148 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1149 kunmap_atomic(vapic, KM_USER0);
1150}
1151
1152void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1153{
1154 if (!irqchip_in_kernel(vcpu->kvm))
1155 return;
1156
1157 vcpu->arch.apic->vapic_addr = vapic_addr;
1158}
Linux kernel - Deliverables
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