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[PATCH] ppc64: pcibus_to_node fix
[deliverable/linux.git] / arch / x86_64 / kernel / mpparse.c
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1da177e4
LT		 1/*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16#include <linux/mm.h>
17#include <linux/irq.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/config.h>
21#include <linux/bootmem.h>
22#include <linux/smp_lock.h>
23#include <linux/kernel_stat.h>
24#include <linux/mc146818rtc.h>
25#include <linux/acpi.h>
26
27#include <asm/smp.h>
28#include <asm/mtrr.h>
29#include <asm/mpspec.h>
30#include <asm/pgalloc.h>
31#include <asm/io_apic.h>
32#include <asm/proto.h>
8d916406 33#include <asm/acpi.h>
1da177e4
LT		 34
35/* Have we found an MP table */
36int smp_found_config;
37unsigned int __initdata maxcpus = NR_CPUS;
38
39int acpi_found_madt;
40
41/*
42 * Various Linux-internal data structures created from the
43 * MP-table.
44 */
45int apic_version [MAX_APICS];
46unsigned char mp_bus_id_to_type [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
47int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
48cpumask_t pci_bus_to_cpumask [256] = { [0 ... 255] = CPU_MASK_ALL };
49
50static int mp_current_pci_id = 0;
51/* I/O APIC entries */
52struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
53
54/* # of MP IRQ source entries */
55struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
56
57/* MP IRQ source entries */
58int mp_irq_entries;
59
60int nr_ioapics;
61int pic_mode;
62unsigned long mp_lapic_addr = 0;
63
64
65
66/* Processor that is doing the boot up */
67unsigned int boot_cpu_id = -1U;
68/* Internal processor count */
69static unsigned int num_processors = 0;
70
71/* Bitmask of physically existing CPUs */
72physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;
73
74/* ACPI MADT entry parsing functions */
75#ifdef CONFIG_ACPI_BOOT
76extern struct acpi_boot_flags acpi_boot;
77#ifdef CONFIG_X86_LOCAL_APIC
78extern int acpi_parse_lapic (acpi_table_entry_header *header);
79extern int acpi_parse_lapic_addr_ovr (acpi_table_entry_header *header);
80extern int acpi_parse_lapic_nmi (acpi_table_entry_header *header);
81#endif /*CONFIG_X86_LOCAL_APIC*/
82#ifdef CONFIG_X86_IO_APIC
83extern int acpi_parse_ioapic (acpi_table_entry_header *header);
84#endif /*CONFIG_X86_IO_APIC*/
85#endif /*CONFIG_ACPI_BOOT*/
86
87u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
88
89
90/*
91 * Intel MP BIOS table parsing routines:
92 */
93
94/*
95 * Checksum an MP configuration block.
96 */
97
98static int __init mpf_checksum(unsigned char *mp, int len)
99{
100 int sum = 0;
101
102 while (len--)
103 sum += *mp++;
104
105 return sum & 0xFF;
106}
107
108static void __init MP_processor_info (struct mpc_config_processor *m)
109{
110 int ver;
18a2b647 111 static int found_bsp=0;
1da177e4
LT		 112
113 if (!(m->mpc_cpuflag & CPU_ENABLED))
114 return;
115
116 printk(KERN_INFO "Processor #%d %d:%d APIC version %d\n",
117 m->mpc_apicid,
118 (m->mpc_cpufeature & CPU_FAMILY_MASK)>>8,
119 (m->mpc_cpufeature & CPU_MODEL_MASK)>>4,
120 m->mpc_apicver);
121
122 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
123 Dprintk(" Bootup CPU\n");
124 boot_cpu_id = m->mpc_apicid;
125 }
126 if (num_processors >= NR_CPUS) {
127 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
128 " Processor ignored.\n", NR_CPUS);
129 return;
130 }
1da177e4
LT		 131
132 num_processors++;
133
134 if (m->mpc_apicid > MAX_APICS) {
135 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
136 m->mpc_apicid, MAX_APICS);
137 return;
138 }
139 ver = m->mpc_apicver;
140
141 physid_set(m->mpc_apicid, phys_cpu_present_map);
142 /*
143 * Validate version
144 */
145 if (ver == 0x0) {
146 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
147 ver = 0x10;
148 }
149 apic_version[m->mpc_apicid] = ver;
18a2b647
AK		 150 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
151 /*
152 * bios_cpu_apicid is required to have processors listed
153 * in same order as logical cpu numbers. Hence the first
154 * entry is BSP, and so on.
155 */
156 bios_cpu_apicid[0] = m->mpc_apicid;
157 x86_cpu_to_apicid[0] = m->mpc_apicid;
158 found_bsp = 1;
159 } else {
160 bios_cpu_apicid[num_processors - found_bsp] = m->mpc_apicid;
161 x86_cpu_to_apicid[num_processors - found_bsp] = m->mpc_apicid;
162 }
1da177e4
LT		 163}
164
165static void __init MP_bus_info (struct mpc_config_bus *m)
166{
167 char str[7];
168
169 memcpy(str, m->mpc_bustype, 6);
170 str[6] = 0;
171 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
172
173 if (strncmp(str, "ISA", 3) == 0) {
174 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
175 } else if (strncmp(str, "EISA", 4) == 0) {
176 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
177 } else if (strncmp(str, "PCI", 3) == 0) {
178 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
179 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
180 mp_current_pci_id++;
181 } else if (strncmp(str, "MCA", 3) == 0) {
182 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
183 } else {
184 printk(KERN_ERR "Unknown bustype %s\n", str);
185 }
186}
187
188static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
189{
190 if (!(m->mpc_flags & MPC_APIC_USABLE))
191 return;
192
193 printk("I/O APIC #%d Version %d at 0x%X.\n",
194 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
195 if (nr_ioapics >= MAX_IO_APICS) {
196 printk(KERN_ERR "Max # of I/O APICs (%d) exceeded (found %d).\n",
197 MAX_IO_APICS, nr_ioapics);
198 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
199 }
200 if (!m->mpc_apicaddr) {
201 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
202 " found in MP table, skipping!\n");
203 return;
204 }
205 mp_ioapics[nr_ioapics] = *m;
206 nr_ioapics++;
207}
208
209static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
210{
211 mp_irqs [mp_irq_entries] = *m;
212 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
213 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
214 m->mpc_irqtype, m->mpc_irqflag & 3,
215 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
216 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
217 if (++mp_irq_entries == MAX_IRQ_SOURCES)
218 panic("Max # of irq sources exceeded!!\n");
219}
220
221static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
222{
223 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
224 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
225 m->mpc_irqtype, m->mpc_irqflag & 3,
226 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
227 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
228 /*
229 * Well it seems all SMP boards in existence
230 * use ExtINT/LVT1 == LINT0 and
231 * NMI/LVT2 == LINT1 - the following check
232 * will show us if this assumptions is false.
233 * Until then we do not have to add baggage.
234 */
235 if ((m->mpc_irqtype == mp_ExtINT) &&
236 (m->mpc_destapiclint != 0))
237 BUG();
238 if ((m->mpc_irqtype == mp_NMI) &&
239 (m->mpc_destapiclint != 1))
240 BUG();
241}
242
243/*
244 * Read/parse the MPC
245 */
246
247static int __init smp_read_mpc(struct mp_config_table *mpc)
248{
249 char str[16];
250 int count=sizeof(*mpc);
251 unsigned char *mpt=((unsigned char *)mpc)+count;
252
253 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
254 printk("SMP mptable: bad signature [%c%c%c%c]!\n",
255 mpc->mpc_signature[0],
256 mpc->mpc_signature[1],
257 mpc->mpc_signature[2],
258 mpc->mpc_signature[3]);
259 return 0;
260 }
261 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
262 printk("SMP mptable: checksum error!\n");
263 return 0;
264 }
265 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
266 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
267 mpc->mpc_spec);
268 return 0;
269 }
270 if (!mpc->mpc_lapic) {
271 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
272 return 0;
273 }
274 memcpy(str,mpc->mpc_oem,8);
275 str[8]=0;
276 printk(KERN_INFO "OEM ID: %s ",str);
277
278 memcpy(str,mpc->mpc_productid,12);
279 str[12]=0;
280 printk(KERN_INFO "Product ID: %s ",str);
281
282 printk(KERN_INFO "APIC at: 0x%X\n",mpc->mpc_lapic);
283
284 /* save the local APIC address, it might be non-default */
285 if (!acpi_lapic)
286 mp_lapic_addr = mpc->mpc_lapic;
287
288 /*
289 * Now process the configuration blocks.
290 */
291 while (count < mpc->mpc_length) {
292 switch(*mpt) {
293 case MP_PROCESSOR:
294 {
295 struct mpc_config_processor *m=
296 (struct mpc_config_processor *)mpt;
297 if (!acpi_lapic)
298 MP_processor_info(m);
299 mpt += sizeof(*m);
300 count += sizeof(*m);
301 break;
302 }
303 case MP_BUS:
304 {
305 struct mpc_config_bus *m=
306 (struct mpc_config_bus *)mpt;
307 MP_bus_info(m);
308 mpt += sizeof(*m);
309 count += sizeof(*m);
310 break;
311 }
312 case MP_IOAPIC:
313 {
314 struct mpc_config_ioapic *m=
315 (struct mpc_config_ioapic *)mpt;
316 MP_ioapic_info(m);
317 mpt+=sizeof(*m);
318 count+=sizeof(*m);
319 break;
320 }
321 case MP_INTSRC:
322 {
323 struct mpc_config_intsrc *m=
324 (struct mpc_config_intsrc *)mpt;
325
326 MP_intsrc_info(m);
327 mpt+=sizeof(*m);
328 count+=sizeof(*m);
329 break;
330 }
331 case MP_LINTSRC:
332 {
333 struct mpc_config_lintsrc *m=
334 (struct mpc_config_lintsrc *)mpt;
335 MP_lintsrc_info(m);
336 mpt+=sizeof(*m);
337 count+=sizeof(*m);
338 break;
339 }
340 }
341 }
342 clustered_apic_check();
343 if (!num_processors)
344 printk(KERN_ERR "SMP mptable: no processors registered!\n");
345 return num_processors;
346}
347
348static int __init ELCR_trigger(unsigned int irq)
349{
350 unsigned int port;
351
352 port = 0x4d0 + (irq >> 3);
353 return (inb(port) >> (irq & 7)) & 1;
354}
355
356static void __init construct_default_ioirq_mptable(int mpc_default_type)
357{
358 struct mpc_config_intsrc intsrc;
359 int i;
360 int ELCR_fallback = 0;
361
362 intsrc.mpc_type = MP_INTSRC;
363 intsrc.mpc_irqflag = 0; /* conforming */
364 intsrc.mpc_srcbus = 0;
365 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
366
367 intsrc.mpc_irqtype = mp_INT;
368
369 /*
370 * If true, we have an ISA/PCI system with no IRQ entries
371 * in the MP table. To prevent the PCI interrupts from being set up
372 * incorrectly, we try to use the ELCR. The sanity check to see if
373 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
374 * never be level sensitive, so we simply see if the ELCR agrees.
375 * If it does, we assume it's valid.
376 */
377 if (mpc_default_type == 5) {
378 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
379
380 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
381 printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
382 else {
383 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
384 ELCR_fallback = 1;
385 }
386 }
387
388 for (i = 0; i < 16; i++) {
389 switch (mpc_default_type) {
390 case 2:
391 if (i == 0 || i == 13)
392 continue; /* IRQ0 & IRQ13 not connected */
393 /* fall through */
394 default:
395 if (i == 2)
396 continue; /* IRQ2 is never connected */
397 }
398
399 if (ELCR_fallback) {
400 /*
401 * If the ELCR indicates a level-sensitive interrupt, we
402 * copy that information over to the MP table in the
403 * irqflag field (level sensitive, active high polarity).
404 */
405 if (ELCR_trigger(i))
406 intsrc.mpc_irqflag = 13;
407 else
408 intsrc.mpc_irqflag = 0;
409 }
410
411 intsrc.mpc_srcbusirq = i;
412 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
413 MP_intsrc_info(&intsrc);
414 }
415
416 intsrc.mpc_irqtype = mp_ExtINT;
417 intsrc.mpc_srcbusirq = 0;
418 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
419 MP_intsrc_info(&intsrc);
420}
421
422static inline void __init construct_default_ISA_mptable(int mpc_default_type)
423{
424 struct mpc_config_processor processor;
425 struct mpc_config_bus bus;
426 struct mpc_config_ioapic ioapic;
427 struct mpc_config_lintsrc lintsrc;
428 int linttypes[2] = { mp_ExtINT, mp_NMI };
429 int i;
430
431 /*
432 * local APIC has default address
433 */
434 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
435
436 /*
437 * 2 CPUs, numbered 0 & 1.
438 */
439 processor.mpc_type = MP_PROCESSOR;
440 /* Either an integrated APIC or a discrete 82489DX. */
441 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
442 processor.mpc_cpuflag = CPU_ENABLED;
443 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
444 (boot_cpu_data.x86_model << 4) |
445 boot_cpu_data.x86_mask;
446 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
447 processor.mpc_reserved[0] = 0;
448 processor.mpc_reserved[1] = 0;
449 for (i = 0; i < 2; i++) {
450 processor.mpc_apicid = i;
451 MP_processor_info(&processor);
452 }
453
454 bus.mpc_type = MP_BUS;
455 bus.mpc_busid = 0;
456 switch (mpc_default_type) {
457 default:
458 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
459 mpc_default_type);
460 /* fall through */
461 case 1:
462 case 5:
463 memcpy(bus.mpc_bustype, "ISA ", 6);
464 break;
465 case 2:
466 case 6:
467 case 3:
468 memcpy(bus.mpc_bustype, "EISA ", 6);
469 break;
470 case 4:
471 case 7:
472 memcpy(bus.mpc_bustype, "MCA ", 6);
473 }
474 MP_bus_info(&bus);
475 if (mpc_default_type > 4) {
476 bus.mpc_busid = 1;
477 memcpy(bus.mpc_bustype, "PCI ", 6);
478 MP_bus_info(&bus);
479 }
480
481 ioapic.mpc_type = MP_IOAPIC;
482 ioapic.mpc_apicid = 2;
483 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
484 ioapic.mpc_flags = MPC_APIC_USABLE;
485 ioapic.mpc_apicaddr = 0xFEC00000;
486 MP_ioapic_info(&ioapic);
487
488 /*
489 * We set up most of the low 16 IO-APIC pins according to MPS rules.
490 */
491 construct_default_ioirq_mptable(mpc_default_type);
492
493 lintsrc.mpc_type = MP_LINTSRC;
494 lintsrc.mpc_irqflag = 0; /* conforming */
495 lintsrc.mpc_srcbusid = 0;
496 lintsrc.mpc_srcbusirq = 0;
497 lintsrc.mpc_destapic = MP_APIC_ALL;
498 for (i = 0; i < 2; i++) {
499 lintsrc.mpc_irqtype = linttypes[i];
500 lintsrc.mpc_destapiclint = i;
501 MP_lintsrc_info(&lintsrc);
502 }
503}
504
505static struct intel_mp_floating *mpf_found;
506
507/*
508 * Scan the memory blocks for an SMP configuration block.
509 */
510void __init get_smp_config (void)
511{
512 struct intel_mp_floating *mpf = mpf_found;
513
514 /*
515 * ACPI may be used to obtain the entire SMP configuration or just to
516 * enumerate/configure processors (CONFIG_ACPI_BOOT). Note that
517 * ACPI supports both logical (e.g. Hyper-Threading) and physical
518 * processors, where MPS only supports physical.
519 */
520 if (acpi_lapic && acpi_ioapic) {
521 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
522 return;
523 }
524 else if (acpi_lapic)
525 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
526
527 printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
528 if (mpf->mpf_feature2 & (1<<7)) {
529 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
530 pic_mode = 1;
531 } else {
532 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
533 pic_mode = 0;
534 }
535
536 /*
537 * Now see if we need to read further.
538 */
539 if (mpf->mpf_feature1 != 0) {
540
541 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
542 construct_default_ISA_mptable(mpf->mpf_feature1);
543
544 } else if (mpf->mpf_physptr) {
545
546 /*
547 * Read the physical hardware table. Anything here will
548 * override the defaults.
549 */
550 if (!smp_read_mpc((void *)(unsigned long)mpf->mpf_physptr)) {
551 smp_found_config = 0;
552 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
553 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
554 return;
555 }
556 /*
557 * If there are no explicit MP IRQ entries, then we are
558 * broken. We set up most of the low 16 IO-APIC pins to
559 * ISA defaults and hope it will work.
560 */
561 if (!mp_irq_entries) {
562 struct mpc_config_bus bus;
563
564 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
565
566 bus.mpc_type = MP_BUS;
567 bus.mpc_busid = 0;
568 memcpy(bus.mpc_bustype, "ISA ", 6);
569 MP_bus_info(&bus);
570
571 construct_default_ioirq_mptable(0);
572 }
573
574 } else
575 BUG();
576
577 printk(KERN_INFO "Processors: %d\n", num_processors);
578 /*
579 * Only use the first configuration found.
580 */
581}
582
583static int __init smp_scan_config (unsigned long base, unsigned long length)
584{
585 extern void __bad_mpf_size(void);
586 unsigned int *bp = phys_to_virt(base);
587 struct intel_mp_floating *mpf;
588
589 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
590 if (sizeof(*mpf) != 16)
591 __bad_mpf_size();
592
593 while (length > 0) {
594 mpf = (struct intel_mp_floating *)bp;
595 if ((*bp == SMP_MAGIC_IDENT) &&
596 (mpf->mpf_length == 1) &&
597 !mpf_checksum((unsigned char *)bp, 16) &&
598 ((mpf->mpf_specification == 1)
599 || (mpf->mpf_specification == 4)) ) {
600
601 smp_found_config = 1;
602 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
603 if (mpf->mpf_physptr)
604 reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE);
605 mpf_found = mpf;
606 return 1;
607 }
608 bp += 4;
609 length -= 16;
610 }
611 return 0;
612}
613
614void __init find_intel_smp (void)
615{
616 unsigned int address;
617
618 /*
619 * FIXME: Linux assumes you have 640K of base ram..
620 * this continues the error...
621 *
622 * 1) Scan the bottom 1K for a signature
623 * 2) Scan the top 1K of base RAM
624 * 3) Scan the 64K of bios
625 */
626 if (smp_scan_config(0x0,0x400) ||
627 smp_scan_config(639*0x400,0x400) ||
628 smp_scan_config(0xF0000,0x10000))
629 return;
630 /*
631 * If it is an SMP machine we should know now, unless the
632 * configuration is in an EISA/MCA bus machine with an
633 * extended bios data area.
634 *
635 * there is a real-mode segmented pointer pointing to the
636 * 4K EBDA area at 0x40E, calculate and scan it here.
637 *
638 * NOTE! There are Linux loaders that will corrupt the EBDA
639 * area, and as such this kind of SMP config may be less
640 * trustworthy, simply because the SMP table may have been
641 * stomped on during early boot. These loaders are buggy and
642 * should be fixed.
643 */
644
645 address = *(unsigned short *)phys_to_virt(0x40E);
646 address <<= 4;
647 if (smp_scan_config(address, 0x1000))
648 return;
649
650 /* If we have come this far, we did not find an MP table */
651 printk(KERN_INFO "No mptable found.\n");
652}
653
654/*
655 * - Intel MP Configuration Table
656 */
657void __init find_smp_config (void)
658{
659#ifdef CONFIG_X86_LOCAL_APIC
660 find_intel_smp();
661#endif
662}
663
664
665/* --------------------------------------------------------------------------
666 ACPI-based MP Configuration
667 -------------------------------------------------------------------------- */
668
669#ifdef CONFIG_ACPI_BOOT
670
671void __init mp_register_lapic_address (
672 u64 address)
673{
674 mp_lapic_addr = (unsigned long) address;
675
676 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
677
678 if (boot_cpu_id == -1U)
679 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
680
681 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
682}
683
684
685void __init mp_register_lapic (
686 u8 id,
687 u8 enabled)
688{
689 struct mpc_config_processor processor;
690 int boot_cpu = 0;
691
692 if (id >= MAX_APICS) {
693 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
694 id, MAX_APICS);
695 return;
696 }
697
698 if (id == boot_cpu_physical_apicid)
699 boot_cpu = 1;
700
701 processor.mpc_type = MP_PROCESSOR;
702 processor.mpc_apicid = id;
703 processor.mpc_apicver = 0x10; /* TBD: lapic version */
704 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
705 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
706 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
707 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
708 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
709 processor.mpc_reserved[0] = 0;
710 processor.mpc_reserved[1] = 0;
711
712 MP_processor_info(&processor);
713}
714
715#ifdef CONFIG_X86_IO_APIC
716
717#define MP_ISA_BUS 0
718#define MP_MAX_IOAPIC_PIN 127
719
720static struct mp_ioapic_routing {
721 int apic_id;
722 int gsi_start;
723 int gsi_end;
724 u32 pin_programmed[4];
725} mp_ioapic_routing[MAX_IO_APICS];
726
727
728static int mp_find_ioapic (
729 int gsi)
730{
731 int i = 0;
732
733 /* Find the IOAPIC that manages this GSI. */
734 for (i = 0; i < nr_ioapics; i++) {
735 if ((gsi >= mp_ioapic_routing[i].gsi_start)
736 && (gsi <= mp_ioapic_routing[i].gsi_end))
737 return i;
738 }
739
740 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
741
742 return -1;
743}
744
745
746void __init mp_register_ioapic (
747 u8 id,
748 u32 address,
749 u32 gsi_base)
750{
751 int idx = 0;
752
753 if (nr_ioapics >= MAX_IO_APICS) {
754 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
755 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
756 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
757 }
758 if (!address) {
759 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
760 " found in MADT table, skipping!\n");
761 return;
762 }
763
764 idx = nr_ioapics++;
765
766 mp_ioapics[idx].mpc_type = MP_IOAPIC;
767 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
768 mp_ioapics[idx].mpc_apicaddr = address;
769
770 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
0af2be0b 771 mp_ioapics[idx].mpc_apicid = id;
1da177e4
LT		 772 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
773
774 /*
775 * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
776 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
777 */
778 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
779 mp_ioapic_routing[idx].gsi_start = gsi_base;
780 mp_ioapic_routing[idx].gsi_end = gsi_base +
781 io_apic_get_redir_entries(idx);
782
783 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
784 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
785 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
786 mp_ioapic_routing[idx].gsi_start,
787 mp_ioapic_routing[idx].gsi_end);
788
789 return;
790}
791
792
793void __init mp_override_legacy_irq (
794 u8 bus_irq,
795 u8 polarity,
796 u8 trigger,
797 u32 gsi)
798{
799 struct mpc_config_intsrc intsrc;
800 int ioapic = -1;
801 int pin = -1;
802
803 /*
804 * Convert 'gsi' to 'ioapic.pin'.
805 */
806 ioapic = mp_find_ioapic(gsi);
807 if (ioapic < 0)
808 return;
809 pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
810
811 /*
812 * TBD: This check is for faulty timer entries, where the override
813 * erroneously sets the trigger to level, resulting in a HUGE
814 * increase of timer interrupts!
815 */
816 if ((bus_irq == 0) && (trigger == 3))
817 trigger = 1;
818
819 intsrc.mpc_type = MP_INTSRC;
820 intsrc.mpc_irqtype = mp_INT;
821 intsrc.mpc_irqflag = (trigger << 2) | polarity;
822 intsrc.mpc_srcbus = MP_ISA_BUS;
823 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
824 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
825 intsrc.mpc_dstirq = pin; /* INTIN# */
826
827 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
828 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
829 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
830 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
831
832 mp_irqs[mp_irq_entries] = intsrc;
833 if (++mp_irq_entries == MAX_IRQ_SOURCES)
834 panic("Max # of irq sources exceeded!\n");
835
836 return;
837}
838
839
840void __init mp_config_acpi_legacy_irqs (void)
841{
842 struct mpc_config_intsrc intsrc;
843 int i = 0;
844 int ioapic = -1;
845
846 /*
847 * Fabricate the legacy ISA bus (bus #31).
848 */
849 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
850 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
851
852 /*
853 * Locate the IOAPIC that manages the ISA IRQs (0-15).
854 */
855 ioapic = mp_find_ioapic(0);
856 if (ioapic < 0)
857 return;
858
859 intsrc.mpc_type = MP_INTSRC;
860 intsrc.mpc_irqflag = 0; /* Conforming */
861 intsrc.mpc_srcbus = MP_ISA_BUS;
862 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
863
864 /*
865 * Use the default configuration for the IRQs 0-15. Unless
866 * overridden by (MADT) interrupt source override entries.
867 */
868 for (i = 0; i < 16; i++) {
869 int idx;
870
871 for (idx = 0; idx < mp_irq_entries; idx++) {
872 struct mpc_config_intsrc *irq = mp_irqs + idx;
873
874 /* Do we already have a mapping for this ISA IRQ? */
875 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
876 break;
877
878 /* Do we already have a mapping for this IOAPIC pin */
879 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
880 (irq->mpc_dstirq == i))
881 break;
882 }
883
884 if (idx != mp_irq_entries) {
885 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
886 continue; /* IRQ already used */
887 }
888
889 intsrc.mpc_irqtype = mp_INT;
890 intsrc.mpc_srcbusirq = i; /* Identity mapped */
891 intsrc.mpc_dstirq = i;
892
893 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
894 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
895 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
896 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
897 intsrc.mpc_dstirq);
898
899 mp_irqs[mp_irq_entries] = intsrc;
900 if (++mp_irq_entries == MAX_IRQ_SOURCES)
901 panic("Max # of irq sources exceeded!\n");
902 }
903
904 return;
905}
906
907int mp_register_gsi(u32 gsi, int edge_level, int active_high_low)
908{
909 int ioapic = -1;
910 int ioapic_pin = 0;
911 int idx, bit = 0;
912
913 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
914 return gsi;
915
916#ifdef CONFIG_ACPI_BUS
917 /* Don't set up the ACPI SCI because it's already set up */
918 if (acpi_fadt.sci_int == gsi)
919 return gsi;
920#endif
921
922 ioapic = mp_find_ioapic(gsi);
923 if (ioapic < 0) {
924 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
925 return gsi;
926 }
927
928 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
929
930 /*
931 * Avoid pin reprogramming. PRTs typically include entries
932 * with redundant pin->gsi mappings (but unique PCI devices);
933 * we only program the IOAPIC on the first.
934 */
935 bit = ioapic_pin % 32;
936 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
937 if (idx > 3) {
938 printk(KERN_ERR "Invalid reference to IOAPIC pin "
939 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
940 ioapic_pin);
941 return gsi;
942 }
943 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
944 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
945 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
946 return gsi;
947 }
948
949 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
950
951 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
952 edge_level == ACPI_EDGE_SENSITIVE ? 0 : 1,
953 active_high_low == ACPI_ACTIVE_HIGH ? 0 : 1);
954 return gsi;
955}
956
957#endif /*CONFIG_X86_IO_APIC*/
958#endif /*CONFIG_ACPI_BOOT*/
Linux kernel - Deliverables
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