Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel Multiprocessor Specification 1.1 and 1.4 | |
3 | * compliant MP-table parsing routines. | |
4 | * | |
5 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
6 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
7 | * | |
8 | * Fixes | |
9 | * Erich Boleyn : MP v1.4 and additional changes. | |
10 | * Alan Cox : Added EBDA scanning | |
11 | * Ingo Molnar : various cleanups and rewrites | |
12 | * Maciej W. Rozycki: Bits for default MP configurations | |
13 | * Paul Diefenbaugh: Added full ACPI support | |
14 | */ | |
15 | ||
16 | #include <linux/mm.h> | |
1da177e4 LT |
17 | #include <linux/init.h> |
18 | #include <linux/delay.h> | |
1da177e4 LT |
19 | #include <linux/bootmem.h> |
20 | #include <linux/smp_lock.h> | |
21 | #include <linux/kernel_stat.h> | |
22 | #include <linux/mc146818rtc.h> | |
23 | #include <linux/acpi.h> | |
8c5a0908 | 24 | #include <linux/module.h> |
1da177e4 LT |
25 | |
26 | #include <asm/smp.h> | |
27 | #include <asm/mtrr.h> | |
28 | #include <asm/mpspec.h> | |
29 | #include <asm/pgalloc.h> | |
30 | #include <asm/io_apic.h> | |
31 | #include <asm/proto.h> | |
8d916406 | 32 | #include <asm/acpi.h> |
1da177e4 LT |
33 | |
34 | /* Have we found an MP table */ | |
35 | int smp_found_config; | |
36 | unsigned int __initdata maxcpus = NR_CPUS; | |
37 | ||
38 | int acpi_found_madt; | |
39 | ||
40 | /* | |
41 | * Various Linux-internal data structures created from the | |
42 | * MP-table. | |
43 | */ | |
55f05ffa | 44 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
1da177e4 | 45 | int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 }; |
1da177e4 LT |
46 | |
47 | static int mp_current_pci_id = 0; | |
48 | /* I/O APIC entries */ | |
49 | struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; | |
50 | ||
51 | /* # of MP IRQ source entries */ | |
52 | struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; | |
53 | ||
54 | /* MP IRQ source entries */ | |
55 | int mp_irq_entries; | |
56 | ||
57 | int nr_ioapics; | |
1da177e4 LT |
58 | unsigned long mp_lapic_addr = 0; |
59 | ||
60 | ||
61 | ||
62 | /* Processor that is doing the boot up */ | |
63 | unsigned int boot_cpu_id = -1U; | |
64 | /* Internal processor count */ | |
420f8f68 AK |
65 | unsigned int num_processors __initdata = 0; |
66 | ||
67 | unsigned disabled_cpus __initdata; | |
1da177e4 LT |
68 | |
69 | /* Bitmask of physically existing CPUs */ | |
70 | physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE; | |
71 | ||
1da177e4 LT |
72 | u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID }; |
73 | ||
74 | ||
75 | /* | |
76 | * Intel MP BIOS table parsing routines: | |
77 | */ | |
78 | ||
79 | /* | |
80 | * Checksum an MP configuration block. | |
81 | */ | |
82 | ||
83 | static int __init mpf_checksum(unsigned char *mp, int len) | |
84 | { | |
85 | int sum = 0; | |
86 | ||
87 | while (len--) | |
88 | sum += *mp++; | |
89 | ||
90 | return sum & 0xFF; | |
91 | } | |
92 | ||
51f62e18 | 93 | static void __cpuinit MP_processor_info (struct mpc_config_processor *m) |
1da177e4 | 94 | { |
8893166f | 95 | int cpu; |
51f62e18 | 96 | cpumask_t tmp_map; |
f2c2cca3 | 97 | char *bootup_cpu = ""; |
1da177e4 | 98 | |
420f8f68 AK |
99 | if (!(m->mpc_cpuflag & CPU_ENABLED)) { |
100 | disabled_cpus++; | |
1da177e4 | 101 | return; |
420f8f68 | 102 | } |
1da177e4 | 103 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { |
f2c2cca3 | 104 | bootup_cpu = " (Bootup-CPU)"; |
1da177e4 LT |
105 | boot_cpu_id = m->mpc_apicid; |
106 | } | |
f2c2cca3 AK |
107 | |
108 | printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu); | |
109 | ||
1da177e4 LT |
110 | if (num_processors >= NR_CPUS) { |
111 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
112 | " Processor ignored.\n", NR_CPUS); | |
113 | return; | |
114 | } | |
1da177e4 | 115 | |
51f62e18 AR |
116 | num_processors++; |
117 | cpus_complement(tmp_map, cpu_present_map); | |
118 | cpu = first_cpu(tmp_map); | |
119 | ||
1da177e4 | 120 | physid_set(m->mpc_apicid, phys_cpu_present_map); |
18a2b647 AK |
121 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { |
122 | /* | |
123 | * bios_cpu_apicid is required to have processors listed | |
124 | * in same order as logical cpu numbers. Hence the first | |
125 | * entry is BSP, and so on. | |
126 | */ | |
61b1b2d0 | 127 | cpu = 0; |
51f62e18 | 128 | } |
61b1b2d0 AK |
129 | bios_cpu_apicid[cpu] = m->mpc_apicid; |
130 | x86_cpu_to_apicid[cpu] = m->mpc_apicid; | |
131 | ||
132 | cpu_set(cpu, cpu_possible_map); | |
133 | cpu_set(cpu, cpu_present_map); | |
1da177e4 LT |
134 | } |
135 | ||
136 | static void __init MP_bus_info (struct mpc_config_bus *m) | |
137 | { | |
138 | char str[7]; | |
139 | ||
140 | memcpy(str, m->mpc_bustype, 6); | |
141 | str[6] = 0; | |
142 | Dprintk("Bus #%d is %s\n", m->mpc_busid, str); | |
143 | ||
144 | if (strncmp(str, "ISA", 3) == 0) { | |
55f05ffa | 145 | set_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 | 146 | } else if (strncmp(str, "PCI", 3) == 0) { |
55f05ffa | 147 | clear_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 LT |
148 | mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id; |
149 | mp_current_pci_id++; | |
1da177e4 LT |
150 | } else { |
151 | printk(KERN_ERR "Unknown bustype %s\n", str); | |
152 | } | |
153 | } | |
154 | ||
155 | static void __init MP_ioapic_info (struct mpc_config_ioapic *m) | |
156 | { | |
157 | if (!(m->mpc_flags & MPC_APIC_USABLE)) | |
158 | return; | |
159 | ||
f2c2cca3 AK |
160 | printk("I/O APIC #%d at 0x%X.\n", |
161 | m->mpc_apicid, m->mpc_apicaddr); | |
1da177e4 LT |
162 | if (nr_ioapics >= MAX_IO_APICS) { |
163 | printk(KERN_ERR "Max # of I/O APICs (%d) exceeded (found %d).\n", | |
164 | MAX_IO_APICS, nr_ioapics); | |
165 | panic("Recompile kernel with bigger MAX_IO_APICS!.\n"); | |
166 | } | |
167 | if (!m->mpc_apicaddr) { | |
168 | printk(KERN_ERR "WARNING: bogus zero I/O APIC address" | |
169 | " found in MP table, skipping!\n"); | |
170 | return; | |
171 | } | |
172 | mp_ioapics[nr_ioapics] = *m; | |
173 | nr_ioapics++; | |
174 | } | |
175 | ||
176 | static void __init MP_intsrc_info (struct mpc_config_intsrc *m) | |
177 | { | |
178 | mp_irqs [mp_irq_entries] = *m; | |
179 | Dprintk("Int: type %d, pol %d, trig %d, bus %d," | |
180 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
181 | m->mpc_irqtype, m->mpc_irqflag & 3, | |
182 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus, | |
183 | m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq); | |
6004e1b7 | 184 | if (++mp_irq_entries >= MAX_IRQ_SOURCES) |
1da177e4 LT |
185 | panic("Max # of irq sources exceeded!!\n"); |
186 | } | |
187 | ||
188 | static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m) | |
189 | { | |
190 | Dprintk("Lint: type %d, pol %d, trig %d, bus %d," | |
191 | " IRQ %02x, APIC ID %x, APIC LINT %02x\n", | |
192 | m->mpc_irqtype, m->mpc_irqflag & 3, | |
193 | (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid, | |
194 | m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint); | |
1da177e4 LT |
195 | } |
196 | ||
197 | /* | |
198 | * Read/parse the MPC | |
199 | */ | |
200 | ||
201 | static int __init smp_read_mpc(struct mp_config_table *mpc) | |
202 | { | |
203 | char str[16]; | |
204 | int count=sizeof(*mpc); | |
205 | unsigned char *mpt=((unsigned char *)mpc)+count; | |
206 | ||
207 | if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) { | |
208 | printk("SMP mptable: bad signature [%c%c%c%c]!\n", | |
209 | mpc->mpc_signature[0], | |
210 | mpc->mpc_signature[1], | |
211 | mpc->mpc_signature[2], | |
212 | mpc->mpc_signature[3]); | |
213 | return 0; | |
214 | } | |
215 | if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) { | |
216 | printk("SMP mptable: checksum error!\n"); | |
217 | return 0; | |
218 | } | |
219 | if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) { | |
220 | printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n", | |
221 | mpc->mpc_spec); | |
222 | return 0; | |
223 | } | |
224 | if (!mpc->mpc_lapic) { | |
225 | printk(KERN_ERR "SMP mptable: null local APIC address!\n"); | |
226 | return 0; | |
227 | } | |
228 | memcpy(str,mpc->mpc_oem,8); | |
229 | str[8]=0; | |
230 | printk(KERN_INFO "OEM ID: %s ",str); | |
231 | ||
232 | memcpy(str,mpc->mpc_productid,12); | |
233 | str[12]=0; | |
9ff4ced4 | 234 | printk("Product ID: %s ",str); |
1da177e4 | 235 | |
9ff4ced4 | 236 | printk("APIC at: 0x%X\n",mpc->mpc_lapic); |
1da177e4 LT |
237 | |
238 | /* save the local APIC address, it might be non-default */ | |
239 | if (!acpi_lapic) | |
240 | mp_lapic_addr = mpc->mpc_lapic; | |
241 | ||
242 | /* | |
243 | * Now process the configuration blocks. | |
244 | */ | |
245 | while (count < mpc->mpc_length) { | |
246 | switch(*mpt) { | |
247 | case MP_PROCESSOR: | |
248 | { | |
249 | struct mpc_config_processor *m= | |
250 | (struct mpc_config_processor *)mpt; | |
251 | if (!acpi_lapic) | |
252 | MP_processor_info(m); | |
253 | mpt += sizeof(*m); | |
254 | count += sizeof(*m); | |
255 | break; | |
256 | } | |
257 | case MP_BUS: | |
258 | { | |
259 | struct mpc_config_bus *m= | |
260 | (struct mpc_config_bus *)mpt; | |
261 | MP_bus_info(m); | |
262 | mpt += sizeof(*m); | |
263 | count += sizeof(*m); | |
264 | break; | |
265 | } | |
266 | case MP_IOAPIC: | |
267 | { | |
268 | struct mpc_config_ioapic *m= | |
269 | (struct mpc_config_ioapic *)mpt; | |
270 | MP_ioapic_info(m); | |
271 | mpt+=sizeof(*m); | |
272 | count+=sizeof(*m); | |
273 | break; | |
274 | } | |
275 | case MP_INTSRC: | |
276 | { | |
277 | struct mpc_config_intsrc *m= | |
278 | (struct mpc_config_intsrc *)mpt; | |
279 | ||
280 | MP_intsrc_info(m); | |
281 | mpt+=sizeof(*m); | |
282 | count+=sizeof(*m); | |
283 | break; | |
284 | } | |
285 | case MP_LINTSRC: | |
286 | { | |
287 | struct mpc_config_lintsrc *m= | |
288 | (struct mpc_config_lintsrc *)mpt; | |
289 | MP_lintsrc_info(m); | |
290 | mpt+=sizeof(*m); | |
291 | count+=sizeof(*m); | |
292 | break; | |
293 | } | |
294 | } | |
295 | } | |
296 | clustered_apic_check(); | |
297 | if (!num_processors) | |
298 | printk(KERN_ERR "SMP mptable: no processors registered!\n"); | |
299 | return num_processors; | |
300 | } | |
301 | ||
302 | static int __init ELCR_trigger(unsigned int irq) | |
303 | { | |
304 | unsigned int port; | |
305 | ||
306 | port = 0x4d0 + (irq >> 3); | |
307 | return (inb(port) >> (irq & 7)) & 1; | |
308 | } | |
309 | ||
310 | static void __init construct_default_ioirq_mptable(int mpc_default_type) | |
311 | { | |
312 | struct mpc_config_intsrc intsrc; | |
313 | int i; | |
314 | int ELCR_fallback = 0; | |
315 | ||
316 | intsrc.mpc_type = MP_INTSRC; | |
317 | intsrc.mpc_irqflag = 0; /* conforming */ | |
318 | intsrc.mpc_srcbus = 0; | |
319 | intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid; | |
320 | ||
321 | intsrc.mpc_irqtype = mp_INT; | |
322 | ||
323 | /* | |
324 | * If true, we have an ISA/PCI system with no IRQ entries | |
325 | * in the MP table. To prevent the PCI interrupts from being set up | |
326 | * incorrectly, we try to use the ELCR. The sanity check to see if | |
327 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can | |
328 | * never be level sensitive, so we simply see if the ELCR agrees. | |
329 | * If it does, we assume it's valid. | |
330 | */ | |
331 | if (mpc_default_type == 5) { | |
332 | printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n"); | |
333 | ||
334 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13)) | |
335 | printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n"); | |
336 | else { | |
337 | printk(KERN_INFO "Using ELCR to identify PCI interrupts\n"); | |
338 | ELCR_fallback = 1; | |
339 | } | |
340 | } | |
341 | ||
342 | for (i = 0; i < 16; i++) { | |
343 | switch (mpc_default_type) { | |
344 | case 2: | |
345 | if (i == 0 || i == 13) | |
346 | continue; /* IRQ0 & IRQ13 not connected */ | |
347 | /* fall through */ | |
348 | default: | |
349 | if (i == 2) | |
350 | continue; /* IRQ2 is never connected */ | |
351 | } | |
352 | ||
353 | if (ELCR_fallback) { | |
354 | /* | |
355 | * If the ELCR indicates a level-sensitive interrupt, we | |
356 | * copy that information over to the MP table in the | |
357 | * irqflag field (level sensitive, active high polarity). | |
358 | */ | |
359 | if (ELCR_trigger(i)) | |
360 | intsrc.mpc_irqflag = 13; | |
361 | else | |
362 | intsrc.mpc_irqflag = 0; | |
363 | } | |
364 | ||
365 | intsrc.mpc_srcbusirq = i; | |
366 | intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ | |
367 | MP_intsrc_info(&intsrc); | |
368 | } | |
369 | ||
370 | intsrc.mpc_irqtype = mp_ExtINT; | |
371 | intsrc.mpc_srcbusirq = 0; | |
372 | intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */ | |
373 | MP_intsrc_info(&intsrc); | |
374 | } | |
375 | ||
376 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) | |
377 | { | |
378 | struct mpc_config_processor processor; | |
379 | struct mpc_config_bus bus; | |
380 | struct mpc_config_ioapic ioapic; | |
381 | struct mpc_config_lintsrc lintsrc; | |
382 | int linttypes[2] = { mp_ExtINT, mp_NMI }; | |
383 | int i; | |
384 | ||
385 | /* | |
386 | * local APIC has default address | |
387 | */ | |
388 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
389 | ||
390 | /* | |
391 | * 2 CPUs, numbered 0 & 1. | |
392 | */ | |
393 | processor.mpc_type = MP_PROCESSOR; | |
f2c2cca3 | 394 | processor.mpc_apicver = 0; |
1da177e4 | 395 | processor.mpc_cpuflag = CPU_ENABLED; |
f2c2cca3 AK |
396 | processor.mpc_cpufeature = 0; |
397 | processor.mpc_featureflag = 0; | |
1da177e4 LT |
398 | processor.mpc_reserved[0] = 0; |
399 | processor.mpc_reserved[1] = 0; | |
400 | for (i = 0; i < 2; i++) { | |
401 | processor.mpc_apicid = i; | |
402 | MP_processor_info(&processor); | |
403 | } | |
404 | ||
405 | bus.mpc_type = MP_BUS; | |
406 | bus.mpc_busid = 0; | |
407 | switch (mpc_default_type) { | |
408 | default: | |
409 | printk(KERN_ERR "???\nUnknown standard configuration %d\n", | |
410 | mpc_default_type); | |
411 | /* fall through */ | |
412 | case 1: | |
413 | case 5: | |
414 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
415 | break; | |
1da177e4 LT |
416 | } |
417 | MP_bus_info(&bus); | |
418 | if (mpc_default_type > 4) { | |
419 | bus.mpc_busid = 1; | |
420 | memcpy(bus.mpc_bustype, "PCI ", 6); | |
421 | MP_bus_info(&bus); | |
422 | } | |
423 | ||
424 | ioapic.mpc_type = MP_IOAPIC; | |
425 | ioapic.mpc_apicid = 2; | |
f2c2cca3 | 426 | ioapic.mpc_apicver = 0; |
1da177e4 LT |
427 | ioapic.mpc_flags = MPC_APIC_USABLE; |
428 | ioapic.mpc_apicaddr = 0xFEC00000; | |
429 | MP_ioapic_info(&ioapic); | |
430 | ||
431 | /* | |
432 | * We set up most of the low 16 IO-APIC pins according to MPS rules. | |
433 | */ | |
434 | construct_default_ioirq_mptable(mpc_default_type); | |
435 | ||
436 | lintsrc.mpc_type = MP_LINTSRC; | |
437 | lintsrc.mpc_irqflag = 0; /* conforming */ | |
438 | lintsrc.mpc_srcbusid = 0; | |
439 | lintsrc.mpc_srcbusirq = 0; | |
440 | lintsrc.mpc_destapic = MP_APIC_ALL; | |
441 | for (i = 0; i < 2; i++) { | |
442 | lintsrc.mpc_irqtype = linttypes[i]; | |
443 | lintsrc.mpc_destapiclint = i; | |
444 | MP_lintsrc_info(&lintsrc); | |
445 | } | |
446 | } | |
447 | ||
448 | static struct intel_mp_floating *mpf_found; | |
449 | ||
450 | /* | |
451 | * Scan the memory blocks for an SMP configuration block. | |
452 | */ | |
453 | void __init get_smp_config (void) | |
454 | { | |
455 | struct intel_mp_floating *mpf = mpf_found; | |
456 | ||
457 | /* | |
1da177e4 LT |
458 | * ACPI supports both logical (e.g. Hyper-Threading) and physical |
459 | * processors, where MPS only supports physical. | |
460 | */ | |
461 | if (acpi_lapic && acpi_ioapic) { | |
462 | printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n"); | |
463 | return; | |
464 | } | |
465 | else if (acpi_lapic) | |
466 | printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n"); | |
467 | ||
468 | printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification); | |
1da177e4 LT |
469 | |
470 | /* | |
471 | * Now see if we need to read further. | |
472 | */ | |
473 | if (mpf->mpf_feature1 != 0) { | |
474 | ||
475 | printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1); | |
476 | construct_default_ISA_mptable(mpf->mpf_feature1); | |
477 | ||
478 | } else if (mpf->mpf_physptr) { | |
479 | ||
480 | /* | |
481 | * Read the physical hardware table. Anything here will | |
482 | * override the defaults. | |
483 | */ | |
f6c2e333 | 484 | if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) { |
1da177e4 LT |
485 | smp_found_config = 0; |
486 | printk(KERN_ERR "BIOS bug, MP table errors detected!...\n"); | |
487 | printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n"); | |
488 | return; | |
489 | } | |
490 | /* | |
491 | * If there are no explicit MP IRQ entries, then we are | |
492 | * broken. We set up most of the low 16 IO-APIC pins to | |
493 | * ISA defaults and hope it will work. | |
494 | */ | |
495 | if (!mp_irq_entries) { | |
496 | struct mpc_config_bus bus; | |
497 | ||
498 | printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n"); | |
499 | ||
500 | bus.mpc_type = MP_BUS; | |
501 | bus.mpc_busid = 0; | |
502 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
503 | MP_bus_info(&bus); | |
504 | ||
505 | construct_default_ioirq_mptable(0); | |
506 | } | |
507 | ||
508 | } else | |
509 | BUG(); | |
510 | ||
511 | printk(KERN_INFO "Processors: %d\n", num_processors); | |
512 | /* | |
513 | * Only use the first configuration found. | |
514 | */ | |
515 | } | |
516 | ||
517 | static int __init smp_scan_config (unsigned long base, unsigned long length) | |
518 | { | |
519 | extern void __bad_mpf_size(void); | |
520 | unsigned int *bp = phys_to_virt(base); | |
521 | struct intel_mp_floating *mpf; | |
522 | ||
523 | Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length); | |
524 | if (sizeof(*mpf) != 16) | |
525 | __bad_mpf_size(); | |
526 | ||
527 | while (length > 0) { | |
528 | mpf = (struct intel_mp_floating *)bp; | |
529 | if ((*bp == SMP_MAGIC_IDENT) && | |
530 | (mpf->mpf_length == 1) && | |
531 | !mpf_checksum((unsigned char *)bp, 16) && | |
532 | ((mpf->mpf_specification == 1) | |
533 | || (mpf->mpf_specification == 4)) ) { | |
534 | ||
535 | smp_found_config = 1; | |
536 | reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE); | |
537 | if (mpf->mpf_physptr) | |
538 | reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE); | |
539 | mpf_found = mpf; | |
540 | return 1; | |
541 | } | |
542 | bp += 4; | |
543 | length -= 16; | |
544 | } | |
545 | return 0; | |
546 | } | |
547 | ||
a01fd3ba | 548 | void __init find_smp_config(void) |
1da177e4 LT |
549 | { |
550 | unsigned int address; | |
551 | ||
552 | /* | |
553 | * FIXME: Linux assumes you have 640K of base ram.. | |
554 | * this continues the error... | |
555 | * | |
556 | * 1) Scan the bottom 1K for a signature | |
557 | * 2) Scan the top 1K of base RAM | |
558 | * 3) Scan the 64K of bios | |
559 | */ | |
560 | if (smp_scan_config(0x0,0x400) || | |
561 | smp_scan_config(639*0x400,0x400) || | |
562 | smp_scan_config(0xF0000,0x10000)) | |
563 | return; | |
564 | /* | |
e5099134 | 565 | * If it is an SMP machine we should know now. |
1da177e4 LT |
566 | * |
567 | * there is a real-mode segmented pointer pointing to the | |
568 | * 4K EBDA area at 0x40E, calculate and scan it here. | |
569 | * | |
570 | * NOTE! There are Linux loaders that will corrupt the EBDA | |
571 | * area, and as such this kind of SMP config may be less | |
572 | * trustworthy, simply because the SMP table may have been | |
573 | * stomped on during early boot. These loaders are buggy and | |
574 | * should be fixed. | |
575 | */ | |
576 | ||
577 | address = *(unsigned short *)phys_to_virt(0x40E); | |
578 | address <<= 4; | |
579 | if (smp_scan_config(address, 0x1000)) | |
580 | return; | |
581 | ||
582 | /* If we have come this far, we did not find an MP table */ | |
583 | printk(KERN_INFO "No mptable found.\n"); | |
584 | } | |
585 | ||
1da177e4 LT |
586 | /* -------------------------------------------------------------------------- |
587 | ACPI-based MP Configuration | |
588 | -------------------------------------------------------------------------- */ | |
589 | ||
888ba6c6 | 590 | #ifdef CONFIG_ACPI |
1da177e4 | 591 | |
efec3b9a | 592 | void __init mp_register_lapic_address(u64 address) |
1da177e4 LT |
593 | { |
594 | mp_lapic_addr = (unsigned long) address; | |
1da177e4 | 595 | set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); |
1da177e4 LT |
596 | if (boot_cpu_id == -1U) |
597 | boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID)); | |
1da177e4 LT |
598 | } |
599 | ||
efec3b9a | 600 | void __cpuinit mp_register_lapic (u8 id, u8 enabled) |
1da177e4 LT |
601 | { |
602 | struct mpc_config_processor processor; | |
603 | int boot_cpu = 0; | |
604 | ||
e4251e13 | 605 | if (id == boot_cpu_id) |
1da177e4 LT |
606 | boot_cpu = 1; |
607 | ||
608 | processor.mpc_type = MP_PROCESSOR; | |
609 | processor.mpc_apicid = id; | |
f2c2cca3 | 610 | processor.mpc_apicver = 0; |
1da177e4 LT |
611 | processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0); |
612 | processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0); | |
f2c2cca3 AK |
613 | processor.mpc_cpufeature = 0; |
614 | processor.mpc_featureflag = 0; | |
1da177e4 LT |
615 | processor.mpc_reserved[0] = 0; |
616 | processor.mpc_reserved[1] = 0; | |
617 | ||
618 | MP_processor_info(&processor); | |
619 | } | |
620 | ||
1da177e4 LT |
621 | #define MP_ISA_BUS 0 |
622 | #define MP_MAX_IOAPIC_PIN 127 | |
623 | ||
624 | static struct mp_ioapic_routing { | |
625 | int apic_id; | |
626 | int gsi_start; | |
627 | int gsi_end; | |
628 | u32 pin_programmed[4]; | |
629 | } mp_ioapic_routing[MAX_IO_APICS]; | |
630 | ||
efec3b9a | 631 | static int mp_find_ioapic(int gsi) |
1da177e4 | 632 | { |
efec3b9a | 633 | int i = 0; |
1da177e4 LT |
634 | |
635 | /* Find the IOAPIC that manages this GSI. */ | |
636 | for (i = 0; i < nr_ioapics; i++) { | |
637 | if ((gsi >= mp_ioapic_routing[i].gsi_start) | |
638 | && (gsi <= mp_ioapic_routing[i].gsi_end)) | |
639 | return i; | |
640 | } | |
641 | ||
642 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); | |
1da177e4 LT |
643 | return -1; |
644 | } | |
1da177e4 | 645 | |
efec3b9a | 646 | void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base) |
1da177e4 | 647 | { |
efec3b9a | 648 | int idx = 0; |
1da177e4 LT |
649 | |
650 | if (nr_ioapics >= MAX_IO_APICS) { | |
651 | printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded " | |
652 | "(found %d)\n", MAX_IO_APICS, nr_ioapics); | |
653 | panic("Recompile kernel with bigger MAX_IO_APICS!\n"); | |
654 | } | |
655 | if (!address) { | |
656 | printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address" | |
657 | " found in MADT table, skipping!\n"); | |
658 | return; | |
659 | } | |
660 | ||
661 | idx = nr_ioapics++; | |
662 | ||
663 | mp_ioapics[idx].mpc_type = MP_IOAPIC; | |
664 | mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE; | |
665 | mp_ioapics[idx].mpc_apicaddr = address; | |
666 | ||
667 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
0af2be0b | 668 | mp_ioapics[idx].mpc_apicid = id; |
f2c2cca3 | 669 | mp_ioapics[idx].mpc_apicver = 0; |
1da177e4 LT |
670 | |
671 | /* | |
672 | * Build basic IRQ lookup table to facilitate gsi->io_apic lookups | |
673 | * and to prevent reprogramming of IOAPIC pins (PCI IRQs). | |
674 | */ | |
675 | mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid; | |
676 | mp_ioapic_routing[idx].gsi_start = gsi_base; | |
677 | mp_ioapic_routing[idx].gsi_end = gsi_base + | |
678 | io_apic_get_redir_entries(idx); | |
679 | ||
f2c2cca3 | 680 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, " |
1da177e4 | 681 | "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, |
f2c2cca3 | 682 | mp_ioapics[idx].mpc_apicaddr, |
1da177e4 LT |
683 | mp_ioapic_routing[idx].gsi_start, |
684 | mp_ioapic_routing[idx].gsi_end); | |
1da177e4 LT |
685 | } |
686 | ||
efec3b9a AK |
687 | void __init |
688 | mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi) | |
1da177e4 LT |
689 | { |
690 | struct mpc_config_intsrc intsrc; | |
691 | int ioapic = -1; | |
692 | int pin = -1; | |
693 | ||
694 | /* | |
695 | * Convert 'gsi' to 'ioapic.pin'. | |
696 | */ | |
697 | ioapic = mp_find_ioapic(gsi); | |
698 | if (ioapic < 0) | |
699 | return; | |
700 | pin = gsi - mp_ioapic_routing[ioapic].gsi_start; | |
701 | ||
702 | /* | |
703 | * TBD: This check is for faulty timer entries, where the override | |
704 | * erroneously sets the trigger to level, resulting in a HUGE | |
705 | * increase of timer interrupts! | |
706 | */ | |
707 | if ((bus_irq == 0) && (trigger == 3)) | |
708 | trigger = 1; | |
709 | ||
710 | intsrc.mpc_type = MP_INTSRC; | |
711 | intsrc.mpc_irqtype = mp_INT; | |
712 | intsrc.mpc_irqflag = (trigger << 2) | polarity; | |
713 | intsrc.mpc_srcbus = MP_ISA_BUS; | |
714 | intsrc.mpc_srcbusirq = bus_irq; /* IRQ */ | |
715 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */ | |
716 | intsrc.mpc_dstirq = pin; /* INTIN# */ | |
717 | ||
718 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n", | |
719 | intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, | |
720 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
721 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq); | |
722 | ||
723 | mp_irqs[mp_irq_entries] = intsrc; | |
724 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
725 | panic("Max # of irq sources exceeded!\n"); | |
1da177e4 LT |
726 | } |
727 | ||
efec3b9a | 728 | void __init mp_config_acpi_legacy_irqs(void) |
1da177e4 LT |
729 | { |
730 | struct mpc_config_intsrc intsrc; | |
efec3b9a AK |
731 | int i = 0; |
732 | int ioapic = -1; | |
1da177e4 LT |
733 | |
734 | /* | |
735 | * Fabricate the legacy ISA bus (bus #31). | |
736 | */ | |
55f05ffa | 737 | set_bit(MP_ISA_BUS, mp_bus_not_pci); |
1da177e4 LT |
738 | |
739 | /* | |
740 | * Locate the IOAPIC that manages the ISA IRQs (0-15). | |
741 | */ | |
742 | ioapic = mp_find_ioapic(0); | |
743 | if (ioapic < 0) | |
744 | return; | |
745 | ||
746 | intsrc.mpc_type = MP_INTSRC; | |
747 | intsrc.mpc_irqflag = 0; /* Conforming */ | |
748 | intsrc.mpc_srcbus = MP_ISA_BUS; | |
749 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; | |
750 | ||
751 | /* | |
752 | * Use the default configuration for the IRQs 0-15. Unless | |
753 | * overridden by (MADT) interrupt source override entries. | |
754 | */ | |
755 | for (i = 0; i < 16; i++) { | |
756 | int idx; | |
757 | ||
758 | for (idx = 0; idx < mp_irq_entries; idx++) { | |
759 | struct mpc_config_intsrc *irq = mp_irqs + idx; | |
760 | ||
761 | /* Do we already have a mapping for this ISA IRQ? */ | |
762 | if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i) | |
763 | break; | |
764 | ||
765 | /* Do we already have a mapping for this IOAPIC pin */ | |
766 | if ((irq->mpc_dstapic == intsrc.mpc_dstapic) && | |
767 | (irq->mpc_dstirq == i)) | |
768 | break; | |
769 | } | |
770 | ||
771 | if (idx != mp_irq_entries) { | |
772 | printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i); | |
773 | continue; /* IRQ already used */ | |
774 | } | |
775 | ||
776 | intsrc.mpc_irqtype = mp_INT; | |
777 | intsrc.mpc_srcbusirq = i; /* Identity mapped */ | |
778 | intsrc.mpc_dstirq = i; | |
779 | ||
780 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, " | |
781 | "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, | |
782 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
783 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, | |
784 | intsrc.mpc_dstirq); | |
785 | ||
786 | mp_irqs[mp_irq_entries] = intsrc; | |
787 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
788 | panic("Max # of irq sources exceeded!\n"); | |
789 | } | |
1da177e4 LT |
790 | } |
791 | ||
701067c4 NP |
792 | #define MAX_GSI_NUM 4096 |
793 | ||
50eca3eb | 794 | int mp_register_gsi(u32 gsi, int triggering, int polarity) |
1da177e4 | 795 | { |
efec3b9a AK |
796 | int ioapic = -1; |
797 | int ioapic_pin = 0; | |
798 | int idx, bit = 0; | |
799 | static int pci_irq = 16; | |
701067c4 NP |
800 | /* |
801 | * Mapping between Global System Interrupts, which | |
802 | * represent all possible interrupts, to the IRQs | |
803 | * assigned to actual devices. | |
804 | */ | |
efec3b9a | 805 | static int gsi_to_irq[MAX_GSI_NUM]; |
1da177e4 LT |
806 | |
807 | if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC) | |
808 | return gsi; | |
809 | ||
1da177e4 LT |
810 | /* Don't set up the ACPI SCI because it's already set up */ |
811 | if (acpi_fadt.sci_int == gsi) | |
812 | return gsi; | |
1da177e4 LT |
813 | |
814 | ioapic = mp_find_ioapic(gsi); | |
815 | if (ioapic < 0) { | |
816 | printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi); | |
817 | return gsi; | |
818 | } | |
819 | ||
820 | ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start; | |
821 | ||
822 | /* | |
823 | * Avoid pin reprogramming. PRTs typically include entries | |
824 | * with redundant pin->gsi mappings (but unique PCI devices); | |
825 | * we only program the IOAPIC on the first. | |
826 | */ | |
827 | bit = ioapic_pin % 32; | |
828 | idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32); | |
829 | if (idx > 3) { | |
830 | printk(KERN_ERR "Invalid reference to IOAPIC pin " | |
831 | "%d-%d\n", mp_ioapic_routing[ioapic].apic_id, | |
832 | ioapic_pin); | |
833 | return gsi; | |
834 | } | |
835 | if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) { | |
836 | Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n", | |
837 | mp_ioapic_routing[ioapic].apic_id, ioapic_pin); | |
701067c4 | 838 | return gsi_to_irq[gsi]; |
1da177e4 LT |
839 | } |
840 | ||
841 | mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit); | |
842 | ||
cb654695 | 843 | if (triggering == ACPI_LEVEL_SENSITIVE) { |
701067c4 NP |
844 | /* |
845 | * For PCI devices assign IRQs in order, avoiding gaps | |
846 | * due to unused I/O APIC pins. | |
847 | */ | |
848 | int irq = gsi; | |
6a1caa21 | 849 | if (gsi < MAX_GSI_NUM) { |
e0c1e9bf KM |
850 | /* |
851 | * Retain the VIA chipset work-around (gsi > 15), but | |
852 | * avoid a problem where the 8254 timer (IRQ0) is setup | |
853 | * via an override (so it's not on pin 0 of the ioapic), | |
854 | * and at the same time, the pin 0 interrupt is a PCI | |
855 | * type. The gsi > 15 test could cause these two pins | |
856 | * to be shared as IRQ0, and they are not shareable. | |
857 | * So test for this condition, and if necessary, avoid | |
858 | * the pin collision. | |
859 | */ | |
860 | if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0)) | |
6a1caa21 | 861 | gsi = pci_irq++; |
6a1caa21 NP |
862 | /* |
863 | * Don't assign IRQ used by ACPI SCI | |
864 | */ | |
865 | if (gsi == acpi_fadt.sci_int) | |
866 | gsi = pci_irq++; | |
6a1caa21 NP |
867 | gsi_to_irq[irq] = gsi; |
868 | } else { | |
869 | printk(KERN_ERR "GSI %u is too high\n", gsi); | |
870 | return gsi; | |
871 | } | |
701067c4 NP |
872 | } |
873 | ||
1da177e4 | 874 | io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, |
50eca3eb BM |
875 | triggering == ACPI_EDGE_SENSITIVE ? 0 : 1, |
876 | polarity == ACPI_ACTIVE_HIGH ? 0 : 1); | |
1da177e4 LT |
877 | return gsi; |
878 | } | |
888ba6c6 | 879 | #endif /*CONFIG_ACPI*/ |