Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. | |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
a8ab26fe | 15 | * This code is released under the GNU General Public License version 2 |
1da177e4 LT |
16 | * |
17 | * Fixes | |
18 | * Felix Koop : NR_CPUS used properly | |
19 | * Jose Renau : Handle single CPU case. | |
20 | * Alan Cox : By repeated request 8) - Total BogoMIP report. | |
21 | * Greg Wright : Fix for kernel stacks panic. | |
22 | * Erich Boleyn : MP v1.4 and additional changes. | |
23 | * Matthias Sattler : Changes for 2.1 kernel map. | |
24 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
25 | * Michael Chastain : Change trampoline.S to gnu as. | |
26 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
27 | * Ingo Molnar : Added APIC timers, based on code | |
28 | * from Jose Renau | |
29 | * Ingo Molnar : various cleanups and rewrites | |
30 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
31 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
32 | * Andi Kleen : Changed for SMP boot into long mode. | |
a8ab26fe AK |
33 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. |
34 | * Andi Kleen : Converted to new state machine. | |
35 | * Various cleanups. | |
36 | * Probably mostly hotplug CPU ready now. | |
76e4f660 | 37 | * Ashok Raj : CPU hotplug support |
1da177e4 LT |
38 | */ |
39 | ||
a8ab26fe | 40 | |
1da177e4 LT |
41 | #include <linux/init.h> |
42 | ||
43 | #include <linux/mm.h> | |
44 | #include <linux/kernel_stat.h> | |
45 | #include <linux/smp_lock.h> | |
1da177e4 LT |
46 | #include <linux/bootmem.h> |
47 | #include <linux/thread_info.h> | |
48 | #include <linux/module.h> | |
49 | ||
50 | #include <linux/delay.h> | |
51 | #include <linux/mc146818rtc.h> | |
52 | #include <asm/mtrr.h> | |
53 | #include <asm/pgalloc.h> | |
54 | #include <asm/desc.h> | |
55 | #include <asm/kdebug.h> | |
56 | #include <asm/tlbflush.h> | |
57 | #include <asm/proto.h> | |
75152114 | 58 | #include <asm/nmi.h> |
9cdd304b AV |
59 | #include <asm/irq.h> |
60 | #include <asm/hw_irq.h> | |
488fc08d | 61 | #include <asm/numa.h> |
1da177e4 LT |
62 | |
63 | /* Number of siblings per CPU package */ | |
64 | int smp_num_siblings = 1; | |
2ee60e17 | 65 | EXPORT_SYMBOL(smp_num_siblings); |
1da177e4 | 66 | |
1e9f28fa SS |
67 | /* Last level cache ID of each logical CPU */ |
68 | u8 cpu_llc_id[NR_CPUS] __cpuinitdata = {[0 ... NR_CPUS-1] = BAD_APICID}; | |
2ee60e17 | 69 | EXPORT_SYMBOL(cpu_llc_id); |
1e9f28fa | 70 | |
1da177e4 | 71 | /* Bitmask of currently online CPUs */ |
6c231b7b | 72 | cpumask_t cpu_online_map __read_mostly; |
1da177e4 | 73 | |
a8ab26fe AK |
74 | EXPORT_SYMBOL(cpu_online_map); |
75 | ||
76 | /* | |
77 | * Private maps to synchronize booting between AP and BP. | |
78 | * Probably not needed anymore, but it makes for easier debugging. -AK | |
79 | */ | |
1da177e4 LT |
80 | cpumask_t cpu_callin_map; |
81 | cpumask_t cpu_callout_map; | |
2ee60e17 | 82 | EXPORT_SYMBOL(cpu_callout_map); |
a8ab26fe AK |
83 | |
84 | cpumask_t cpu_possible_map; | |
85 | EXPORT_SYMBOL(cpu_possible_map); | |
1da177e4 LT |
86 | |
87 | /* Per CPU bogomips and other parameters */ | |
88 | struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned; | |
2ee60e17 | 89 | EXPORT_SYMBOL(cpu_data); |
1da177e4 | 90 | |
a8ab26fe AK |
91 | /* Set when the idlers are all forked */ |
92 | int smp_threads_ready; | |
93 | ||
94605eff | 94 | /* representing HT siblings of each logical CPU */ |
6c231b7b | 95 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; |
2ee60e17 | 96 | EXPORT_SYMBOL(cpu_sibling_map); |
94605eff SS |
97 | |
98 | /* representing HT and core siblings of each logical CPU */ | |
6c231b7b | 99 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly; |
2df9fa36 | 100 | EXPORT_SYMBOL(cpu_core_map); |
1da177e4 LT |
101 | |
102 | /* | |
103 | * Trampoline 80x86 program as an array. | |
104 | */ | |
105 | ||
a8ab26fe AK |
106 | extern unsigned char trampoline_data[]; |
107 | extern unsigned char trampoline_end[]; | |
1da177e4 | 108 | |
76e4f660 AR |
109 | /* State of each CPU */ |
110 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
111 | ||
112 | /* | |
113 | * Store all idle threads, this can be reused instead of creating | |
114 | * a new thread. Also avoids complicated thread destroy functionality | |
115 | * for idle threads. | |
116 | */ | |
117 | struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; | |
118 | ||
119 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) | |
120 | #define set_idle_for_cpu(x,p) (idle_thread_array[(x)] = (p)) | |
121 | ||
1da177e4 LT |
122 | /* |
123 | * Currently trivial. Write the real->protected mode | |
124 | * bootstrap into the page concerned. The caller | |
125 | * has made sure it's suitably aligned. | |
126 | */ | |
127 | ||
a8ab26fe | 128 | static unsigned long __cpuinit setup_trampoline(void) |
1da177e4 LT |
129 | { |
130 | void *tramp = __va(SMP_TRAMPOLINE_BASE); | |
131 | memcpy(tramp, trampoline_data, trampoline_end - trampoline_data); | |
132 | return virt_to_phys(tramp); | |
133 | } | |
134 | ||
135 | /* | |
136 | * The bootstrap kernel entry code has set these up. Save them for | |
137 | * a given CPU | |
138 | */ | |
139 | ||
a8ab26fe | 140 | static void __cpuinit smp_store_cpu_info(int id) |
1da177e4 LT |
141 | { |
142 | struct cpuinfo_x86 *c = cpu_data + id; | |
143 | ||
144 | *c = boot_cpu_data; | |
145 | identify_cpu(c); | |
dda50e71 | 146 | print_cpu_info(c); |
1da177e4 LT |
147 | } |
148 | ||
149 | /* | |
dda50e71 AK |
150 | * New Funky TSC sync algorithm borrowed from IA64. |
151 | * Main advantage is that it doesn't reset the TSCs fully and | |
152 | * in general looks more robust and it works better than my earlier | |
153 | * attempts. I believe it was written by David Mosberger. Some minor | |
154 | * adjustments for x86-64 by me -AK | |
1da177e4 | 155 | * |
dda50e71 AK |
156 | * Original comment reproduced below. |
157 | * | |
158 | * Synchronize TSC of the current (slave) CPU with the TSC of the | |
159 | * MASTER CPU (normally the time-keeper CPU). We use a closed loop to | |
160 | * eliminate the possibility of unaccounted-for errors (such as | |
161 | * getting a machine check in the middle of a calibration step). The | |
162 | * basic idea is for the slave to ask the master what itc value it has | |
163 | * and to read its own itc before and after the master responds. Each | |
164 | * iteration gives us three timestamps: | |
165 | * | |
166 | * slave master | |
167 | * | |
168 | * t0 ---\ | |
169 | * ---\ | |
170 | * ---> | |
171 | * tm | |
172 | * /--- | |
173 | * /--- | |
174 | * t1 <--- | |
175 | * | |
176 | * | |
177 | * The goal is to adjust the slave's TSC such that tm falls exactly | |
178 | * half-way between t0 and t1. If we achieve this, the clocks are | |
179 | * synchronized provided the interconnect between the slave and the | |
180 | * master is symmetric. Even if the interconnect were asymmetric, we | |
181 | * would still know that the synchronization error is smaller than the | |
182 | * roundtrip latency (t0 - t1). | |
183 | * | |
184 | * When the interconnect is quiet and symmetric, this lets us | |
185 | * synchronize the TSC to within one or two cycles. However, we can | |
186 | * only *guarantee* that the synchronization is accurate to within a | |
187 | * round-trip time, which is typically in the range of several hundred | |
188 | * cycles (e.g., ~500 cycles). In practice, this means that the TSCs | |
189 | * are usually almost perfectly synchronized, but we shouldn't assume | |
190 | * that the accuracy is much better than half a micro second or so. | |
191 | * | |
192 | * [there are other errors like the latency of RDTSC and of the | |
193 | * WRMSR. These can also account to hundreds of cycles. So it's | |
194 | * probably worse. It claims 153 cycles error on a dual Opteron, | |
195 | * but I suspect the numbers are actually somewhat worse -AK] | |
1da177e4 LT |
196 | */ |
197 | ||
dda50e71 AK |
198 | #define MASTER 0 |
199 | #define SLAVE (SMP_CACHE_BYTES/8) | |
200 | ||
201 | /* Intentionally don't use cpu_relax() while TSC synchronization | |
202 | because we don't want to go into funky power save modi or cause | |
203 | hypervisors to schedule us away. Going to sleep would likely affect | |
204 | latency and low latency is the primary objective here. -AK */ | |
205 | #define no_cpu_relax() barrier() | |
206 | ||
a8ab26fe | 207 | static __cpuinitdata DEFINE_SPINLOCK(tsc_sync_lock); |
dda50e71 AK |
208 | static volatile __cpuinitdata unsigned long go[SLAVE + 1]; |
209 | static int notscsync __cpuinitdata; | |
210 | ||
211 | #undef DEBUG_TSC_SYNC | |
1da177e4 | 212 | |
dda50e71 AK |
213 | #define NUM_ROUNDS 64 /* magic value */ |
214 | #define NUM_ITERS 5 /* likewise */ | |
1da177e4 | 215 | |
dda50e71 AK |
216 | /* Callback on boot CPU */ |
217 | static __cpuinit void sync_master(void *arg) | |
1da177e4 | 218 | { |
dda50e71 AK |
219 | unsigned long flags, i; |
220 | ||
dda50e71 AK |
221 | go[MASTER] = 0; |
222 | ||
223 | local_irq_save(flags); | |
224 | { | |
225 | for (i = 0; i < NUM_ROUNDS*NUM_ITERS; ++i) { | |
226 | while (!go[MASTER]) | |
227 | no_cpu_relax(); | |
228 | go[MASTER] = 0; | |
229 | rdtscll(go[SLAVE]); | |
230 | } | |
231 | } | |
232 | local_irq_restore(flags); | |
a8ab26fe | 233 | } |
1da177e4 | 234 | |
a8ab26fe | 235 | /* |
dda50e71 AK |
236 | * Return the number of cycles by which our tsc differs from the tsc |
237 | * on the master (time-keeper) CPU. A positive number indicates our | |
238 | * tsc is ahead of the master, negative that it is behind. | |
a8ab26fe | 239 | */ |
dda50e71 AK |
240 | static inline long |
241 | get_delta(long *rt, long *master) | |
a8ab26fe | 242 | { |
dda50e71 AK |
243 | unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0; |
244 | unsigned long tcenter, t0, t1, tm; | |
245 | int i; | |
a8ab26fe | 246 | |
dda50e71 AK |
247 | for (i = 0; i < NUM_ITERS; ++i) { |
248 | rdtscll(t0); | |
249 | go[MASTER] = 1; | |
250 | while (!(tm = go[SLAVE])) | |
251 | no_cpu_relax(); | |
252 | go[SLAVE] = 0; | |
253 | rdtscll(t1); | |
254 | ||
255 | if (t1 - t0 < best_t1 - best_t0) | |
256 | best_t0 = t0, best_t1 = t1, best_tm = tm; | |
257 | } | |
258 | ||
259 | *rt = best_t1 - best_t0; | |
260 | *master = best_tm - best_t0; | |
261 | ||
262 | /* average best_t0 and best_t1 without overflow: */ | |
263 | tcenter = (best_t0/2 + best_t1/2); | |
264 | if (best_t0 % 2 + best_t1 % 2 == 2) | |
265 | ++tcenter; | |
266 | return tcenter - best_tm; | |
1da177e4 LT |
267 | } |
268 | ||
3d483f47 | 269 | static __cpuinit void sync_tsc(unsigned int master) |
1da177e4 | 270 | { |
dda50e71 AK |
271 | int i, done = 0; |
272 | long delta, adj, adjust_latency = 0; | |
273 | unsigned long flags, rt, master_time_stamp, bound; | |
44456d37 | 274 | #ifdef DEBUG_TSC_SYNC |
dda50e71 AK |
275 | static struct syncdebug { |
276 | long rt; /* roundtrip time */ | |
277 | long master; /* master's timestamp */ | |
278 | long diff; /* difference between midpoint and master's timestamp */ | |
279 | long lat; /* estimate of tsc adjustment latency */ | |
280 | } t[NUM_ROUNDS] __cpuinitdata; | |
281 | #endif | |
282 | ||
3d483f47 EB |
283 | printk(KERN_INFO "CPU %d: Syncing TSC to CPU %u.\n", |
284 | smp_processor_id(), master); | |
285 | ||
dda50e71 AK |
286 | go[MASTER] = 1; |
287 | ||
3d483f47 EB |
288 | /* It is dangerous to broadcast IPI as cpus are coming up, |
289 | * as they may not be ready to accept them. So since | |
290 | * we only need to send the ipi to the boot cpu direct | |
291 | * the message, and avoid the race. | |
292 | */ | |
293 | smp_call_function_single(master, sync_master, NULL, 1, 0); | |
dda50e71 AK |
294 | |
295 | while (go[MASTER]) /* wait for master to be ready */ | |
296 | no_cpu_relax(); | |
297 | ||
298 | spin_lock_irqsave(&tsc_sync_lock, flags); | |
299 | { | |
300 | for (i = 0; i < NUM_ROUNDS; ++i) { | |
301 | delta = get_delta(&rt, &master_time_stamp); | |
302 | if (delta == 0) { | |
303 | done = 1; /* let's lock on to this... */ | |
304 | bound = rt; | |
305 | } | |
306 | ||
307 | if (!done) { | |
308 | unsigned long t; | |
309 | if (i > 0) { | |
310 | adjust_latency += -delta; | |
311 | adj = -delta + adjust_latency/4; | |
312 | } else | |
313 | adj = -delta; | |
314 | ||
315 | rdtscll(t); | |
316 | wrmsrl(MSR_IA32_TSC, t + adj); | |
317 | } | |
44456d37 | 318 | #ifdef DEBUG_TSC_SYNC |
dda50e71 AK |
319 | t[i].rt = rt; |
320 | t[i].master = master_time_stamp; | |
321 | t[i].diff = delta; | |
322 | t[i].lat = adjust_latency/4; | |
323 | #endif | |
324 | } | |
325 | } | |
326 | spin_unlock_irqrestore(&tsc_sync_lock, flags); | |
327 | ||
44456d37 | 328 | #ifdef DEBUG_TSC_SYNC |
dda50e71 AK |
329 | for (i = 0; i < NUM_ROUNDS; ++i) |
330 | printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n", | |
331 | t[i].rt, t[i].master, t[i].diff, t[i].lat); | |
332 | #endif | |
333 | ||
334 | printk(KERN_INFO | |
335 | "CPU %d: synchronized TSC with CPU %u (last diff %ld cycles, " | |
336 | "maxerr %lu cycles)\n", | |
3d483f47 | 337 | smp_processor_id(), master, delta, rt); |
a8ab26fe | 338 | } |
1da177e4 | 339 | |
dda50e71 | 340 | static void __cpuinit tsc_sync_wait(void) |
a8ab26fe | 341 | { |
737c5c3b AK |
342 | /* |
343 | * When the CPU has synchronized TSCs assume the BIOS | |
344 | * or the hardware already synced. Otherwise we could | |
345 | * mess up a possible perfect synchronization with a | |
346 | * not-quite-perfect algorithm. | |
347 | */ | |
348 | if (notscsync || !cpu_has_tsc || !unsynchronized_tsc()) | |
a8ab26fe | 349 | return; |
349188f6 | 350 | sync_tsc(0); |
a8ab26fe | 351 | } |
1da177e4 | 352 | |
dda50e71 | 353 | static __init int notscsync_setup(char *s) |
a8ab26fe | 354 | { |
dda50e71 | 355 | notscsync = 1; |
9b41046c | 356 | return 1; |
1da177e4 | 357 | } |
dda50e71 | 358 | __setup("notscsync", notscsync_setup); |
1da177e4 | 359 | |
a8ab26fe | 360 | static atomic_t init_deasserted __cpuinitdata; |
1da177e4 | 361 | |
a8ab26fe AK |
362 | /* |
363 | * Report back to the Boot Processor. | |
364 | * Running on AP. | |
365 | */ | |
366 | void __cpuinit smp_callin(void) | |
1da177e4 LT |
367 | { |
368 | int cpuid, phys_id; | |
369 | unsigned long timeout; | |
370 | ||
371 | /* | |
372 | * If waken up by an INIT in an 82489DX configuration | |
373 | * we may get here before an INIT-deassert IPI reaches | |
374 | * our local APIC. We have to wait for the IPI or we'll | |
375 | * lock up on an APIC access. | |
376 | */ | |
a8ab26fe AK |
377 | while (!atomic_read(&init_deasserted)) |
378 | cpu_relax(); | |
1da177e4 LT |
379 | |
380 | /* | |
381 | * (This works even if the APIC is not enabled.) | |
382 | */ | |
383 | phys_id = GET_APIC_ID(apic_read(APIC_ID)); | |
384 | cpuid = smp_processor_id(); | |
385 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
386 | panic("smp_callin: phys CPU#%d, CPU#%d already present??\n", | |
387 | phys_id, cpuid); | |
388 | } | |
389 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
390 | ||
391 | /* | |
392 | * STARTUP IPIs are fragile beasts as they might sometimes | |
393 | * trigger some glue motherboard logic. Complete APIC bus | |
394 | * silence for 1 second, this overestimates the time the | |
395 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
396 | * by a factor of two. This should be enough. | |
397 | */ | |
398 | ||
399 | /* | |
400 | * Waiting 2s total for startup (udelay is not yet working) | |
401 | */ | |
402 | timeout = jiffies + 2*HZ; | |
403 | while (time_before(jiffies, timeout)) { | |
404 | /* | |
405 | * Has the boot CPU finished it's STARTUP sequence? | |
406 | */ | |
407 | if (cpu_isset(cpuid, cpu_callout_map)) | |
408 | break; | |
a8ab26fe | 409 | cpu_relax(); |
1da177e4 LT |
410 | } |
411 | ||
412 | if (!time_before(jiffies, timeout)) { | |
413 | panic("smp_callin: CPU%d started up but did not get a callout!\n", | |
414 | cpuid); | |
415 | } | |
416 | ||
417 | /* | |
418 | * the boot CPU has finished the init stage and is spinning | |
419 | * on callin_map until we finish. We are free to set up this | |
420 | * CPU, first the APIC. (this is probably redundant on most | |
421 | * boards) | |
422 | */ | |
423 | ||
424 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
425 | setup_local_APIC(); | |
426 | ||
1da177e4 LT |
427 | /* |
428 | * Get our bogomips. | |
b4452218 AK |
429 | * |
430 | * Need to enable IRQs because it can take longer and then | |
431 | * the NMI watchdog might kill us. | |
1da177e4 | 432 | */ |
b4452218 | 433 | local_irq_enable(); |
1da177e4 | 434 | calibrate_delay(); |
b4452218 | 435 | local_irq_disable(); |
1da177e4 LT |
436 | Dprintk("Stack at about %p\n",&cpuid); |
437 | ||
438 | disable_APIC_timer(); | |
439 | ||
440 | /* | |
441 | * Save our processor parameters | |
442 | */ | |
443 | smp_store_cpu_info(cpuid); | |
444 | ||
1da177e4 LT |
445 | /* |
446 | * Allow the master to continue. | |
447 | */ | |
448 | cpu_set(cpuid, cpu_callin_map); | |
1da177e4 LT |
449 | } |
450 | ||
1e9f28fa SS |
451 | /* maps the cpu to the sched domain representing multi-core */ |
452 | cpumask_t cpu_coregroup_map(int cpu) | |
453 | { | |
454 | struct cpuinfo_x86 *c = cpu_data + cpu; | |
455 | /* | |
456 | * For perf, we return last level cache shared map. | |
5c45bf27 | 457 | * And for power savings, we return cpu_core_map |
1e9f28fa | 458 | */ |
5c45bf27 SS |
459 | if (sched_mc_power_savings || sched_smt_power_savings) |
460 | return cpu_core_map[cpu]; | |
461 | else | |
462 | return c->llc_shared_map; | |
1e9f28fa SS |
463 | } |
464 | ||
94605eff SS |
465 | /* representing cpus for which sibling maps can be computed */ |
466 | static cpumask_t cpu_sibling_setup_map; | |
467 | ||
cb0cd8d4 AR |
468 | static inline void set_cpu_sibling_map(int cpu) |
469 | { | |
470 | int i; | |
94605eff SS |
471 | struct cpuinfo_x86 *c = cpu_data; |
472 | ||
473 | cpu_set(cpu, cpu_sibling_setup_map); | |
cb0cd8d4 AR |
474 | |
475 | if (smp_num_siblings > 1) { | |
94605eff | 476 | for_each_cpu_mask(i, cpu_sibling_setup_map) { |
f3fa8ebc RS |
477 | if (c[cpu].phys_proc_id == c[i].phys_proc_id && |
478 | c[cpu].cpu_core_id == c[i].cpu_core_id) { | |
cb0cd8d4 AR |
479 | cpu_set(i, cpu_sibling_map[cpu]); |
480 | cpu_set(cpu, cpu_sibling_map[i]); | |
94605eff SS |
481 | cpu_set(i, cpu_core_map[cpu]); |
482 | cpu_set(cpu, cpu_core_map[i]); | |
1e9f28fa SS |
483 | cpu_set(i, c[cpu].llc_shared_map); |
484 | cpu_set(cpu, c[i].llc_shared_map); | |
cb0cd8d4 AR |
485 | } |
486 | } | |
487 | } else { | |
488 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
489 | } | |
490 | ||
1e9f28fa SS |
491 | cpu_set(cpu, c[cpu].llc_shared_map); |
492 | ||
94605eff | 493 | if (current_cpu_data.x86_max_cores == 1) { |
cb0cd8d4 | 494 | cpu_core_map[cpu] = cpu_sibling_map[cpu]; |
94605eff SS |
495 | c[cpu].booted_cores = 1; |
496 | return; | |
497 | } | |
498 | ||
499 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
1e9f28fa SS |
500 | if (cpu_llc_id[cpu] != BAD_APICID && |
501 | cpu_llc_id[cpu] == cpu_llc_id[i]) { | |
502 | cpu_set(i, c[cpu].llc_shared_map); | |
503 | cpu_set(cpu, c[i].llc_shared_map); | |
504 | } | |
f3fa8ebc | 505 | if (c[cpu].phys_proc_id == c[i].phys_proc_id) { |
94605eff SS |
506 | cpu_set(i, cpu_core_map[cpu]); |
507 | cpu_set(cpu, cpu_core_map[i]); | |
508 | /* | |
509 | * Does this new cpu bringup a new core? | |
510 | */ | |
511 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) { | |
512 | /* | |
513 | * for each core in package, increment | |
514 | * the booted_cores for this new cpu | |
515 | */ | |
516 | if (first_cpu(cpu_sibling_map[i]) == i) | |
517 | c[cpu].booted_cores++; | |
518 | /* | |
519 | * increment the core count for all | |
520 | * the other cpus in this package | |
521 | */ | |
522 | if (i != cpu) | |
523 | c[i].booted_cores++; | |
524 | } else if (i != cpu && !c[cpu].booted_cores) | |
525 | c[cpu].booted_cores = c[i].booted_cores; | |
526 | } | |
cb0cd8d4 AR |
527 | } |
528 | } | |
529 | ||
1da177e4 | 530 | /* |
a8ab26fe | 531 | * Setup code on secondary processor (after comming out of the trampoline) |
1da177e4 | 532 | */ |
a8ab26fe | 533 | void __cpuinit start_secondary(void) |
1da177e4 LT |
534 | { |
535 | /* | |
536 | * Dont put anything before smp_callin(), SMP | |
537 | * booting is too fragile that we want to limit the | |
538 | * things done here to the most necessary things. | |
539 | */ | |
540 | cpu_init(); | |
5bfb5d69 | 541 | preempt_disable(); |
1da177e4 LT |
542 | smp_callin(); |
543 | ||
544 | /* otherwise gcc will move up the smp_processor_id before the cpu_init */ | |
545 | barrier(); | |
546 | ||
1da177e4 LT |
547 | Dprintk("cpu %d: setting up apic clock\n", smp_processor_id()); |
548 | setup_secondary_APIC_clock(); | |
549 | ||
a8ab26fe | 550 | Dprintk("cpu %d: enabling apic timer\n", smp_processor_id()); |
1da177e4 LT |
551 | |
552 | if (nmi_watchdog == NMI_IO_APIC) { | |
553 | disable_8259A_irq(0); | |
554 | enable_NMI_through_LVT0(NULL); | |
555 | enable_8259A_irq(0); | |
556 | } | |
557 | ||
a8ab26fe | 558 | enable_APIC_timer(); |
1da177e4 | 559 | |
cb0cd8d4 AR |
560 | /* |
561 | * The sibling maps must be set before turing the online map on for | |
562 | * this cpu | |
563 | */ | |
564 | set_cpu_sibling_map(smp_processor_id()); | |
565 | ||
1eecd73c AK |
566 | /* |
567 | * Wait for TSC sync to not schedule things before. | |
568 | * We still process interrupts, which could see an inconsistent | |
569 | * time in that window unfortunately. | |
570 | * Do this here because TSC sync has global unprotected state. | |
571 | */ | |
572 | tsc_sync_wait(); | |
573 | ||
884d9e40 AR |
574 | /* |
575 | * We need to hold call_lock, so there is no inconsistency | |
576 | * between the time smp_call_function() determines number of | |
577 | * IPI receipients, and the time when the determination is made | |
578 | * for which cpus receive the IPI in genapic_flat.c. Holding this | |
579 | * lock helps us to not include this cpu in a currently in progress | |
580 | * smp_call_function(). | |
581 | */ | |
582 | lock_ipi_call_lock(); | |
583 | ||
1da177e4 | 584 | /* |
a8ab26fe | 585 | * Allow the master to continue. |
1da177e4 | 586 | */ |
1da177e4 | 587 | cpu_set(smp_processor_id(), cpu_online_map); |
884d9e40 AR |
588 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
589 | unlock_ipi_call_lock(); | |
590 | ||
1da177e4 LT |
591 | cpu_idle(); |
592 | } | |
593 | ||
a8ab26fe | 594 | extern volatile unsigned long init_rsp; |
1da177e4 LT |
595 | extern void (*initial_code)(void); |
596 | ||
44456d37 | 597 | #ifdef APIC_DEBUG |
a8ab26fe | 598 | static void inquire_remote_apic(int apicid) |
1da177e4 LT |
599 | { |
600 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
601 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
602 | int timeout, status; | |
603 | ||
604 | printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid); | |
605 | ||
606 | for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) { | |
607 | printk("... APIC #%d %s: ", apicid, names[i]); | |
608 | ||
609 | /* | |
610 | * Wait for idle. | |
611 | */ | |
612 | apic_wait_icr_idle(); | |
613 | ||
c1507eb2 AK |
614 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); |
615 | apic_write(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
1da177e4 LT |
616 | |
617 | timeout = 0; | |
618 | do { | |
619 | udelay(100); | |
620 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
621 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
622 | ||
623 | switch (status) { | |
624 | case APIC_ICR_RR_VALID: | |
625 | status = apic_read(APIC_RRR); | |
626 | printk("%08x\n", status); | |
627 | break; | |
628 | default: | |
629 | printk("failed\n"); | |
630 | } | |
631 | } | |
632 | } | |
633 | #endif | |
634 | ||
a8ab26fe AK |
635 | /* |
636 | * Kick the secondary to wake up. | |
637 | */ | |
638 | static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int start_rip) | |
1da177e4 LT |
639 | { |
640 | unsigned long send_status = 0, accept_status = 0; | |
641 | int maxlvt, timeout, num_starts, j; | |
642 | ||
643 | Dprintk("Asserting INIT.\n"); | |
644 | ||
645 | /* | |
646 | * Turn INIT on target chip | |
647 | */ | |
c1507eb2 | 648 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
649 | |
650 | /* | |
651 | * Send IPI | |
652 | */ | |
c1507eb2 | 653 | apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT |
1da177e4 LT |
654 | | APIC_DM_INIT); |
655 | ||
656 | Dprintk("Waiting for send to finish...\n"); | |
657 | timeout = 0; | |
658 | do { | |
659 | Dprintk("+"); | |
660 | udelay(100); | |
661 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
662 | } while (send_status && (timeout++ < 1000)); | |
663 | ||
664 | mdelay(10); | |
665 | ||
666 | Dprintk("Deasserting INIT.\n"); | |
667 | ||
668 | /* Target chip */ | |
c1507eb2 | 669 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
670 | |
671 | /* Send IPI */ | |
c1507eb2 | 672 | apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); |
1da177e4 LT |
673 | |
674 | Dprintk("Waiting for send to finish...\n"); | |
675 | timeout = 0; | |
676 | do { | |
677 | Dprintk("+"); | |
678 | udelay(100); | |
679 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
680 | } while (send_status && (timeout++ < 1000)); | |
681 | ||
f2ecfab9 | 682 | mb(); |
1da177e4 LT |
683 | atomic_set(&init_deasserted, 1); |
684 | ||
5a40b7c2 | 685 | num_starts = 2; |
1da177e4 LT |
686 | |
687 | /* | |
688 | * Run STARTUP IPI loop. | |
689 | */ | |
690 | Dprintk("#startup loops: %d.\n", num_starts); | |
691 | ||
692 | maxlvt = get_maxlvt(); | |
693 | ||
694 | for (j = 1; j <= num_starts; j++) { | |
695 | Dprintk("Sending STARTUP #%d.\n",j); | |
1da177e4 LT |
696 | apic_write(APIC_ESR, 0); |
697 | apic_read(APIC_ESR); | |
698 | Dprintk("After apic_write.\n"); | |
699 | ||
700 | /* | |
701 | * STARTUP IPI | |
702 | */ | |
703 | ||
704 | /* Target chip */ | |
c1507eb2 | 705 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
706 | |
707 | /* Boot on the stack */ | |
708 | /* Kick the second */ | |
c1507eb2 | 709 | apic_write(APIC_ICR, APIC_DM_STARTUP | (start_rip >> 12)); |
1da177e4 LT |
710 | |
711 | /* | |
712 | * Give the other CPU some time to accept the IPI. | |
713 | */ | |
714 | udelay(300); | |
715 | ||
716 | Dprintk("Startup point 1.\n"); | |
717 | ||
718 | Dprintk("Waiting for send to finish...\n"); | |
719 | timeout = 0; | |
720 | do { | |
721 | Dprintk("+"); | |
722 | udelay(100); | |
723 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
724 | } while (send_status && (timeout++ < 1000)); | |
725 | ||
726 | /* | |
727 | * Give the other CPU some time to accept the IPI. | |
728 | */ | |
729 | udelay(200); | |
730 | /* | |
731 | * Due to the Pentium erratum 3AP. | |
732 | */ | |
733 | if (maxlvt > 3) { | |
1da177e4 LT |
734 | apic_write(APIC_ESR, 0); |
735 | } | |
736 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
737 | if (send_status || accept_status) | |
738 | break; | |
739 | } | |
740 | Dprintk("After Startup.\n"); | |
741 | ||
742 | if (send_status) | |
743 | printk(KERN_ERR "APIC never delivered???\n"); | |
744 | if (accept_status) | |
745 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
746 | ||
747 | return (send_status | accept_status); | |
748 | } | |
749 | ||
76e4f660 AR |
750 | struct create_idle { |
751 | struct task_struct *idle; | |
752 | struct completion done; | |
753 | int cpu; | |
754 | }; | |
755 | ||
756 | void do_fork_idle(void *_c_idle) | |
757 | { | |
758 | struct create_idle *c_idle = _c_idle; | |
759 | ||
760 | c_idle->idle = fork_idle(c_idle->cpu); | |
761 | complete(&c_idle->done); | |
762 | } | |
763 | ||
a8ab26fe AK |
764 | /* |
765 | * Boot one CPU. | |
766 | */ | |
767 | static int __cpuinit do_boot_cpu(int cpu, int apicid) | |
1da177e4 | 768 | { |
1da177e4 | 769 | unsigned long boot_error; |
a8ab26fe | 770 | int timeout; |
1da177e4 | 771 | unsigned long start_rip; |
76e4f660 AR |
772 | struct create_idle c_idle = { |
773 | .cpu = cpu, | |
774 | .done = COMPLETION_INITIALIZER(c_idle.done), | |
775 | }; | |
776 | DECLARE_WORK(work, do_fork_idle, &c_idle); | |
777 | ||
60be6b9a IM |
778 | lockdep_set_class(&c_idle.done.wait.lock, &waitqueue_lock_key); |
779 | ||
c11efdf9 RT |
780 | /* allocate memory for gdts of secondary cpus. Hotplug is considered */ |
781 | if (!cpu_gdt_descr[cpu].address && | |
782 | !(cpu_gdt_descr[cpu].address = get_zeroed_page(GFP_KERNEL))) { | |
783 | printk(KERN_ERR "Failed to allocate GDT for CPU %d\n", cpu); | |
784 | return -1; | |
785 | } | |
786 | ||
365ba917 RT |
787 | /* Allocate node local memory for AP pdas */ |
788 | if (cpu_pda(cpu) == &boot_cpu_pda[cpu]) { | |
789 | struct x8664_pda *newpda, *pda; | |
790 | int node = cpu_to_node(cpu); | |
791 | pda = cpu_pda(cpu); | |
792 | newpda = kmalloc_node(sizeof (struct x8664_pda), GFP_ATOMIC, | |
793 | node); | |
794 | if (newpda) { | |
795 | memcpy(newpda, pda, sizeof (struct x8664_pda)); | |
796 | cpu_pda(cpu) = newpda; | |
797 | } else | |
798 | printk(KERN_ERR | |
799 | "Could not allocate node local PDA for CPU %d on node %d\n", | |
800 | cpu, node); | |
801 | } | |
802 | ||
803 | ||
d167a518 GH |
804 | alternatives_smp_switch(1); |
805 | ||
76e4f660 AR |
806 | c_idle.idle = get_idle_for_cpu(cpu); |
807 | ||
808 | if (c_idle.idle) { | |
809 | c_idle.idle->thread.rsp = (unsigned long) (((struct pt_regs *) | |
57eafdc2 | 810 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); |
76e4f660 AR |
811 | init_idle(c_idle.idle, cpu); |
812 | goto do_rest; | |
813 | } | |
814 | ||
1da177e4 | 815 | /* |
76e4f660 AR |
816 | * During cold boot process, keventd thread is not spun up yet. |
817 | * When we do cpu hot-add, we create idle threads on the fly, we should | |
818 | * not acquire any attributes from the calling context. Hence the clean | |
819 | * way to create kernel_threads() is to do that from keventd(). | |
820 | * We do the current_is_keventd() due to the fact that ACPI notifier | |
821 | * was also queuing to keventd() and when the caller is already running | |
822 | * in context of keventd(), we would end up with locking up the keventd | |
823 | * thread. | |
1da177e4 | 824 | */ |
76e4f660 AR |
825 | if (!keventd_up() || current_is_keventd()) |
826 | work.func(work.data); | |
827 | else { | |
828 | schedule_work(&work); | |
829 | wait_for_completion(&c_idle.done); | |
830 | } | |
831 | ||
832 | if (IS_ERR(c_idle.idle)) { | |
a8ab26fe | 833 | printk("failed fork for CPU %d\n", cpu); |
76e4f660 | 834 | return PTR_ERR(c_idle.idle); |
a8ab26fe | 835 | } |
1da177e4 | 836 | |
76e4f660 AR |
837 | set_idle_for_cpu(cpu, c_idle.idle); |
838 | ||
839 | do_rest: | |
840 | ||
df79efde | 841 | cpu_pda(cpu)->pcurrent = c_idle.idle; |
1da177e4 LT |
842 | |
843 | start_rip = setup_trampoline(); | |
844 | ||
76e4f660 | 845 | init_rsp = c_idle.idle->thread.rsp; |
1da177e4 LT |
846 | per_cpu(init_tss,cpu).rsp0 = init_rsp; |
847 | initial_code = start_secondary; | |
e4f17c43 | 848 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
1da177e4 | 849 | |
de04f322 AK |
850 | printk(KERN_INFO "Booting processor %d/%d APIC 0x%x\n", cpu, |
851 | cpus_weight(cpu_present_map), | |
852 | apicid); | |
1da177e4 LT |
853 | |
854 | /* | |
855 | * This grunge runs the startup process for | |
856 | * the targeted processor. | |
857 | */ | |
858 | ||
859 | atomic_set(&init_deasserted, 0); | |
860 | ||
861 | Dprintk("Setting warm reset code and vector.\n"); | |
862 | ||
863 | CMOS_WRITE(0xa, 0xf); | |
864 | local_flush_tlb(); | |
865 | Dprintk("1.\n"); | |
866 | *((volatile unsigned short *) phys_to_virt(0x469)) = start_rip >> 4; | |
867 | Dprintk("2.\n"); | |
868 | *((volatile unsigned short *) phys_to_virt(0x467)) = start_rip & 0xf; | |
869 | Dprintk("3.\n"); | |
870 | ||
871 | /* | |
872 | * Be paranoid about clearing APIC errors. | |
873 | */ | |
11a8e778 AK |
874 | apic_write(APIC_ESR, 0); |
875 | apic_read(APIC_ESR); | |
1da177e4 LT |
876 | |
877 | /* | |
878 | * Status is now clean | |
879 | */ | |
880 | boot_error = 0; | |
881 | ||
882 | /* | |
883 | * Starting actual IPI sequence... | |
884 | */ | |
a8ab26fe | 885 | boot_error = wakeup_secondary_via_INIT(apicid, start_rip); |
1da177e4 LT |
886 | |
887 | if (!boot_error) { | |
888 | /* | |
889 | * allow APs to start initializing. | |
890 | */ | |
891 | Dprintk("Before Callout %d.\n", cpu); | |
892 | cpu_set(cpu, cpu_callout_map); | |
893 | Dprintk("After Callout %d.\n", cpu); | |
894 | ||
895 | /* | |
896 | * Wait 5s total for a response | |
897 | */ | |
898 | for (timeout = 0; timeout < 50000; timeout++) { | |
899 | if (cpu_isset(cpu, cpu_callin_map)) | |
900 | break; /* It has booted */ | |
901 | udelay(100); | |
902 | } | |
903 | ||
904 | if (cpu_isset(cpu, cpu_callin_map)) { | |
905 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
1da177e4 LT |
906 | Dprintk("CPU has booted.\n"); |
907 | } else { | |
908 | boot_error = 1; | |
909 | if (*((volatile unsigned char *)phys_to_virt(SMP_TRAMPOLINE_BASE)) | |
910 | == 0xA5) | |
911 | /* trampoline started but...? */ | |
912 | printk("Stuck ??\n"); | |
913 | else | |
914 | /* trampoline code not run */ | |
915 | printk("Not responding.\n"); | |
44456d37 | 916 | #ifdef APIC_DEBUG |
1da177e4 LT |
917 | inquire_remote_apic(apicid); |
918 | #endif | |
919 | } | |
920 | } | |
921 | if (boot_error) { | |
922 | cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */ | |
923 | clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */ | |
488fc08d | 924 | clear_node_cpumask(cpu); /* was set by numa_add_cpu */ |
a8ab26fe AK |
925 | cpu_clear(cpu, cpu_present_map); |
926 | cpu_clear(cpu, cpu_possible_map); | |
1da177e4 LT |
927 | x86_cpu_to_apicid[cpu] = BAD_APICID; |
928 | x86_cpu_to_log_apicid[cpu] = BAD_APICID; | |
a8ab26fe | 929 | return -EIO; |
1da177e4 | 930 | } |
a8ab26fe AK |
931 | |
932 | return 0; | |
1da177e4 LT |
933 | } |
934 | ||
a8ab26fe AK |
935 | cycles_t cacheflush_time; |
936 | unsigned long cache_decay_ticks; | |
937 | ||
1da177e4 | 938 | /* |
a8ab26fe | 939 | * Cleanup possible dangling ends... |
1da177e4 | 940 | */ |
a8ab26fe | 941 | static __cpuinit void smp_cleanup_boot(void) |
1da177e4 | 942 | { |
a8ab26fe AK |
943 | /* |
944 | * Paranoid: Set warm reset code and vector here back | |
945 | * to default values. | |
946 | */ | |
947 | CMOS_WRITE(0, 0xf); | |
1da177e4 | 948 | |
a8ab26fe AK |
949 | /* |
950 | * Reset trampoline flag | |
951 | */ | |
952 | *((volatile int *) phys_to_virt(0x467)) = 0; | |
a8ab26fe AK |
953 | } |
954 | ||
955 | /* | |
956 | * Fall back to non SMP mode after errors. | |
957 | * | |
958 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
959 | */ | |
e6982c67 | 960 | static __init void disable_smp(void) |
a8ab26fe AK |
961 | { |
962 | cpu_present_map = cpumask_of_cpu(0); | |
963 | cpu_possible_map = cpumask_of_cpu(0); | |
964 | if (smp_found_config) | |
965 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id); | |
966 | else | |
967 | phys_cpu_present_map = physid_mask_of_physid(0); | |
968 | cpu_set(0, cpu_sibling_map[0]); | |
969 | cpu_set(0, cpu_core_map[0]); | |
970 | } | |
971 | ||
61b1b2d0 | 972 | #ifdef CONFIG_HOTPLUG_CPU |
420f8f68 AK |
973 | |
974 | int additional_cpus __initdata = -1; | |
975 | ||
61b1b2d0 AK |
976 | /* |
977 | * cpu_possible_map should be static, it cannot change as cpu's | |
978 | * are onlined, or offlined. The reason is per-cpu data-structures | |
979 | * are allocated by some modules at init time, and dont expect to | |
980 | * do this dynamically on cpu arrival/departure. | |
981 | * cpu_present_map on the other hand can change dynamically. | |
982 | * In case when cpu_hotplug is not compiled, then we resort to current | |
983 | * behaviour, which is cpu_possible == cpu_present. | |
61b1b2d0 | 984 | * - Ashok Raj |
420f8f68 AK |
985 | * |
986 | * Three ways to find out the number of additional hotplug CPUs: | |
987 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
420f8f68 | 988 | * - The user can overwrite it with additional_cpus=NUM |
f62a91f6 | 989 | * - Otherwise don't reserve additional CPUs. |
420f8f68 AK |
990 | * We do this because additional CPUs waste a lot of memory. |
991 | * -AK | |
61b1b2d0 | 992 | */ |
421c7ce6 | 993 | __init void prefill_possible_map(void) |
61b1b2d0 AK |
994 | { |
995 | int i; | |
420f8f68 AK |
996 | int possible; |
997 | ||
998 | if (additional_cpus == -1) { | |
f62a91f6 | 999 | if (disabled_cpus > 0) |
420f8f68 | 1000 | additional_cpus = disabled_cpus; |
f62a91f6 AK |
1001 | else |
1002 | additional_cpus = 0; | |
420f8f68 AK |
1003 | } |
1004 | possible = num_processors + additional_cpus; | |
1005 | if (possible > NR_CPUS) | |
1006 | possible = NR_CPUS; | |
1007 | ||
1008 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", | |
1009 | possible, | |
1010 | max_t(int, possible - num_processors, 0)); | |
1011 | ||
1012 | for (i = 0; i < possible; i++) | |
61b1b2d0 AK |
1013 | cpu_set(i, cpu_possible_map); |
1014 | } | |
1015 | #endif | |
1016 | ||
a8ab26fe AK |
1017 | /* |
1018 | * Various sanity checks. | |
1019 | */ | |
e6982c67 | 1020 | static int __init smp_sanity_check(unsigned max_cpus) |
a8ab26fe | 1021 | { |
1da177e4 LT |
1022 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
1023 | printk("weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1024 | hard_smp_processor_id()); | |
1025 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1026 | } | |
1027 | ||
1028 | /* | |
1029 | * If we couldn't find an SMP configuration at boot time, | |
1030 | * get out of here now! | |
1031 | */ | |
1032 | if (!smp_found_config) { | |
1033 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | |
a8ab26fe | 1034 | disable_smp(); |
1da177e4 LT |
1035 | if (APIC_init_uniprocessor()) |
1036 | printk(KERN_NOTICE "Local APIC not detected." | |
1037 | " Using dummy APIC emulation.\n"); | |
a8ab26fe | 1038 | return -1; |
1da177e4 LT |
1039 | } |
1040 | ||
1041 | /* | |
1042 | * Should not be necessary because the MP table should list the boot | |
1043 | * CPU too, but we do it for the sake of robustness anyway. | |
1044 | */ | |
1045 | if (!physid_isset(boot_cpu_id, phys_cpu_present_map)) { | |
1046 | printk(KERN_NOTICE "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1047 | boot_cpu_id); | |
1048 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1049 | } | |
1050 | ||
1051 | /* | |
1052 | * If we couldn't find a local APIC, then get out of here now! | |
1053 | */ | |
11a8e778 | 1054 | if (!cpu_has_apic) { |
1da177e4 LT |
1055 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", |
1056 | boot_cpu_id); | |
1057 | printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n"); | |
a8ab26fe AK |
1058 | nr_ioapics = 0; |
1059 | return -1; | |
1da177e4 LT |
1060 | } |
1061 | ||
1da177e4 LT |
1062 | /* |
1063 | * If SMP should be disabled, then really disable it! | |
1064 | */ | |
1065 | if (!max_cpus) { | |
1da177e4 | 1066 | printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n"); |
a8ab26fe AK |
1067 | nr_ioapics = 0; |
1068 | return -1; | |
1da177e4 LT |
1069 | } |
1070 | ||
a8ab26fe AK |
1071 | return 0; |
1072 | } | |
1da177e4 | 1073 | |
a8ab26fe AK |
1074 | /* |
1075 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1076 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1077 | */ | |
e6982c67 | 1078 | void __init smp_prepare_cpus(unsigned int max_cpus) |
a8ab26fe | 1079 | { |
a8ab26fe AK |
1080 | nmi_watchdog_default(); |
1081 | current_cpu_data = boot_cpu_data; | |
1082 | current_thread_info()->cpu = 0; /* needed? */ | |
94605eff | 1083 | set_cpu_sibling_map(0); |
1da177e4 | 1084 | |
a8ab26fe AK |
1085 | if (smp_sanity_check(max_cpus) < 0) { |
1086 | printk(KERN_INFO "SMP disabled\n"); | |
1087 | disable_smp(); | |
1088 | return; | |
1da177e4 LT |
1089 | } |
1090 | ||
a8ab26fe | 1091 | |
1da177e4 | 1092 | /* |
a8ab26fe | 1093 | * Switch from PIC to APIC mode. |
1da177e4 | 1094 | */ |
a8ab26fe AK |
1095 | connect_bsp_APIC(); |
1096 | setup_local_APIC(); | |
1da177e4 | 1097 | |
a8ab26fe AK |
1098 | if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_id) { |
1099 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", | |
1100 | GET_APIC_ID(apic_read(APIC_ID)), boot_cpu_id); | |
1101 | /* Or can we switch back to PIC here? */ | |
1da177e4 | 1102 | } |
1da177e4 LT |
1103 | |
1104 | /* | |
a8ab26fe | 1105 | * Now start the IO-APICs |
1da177e4 LT |
1106 | */ |
1107 | if (!skip_ioapic_setup && nr_ioapics) | |
1108 | setup_IO_APIC(); | |
1109 | else | |
1110 | nr_ioapics = 0; | |
1111 | ||
1da177e4 | 1112 | /* |
a8ab26fe | 1113 | * Set up local APIC timer on boot CPU. |
1da177e4 | 1114 | */ |
1da177e4 | 1115 | |
a8ab26fe | 1116 | setup_boot_APIC_clock(); |
1da177e4 LT |
1117 | } |
1118 | ||
a8ab26fe AK |
1119 | /* |
1120 | * Early setup to make printk work. | |
1121 | */ | |
1122 | void __init smp_prepare_boot_cpu(void) | |
1da177e4 | 1123 | { |
a8ab26fe AK |
1124 | int me = smp_processor_id(); |
1125 | cpu_set(me, cpu_online_map); | |
1126 | cpu_set(me, cpu_callout_map); | |
884d9e40 | 1127 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1da177e4 LT |
1128 | } |
1129 | ||
a8ab26fe AK |
1130 | /* |
1131 | * Entry point to boot a CPU. | |
a8ab26fe AK |
1132 | */ |
1133 | int __cpuinit __cpu_up(unsigned int cpu) | |
1da177e4 | 1134 | { |
a8ab26fe AK |
1135 | int err; |
1136 | int apicid = cpu_present_to_apicid(cpu); | |
1da177e4 | 1137 | |
a8ab26fe | 1138 | WARN_ON(irqs_disabled()); |
1da177e4 | 1139 | |
a8ab26fe AK |
1140 | Dprintk("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
1141 | ||
1142 | if (apicid == BAD_APICID || apicid == boot_cpu_id || | |
1143 | !physid_isset(apicid, phys_cpu_present_map)) { | |
1144 | printk("__cpu_up: bad cpu %d\n", cpu); | |
1145 | return -EINVAL; | |
1146 | } | |
a8ab26fe | 1147 | |
76e4f660 AR |
1148 | /* |
1149 | * Already booted CPU? | |
1150 | */ | |
1151 | if (cpu_isset(cpu, cpu_callin_map)) { | |
1152 | Dprintk("do_boot_cpu %d Already started\n", cpu); | |
1153 | return -ENOSYS; | |
1154 | } | |
1155 | ||
884d9e40 | 1156 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; |
a8ab26fe AK |
1157 | /* Boot it! */ |
1158 | err = do_boot_cpu(cpu, apicid); | |
1159 | if (err < 0) { | |
a8ab26fe AK |
1160 | Dprintk("do_boot_cpu failed %d\n", err); |
1161 | return err; | |
1da177e4 | 1162 | } |
a8ab26fe | 1163 | |
1da177e4 LT |
1164 | /* Unleash the CPU! */ |
1165 | Dprintk("waiting for cpu %d\n", cpu); | |
1166 | ||
1da177e4 | 1167 | while (!cpu_isset(cpu, cpu_online_map)) |
a8ab26fe | 1168 | cpu_relax(); |
76e4f660 AR |
1169 | err = 0; |
1170 | ||
1171 | return err; | |
1da177e4 LT |
1172 | } |
1173 | ||
a8ab26fe AK |
1174 | /* |
1175 | * Finish the SMP boot. | |
1176 | */ | |
e6982c67 | 1177 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 1178 | { |
a8ab26fe AK |
1179 | smp_cleanup_boot(); |
1180 | ||
1da177e4 LT |
1181 | #ifdef CONFIG_X86_IO_APIC |
1182 | setup_ioapic_dest(); | |
1183 | #endif | |
1da177e4 | 1184 | |
75152114 | 1185 | check_nmi_watchdog(); |
a8ab26fe | 1186 | } |
76e4f660 AR |
1187 | |
1188 | #ifdef CONFIG_HOTPLUG_CPU | |
1189 | ||
cb0cd8d4 | 1190 | static void remove_siblinginfo(int cpu) |
76e4f660 AR |
1191 | { |
1192 | int sibling; | |
94605eff | 1193 | struct cpuinfo_x86 *c = cpu_data; |
76e4f660 | 1194 | |
94605eff SS |
1195 | for_each_cpu_mask(sibling, cpu_core_map[cpu]) { |
1196 | cpu_clear(cpu, cpu_core_map[sibling]); | |
1197 | /* | |
1198 | * last thread sibling in this cpu core going down | |
1199 | */ | |
1200 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) | |
1201 | c[sibling].booted_cores--; | |
1202 | } | |
1203 | ||
76e4f660 AR |
1204 | for_each_cpu_mask(sibling, cpu_sibling_map[cpu]) |
1205 | cpu_clear(cpu, cpu_sibling_map[sibling]); | |
76e4f660 AR |
1206 | cpus_clear(cpu_sibling_map[cpu]); |
1207 | cpus_clear(cpu_core_map[cpu]); | |
f3fa8ebc RS |
1208 | c[cpu].phys_proc_id = 0; |
1209 | c[cpu].cpu_core_id = 0; | |
94605eff | 1210 | cpu_clear(cpu, cpu_sibling_setup_map); |
76e4f660 AR |
1211 | } |
1212 | ||
1213 | void remove_cpu_from_maps(void) | |
1214 | { | |
1215 | int cpu = smp_processor_id(); | |
1216 | ||
1217 | cpu_clear(cpu, cpu_callout_map); | |
1218 | cpu_clear(cpu, cpu_callin_map); | |
1219 | clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */ | |
488fc08d | 1220 | clear_node_cpumask(cpu); |
76e4f660 AR |
1221 | } |
1222 | ||
1223 | int __cpu_disable(void) | |
1224 | { | |
1225 | int cpu = smp_processor_id(); | |
1226 | ||
1227 | /* | |
1228 | * Perhaps use cpufreq to drop frequency, but that could go | |
1229 | * into generic code. | |
1230 | * | |
1231 | * We won't take down the boot processor on i386 due to some | |
1232 | * interrupts only being able to be serviced by the BSP. | |
1233 | * Especially so if we're not using an IOAPIC -zwane | |
1234 | */ | |
1235 | if (cpu == 0) | |
1236 | return -EBUSY; | |
1237 | ||
5e9ef02e | 1238 | clear_local_APIC(); |
76e4f660 AR |
1239 | |
1240 | /* | |
1241 | * HACK: | |
1242 | * Allow any queued timer interrupts to get serviced | |
1243 | * This is only a temporary solution until we cleanup | |
1244 | * fixup_irqs as we do for IA64. | |
1245 | */ | |
1246 | local_irq_enable(); | |
1247 | mdelay(1); | |
1248 | ||
1249 | local_irq_disable(); | |
1250 | remove_siblinginfo(cpu); | |
1251 | ||
1252 | /* It's now safe to remove this processor from the online map */ | |
1253 | cpu_clear(cpu, cpu_online_map); | |
1254 | remove_cpu_from_maps(); | |
1255 | fixup_irqs(cpu_online_map); | |
1256 | return 0; | |
1257 | } | |
1258 | ||
1259 | void __cpu_die(unsigned int cpu) | |
1260 | { | |
1261 | /* We don't do anything here: idle task is faking death itself. */ | |
1262 | unsigned int i; | |
1263 | ||
1264 | for (i = 0; i < 10; i++) { | |
1265 | /* They ack this in play_dead by setting CPU_DEAD */ | |
884d9e40 AR |
1266 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { |
1267 | printk ("CPU %d is now offline\n", cpu); | |
d167a518 GH |
1268 | if (1 == num_online_cpus()) |
1269 | alternatives_smp_switch(0); | |
76e4f660 | 1270 | return; |
884d9e40 | 1271 | } |
ef6e5253 | 1272 | msleep(100); |
76e4f660 AR |
1273 | } |
1274 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); | |
1275 | } | |
1276 | ||
e2c03888 | 1277 | __init int setup_additional_cpus(char *s) |
420f8f68 AK |
1278 | { |
1279 | return get_option(&s, &additional_cpus); | |
1280 | } | |
1281 | __setup("additional_cpus=", setup_additional_cpus); | |
1282 | ||
76e4f660 AR |
1283 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
1284 | ||
1285 | int __cpu_disable(void) | |
1286 | { | |
1287 | return -ENOSYS; | |
1288 | } | |
1289 | ||
1290 | void __cpu_die(unsigned int cpu) | |
1291 | { | |
1292 | /* We said "no" in __cpu_disable */ | |
1293 | BUG(); | |
1294 | } | |
1295 | #endif /* CONFIG_HOTPLUG_CPU */ |