Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * ahci.c - AHCI SATA support | |
3 | * | |
af36d7f0 JG |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * AHCI hardware documentation: | |
1da177e4 | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
af36d7f0 | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
1da177e4 LT |
32 | * |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
87507cfd | 42 | #include <linux/dma-mapping.h> |
a9524a76 | 43 | #include <linux/device.h> |
edc93052 | 44 | #include <linux/dmi.h> |
1da177e4 | 45 | #include <scsi/scsi_host.h> |
193515d5 | 46 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 47 | #include <linux/libata.h> |
1da177e4 LT |
48 | |
49 | #define DRV_NAME "ahci" | |
7d50b60b | 50 | #define DRV_VERSION "3.0" |
1da177e4 | 51 | |
31556594 KCA |
52 | static int ahci_enable_alpm(struct ata_port *ap, |
53 | enum link_pm policy); | |
54 | static void ahci_disable_alpm(struct ata_port *ap); | |
1da177e4 LT |
55 | |
56 | enum { | |
57 | AHCI_PCI_BAR = 5, | |
648a88be | 58 | AHCI_MAX_PORTS = 32, |
1da177e4 LT |
59 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
60 | AHCI_DMA_BOUNDARY = 0xffffffff, | |
be5d8218 | 61 | AHCI_USE_CLUSTERING = 1, |
12fad3f9 | 62 | AHCI_MAX_CMDS = 32, |
dd410ff1 | 63 | AHCI_CMD_SZ = 32, |
12fad3f9 | 64 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
1da177e4 | 65 | AHCI_RX_FIS_SZ = 256, |
a0ea7328 | 66 | AHCI_CMD_TBL_CDB = 0x40, |
dd410ff1 TH |
67 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
68 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), | |
69 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, | |
70 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + | |
1da177e4 LT |
71 | AHCI_RX_FIS_SZ, |
72 | AHCI_IRQ_ON_SG = (1 << 31), | |
73 | AHCI_CMD_ATAPI = (1 << 5), | |
74 | AHCI_CMD_WRITE = (1 << 6), | |
4b10e559 | 75 | AHCI_CMD_PREFETCH = (1 << 7), |
22b49985 TH |
76 | AHCI_CMD_RESET = (1 << 8), |
77 | AHCI_CMD_CLR_BUSY = (1 << 10), | |
1da177e4 LT |
78 | |
79 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ | |
0291f95f | 80 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
78cd52d0 | 81 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
1da177e4 LT |
82 | |
83 | board_ahci = 0, | |
7a234aff TH |
84 | board_ahci_vt8251 = 1, |
85 | board_ahci_ign_iferr = 2, | |
86 | board_ahci_sb600 = 3, | |
87 | board_ahci_mv = 4, | |
1da177e4 LT |
88 | |
89 | /* global controller registers */ | |
90 | HOST_CAP = 0x00, /* host capabilities */ | |
91 | HOST_CTL = 0x04, /* global host control */ | |
92 | HOST_IRQ_STAT = 0x08, /* interrupt status */ | |
93 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ | |
94 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ | |
95 | ||
96 | /* HOST_CTL bits */ | |
97 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ | |
98 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ | |
99 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ | |
100 | ||
101 | /* HOST_CAP bits */ | |
0be0aa98 | 102 | HOST_CAP_SSC = (1 << 14), /* Slumber capable */ |
7d50b60b | 103 | HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ |
22b49985 | 104 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
31556594 | 105 | HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ |
0be0aa98 | 106 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
203ef6c4 | 107 | HOST_CAP_SNTF = (1 << 29), /* SNotification register */ |
979db803 | 108 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
dd410ff1 | 109 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
1da177e4 LT |
110 | |
111 | /* registers for each SATA port */ | |
112 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ | |
113 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ | |
114 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ | |
115 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ | |
116 | PORT_IRQ_STAT = 0x10, /* interrupt status */ | |
117 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ | |
118 | PORT_CMD = 0x18, /* port command */ | |
119 | PORT_TFDATA = 0x20, /* taskfile data */ | |
120 | PORT_SIG = 0x24, /* device TF signature */ | |
121 | PORT_CMD_ISSUE = 0x38, /* command issue */ | |
1da177e4 LT |
122 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ |
123 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ | |
124 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ | |
125 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ | |
203ef6c4 | 126 | PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ |
1da177e4 LT |
127 | |
128 | /* PORT_IRQ_{STAT,MASK} bits */ | |
129 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ | |
130 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ | |
131 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ | |
132 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ | |
133 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ | |
134 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ | |
135 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ | |
136 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ | |
137 | ||
138 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ | |
139 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ | |
140 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ | |
141 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ | |
142 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ | |
143 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ | |
144 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ | |
145 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ | |
146 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ | |
147 | ||
78cd52d0 TH |
148 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
149 | PORT_IRQ_IF_ERR | | |
150 | PORT_IRQ_CONNECT | | |
4296971d | 151 | PORT_IRQ_PHYRDY | |
7d50b60b TH |
152 | PORT_IRQ_UNK_FIS | |
153 | PORT_IRQ_BAD_PMP, | |
78cd52d0 TH |
154 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | |
155 | PORT_IRQ_TF_ERR | | |
156 | PORT_IRQ_HBUS_DATA_ERR, | |
157 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | | |
158 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | | |
159 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, | |
1da177e4 LT |
160 | |
161 | /* PORT_CMD bits */ | |
31556594 KCA |
162 | PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ |
163 | PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ | |
02eaa666 | 164 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
7d50b60b | 165 | PORT_CMD_PMP = (1 << 17), /* PMP attached */ |
1da177e4 LT |
166 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
167 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ | |
168 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ | |
22b49985 | 169 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
1da177e4 LT |
170 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
171 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ | |
172 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ | |
173 | ||
0be0aa98 | 174 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
1da177e4 LT |
175 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
176 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ | |
177 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ | |
4b0060f4 | 178 | |
417a1a6d TH |
179 | /* hpriv->flags bits */ |
180 | AHCI_HFLAG_NO_NCQ = (1 << 0), | |
181 | AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ | |
182 | AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ | |
183 | AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ | |
184 | AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ | |
185 | AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ | |
6949b914 | 186 | AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ |
31556594 | 187 | AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */ |
417a1a6d | 188 | |
bf2af2a2 | 189 | /* ap->flags bits */ |
1188c0d8 TH |
190 | |
191 | AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
192 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
31556594 KCA |
193 | ATA_FLAG_ACPI_SATA | ATA_FLAG_AN | |
194 | ATA_FLAG_IPM, | |
0c88758b | 195 | AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY, |
c4f7792c TH |
196 | |
197 | ICH_MAP = 0x90, /* ICH MAP register */ | |
1da177e4 LT |
198 | }; |
199 | ||
200 | struct ahci_cmd_hdr { | |
201 | u32 opts; | |
202 | u32 status; | |
203 | u32 tbl_addr; | |
204 | u32 tbl_addr_hi; | |
205 | u32 reserved[4]; | |
206 | }; | |
207 | ||
208 | struct ahci_sg { | |
209 | u32 addr; | |
210 | u32 addr_hi; | |
211 | u32 reserved; | |
212 | u32 flags_size; | |
213 | }; | |
214 | ||
215 | struct ahci_host_priv { | |
417a1a6d | 216 | unsigned int flags; /* AHCI_HFLAG_* */ |
d447df14 TH |
217 | u32 cap; /* cap to use */ |
218 | u32 port_map; /* port map to use */ | |
219 | u32 saved_cap; /* saved initial cap */ | |
220 | u32 saved_port_map; /* saved initial port_map */ | |
1da177e4 LT |
221 | }; |
222 | ||
223 | struct ahci_port_priv { | |
7d50b60b | 224 | struct ata_link *active_link; |
1da177e4 LT |
225 | struct ahci_cmd_hdr *cmd_slot; |
226 | dma_addr_t cmd_slot_dma; | |
227 | void *cmd_tbl; | |
228 | dma_addr_t cmd_tbl_dma; | |
1da177e4 LT |
229 | void *rx_fis; |
230 | dma_addr_t rx_fis_dma; | |
0291f95f | 231 | /* for NCQ spurious interrupt analysis */ |
0291f95f TH |
232 | unsigned int ncq_saw_d2h:1; |
233 | unsigned int ncq_saw_dmas:1; | |
afb2d552 | 234 | unsigned int ncq_saw_sdb:1; |
a7384925 | 235 | u32 intr_mask; /* interrupts to enable */ |
1da177e4 LT |
236 | }; |
237 | ||
da3dbb17 TH |
238 | static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); |
239 | static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); | |
2dcb407e | 240 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
9a3d9eb0 | 241 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
1da177e4 | 242 | static void ahci_irq_clear(struct ata_port *ap); |
1da177e4 LT |
243 | static int ahci_port_start(struct ata_port *ap); |
244 | static void ahci_port_stop(struct ata_port *ap); | |
1da177e4 LT |
245 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
246 | static void ahci_qc_prep(struct ata_queued_cmd *qc); | |
247 | static u8 ahci_check_status(struct ata_port *ap); | |
78cd52d0 TH |
248 | static void ahci_freeze(struct ata_port *ap); |
249 | static void ahci_thaw(struct ata_port *ap); | |
7d50b60b TH |
250 | static void ahci_pmp_attach(struct ata_port *ap); |
251 | static void ahci_pmp_detach(struct ata_port *ap); | |
78cd52d0 | 252 | static void ahci_error_handler(struct ata_port *ap); |
ad616ffb | 253 | static void ahci_vt8251_error_handler(struct ata_port *ap); |
edc93052 | 254 | static void ahci_p5wdh_error_handler(struct ata_port *ap); |
78cd52d0 | 255 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); |
df69c9c5 | 256 | static int ahci_port_resume(struct ata_port *ap); |
dab632e8 JG |
257 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl); |
258 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, | |
259 | u32 opts); | |
438ac6d5 | 260 | #ifdef CONFIG_PM |
c1332875 | 261 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); |
c1332875 TH |
262 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
263 | static int ahci_pci_device_resume(struct pci_dev *pdev); | |
438ac6d5 | 264 | #endif |
1da177e4 | 265 | |
31556594 KCA |
266 | static struct class_device_attribute *ahci_shost_attrs[] = { |
267 | &class_device_attr_link_power_management_policy, | |
268 | NULL | |
269 | }; | |
270 | ||
193515d5 | 271 | static struct scsi_host_template ahci_sht = { |
1da177e4 LT |
272 | .module = THIS_MODULE, |
273 | .name = DRV_NAME, | |
274 | .ioctl = ata_scsi_ioctl, | |
275 | .queuecommand = ata_scsi_queuecmd, | |
12fad3f9 TH |
276 | .change_queue_depth = ata_scsi_change_queue_depth, |
277 | .can_queue = AHCI_MAX_CMDS - 1, | |
1da177e4 LT |
278 | .this_id = ATA_SHT_THIS_ID, |
279 | .sg_tablesize = AHCI_MAX_SG, | |
1da177e4 LT |
280 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
281 | .emulated = ATA_SHT_EMULATED, | |
282 | .use_clustering = AHCI_USE_CLUSTERING, | |
283 | .proc_name = DRV_NAME, | |
284 | .dma_boundary = AHCI_DMA_BOUNDARY, | |
285 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 286 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 287 | .bios_param = ata_std_bios_param, |
31556594 | 288 | .shost_attrs = ahci_shost_attrs, |
1da177e4 LT |
289 | }; |
290 | ||
057ace5e | 291 | static const struct ata_port_operations ahci_ops = { |
1da177e4 LT |
292 | .check_status = ahci_check_status, |
293 | .check_altstatus = ahci_check_status, | |
1da177e4 LT |
294 | .dev_select = ata_noop_dev_select, |
295 | ||
296 | .tf_read = ahci_tf_read, | |
297 | ||
7d50b60b | 298 | .qc_defer = sata_pmp_qc_defer_cmd_switch, |
1da177e4 LT |
299 | .qc_prep = ahci_qc_prep, |
300 | .qc_issue = ahci_qc_issue, | |
301 | ||
1da177e4 LT |
302 | .irq_clear = ahci_irq_clear, |
303 | ||
304 | .scr_read = ahci_scr_read, | |
305 | .scr_write = ahci_scr_write, | |
306 | ||
78cd52d0 TH |
307 | .freeze = ahci_freeze, |
308 | .thaw = ahci_thaw, | |
309 | ||
310 | .error_handler = ahci_error_handler, | |
311 | .post_internal_cmd = ahci_post_internal_cmd, | |
312 | ||
7d50b60b TH |
313 | .pmp_attach = ahci_pmp_attach, |
314 | .pmp_detach = ahci_pmp_detach, | |
7d50b60b | 315 | |
438ac6d5 | 316 | #ifdef CONFIG_PM |
c1332875 TH |
317 | .port_suspend = ahci_port_suspend, |
318 | .port_resume = ahci_port_resume, | |
438ac6d5 | 319 | #endif |
31556594 KCA |
320 | .enable_pm = ahci_enable_alpm, |
321 | .disable_pm = ahci_disable_alpm, | |
c1332875 | 322 | |
1da177e4 LT |
323 | .port_start = ahci_port_start, |
324 | .port_stop = ahci_port_stop, | |
1da177e4 LT |
325 | }; |
326 | ||
ad616ffb | 327 | static const struct ata_port_operations ahci_vt8251_ops = { |
ad616ffb TH |
328 | .check_status = ahci_check_status, |
329 | .check_altstatus = ahci_check_status, | |
330 | .dev_select = ata_noop_dev_select, | |
331 | ||
332 | .tf_read = ahci_tf_read, | |
333 | ||
7d50b60b | 334 | .qc_defer = sata_pmp_qc_defer_cmd_switch, |
ad616ffb TH |
335 | .qc_prep = ahci_qc_prep, |
336 | .qc_issue = ahci_qc_issue, | |
337 | ||
ad616ffb TH |
338 | .irq_clear = ahci_irq_clear, |
339 | ||
340 | .scr_read = ahci_scr_read, | |
341 | .scr_write = ahci_scr_write, | |
342 | ||
343 | .freeze = ahci_freeze, | |
344 | .thaw = ahci_thaw, | |
345 | ||
346 | .error_handler = ahci_vt8251_error_handler, | |
347 | .post_internal_cmd = ahci_post_internal_cmd, | |
348 | ||
7d50b60b TH |
349 | .pmp_attach = ahci_pmp_attach, |
350 | .pmp_detach = ahci_pmp_detach, | |
7d50b60b | 351 | |
438ac6d5 | 352 | #ifdef CONFIG_PM |
ad616ffb TH |
353 | .port_suspend = ahci_port_suspend, |
354 | .port_resume = ahci_port_resume, | |
438ac6d5 | 355 | #endif |
ad616ffb TH |
356 | |
357 | .port_start = ahci_port_start, | |
358 | .port_stop = ahci_port_stop, | |
359 | }; | |
360 | ||
edc93052 TH |
361 | static const struct ata_port_operations ahci_p5wdh_ops = { |
362 | .check_status = ahci_check_status, | |
363 | .check_altstatus = ahci_check_status, | |
364 | .dev_select = ata_noop_dev_select, | |
365 | ||
366 | .tf_read = ahci_tf_read, | |
367 | ||
368 | .qc_defer = sata_pmp_qc_defer_cmd_switch, | |
369 | .qc_prep = ahci_qc_prep, | |
370 | .qc_issue = ahci_qc_issue, | |
371 | ||
372 | .irq_clear = ahci_irq_clear, | |
373 | ||
374 | .scr_read = ahci_scr_read, | |
375 | .scr_write = ahci_scr_write, | |
376 | ||
377 | .freeze = ahci_freeze, | |
378 | .thaw = ahci_thaw, | |
379 | ||
380 | .error_handler = ahci_p5wdh_error_handler, | |
381 | .post_internal_cmd = ahci_post_internal_cmd, | |
382 | ||
383 | .pmp_attach = ahci_pmp_attach, | |
384 | .pmp_detach = ahci_pmp_detach, | |
385 | ||
386 | #ifdef CONFIG_PM | |
387 | .port_suspend = ahci_port_suspend, | |
388 | .port_resume = ahci_port_resume, | |
389 | #endif | |
390 | ||
391 | .port_start = ahci_port_start, | |
392 | .port_stop = ahci_port_stop, | |
393 | }; | |
394 | ||
417a1a6d TH |
395 | #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) |
396 | ||
98ac62de | 397 | static const struct ata_port_info ahci_port_info[] = { |
1da177e4 LT |
398 | /* board_ahci */ |
399 | { | |
1188c0d8 | 400 | .flags = AHCI_FLAG_COMMON, |
0c88758b | 401 | .link_flags = AHCI_LFLAG_COMMON, |
7da79312 | 402 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 403 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
404 | .port_ops = &ahci_ops, |
405 | }, | |
bf2af2a2 BJ |
406 | /* board_ahci_vt8251 */ |
407 | { | |
6949b914 | 408 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), |
417a1a6d | 409 | .flags = AHCI_FLAG_COMMON, |
0c88758b | 410 | .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME, |
bf2af2a2 | 411 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 412 | .udma_mask = ATA_UDMA6, |
ad616ffb | 413 | .port_ops = &ahci_vt8251_ops, |
bf2af2a2 | 414 | }, |
41669553 TH |
415 | /* board_ahci_ign_iferr */ |
416 | { | |
417a1a6d TH |
417 | AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), |
418 | .flags = AHCI_FLAG_COMMON, | |
0c88758b | 419 | .link_flags = AHCI_LFLAG_COMMON, |
41669553 | 420 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 421 | .udma_mask = ATA_UDMA6, |
41669553 TH |
422 | .port_ops = &ahci_ops, |
423 | }, | |
55a61604 CH |
424 | /* board_ahci_sb600 */ |
425 | { | |
417a1a6d | 426 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | |
6949b914 | 427 | AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP), |
417a1a6d | 428 | .flags = AHCI_FLAG_COMMON, |
0c88758b | 429 | .link_flags = AHCI_LFLAG_COMMON, |
55a61604 | 430 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 431 | .udma_mask = ATA_UDMA6, |
55a61604 CH |
432 | .port_ops = &ahci_ops, |
433 | }, | |
cd70c266 JG |
434 | /* board_ahci_mv */ |
435 | { | |
417a1a6d TH |
436 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | |
437 | AHCI_HFLAG_MV_PATA), | |
cd70c266 | 438 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
417a1a6d | 439 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA, |
0c88758b | 440 | .link_flags = AHCI_LFLAG_COMMON, |
cd70c266 JG |
441 | .pio_mask = 0x1f, /* pio0-4 */ |
442 | .udma_mask = ATA_UDMA6, | |
443 | .port_ops = &ahci_ops, | |
444 | }, | |
1da177e4 LT |
445 | }; |
446 | ||
3b7d697d | 447 | static const struct pci_device_id ahci_pci_tbl[] = { |
fe7fa31a | 448 | /* Intel */ |
54bb3a94 JG |
449 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
450 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ | |
451 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ | |
452 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ | |
453 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ | |
82490c09 | 454 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
54bb3a94 JG |
455 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
456 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ | |
457 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ | |
458 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ | |
7a234aff TH |
459 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ |
460 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */ | |
461 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ | |
462 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ | |
463 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ | |
464 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ | |
465 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ | |
466 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ | |
467 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ | |
468 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ | |
469 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ | |
470 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ | |
471 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ | |
472 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ | |
473 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ | |
474 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ | |
475 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ | |
d4155e6f JG |
476 | { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ |
477 | { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ | |
fe7fa31a | 478 | |
e34bb370 TH |
479 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
480 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
481 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, | |
fe7fa31a JG |
482 | |
483 | /* ATI */ | |
c65ec1c2 | 484 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
c69c0892 | 485 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */ |
486 | { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */ | |
487 | { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */ | |
488 | { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */ | |
489 | { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */ | |
490 | { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */ | |
fe7fa31a JG |
491 | |
492 | /* VIA */ | |
54bb3a94 | 493 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
bf335542 | 494 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
fe7fa31a JG |
495 | |
496 | /* NVIDIA */ | |
54bb3a94 JG |
497 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */ |
498 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */ | |
499 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */ | |
500 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */ | |
6fbf5ba4 PC |
501 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */ |
502 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */ | |
503 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */ | |
504 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */ | |
505 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */ | |
506 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */ | |
507 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */ | |
508 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */ | |
895663cd PC |
509 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */ |
510 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */ | |
511 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */ | |
512 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */ | |
513 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */ | |
514 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */ | |
515 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */ | |
516 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */ | |
0522b286 PC |
517 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */ |
518 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */ | |
519 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */ | |
520 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */ | |
521 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */ | |
522 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */ | |
523 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */ | |
524 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */ | |
525 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */ | |
526 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */ | |
527 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */ | |
528 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */ | |
529 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */ | |
530 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */ | |
531 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */ | |
532 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */ | |
533 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */ | |
534 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */ | |
535 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */ | |
536 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */ | |
537 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */ | |
538 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */ | |
539 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */ | |
540 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */ | |
6ba86958 | 541 | { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */ |
542 | { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */ | |
543 | { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */ | |
544 | { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */ | |
7100819f PC |
545 | { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */ |
546 | { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */ | |
547 | { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */ | |
548 | { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */ | |
549 | { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */ | |
550 | { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */ | |
551 | { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */ | |
552 | { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */ | |
fe7fa31a | 553 | |
95916edd | 554 | /* SiS */ |
54bb3a94 JG |
555 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
556 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */ | |
557 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ | |
95916edd | 558 | |
cd70c266 JG |
559 | /* Marvell */ |
560 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ | |
561 | ||
415ae2b5 JG |
562 | /* Generic, PCI class code for AHCI */ |
563 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
c9f89475 | 564 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
415ae2b5 | 565 | |
1da177e4 LT |
566 | { } /* terminate list */ |
567 | }; | |
568 | ||
569 | ||
570 | static struct pci_driver ahci_pci_driver = { | |
571 | .name = DRV_NAME, | |
572 | .id_table = ahci_pci_tbl, | |
573 | .probe = ahci_init_one, | |
24dc5f33 | 574 | .remove = ata_pci_remove_one, |
438ac6d5 | 575 | #ifdef CONFIG_PM |
c1332875 TH |
576 | .suspend = ahci_pci_device_suspend, |
577 | .resume = ahci_pci_device_resume, | |
438ac6d5 | 578 | #endif |
1da177e4 LT |
579 | }; |
580 | ||
581 | ||
98fa4b60 TH |
582 | static inline int ahci_nr_ports(u32 cap) |
583 | { | |
584 | return (cap & 0x1f) + 1; | |
585 | } | |
586 | ||
dab632e8 JG |
587 | static inline void __iomem *__ahci_port_base(struct ata_host *host, |
588 | unsigned int port_no) | |
1da177e4 | 589 | { |
dab632e8 | 590 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
4447d351 | 591 | |
dab632e8 JG |
592 | return mmio + 0x100 + (port_no * 0x80); |
593 | } | |
594 | ||
595 | static inline void __iomem *ahci_port_base(struct ata_port *ap) | |
596 | { | |
597 | return __ahci_port_base(ap->host, ap->port_no); | |
1da177e4 LT |
598 | } |
599 | ||
d447df14 TH |
600 | /** |
601 | * ahci_save_initial_config - Save and fixup initial config values | |
4447d351 | 602 | * @pdev: target PCI device |
4447d351 | 603 | * @hpriv: host private area to store config values |
d447df14 TH |
604 | * |
605 | * Some registers containing configuration info might be setup by | |
606 | * BIOS and might be cleared on reset. This function saves the | |
607 | * initial values of those registers into @hpriv such that they | |
608 | * can be restored after controller reset. | |
609 | * | |
610 | * If inconsistent, config values are fixed up by this function. | |
611 | * | |
612 | * LOCKING: | |
613 | * None. | |
614 | */ | |
4447d351 | 615 | static void ahci_save_initial_config(struct pci_dev *pdev, |
4447d351 | 616 | struct ahci_host_priv *hpriv) |
d447df14 | 617 | { |
4447d351 | 618 | void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; |
d447df14 | 619 | u32 cap, port_map; |
17199b18 | 620 | int i; |
d447df14 TH |
621 | |
622 | /* Values prefixed with saved_ are written back to host after | |
623 | * reset. Values without are used for driver operation. | |
624 | */ | |
625 | hpriv->saved_cap = cap = readl(mmio + HOST_CAP); | |
626 | hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); | |
627 | ||
274c1fde | 628 | /* some chips have errata preventing 64bit use */ |
417a1a6d | 629 | if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { |
c7a42156 TH |
630 | dev_printk(KERN_INFO, &pdev->dev, |
631 | "controller can't do 64bit DMA, forcing 32bit\n"); | |
632 | cap &= ~HOST_CAP_64; | |
633 | } | |
634 | ||
417a1a6d | 635 | if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { |
274c1fde TH |
636 | dev_printk(KERN_INFO, &pdev->dev, |
637 | "controller can't do NCQ, turning off CAP_NCQ\n"); | |
638 | cap &= ~HOST_CAP_NCQ; | |
639 | } | |
640 | ||
6949b914 TH |
641 | if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { |
642 | dev_printk(KERN_INFO, &pdev->dev, | |
643 | "controller can't do PMP, turning off CAP_PMP\n"); | |
644 | cap &= ~HOST_CAP_PMP; | |
645 | } | |
646 | ||
cd70c266 JG |
647 | /* |
648 | * Temporary Marvell 6145 hack: PATA port presence | |
649 | * is asserted through the standard AHCI port | |
650 | * presence register, as bit 4 (counting from 0) | |
651 | */ | |
417a1a6d | 652 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
cd70c266 JG |
653 | dev_printk(KERN_ERR, &pdev->dev, |
654 | "MV_AHCI HACK: port_map %x -> %x\n", | |
655 | hpriv->port_map, | |
656 | hpriv->port_map & 0xf); | |
657 | ||
658 | port_map &= 0xf; | |
659 | } | |
660 | ||
17199b18 | 661 | /* cross check port_map and cap.n_ports */ |
7a234aff | 662 | if (port_map) { |
17199b18 TH |
663 | u32 tmp_port_map = port_map; |
664 | int n_ports = ahci_nr_ports(cap); | |
665 | ||
666 | for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) { | |
667 | if (tmp_port_map & (1 << i)) { | |
668 | n_ports--; | |
669 | tmp_port_map &= ~(1 << i); | |
670 | } | |
671 | } | |
672 | ||
7a234aff TH |
673 | /* If n_ports and port_map are inconsistent, whine and |
674 | * clear port_map and let it be generated from n_ports. | |
17199b18 | 675 | */ |
7a234aff | 676 | if (n_ports || tmp_port_map) { |
4447d351 | 677 | dev_printk(KERN_WARNING, &pdev->dev, |
17199b18 | 678 | "nr_ports (%u) and implemented port map " |
7a234aff | 679 | "(0x%x) don't match, using nr_ports\n", |
17199b18 | 680 | ahci_nr_ports(cap), port_map); |
7a234aff TH |
681 | port_map = 0; |
682 | } | |
683 | } | |
684 | ||
685 | /* fabricate port_map from cap.nr_ports */ | |
686 | if (!port_map) { | |
17199b18 | 687 | port_map = (1 << ahci_nr_ports(cap)) - 1; |
7a234aff TH |
688 | dev_printk(KERN_WARNING, &pdev->dev, |
689 | "forcing PORTS_IMPL to 0x%x\n", port_map); | |
690 | ||
691 | /* write the fixed up value to the PI register */ | |
692 | hpriv->saved_port_map = port_map; | |
17199b18 TH |
693 | } |
694 | ||
d447df14 TH |
695 | /* record values to use during operation */ |
696 | hpriv->cap = cap; | |
697 | hpriv->port_map = port_map; | |
698 | } | |
699 | ||
700 | /** | |
701 | * ahci_restore_initial_config - Restore initial config | |
4447d351 | 702 | * @host: target ATA host |
d447df14 TH |
703 | * |
704 | * Restore initial config stored by ahci_save_initial_config(). | |
705 | * | |
706 | * LOCKING: | |
707 | * None. | |
708 | */ | |
4447d351 | 709 | static void ahci_restore_initial_config(struct ata_host *host) |
d447df14 | 710 | { |
4447d351 TH |
711 | struct ahci_host_priv *hpriv = host->private_data; |
712 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
713 | ||
d447df14 TH |
714 | writel(hpriv->saved_cap, mmio + HOST_CAP); |
715 | writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); | |
716 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ | |
717 | } | |
718 | ||
203ef6c4 | 719 | static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) |
1da177e4 | 720 | { |
203ef6c4 TH |
721 | static const int offset[] = { |
722 | [SCR_STATUS] = PORT_SCR_STAT, | |
723 | [SCR_CONTROL] = PORT_SCR_CTL, | |
724 | [SCR_ERROR] = PORT_SCR_ERR, | |
725 | [SCR_ACTIVE] = PORT_SCR_ACT, | |
726 | [SCR_NOTIFICATION] = PORT_SCR_NTF, | |
727 | }; | |
728 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
1da177e4 | 729 | |
203ef6c4 TH |
730 | if (sc_reg < ARRAY_SIZE(offset) && |
731 | (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) | |
732 | return offset[sc_reg]; | |
da3dbb17 | 733 | return 0; |
1da177e4 LT |
734 | } |
735 | ||
203ef6c4 | 736 | static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) |
1da177e4 | 737 | { |
203ef6c4 TH |
738 | void __iomem *port_mmio = ahci_port_base(ap); |
739 | int offset = ahci_scr_offset(ap, sc_reg); | |
740 | ||
741 | if (offset) { | |
742 | *val = readl(port_mmio + offset); | |
743 | return 0; | |
1da177e4 | 744 | } |
203ef6c4 TH |
745 | return -EINVAL; |
746 | } | |
1da177e4 | 747 | |
203ef6c4 TH |
748 | static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) |
749 | { | |
750 | void __iomem *port_mmio = ahci_port_base(ap); | |
751 | int offset = ahci_scr_offset(ap, sc_reg); | |
752 | ||
753 | if (offset) { | |
754 | writel(val, port_mmio + offset); | |
755 | return 0; | |
756 | } | |
757 | return -EINVAL; | |
1da177e4 LT |
758 | } |
759 | ||
4447d351 | 760 | static void ahci_start_engine(struct ata_port *ap) |
7c76d1e8 | 761 | { |
4447d351 | 762 | void __iomem *port_mmio = ahci_port_base(ap); |
7c76d1e8 TH |
763 | u32 tmp; |
764 | ||
d8fcd116 | 765 | /* start DMA */ |
9f592056 | 766 | tmp = readl(port_mmio + PORT_CMD); |
7c76d1e8 TH |
767 | tmp |= PORT_CMD_START; |
768 | writel(tmp, port_mmio + PORT_CMD); | |
769 | readl(port_mmio + PORT_CMD); /* flush */ | |
770 | } | |
771 | ||
4447d351 | 772 | static int ahci_stop_engine(struct ata_port *ap) |
254950cd | 773 | { |
4447d351 | 774 | void __iomem *port_mmio = ahci_port_base(ap); |
254950cd TH |
775 | u32 tmp; |
776 | ||
777 | tmp = readl(port_mmio + PORT_CMD); | |
778 | ||
d8fcd116 | 779 | /* check if the HBA is idle */ |
254950cd TH |
780 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
781 | return 0; | |
782 | ||
d8fcd116 | 783 | /* setting HBA to idle */ |
254950cd TH |
784 | tmp &= ~PORT_CMD_START; |
785 | writel(tmp, port_mmio + PORT_CMD); | |
786 | ||
d8fcd116 | 787 | /* wait for engine to stop. This could be as long as 500 msec */ |
254950cd | 788 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
2dcb407e | 789 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); |
d8fcd116 | 790 | if (tmp & PORT_CMD_LIST_ON) |
254950cd TH |
791 | return -EIO; |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
4447d351 | 796 | static void ahci_start_fis_rx(struct ata_port *ap) |
0be0aa98 | 797 | { |
4447d351 TH |
798 | void __iomem *port_mmio = ahci_port_base(ap); |
799 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
800 | struct ahci_port_priv *pp = ap->private_data; | |
0be0aa98 TH |
801 | u32 tmp; |
802 | ||
803 | /* set FIS registers */ | |
4447d351 TH |
804 | if (hpriv->cap & HOST_CAP_64) |
805 | writel((pp->cmd_slot_dma >> 16) >> 16, | |
806 | port_mmio + PORT_LST_ADDR_HI); | |
807 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); | |
0be0aa98 | 808 | |
4447d351 TH |
809 | if (hpriv->cap & HOST_CAP_64) |
810 | writel((pp->rx_fis_dma >> 16) >> 16, | |
811 | port_mmio + PORT_FIS_ADDR_HI); | |
812 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); | |
0be0aa98 TH |
813 | |
814 | /* enable FIS reception */ | |
815 | tmp = readl(port_mmio + PORT_CMD); | |
816 | tmp |= PORT_CMD_FIS_RX; | |
817 | writel(tmp, port_mmio + PORT_CMD); | |
818 | ||
819 | /* flush */ | |
820 | readl(port_mmio + PORT_CMD); | |
821 | } | |
822 | ||
4447d351 | 823 | static int ahci_stop_fis_rx(struct ata_port *ap) |
0be0aa98 | 824 | { |
4447d351 | 825 | void __iomem *port_mmio = ahci_port_base(ap); |
0be0aa98 TH |
826 | u32 tmp; |
827 | ||
828 | /* disable FIS reception */ | |
829 | tmp = readl(port_mmio + PORT_CMD); | |
830 | tmp &= ~PORT_CMD_FIS_RX; | |
831 | writel(tmp, port_mmio + PORT_CMD); | |
832 | ||
833 | /* wait for completion, spec says 500ms, give it 1000 */ | |
834 | tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, | |
835 | PORT_CMD_FIS_ON, 10, 1000); | |
836 | if (tmp & PORT_CMD_FIS_ON) | |
837 | return -EBUSY; | |
838 | ||
839 | return 0; | |
840 | } | |
841 | ||
4447d351 | 842 | static void ahci_power_up(struct ata_port *ap) |
0be0aa98 | 843 | { |
4447d351 TH |
844 | struct ahci_host_priv *hpriv = ap->host->private_data; |
845 | void __iomem *port_mmio = ahci_port_base(ap); | |
0be0aa98 TH |
846 | u32 cmd; |
847 | ||
848 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
849 | ||
850 | /* spin up device */ | |
4447d351 | 851 | if (hpriv->cap & HOST_CAP_SSS) { |
0be0aa98 TH |
852 | cmd |= PORT_CMD_SPIN_UP; |
853 | writel(cmd, port_mmio + PORT_CMD); | |
854 | } | |
855 | ||
856 | /* wake up link */ | |
857 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); | |
858 | } | |
859 | ||
31556594 KCA |
860 | static void ahci_disable_alpm(struct ata_port *ap) |
861 | { | |
862 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
863 | void __iomem *port_mmio = ahci_port_base(ap); | |
864 | u32 cmd; | |
865 | struct ahci_port_priv *pp = ap->private_data; | |
866 | ||
867 | /* IPM bits should be disabled by libata-core */ | |
868 | /* get the existing command bits */ | |
869 | cmd = readl(port_mmio + PORT_CMD); | |
870 | ||
871 | /* disable ALPM and ASP */ | |
872 | cmd &= ~PORT_CMD_ASP; | |
873 | cmd &= ~PORT_CMD_ALPE; | |
874 | ||
875 | /* force the interface back to active */ | |
876 | cmd |= PORT_CMD_ICC_ACTIVE; | |
877 | ||
878 | /* write out new cmd value */ | |
879 | writel(cmd, port_mmio + PORT_CMD); | |
880 | cmd = readl(port_mmio + PORT_CMD); | |
881 | ||
882 | /* wait 10ms to be sure we've come out of any low power state */ | |
883 | msleep(10); | |
884 | ||
885 | /* clear out any PhyRdy stuff from interrupt status */ | |
886 | writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT); | |
887 | ||
888 | /* go ahead and clean out PhyRdy Change from Serror too */ | |
889 | ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18))); | |
890 | ||
891 | /* | |
892 | * Clear flag to indicate that we should ignore all PhyRdy | |
893 | * state changes | |
894 | */ | |
895 | hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG; | |
896 | ||
897 | /* | |
898 | * Enable interrupts on Phy Ready. | |
899 | */ | |
900 | pp->intr_mask |= PORT_IRQ_PHYRDY; | |
901 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
902 | ||
903 | /* | |
904 | * don't change the link pm policy - we can be called | |
905 | * just to turn of link pm temporarily | |
906 | */ | |
907 | } | |
908 | ||
909 | static int ahci_enable_alpm(struct ata_port *ap, | |
910 | enum link_pm policy) | |
911 | { | |
912 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
913 | void __iomem *port_mmio = ahci_port_base(ap); | |
914 | u32 cmd; | |
915 | struct ahci_port_priv *pp = ap->private_data; | |
916 | u32 asp; | |
917 | ||
918 | /* Make sure the host is capable of link power management */ | |
919 | if (!(hpriv->cap & HOST_CAP_ALPM)) | |
920 | return -EINVAL; | |
921 | ||
922 | switch (policy) { | |
923 | case MAX_PERFORMANCE: | |
924 | case NOT_AVAILABLE: | |
925 | /* | |
926 | * if we came here with NOT_AVAILABLE, | |
927 | * it just means this is the first time we | |
928 | * have tried to enable - default to max performance, | |
929 | * and let the user go to lower power modes on request. | |
930 | */ | |
931 | ahci_disable_alpm(ap); | |
932 | return 0; | |
933 | case MIN_POWER: | |
934 | /* configure HBA to enter SLUMBER */ | |
935 | asp = PORT_CMD_ASP; | |
936 | break; | |
937 | case MEDIUM_POWER: | |
938 | /* configure HBA to enter PARTIAL */ | |
939 | asp = 0; | |
940 | break; | |
941 | default: | |
942 | return -EINVAL; | |
943 | } | |
944 | ||
945 | /* | |
946 | * Disable interrupts on Phy Ready. This keeps us from | |
947 | * getting woken up due to spurious phy ready interrupts | |
948 | * TBD - Hot plug should be done via polling now, is | |
949 | * that even supported? | |
950 | */ | |
951 | pp->intr_mask &= ~PORT_IRQ_PHYRDY; | |
952 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
953 | ||
954 | /* | |
955 | * Set a flag to indicate that we should ignore all PhyRdy | |
956 | * state changes since these can happen now whenever we | |
957 | * change link state | |
958 | */ | |
959 | hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG; | |
960 | ||
961 | /* get the existing command bits */ | |
962 | cmd = readl(port_mmio + PORT_CMD); | |
963 | ||
964 | /* | |
965 | * Set ASP based on Policy | |
966 | */ | |
967 | cmd |= asp; | |
968 | ||
969 | /* | |
970 | * Setting this bit will instruct the HBA to aggressively | |
971 | * enter a lower power link state when it's appropriate and | |
972 | * based on the value set above for ASP | |
973 | */ | |
974 | cmd |= PORT_CMD_ALPE; | |
975 | ||
976 | /* write out new cmd value */ | |
977 | writel(cmd, port_mmio + PORT_CMD); | |
978 | cmd = readl(port_mmio + PORT_CMD); | |
979 | ||
980 | /* IPM bits should be set by libata-core */ | |
981 | return 0; | |
982 | } | |
983 | ||
438ac6d5 | 984 | #ifdef CONFIG_PM |
4447d351 | 985 | static void ahci_power_down(struct ata_port *ap) |
0be0aa98 | 986 | { |
4447d351 TH |
987 | struct ahci_host_priv *hpriv = ap->host->private_data; |
988 | void __iomem *port_mmio = ahci_port_base(ap); | |
0be0aa98 TH |
989 | u32 cmd, scontrol; |
990 | ||
4447d351 | 991 | if (!(hpriv->cap & HOST_CAP_SSS)) |
07c53dac | 992 | return; |
0be0aa98 | 993 | |
07c53dac TH |
994 | /* put device into listen mode, first set PxSCTL.DET to 0 */ |
995 | scontrol = readl(port_mmio + PORT_SCR_CTL); | |
996 | scontrol &= ~0xf; | |
997 | writel(scontrol, port_mmio + PORT_SCR_CTL); | |
0be0aa98 | 998 | |
07c53dac TH |
999 | /* then set PxCMD.SUD to 0 */ |
1000 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
1001 | cmd &= ~PORT_CMD_SPIN_UP; | |
1002 | writel(cmd, port_mmio + PORT_CMD); | |
0be0aa98 | 1003 | } |
438ac6d5 | 1004 | #endif |
0be0aa98 | 1005 | |
df69c9c5 | 1006 | static void ahci_start_port(struct ata_port *ap) |
0be0aa98 | 1007 | { |
0be0aa98 | 1008 | /* enable FIS reception */ |
4447d351 | 1009 | ahci_start_fis_rx(ap); |
0be0aa98 TH |
1010 | |
1011 | /* enable DMA */ | |
4447d351 | 1012 | ahci_start_engine(ap); |
0be0aa98 TH |
1013 | } |
1014 | ||
4447d351 | 1015 | static int ahci_deinit_port(struct ata_port *ap, const char **emsg) |
0be0aa98 TH |
1016 | { |
1017 | int rc; | |
1018 | ||
1019 | /* disable DMA */ | |
4447d351 | 1020 | rc = ahci_stop_engine(ap); |
0be0aa98 TH |
1021 | if (rc) { |
1022 | *emsg = "failed to stop engine"; | |
1023 | return rc; | |
1024 | } | |
1025 | ||
1026 | /* disable FIS reception */ | |
4447d351 | 1027 | rc = ahci_stop_fis_rx(ap); |
0be0aa98 TH |
1028 | if (rc) { |
1029 | *emsg = "failed stop FIS RX"; | |
1030 | return rc; | |
1031 | } | |
1032 | ||
0be0aa98 TH |
1033 | return 0; |
1034 | } | |
1035 | ||
4447d351 | 1036 | static int ahci_reset_controller(struct ata_host *host) |
d91542c1 | 1037 | { |
4447d351 | 1038 | struct pci_dev *pdev = to_pci_dev(host->dev); |
49f29090 | 1039 | struct ahci_host_priv *hpriv = host->private_data; |
4447d351 | 1040 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
d447df14 | 1041 | u32 tmp; |
d91542c1 | 1042 | |
3cc3eb11 JG |
1043 | /* we must be in AHCI mode, before using anything |
1044 | * AHCI-specific, such as HOST_RESET. | |
1045 | */ | |
d91542c1 | 1046 | tmp = readl(mmio + HOST_CTL); |
ab6fc95f JG |
1047 | if (!(tmp & HOST_AHCI_EN)) { |
1048 | tmp |= HOST_AHCI_EN; | |
1049 | writel(tmp, mmio + HOST_CTL); | |
1050 | } | |
3cc3eb11 JG |
1051 | |
1052 | /* global controller reset */ | |
d91542c1 TH |
1053 | if ((tmp & HOST_RESET) == 0) { |
1054 | writel(tmp | HOST_RESET, mmio + HOST_CTL); | |
1055 | readl(mmio + HOST_CTL); /* flush */ | |
1056 | } | |
1057 | ||
1058 | /* reset must complete within 1 second, or | |
1059 | * the hardware should be considered fried. | |
1060 | */ | |
1061 | ssleep(1); | |
1062 | ||
1063 | tmp = readl(mmio + HOST_CTL); | |
1064 | if (tmp & HOST_RESET) { | |
4447d351 | 1065 | dev_printk(KERN_ERR, host->dev, |
d91542c1 TH |
1066 | "controller reset failed (0x%x)\n", tmp); |
1067 | return -EIO; | |
1068 | } | |
1069 | ||
98fa4b60 | 1070 | /* turn on AHCI mode */ |
d91542c1 TH |
1071 | writel(HOST_AHCI_EN, mmio + HOST_CTL); |
1072 | (void) readl(mmio + HOST_CTL); /* flush */ | |
98fa4b60 | 1073 | |
d447df14 | 1074 | /* some registers might be cleared on reset. restore initial values */ |
4447d351 | 1075 | ahci_restore_initial_config(host); |
d91542c1 TH |
1076 | |
1077 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { | |
1078 | u16 tmp16; | |
1079 | ||
1080 | /* configure PCS */ | |
1081 | pci_read_config_word(pdev, 0x92, &tmp16); | |
49f29090 TH |
1082 | if ((tmp16 & hpriv->port_map) != hpriv->port_map) { |
1083 | tmp16 |= hpriv->port_map; | |
1084 | pci_write_config_word(pdev, 0x92, tmp16); | |
1085 | } | |
d91542c1 TH |
1086 | } |
1087 | ||
1088 | return 0; | |
1089 | } | |
1090 | ||
2bcd866b JG |
1091 | static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap, |
1092 | int port_no, void __iomem *mmio, | |
1093 | void __iomem *port_mmio) | |
1094 | { | |
1095 | const char *emsg = NULL; | |
1096 | int rc; | |
1097 | u32 tmp; | |
1098 | ||
1099 | /* make sure port is not active */ | |
1100 | rc = ahci_deinit_port(ap, &emsg); | |
1101 | if (rc) | |
1102 | dev_printk(KERN_WARNING, &pdev->dev, | |
1103 | "%s (%d)\n", emsg, rc); | |
1104 | ||
1105 | /* clear SError */ | |
1106 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
1107 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); | |
1108 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
1109 | ||
1110 | /* clear port IRQ */ | |
1111 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1112 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
1113 | if (tmp) | |
1114 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
1115 | ||
1116 | writel(1 << port_no, mmio + HOST_IRQ_STAT); | |
1117 | } | |
1118 | ||
4447d351 | 1119 | static void ahci_init_controller(struct ata_host *host) |
d91542c1 | 1120 | { |
417a1a6d | 1121 | struct ahci_host_priv *hpriv = host->private_data; |
4447d351 TH |
1122 | struct pci_dev *pdev = to_pci_dev(host->dev); |
1123 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
2bcd866b | 1124 | int i; |
cd70c266 | 1125 | void __iomem *port_mmio; |
d91542c1 TH |
1126 | u32 tmp; |
1127 | ||
417a1a6d | 1128 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
cd70c266 JG |
1129 | port_mmio = __ahci_port_base(host, 4); |
1130 | ||
1131 | writel(0, port_mmio + PORT_IRQ_MASK); | |
1132 | ||
1133 | /* clear port IRQ */ | |
1134 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1135 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
1136 | if (tmp) | |
1137 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
1138 | } | |
1139 | ||
4447d351 TH |
1140 | for (i = 0; i < host->n_ports; i++) { |
1141 | struct ata_port *ap = host->ports[i]; | |
d91542c1 | 1142 | |
cd70c266 | 1143 | port_mmio = ahci_port_base(ap); |
4447d351 | 1144 | if (ata_port_is_dummy(ap)) |
d91542c1 | 1145 | continue; |
d91542c1 | 1146 | |
2bcd866b | 1147 | ahci_port_init(pdev, ap, i, mmio, port_mmio); |
d91542c1 TH |
1148 | } |
1149 | ||
1150 | tmp = readl(mmio + HOST_CTL); | |
1151 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
1152 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
1153 | tmp = readl(mmio + HOST_CTL); | |
1154 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
1155 | } | |
1156 | ||
422b7595 | 1157 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
1da177e4 | 1158 | { |
4447d351 | 1159 | void __iomem *port_mmio = ahci_port_base(ap); |
1da177e4 | 1160 | struct ata_taskfile tf; |
422b7595 TH |
1161 | u32 tmp; |
1162 | ||
1163 | tmp = readl(port_mmio + PORT_SIG); | |
1164 | tf.lbah = (tmp >> 24) & 0xff; | |
1165 | tf.lbam = (tmp >> 16) & 0xff; | |
1166 | tf.lbal = (tmp >> 8) & 0xff; | |
1167 | tf.nsect = (tmp) & 0xff; | |
1168 | ||
1169 | return ata_dev_classify(&tf); | |
1170 | } | |
1171 | ||
12fad3f9 TH |
1172 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
1173 | u32 opts) | |
cc9278ed | 1174 | { |
12fad3f9 TH |
1175 | dma_addr_t cmd_tbl_dma; |
1176 | ||
1177 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; | |
1178 | ||
1179 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); | |
1180 | pp->cmd_slot[tag].status = 0; | |
1181 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); | |
1182 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); | |
cc9278ed TH |
1183 | } |
1184 | ||
d2e75dff | 1185 | static int ahci_kick_engine(struct ata_port *ap, int force_restart) |
4658f79b | 1186 | { |
0d5ff566 | 1187 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
cca3974e | 1188 | struct ahci_host_priv *hpriv = ap->host->private_data; |
bf2af2a2 | 1189 | u32 tmp; |
d2e75dff | 1190 | int busy, rc; |
bf2af2a2 | 1191 | |
d2e75dff TH |
1192 | /* do we need to kick the port? */ |
1193 | busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ); | |
1194 | if (!busy && !force_restart) | |
1195 | return 0; | |
1196 | ||
1197 | /* stop engine */ | |
1198 | rc = ahci_stop_engine(ap); | |
1199 | if (rc) | |
1200 | goto out_restart; | |
1201 | ||
1202 | /* need to do CLO? */ | |
1203 | if (!busy) { | |
1204 | rc = 0; | |
1205 | goto out_restart; | |
1206 | } | |
1207 | ||
1208 | if (!(hpriv->cap & HOST_CAP_CLO)) { | |
1209 | rc = -EOPNOTSUPP; | |
1210 | goto out_restart; | |
1211 | } | |
bf2af2a2 | 1212 | |
d2e75dff | 1213 | /* perform CLO */ |
bf2af2a2 BJ |
1214 | tmp = readl(port_mmio + PORT_CMD); |
1215 | tmp |= PORT_CMD_CLO; | |
1216 | writel(tmp, port_mmio + PORT_CMD); | |
1217 | ||
d2e75dff | 1218 | rc = 0; |
bf2af2a2 BJ |
1219 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
1220 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); | |
1221 | if (tmp & PORT_CMD_CLO) | |
d2e75dff | 1222 | rc = -EIO; |
bf2af2a2 | 1223 | |
d2e75dff TH |
1224 | /* restart engine */ |
1225 | out_restart: | |
1226 | ahci_start_engine(ap); | |
1227 | return rc; | |
bf2af2a2 BJ |
1228 | } |
1229 | ||
91c4a2e0 TH |
1230 | static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, |
1231 | struct ata_taskfile *tf, int is_cmd, u16 flags, | |
1232 | unsigned long timeout_msec) | |
bf2af2a2 | 1233 | { |
91c4a2e0 | 1234 | const u32 cmd_fis_len = 5; /* five dwords */ |
4658f79b | 1235 | struct ahci_port_priv *pp = ap->private_data; |
4447d351 | 1236 | void __iomem *port_mmio = ahci_port_base(ap); |
91c4a2e0 TH |
1237 | u8 *fis = pp->cmd_tbl; |
1238 | u32 tmp; | |
1239 | ||
1240 | /* prep the command */ | |
1241 | ata_tf_to_fis(tf, pmp, is_cmd, fis); | |
1242 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); | |
1243 | ||
1244 | /* issue & wait */ | |
1245 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
1246 | ||
1247 | if (timeout_msec) { | |
1248 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, | |
1249 | 1, timeout_msec); | |
1250 | if (tmp & 0x1) { | |
1251 | ahci_kick_engine(ap, 1); | |
1252 | return -EBUSY; | |
1253 | } | |
1254 | } else | |
1255 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ | |
1256 | ||
1257 | return 0; | |
1258 | } | |
1259 | ||
cc0680a5 | 1260 | static int ahci_do_softreset(struct ata_link *link, unsigned int *class, |
a9cf5e85 | 1261 | int pmp, unsigned long deadline) |
91c4a2e0 | 1262 | { |
cc0680a5 | 1263 | struct ata_port *ap = link->ap; |
4658f79b | 1264 | const char *reason = NULL; |
2cbb79eb | 1265 | unsigned long now, msecs; |
4658f79b | 1266 | struct ata_taskfile tf; |
4658f79b TH |
1267 | int rc; |
1268 | ||
1269 | DPRINTK("ENTER\n"); | |
1270 | ||
cc0680a5 | 1271 | if (ata_link_offline(link)) { |
c2a65852 TH |
1272 | DPRINTK("PHY reports no device\n"); |
1273 | *class = ATA_DEV_NONE; | |
1274 | return 0; | |
1275 | } | |
1276 | ||
4658f79b | 1277 | /* prepare for SRST (AHCI-1.1 10.4.1) */ |
d2e75dff | 1278 | rc = ahci_kick_engine(ap, 1); |
994056d7 | 1279 | if (rc && rc != -EOPNOTSUPP) |
cc0680a5 | 1280 | ata_link_printk(link, KERN_WARNING, |
994056d7 | 1281 | "failed to reset engine (errno=%d)\n", rc); |
4658f79b | 1282 | |
cc0680a5 | 1283 | ata_tf_init(link->device, &tf); |
4658f79b TH |
1284 | |
1285 | /* issue the first D2H Register FIS */ | |
2cbb79eb TH |
1286 | msecs = 0; |
1287 | now = jiffies; | |
1288 | if (time_after(now, deadline)) | |
1289 | msecs = jiffies_to_msecs(deadline - now); | |
1290 | ||
4658f79b | 1291 | tf.ctl |= ATA_SRST; |
a9cf5e85 | 1292 | if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, |
91c4a2e0 | 1293 | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { |
4658f79b TH |
1294 | rc = -EIO; |
1295 | reason = "1st FIS failed"; | |
1296 | goto fail; | |
1297 | } | |
1298 | ||
1299 | /* spec says at least 5us, but be generous and sleep for 1ms */ | |
1300 | msleep(1); | |
1301 | ||
1302 | /* issue the second D2H Register FIS */ | |
4658f79b | 1303 | tf.ctl &= ~ATA_SRST; |
a9cf5e85 | 1304 | ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); |
4658f79b | 1305 | |
88ff6eaf TH |
1306 | /* wait a while before checking status */ |
1307 | ata_wait_after_reset(ap, deadline); | |
4658f79b | 1308 | |
9b89391c TH |
1309 | rc = ata_wait_ready(ap, deadline); |
1310 | /* link occupied, -ENODEV too is an error */ | |
1311 | if (rc) { | |
1312 | reason = "device not ready"; | |
1313 | goto fail; | |
4658f79b | 1314 | } |
9b89391c | 1315 | *class = ahci_dev_classify(ap); |
4658f79b TH |
1316 | |
1317 | DPRINTK("EXIT, class=%u\n", *class); | |
1318 | return 0; | |
1319 | ||
4658f79b | 1320 | fail: |
cc0680a5 | 1321 | ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); |
4658f79b TH |
1322 | return rc; |
1323 | } | |
1324 | ||
cc0680a5 | 1325 | static int ahci_softreset(struct ata_link *link, unsigned int *class, |
a9cf5e85 TH |
1326 | unsigned long deadline) |
1327 | { | |
7d50b60b TH |
1328 | int pmp = 0; |
1329 | ||
1330 | if (link->ap->flags & ATA_FLAG_PMP) | |
1331 | pmp = SATA_PMP_CTRL_PORT; | |
1332 | ||
1333 | return ahci_do_softreset(link, class, pmp, deadline); | |
a9cf5e85 TH |
1334 | } |
1335 | ||
cc0680a5 | 1336 | static int ahci_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 1337 | unsigned long deadline) |
422b7595 | 1338 | { |
cc0680a5 | 1339 | struct ata_port *ap = link->ap; |
4296971d TH |
1340 | struct ahci_port_priv *pp = ap->private_data; |
1341 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1342 | struct ata_taskfile tf; | |
4bd00f6a TH |
1343 | int rc; |
1344 | ||
1345 | DPRINTK("ENTER\n"); | |
1da177e4 | 1346 | |
4447d351 | 1347 | ahci_stop_engine(ap); |
4296971d TH |
1348 | |
1349 | /* clear D2H reception area to properly wait for D2H FIS */ | |
cc0680a5 | 1350 | ata_tf_init(link->device, &tf); |
dfd7a3db | 1351 | tf.command = 0x80; |
9977126c | 1352 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
4296971d | 1353 | |
cc0680a5 | 1354 | rc = sata_std_hardreset(link, class, deadline); |
4296971d | 1355 | |
4447d351 | 1356 | ahci_start_engine(ap); |
1da177e4 | 1357 | |
cc0680a5 | 1358 | if (rc == 0 && ata_link_online(link)) |
4bd00f6a | 1359 | *class = ahci_dev_classify(ap); |
7d50b60b | 1360 | if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN) |
4bd00f6a | 1361 | *class = ATA_DEV_NONE; |
1da177e4 | 1362 | |
4bd00f6a TH |
1363 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
1364 | return rc; | |
1365 | } | |
1366 | ||
cc0680a5 | 1367 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 1368 | unsigned long deadline) |
ad616ffb | 1369 | { |
cc0680a5 | 1370 | struct ata_port *ap = link->ap; |
da3dbb17 | 1371 | u32 serror; |
ad616ffb TH |
1372 | int rc; |
1373 | ||
1374 | DPRINTK("ENTER\n"); | |
1375 | ||
4447d351 | 1376 | ahci_stop_engine(ap); |
ad616ffb | 1377 | |
cc0680a5 | 1378 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
d4b2bab4 | 1379 | deadline); |
ad616ffb TH |
1380 | |
1381 | /* vt8251 needs SError cleared for the port to operate */ | |
da3dbb17 TH |
1382 | ahci_scr_read(ap, SCR_ERROR, &serror); |
1383 | ahci_scr_write(ap, SCR_ERROR, serror); | |
ad616ffb | 1384 | |
4447d351 | 1385 | ahci_start_engine(ap); |
ad616ffb TH |
1386 | |
1387 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | |
1388 | ||
1389 | /* vt8251 doesn't clear BSY on signature FIS reception, | |
1390 | * request follow-up softreset. | |
1391 | */ | |
1392 | return rc ?: -EAGAIN; | |
1393 | } | |
1394 | ||
edc93052 TH |
1395 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
1396 | unsigned long deadline) | |
1397 | { | |
1398 | struct ata_port *ap = link->ap; | |
1399 | struct ahci_port_priv *pp = ap->private_data; | |
1400 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1401 | struct ata_taskfile tf; | |
1402 | int rc; | |
1403 | ||
1404 | ahci_stop_engine(ap); | |
1405 | ||
1406 | /* clear D2H reception area to properly wait for D2H FIS */ | |
1407 | ata_tf_init(link->device, &tf); | |
1408 | tf.command = 0x80; | |
1409 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); | |
1410 | ||
1411 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), | |
1412 | deadline); | |
1413 | ||
1414 | ahci_start_engine(ap); | |
1415 | ||
1416 | if (rc || ata_link_offline(link)) | |
1417 | return rc; | |
1418 | ||
1419 | /* spec mandates ">= 2ms" before checking status */ | |
1420 | msleep(150); | |
1421 | ||
1422 | /* The pseudo configuration device on SIMG4726 attached to | |
1423 | * ASUS P5W-DH Deluxe doesn't send signature FIS after | |
1424 | * hardreset if no device is attached to the first downstream | |
1425 | * port && the pseudo device locks up on SRST w/ PMP==0. To | |
1426 | * work around this, wait for !BSY only briefly. If BSY isn't | |
1427 | * cleared, perform CLO and proceed to IDENTIFY (achieved by | |
1428 | * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). | |
1429 | * | |
1430 | * Wait for two seconds. Devices attached to downstream port | |
1431 | * which can't process the following IDENTIFY after this will | |
1432 | * have to be reset again. For most cases, this should | |
1433 | * suffice while making probing snappish enough. | |
1434 | */ | |
1435 | rc = ata_wait_ready(ap, jiffies + 2 * HZ); | |
1436 | if (rc) | |
1437 | ahci_kick_engine(ap, 0); | |
1438 | ||
1439 | return 0; | |
1440 | } | |
1441 | ||
cc0680a5 | 1442 | static void ahci_postreset(struct ata_link *link, unsigned int *class) |
4bd00f6a | 1443 | { |
cc0680a5 | 1444 | struct ata_port *ap = link->ap; |
4447d351 | 1445 | void __iomem *port_mmio = ahci_port_base(ap); |
4bd00f6a TH |
1446 | u32 new_tmp, tmp; |
1447 | ||
cc0680a5 | 1448 | ata_std_postreset(link, class); |
02eaa666 JG |
1449 | |
1450 | /* Make sure port's ATAPI bit is set appropriately */ | |
1451 | new_tmp = tmp = readl(port_mmio + PORT_CMD); | |
4bd00f6a | 1452 | if (*class == ATA_DEV_ATAPI) |
02eaa666 JG |
1453 | new_tmp |= PORT_CMD_ATAPI; |
1454 | else | |
1455 | new_tmp &= ~PORT_CMD_ATAPI; | |
1456 | if (new_tmp != tmp) { | |
1457 | writel(new_tmp, port_mmio + PORT_CMD); | |
1458 | readl(port_mmio + PORT_CMD); /* flush */ | |
1459 | } | |
1da177e4 LT |
1460 | } |
1461 | ||
7d50b60b TH |
1462 | static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class, |
1463 | unsigned long deadline) | |
1464 | { | |
1465 | return ahci_do_softreset(link, class, link->pmp, deadline); | |
1466 | } | |
1467 | ||
1da177e4 LT |
1468 | static u8 ahci_check_status(struct ata_port *ap) |
1469 | { | |
0d5ff566 | 1470 | void __iomem *mmio = ap->ioaddr.cmd_addr; |
1da177e4 LT |
1471 | |
1472 | return readl(mmio + PORT_TFDATA) & 0xFF; | |
1473 | } | |
1474 | ||
1da177e4 LT |
1475 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
1476 | { | |
1477 | struct ahci_port_priv *pp = ap->private_data; | |
1478 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1479 | ||
1480 | ata_tf_from_fis(d2h_fis, tf); | |
1481 | } | |
1482 | ||
12fad3f9 | 1483 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
1da177e4 | 1484 | { |
cedc9a47 JG |
1485 | struct scatterlist *sg; |
1486 | struct ahci_sg *ahci_sg; | |
828d09de | 1487 | unsigned int n_sg = 0; |
1da177e4 LT |
1488 | |
1489 | VPRINTK("ENTER\n"); | |
1490 | ||
1491 | /* | |
1492 | * Next, the S/G list. | |
1493 | */ | |
12fad3f9 | 1494 | ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
cedc9a47 JG |
1495 | ata_for_each_sg(sg, qc) { |
1496 | dma_addr_t addr = sg_dma_address(sg); | |
1497 | u32 sg_len = sg_dma_len(sg); | |
1498 | ||
1499 | ahci_sg->addr = cpu_to_le32(addr & 0xffffffff); | |
1500 | ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
1501 | ahci_sg->flags_size = cpu_to_le32(sg_len - 1); | |
828d09de | 1502 | |
cedc9a47 | 1503 | ahci_sg++; |
828d09de | 1504 | n_sg++; |
1da177e4 | 1505 | } |
828d09de JG |
1506 | |
1507 | return n_sg; | |
1da177e4 LT |
1508 | } |
1509 | ||
1510 | static void ahci_qc_prep(struct ata_queued_cmd *qc) | |
1511 | { | |
a0ea7328 JG |
1512 | struct ata_port *ap = qc->ap; |
1513 | struct ahci_port_priv *pp = ap->private_data; | |
405e66b3 | 1514 | int is_atapi = ata_is_atapi(qc->tf.protocol); |
12fad3f9 | 1515 | void *cmd_tbl; |
1da177e4 LT |
1516 | u32 opts; |
1517 | const u32 cmd_fis_len = 5; /* five dwords */ | |
828d09de | 1518 | unsigned int n_elem; |
1da177e4 | 1519 | |
1da177e4 LT |
1520 | /* |
1521 | * Fill in command table information. First, the header, | |
1522 | * a SATA Register - Host to Device command FIS. | |
1523 | */ | |
12fad3f9 TH |
1524 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
1525 | ||
7d50b60b | 1526 | ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); |
cc9278ed | 1527 | if (is_atapi) { |
12fad3f9 TH |
1528 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
1529 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); | |
a0ea7328 | 1530 | } |
1da177e4 | 1531 | |
cc9278ed TH |
1532 | n_elem = 0; |
1533 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
12fad3f9 | 1534 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
1da177e4 | 1535 | |
cc9278ed TH |
1536 | /* |
1537 | * Fill in command slot information. | |
1538 | */ | |
7d50b60b | 1539 | opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); |
cc9278ed TH |
1540 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
1541 | opts |= AHCI_CMD_WRITE; | |
1542 | if (is_atapi) | |
4b10e559 | 1543 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
828d09de | 1544 | |
12fad3f9 | 1545 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
1da177e4 LT |
1546 | } |
1547 | ||
78cd52d0 | 1548 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
1da177e4 | 1549 | { |
417a1a6d | 1550 | struct ahci_host_priv *hpriv = ap->host->private_data; |
78cd52d0 | 1551 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
1552 | struct ata_eh_info *host_ehi = &ap->link.eh_info; |
1553 | struct ata_link *link = NULL; | |
1554 | struct ata_queued_cmd *active_qc; | |
1555 | struct ata_eh_info *active_ehi; | |
78cd52d0 | 1556 | u32 serror; |
1da177e4 | 1557 | |
7d50b60b TH |
1558 | /* determine active link */ |
1559 | ata_port_for_each_link(link, ap) | |
1560 | if (ata_link_active(link)) | |
1561 | break; | |
1562 | if (!link) | |
1563 | link = &ap->link; | |
1564 | ||
1565 | active_qc = ata_qc_from_tag(ap, link->active_tag); | |
1566 | active_ehi = &link->eh_info; | |
1567 | ||
1568 | /* record irq stat */ | |
1569 | ata_ehi_clear_desc(host_ehi); | |
1570 | ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); | |
1da177e4 | 1571 | |
78cd52d0 | 1572 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
da3dbb17 | 1573 | ahci_scr_read(ap, SCR_ERROR, &serror); |
78cd52d0 | 1574 | ahci_scr_write(ap, SCR_ERROR, serror); |
7d50b60b | 1575 | host_ehi->serror |= serror; |
78cd52d0 | 1576 | |
41669553 | 1577 | /* some controllers set IRQ_IF_ERR on device errors, ignore it */ |
417a1a6d | 1578 | if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) |
41669553 TH |
1579 | irq_stat &= ~PORT_IRQ_IF_ERR; |
1580 | ||
55a61604 | 1581 | if (irq_stat & PORT_IRQ_TF_ERR) { |
7d50b60b TH |
1582 | /* If qc is active, charge it; otherwise, the active |
1583 | * link. There's no active qc on NCQ errors. It will | |
1584 | * be determined by EH by reading log page 10h. | |
1585 | */ | |
1586 | if (active_qc) | |
1587 | active_qc->err_mask |= AC_ERR_DEV; | |
1588 | else | |
1589 | active_ehi->err_mask |= AC_ERR_DEV; | |
1590 | ||
417a1a6d | 1591 | if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) |
7d50b60b TH |
1592 | host_ehi->serror &= ~SERR_INTERNAL; |
1593 | } | |
1594 | ||
1595 | if (irq_stat & PORT_IRQ_UNK_FIS) { | |
1596 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); | |
1597 | ||
1598 | active_ehi->err_mask |= AC_ERR_HSM; | |
1599 | active_ehi->action |= ATA_EH_SOFTRESET; | |
1600 | ata_ehi_push_desc(active_ehi, | |
1601 | "unknown FIS %08x %08x %08x %08x" , | |
1602 | unk[0], unk[1], unk[2], unk[3]); | |
1603 | } | |
1604 | ||
1605 | if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) { | |
1606 | active_ehi->err_mask |= AC_ERR_HSM; | |
1607 | active_ehi->action |= ATA_EH_SOFTRESET; | |
1608 | ata_ehi_push_desc(active_ehi, "incorrect PMP"); | |
55a61604 | 1609 | } |
78cd52d0 TH |
1610 | |
1611 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { | |
7d50b60b TH |
1612 | host_ehi->err_mask |= AC_ERR_HOST_BUS; |
1613 | host_ehi->action |= ATA_EH_SOFTRESET; | |
1614 | ata_ehi_push_desc(host_ehi, "host bus error"); | |
1da177e4 LT |
1615 | } |
1616 | ||
78cd52d0 | 1617 | if (irq_stat & PORT_IRQ_IF_ERR) { |
7d50b60b TH |
1618 | host_ehi->err_mask |= AC_ERR_ATA_BUS; |
1619 | host_ehi->action |= ATA_EH_SOFTRESET; | |
1620 | ata_ehi_push_desc(host_ehi, "interface fatal error"); | |
78cd52d0 | 1621 | } |
1da177e4 | 1622 | |
78cd52d0 | 1623 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
7d50b60b TH |
1624 | ata_ehi_hotplugged(host_ehi); |
1625 | ata_ehi_push_desc(host_ehi, "%s", | |
1626 | irq_stat & PORT_IRQ_CONNECT ? | |
78cd52d0 TH |
1627 | "connection status changed" : "PHY RDY changed"); |
1628 | } | |
1629 | ||
78cd52d0 | 1630 | /* okay, let's hand over to EH */ |
a72ec4ce | 1631 | |
78cd52d0 TH |
1632 | if (irq_stat & PORT_IRQ_FREEZE) |
1633 | ata_port_freeze(ap); | |
1634 | else | |
1635 | ata_port_abort(ap); | |
1da177e4 LT |
1636 | } |
1637 | ||
df69c9c5 | 1638 | static void ahci_port_intr(struct ata_port *ap) |
1da177e4 | 1639 | { |
4447d351 | 1640 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
9af5c9c9 | 1641 | struct ata_eh_info *ehi = &ap->link.eh_info; |
0291f95f | 1642 | struct ahci_port_priv *pp = ap->private_data; |
5f226c6b | 1643 | struct ahci_host_priv *hpriv = ap->host->private_data; |
b06ce3e5 | 1644 | int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); |
12fad3f9 | 1645 | u32 status, qc_active; |
459ad688 | 1646 | int rc; |
1da177e4 LT |
1647 | |
1648 | status = readl(port_mmio + PORT_IRQ_STAT); | |
1649 | writel(status, port_mmio + PORT_IRQ_STAT); | |
1650 | ||
b06ce3e5 TH |
1651 | /* ignore BAD_PMP while resetting */ |
1652 | if (unlikely(resetting)) | |
1653 | status &= ~PORT_IRQ_BAD_PMP; | |
1654 | ||
31556594 KCA |
1655 | /* If we are getting PhyRdy, this is |
1656 | * just a power state change, we should | |
1657 | * clear out this, plus the PhyRdy/Comm | |
1658 | * Wake bits from Serror | |
1659 | */ | |
1660 | if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) && | |
1661 | (status & PORT_IRQ_PHYRDY)) { | |
1662 | status &= ~PORT_IRQ_PHYRDY; | |
1663 | ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18))); | |
1664 | } | |
1665 | ||
78cd52d0 TH |
1666 | if (unlikely(status & PORT_IRQ_ERROR)) { |
1667 | ahci_error_intr(ap, status); | |
1668 | return; | |
1da177e4 LT |
1669 | } |
1670 | ||
2f294968 | 1671 | if (status & PORT_IRQ_SDB_FIS) { |
5f226c6b TH |
1672 | /* If SNotification is available, leave notification |
1673 | * handling to sata_async_notification(). If not, | |
1674 | * emulate it by snooping SDB FIS RX area. | |
1675 | * | |
1676 | * Snooping FIS RX area is probably cheaper than | |
1677 | * poking SNotification but some constrollers which | |
1678 | * implement SNotification, ICH9 for example, don't | |
1679 | * store AN SDB FIS into receive area. | |
2f294968 | 1680 | */ |
5f226c6b | 1681 | if (hpriv->cap & HOST_CAP_SNTF) |
7d77b247 | 1682 | sata_async_notification(ap); |
5f226c6b TH |
1683 | else { |
1684 | /* If the 'N' bit in word 0 of the FIS is set, | |
1685 | * we just received asynchronous notification. | |
1686 | * Tell libata about it. | |
1687 | */ | |
1688 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; | |
1689 | u32 f0 = le32_to_cpu(f[0]); | |
1690 | ||
1691 | if (f0 & (1 << 15)) | |
1692 | sata_async_notification(ap); | |
1693 | } | |
2f294968 KCA |
1694 | } |
1695 | ||
7d50b60b TH |
1696 | /* pp->active_link is valid iff any command is in flight */ |
1697 | if (ap->qc_active && pp->active_link->sactive) | |
12fad3f9 TH |
1698 | qc_active = readl(port_mmio + PORT_SCR_ACT); |
1699 | else | |
1700 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); | |
1701 | ||
1702 | rc = ata_qc_complete_multiple(ap, qc_active, NULL); | |
b06ce3e5 | 1703 | |
459ad688 TH |
1704 | /* while resetting, invalid completions are expected */ |
1705 | if (unlikely(rc < 0 && !resetting)) { | |
12fad3f9 TH |
1706 | ehi->err_mask |= AC_ERR_HSM; |
1707 | ehi->action |= ATA_EH_SOFTRESET; | |
1708 | ata_port_freeze(ap); | |
1da177e4 | 1709 | } |
1da177e4 LT |
1710 | } |
1711 | ||
1712 | static void ahci_irq_clear(struct ata_port *ap) | |
1713 | { | |
1714 | /* TODO */ | |
1715 | } | |
1716 | ||
7d12e780 | 1717 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance) |
1da177e4 | 1718 | { |
cca3974e | 1719 | struct ata_host *host = dev_instance; |
1da177e4 LT |
1720 | struct ahci_host_priv *hpriv; |
1721 | unsigned int i, handled = 0; | |
ea6ba10b | 1722 | void __iomem *mmio; |
1da177e4 LT |
1723 | u32 irq_stat, irq_ack = 0; |
1724 | ||
1725 | VPRINTK("ENTER\n"); | |
1726 | ||
cca3974e | 1727 | hpriv = host->private_data; |
0d5ff566 | 1728 | mmio = host->iomap[AHCI_PCI_BAR]; |
1da177e4 LT |
1729 | |
1730 | /* sigh. 0xffffffff is a valid return from h/w */ | |
1731 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
1732 | irq_stat &= hpriv->port_map; | |
1733 | if (!irq_stat) | |
1734 | return IRQ_NONE; | |
1735 | ||
2dcb407e | 1736 | spin_lock(&host->lock); |
1da177e4 | 1737 | |
2dcb407e | 1738 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 1739 | struct ata_port *ap; |
1da177e4 | 1740 | |
67846b30 JG |
1741 | if (!(irq_stat & (1 << i))) |
1742 | continue; | |
1743 | ||
cca3974e | 1744 | ap = host->ports[i]; |
67846b30 | 1745 | if (ap) { |
df69c9c5 | 1746 | ahci_port_intr(ap); |
67846b30 JG |
1747 | VPRINTK("port %u\n", i); |
1748 | } else { | |
1749 | VPRINTK("port %u (no irq)\n", i); | |
6971ed1f | 1750 | if (ata_ratelimit()) |
cca3974e | 1751 | dev_printk(KERN_WARNING, host->dev, |
a9524a76 | 1752 | "interrupt on disabled port %u\n", i); |
1da177e4 | 1753 | } |
67846b30 JG |
1754 | |
1755 | irq_ack |= (1 << i); | |
1da177e4 LT |
1756 | } |
1757 | ||
1758 | if (irq_ack) { | |
1759 | writel(irq_ack, mmio + HOST_IRQ_STAT); | |
1760 | handled = 1; | |
1761 | } | |
1762 | ||
cca3974e | 1763 | spin_unlock(&host->lock); |
1da177e4 LT |
1764 | |
1765 | VPRINTK("EXIT\n"); | |
1766 | ||
1767 | return IRQ_RETVAL(handled); | |
1768 | } | |
1769 | ||
9a3d9eb0 | 1770 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
1da177e4 LT |
1771 | { |
1772 | struct ata_port *ap = qc->ap; | |
4447d351 | 1773 | void __iomem *port_mmio = ahci_port_base(ap); |
7d50b60b TH |
1774 | struct ahci_port_priv *pp = ap->private_data; |
1775 | ||
1776 | /* Keep track of the currently active link. It will be used | |
1777 | * in completion path to determine whether NCQ phase is in | |
1778 | * progress. | |
1779 | */ | |
1780 | pp->active_link = qc->dev->link; | |
1da177e4 | 1781 | |
12fad3f9 TH |
1782 | if (qc->tf.protocol == ATA_PROT_NCQ) |
1783 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); | |
1784 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); | |
1da177e4 LT |
1785 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
1786 | ||
1787 | return 0; | |
1788 | } | |
1789 | ||
78cd52d0 TH |
1790 | static void ahci_freeze(struct ata_port *ap) |
1791 | { | |
4447d351 | 1792 | void __iomem *port_mmio = ahci_port_base(ap); |
78cd52d0 TH |
1793 | |
1794 | /* turn IRQ off */ | |
1795 | writel(0, port_mmio + PORT_IRQ_MASK); | |
1796 | } | |
1797 | ||
1798 | static void ahci_thaw(struct ata_port *ap) | |
1799 | { | |
0d5ff566 | 1800 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
4447d351 | 1801 | void __iomem *port_mmio = ahci_port_base(ap); |
78cd52d0 | 1802 | u32 tmp; |
a7384925 | 1803 | struct ahci_port_priv *pp = ap->private_data; |
78cd52d0 TH |
1804 | |
1805 | /* clear IRQ */ | |
1806 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1807 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
a718728f | 1808 | writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); |
78cd52d0 | 1809 | |
1c954a4d TH |
1810 | /* turn IRQ back on */ |
1811 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
78cd52d0 TH |
1812 | } |
1813 | ||
1814 | static void ahci_error_handler(struct ata_port *ap) | |
1815 | { | |
b51e9e5d | 1816 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
78cd52d0 | 1817 | /* restart engine */ |
4447d351 TH |
1818 | ahci_stop_engine(ap); |
1819 | ahci_start_engine(ap); | |
78cd52d0 TH |
1820 | } |
1821 | ||
1822 | /* perform recovery */ | |
7d50b60b TH |
1823 | sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset, |
1824 | ahci_hardreset, ahci_postreset, | |
1825 | sata_pmp_std_prereset, ahci_pmp_softreset, | |
1826 | sata_pmp_std_hardreset, sata_pmp_std_postreset); | |
78cd52d0 TH |
1827 | } |
1828 | ||
ad616ffb TH |
1829 | static void ahci_vt8251_error_handler(struct ata_port *ap) |
1830 | { | |
ad616ffb TH |
1831 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
1832 | /* restart engine */ | |
4447d351 TH |
1833 | ahci_stop_engine(ap); |
1834 | ahci_start_engine(ap); | |
ad616ffb TH |
1835 | } |
1836 | ||
1837 | /* perform recovery */ | |
1838 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset, | |
1839 | ahci_postreset); | |
1840 | } | |
1841 | ||
edc93052 TH |
1842 | static void ahci_p5wdh_error_handler(struct ata_port *ap) |
1843 | { | |
1844 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { | |
1845 | /* restart engine */ | |
1846 | ahci_stop_engine(ap); | |
1847 | ahci_start_engine(ap); | |
1848 | } | |
1849 | ||
1850 | /* perform recovery */ | |
1851 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset, | |
1852 | ahci_postreset); | |
1853 | } | |
1854 | ||
78cd52d0 TH |
1855 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
1856 | { | |
1857 | struct ata_port *ap = qc->ap; | |
1858 | ||
d2e75dff TH |
1859 | /* make DMA engine forget about the failed command */ |
1860 | if (qc->flags & ATA_QCFLAG_FAILED) | |
1861 | ahci_kick_engine(ap, 1); | |
78cd52d0 TH |
1862 | } |
1863 | ||
7d50b60b TH |
1864 | static void ahci_pmp_attach(struct ata_port *ap) |
1865 | { | |
1866 | void __iomem *port_mmio = ahci_port_base(ap); | |
1c954a4d | 1867 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
1868 | u32 cmd; |
1869 | ||
1870 | cmd = readl(port_mmio + PORT_CMD); | |
1871 | cmd |= PORT_CMD_PMP; | |
1872 | writel(cmd, port_mmio + PORT_CMD); | |
1c954a4d TH |
1873 | |
1874 | pp->intr_mask |= PORT_IRQ_BAD_PMP; | |
1875 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
7d50b60b TH |
1876 | } |
1877 | ||
1878 | static void ahci_pmp_detach(struct ata_port *ap) | |
1879 | { | |
1880 | void __iomem *port_mmio = ahci_port_base(ap); | |
1c954a4d | 1881 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
1882 | u32 cmd; |
1883 | ||
1884 | cmd = readl(port_mmio + PORT_CMD); | |
1885 | cmd &= ~PORT_CMD_PMP; | |
1886 | writel(cmd, port_mmio + PORT_CMD); | |
1c954a4d TH |
1887 | |
1888 | pp->intr_mask &= ~PORT_IRQ_BAD_PMP; | |
1889 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
7d50b60b TH |
1890 | } |
1891 | ||
028a2596 AD |
1892 | static int ahci_port_resume(struct ata_port *ap) |
1893 | { | |
1894 | ahci_power_up(ap); | |
1895 | ahci_start_port(ap); | |
1896 | ||
7d50b60b TH |
1897 | if (ap->nr_pmp_links) |
1898 | ahci_pmp_attach(ap); | |
1899 | else | |
1900 | ahci_pmp_detach(ap); | |
1901 | ||
028a2596 AD |
1902 | return 0; |
1903 | } | |
1904 | ||
438ac6d5 | 1905 | #ifdef CONFIG_PM |
c1332875 TH |
1906 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) |
1907 | { | |
c1332875 TH |
1908 | const char *emsg = NULL; |
1909 | int rc; | |
1910 | ||
4447d351 | 1911 | rc = ahci_deinit_port(ap, &emsg); |
8e16f941 | 1912 | if (rc == 0) |
4447d351 | 1913 | ahci_power_down(ap); |
8e16f941 | 1914 | else { |
c1332875 | 1915 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); |
df69c9c5 | 1916 | ahci_start_port(ap); |
c1332875 TH |
1917 | } |
1918 | ||
1919 | return rc; | |
1920 | } | |
1921 | ||
c1332875 TH |
1922 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
1923 | { | |
cca3974e | 1924 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
0d5ff566 | 1925 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
c1332875 TH |
1926 | u32 ctl; |
1927 | ||
1928 | if (mesg.event == PM_EVENT_SUSPEND) { | |
1929 | /* AHCI spec rev1.1 section 8.3.3: | |
1930 | * Software must disable interrupts prior to requesting a | |
1931 | * transition of the HBA to D3 state. | |
1932 | */ | |
1933 | ctl = readl(mmio + HOST_CTL); | |
1934 | ctl &= ~HOST_IRQ_EN; | |
1935 | writel(ctl, mmio + HOST_CTL); | |
1936 | readl(mmio + HOST_CTL); /* flush */ | |
1937 | } | |
1938 | ||
1939 | return ata_pci_device_suspend(pdev, mesg); | |
1940 | } | |
1941 | ||
1942 | static int ahci_pci_device_resume(struct pci_dev *pdev) | |
1943 | { | |
cca3974e | 1944 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
c1332875 TH |
1945 | int rc; |
1946 | ||
553c4aa6 TH |
1947 | rc = ata_pci_device_do_resume(pdev); |
1948 | if (rc) | |
1949 | return rc; | |
c1332875 TH |
1950 | |
1951 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
4447d351 | 1952 | rc = ahci_reset_controller(host); |
c1332875 TH |
1953 | if (rc) |
1954 | return rc; | |
1955 | ||
4447d351 | 1956 | ahci_init_controller(host); |
c1332875 TH |
1957 | } |
1958 | ||
cca3974e | 1959 | ata_host_resume(host); |
c1332875 TH |
1960 | |
1961 | return 0; | |
1962 | } | |
438ac6d5 | 1963 | #endif |
c1332875 | 1964 | |
254950cd TH |
1965 | static int ahci_port_start(struct ata_port *ap) |
1966 | { | |
cca3974e | 1967 | struct device *dev = ap->host->dev; |
254950cd | 1968 | struct ahci_port_priv *pp; |
254950cd TH |
1969 | void *mem; |
1970 | dma_addr_t mem_dma; | |
1971 | int rc; | |
1972 | ||
24dc5f33 | 1973 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
254950cd TH |
1974 | if (!pp) |
1975 | return -ENOMEM; | |
254950cd TH |
1976 | |
1977 | rc = ata_pad_alloc(ap, dev); | |
24dc5f33 | 1978 | if (rc) |
254950cd | 1979 | return rc; |
254950cd | 1980 | |
24dc5f33 TH |
1981 | mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, |
1982 | GFP_KERNEL); | |
1983 | if (!mem) | |
254950cd | 1984 | return -ENOMEM; |
254950cd TH |
1985 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
1986 | ||
1987 | /* | |
1988 | * First item in chunk of DMA memory: 32-slot command table, | |
1989 | * 32 bytes each in size | |
1990 | */ | |
1991 | pp->cmd_slot = mem; | |
1992 | pp->cmd_slot_dma = mem_dma; | |
1993 | ||
1994 | mem += AHCI_CMD_SLOT_SZ; | |
1995 | mem_dma += AHCI_CMD_SLOT_SZ; | |
1996 | ||
1997 | /* | |
1998 | * Second item: Received-FIS area | |
1999 | */ | |
2000 | pp->rx_fis = mem; | |
2001 | pp->rx_fis_dma = mem_dma; | |
2002 | ||
2003 | mem += AHCI_RX_FIS_SZ; | |
2004 | mem_dma += AHCI_RX_FIS_SZ; | |
2005 | ||
2006 | /* | |
2007 | * Third item: data area for storing a single command | |
2008 | * and its scatter-gather table | |
2009 | */ | |
2010 | pp->cmd_tbl = mem; | |
2011 | pp->cmd_tbl_dma = mem_dma; | |
2012 | ||
a7384925 | 2013 | /* |
2dcb407e JG |
2014 | * Save off initial list of interrupts to be enabled. |
2015 | * This could be changed later | |
2016 | */ | |
a7384925 KCA |
2017 | pp->intr_mask = DEF_PORT_IRQ; |
2018 | ||
254950cd TH |
2019 | ap->private_data = pp; |
2020 | ||
df69c9c5 JG |
2021 | /* engage engines, captain */ |
2022 | return ahci_port_resume(ap); | |
254950cd TH |
2023 | } |
2024 | ||
2025 | static void ahci_port_stop(struct ata_port *ap) | |
2026 | { | |
0be0aa98 TH |
2027 | const char *emsg = NULL; |
2028 | int rc; | |
254950cd | 2029 | |
0be0aa98 | 2030 | /* de-initialize port */ |
4447d351 | 2031 | rc = ahci_deinit_port(ap, &emsg); |
0be0aa98 TH |
2032 | if (rc) |
2033 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); | |
254950cd TH |
2034 | } |
2035 | ||
4447d351 | 2036 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
1da177e4 | 2037 | { |
1da177e4 | 2038 | int rc; |
1da177e4 | 2039 | |
1da177e4 LT |
2040 | if (using_dac && |
2041 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | |
2042 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
2043 | if (rc) { | |
2044 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
2045 | if (rc) { | |
a9524a76 JG |
2046 | dev_printk(KERN_ERR, &pdev->dev, |
2047 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
2048 | return rc; |
2049 | } | |
2050 | } | |
1da177e4 LT |
2051 | } else { |
2052 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
2053 | if (rc) { | |
a9524a76 JG |
2054 | dev_printk(KERN_ERR, &pdev->dev, |
2055 | "32-bit DMA enable failed\n"); | |
1da177e4 LT |
2056 | return rc; |
2057 | } | |
2058 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
2059 | if (rc) { | |
a9524a76 JG |
2060 | dev_printk(KERN_ERR, &pdev->dev, |
2061 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
2062 | return rc; |
2063 | } | |
2064 | } | |
1da177e4 LT |
2065 | return 0; |
2066 | } | |
2067 | ||
4447d351 | 2068 | static void ahci_print_info(struct ata_host *host) |
1da177e4 | 2069 | { |
4447d351 TH |
2070 | struct ahci_host_priv *hpriv = host->private_data; |
2071 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
2072 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
1da177e4 LT |
2073 | u32 vers, cap, impl, speed; |
2074 | const char *speed_s; | |
2075 | u16 cc; | |
2076 | const char *scc_s; | |
2077 | ||
2078 | vers = readl(mmio + HOST_VERSION); | |
2079 | cap = hpriv->cap; | |
2080 | impl = hpriv->port_map; | |
2081 | ||
2082 | speed = (cap >> 20) & 0xf; | |
2083 | if (speed == 1) | |
2084 | speed_s = "1.5"; | |
2085 | else if (speed == 2) | |
2086 | speed_s = "3"; | |
2087 | else | |
2088 | speed_s = "?"; | |
2089 | ||
2090 | pci_read_config_word(pdev, 0x0a, &cc); | |
c9f89475 | 2091 | if (cc == PCI_CLASS_STORAGE_IDE) |
1da177e4 | 2092 | scc_s = "IDE"; |
c9f89475 | 2093 | else if (cc == PCI_CLASS_STORAGE_SATA) |
1da177e4 | 2094 | scc_s = "SATA"; |
c9f89475 | 2095 | else if (cc == PCI_CLASS_STORAGE_RAID) |
1da177e4 LT |
2096 | scc_s = "RAID"; |
2097 | else | |
2098 | scc_s = "unknown"; | |
2099 | ||
a9524a76 JG |
2100 | dev_printk(KERN_INFO, &pdev->dev, |
2101 | "AHCI %02x%02x.%02x%02x " | |
1da177e4 | 2102 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
2dcb407e | 2103 | , |
1da177e4 | 2104 | |
2dcb407e JG |
2105 | (vers >> 24) & 0xff, |
2106 | (vers >> 16) & 0xff, | |
2107 | (vers >> 8) & 0xff, | |
2108 | vers & 0xff, | |
1da177e4 LT |
2109 | |
2110 | ((cap >> 8) & 0x1f) + 1, | |
2111 | (cap & 0x1f) + 1, | |
2112 | speed_s, | |
2113 | impl, | |
2114 | scc_s); | |
2115 | ||
a9524a76 JG |
2116 | dev_printk(KERN_INFO, &pdev->dev, |
2117 | "flags: " | |
203ef6c4 TH |
2118 | "%s%s%s%s%s%s%s" |
2119 | "%s%s%s%s%s%s%s\n" | |
2dcb407e | 2120 | , |
1da177e4 LT |
2121 | |
2122 | cap & (1 << 31) ? "64bit " : "", | |
2123 | cap & (1 << 30) ? "ncq " : "", | |
203ef6c4 | 2124 | cap & (1 << 29) ? "sntf " : "", |
1da177e4 LT |
2125 | cap & (1 << 28) ? "ilck " : "", |
2126 | cap & (1 << 27) ? "stag " : "", | |
2127 | cap & (1 << 26) ? "pm " : "", | |
2128 | cap & (1 << 25) ? "led " : "", | |
2129 | ||
2130 | cap & (1 << 24) ? "clo " : "", | |
2131 | cap & (1 << 19) ? "nz " : "", | |
2132 | cap & (1 << 18) ? "only " : "", | |
2133 | cap & (1 << 17) ? "pmp " : "", | |
2134 | cap & (1 << 15) ? "pio " : "", | |
2135 | cap & (1 << 14) ? "slum " : "", | |
2136 | cap & (1 << 13) ? "part " : "" | |
2137 | ); | |
2138 | } | |
2139 | ||
edc93052 TH |
2140 | /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is |
2141 | * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't | |
2142 | * support PMP and the 4726 either directly exports the device | |
2143 | * attached to the first downstream port or acts as a hardware storage | |
2144 | * controller and emulate a single ATA device (can be RAID 0/1 or some | |
2145 | * other configuration). | |
2146 | * | |
2147 | * When there's no device attached to the first downstream port of the | |
2148 | * 4726, "Config Disk" appears, which is a pseudo ATA device to | |
2149 | * configure the 4726. However, ATA emulation of the device is very | |
2150 | * lame. It doesn't send signature D2H Reg FIS after the initial | |
2151 | * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. | |
2152 | * | |
2153 | * The following function works around the problem by always using | |
2154 | * hardreset on the port and not depending on receiving signature FIS | |
2155 | * afterward. If signature FIS isn't received soon, ATA class is | |
2156 | * assumed without follow-up softreset. | |
2157 | */ | |
2158 | static void ahci_p5wdh_workaround(struct ata_host *host) | |
2159 | { | |
2160 | static struct dmi_system_id sysids[] = { | |
2161 | { | |
2162 | .ident = "P5W DH Deluxe", | |
2163 | .matches = { | |
2164 | DMI_MATCH(DMI_SYS_VENDOR, | |
2165 | "ASUSTEK COMPUTER INC"), | |
2166 | DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), | |
2167 | }, | |
2168 | }, | |
2169 | { } | |
2170 | }; | |
2171 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
2172 | ||
2173 | if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && | |
2174 | dmi_check_system(sysids)) { | |
2175 | struct ata_port *ap = host->ports[1]; | |
2176 | ||
2177 | dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH " | |
2178 | "Deluxe on-board SIMG4726 workaround\n"); | |
2179 | ||
2180 | ap->ops = &ahci_p5wdh_ops; | |
2181 | ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; | |
2182 | } | |
2183 | } | |
2184 | ||
24dc5f33 | 2185 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 LT |
2186 | { |
2187 | static int printed_version; | |
4447d351 TH |
2188 | struct ata_port_info pi = ahci_port_info[ent->driver_data]; |
2189 | const struct ata_port_info *ppi[] = { &pi, NULL }; | |
24dc5f33 | 2190 | struct device *dev = &pdev->dev; |
1da177e4 | 2191 | struct ahci_host_priv *hpriv; |
4447d351 TH |
2192 | struct ata_host *host; |
2193 | int i, rc; | |
1da177e4 LT |
2194 | |
2195 | VPRINTK("ENTER\n"); | |
2196 | ||
12fad3f9 TH |
2197 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
2198 | ||
1da177e4 | 2199 | if (!printed_version++) |
a9524a76 | 2200 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 2201 | |
4447d351 | 2202 | /* acquire resources */ |
24dc5f33 | 2203 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
2204 | if (rc) |
2205 | return rc; | |
2206 | ||
0d5ff566 TH |
2207 | rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); |
2208 | if (rc == -EBUSY) | |
24dc5f33 | 2209 | pcim_pin_device(pdev); |
0d5ff566 | 2210 | if (rc) |
24dc5f33 | 2211 | return rc; |
1da177e4 | 2212 | |
c4f7792c TH |
2213 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
2214 | (pdev->device == 0x2652 || pdev->device == 0x2653)) { | |
2215 | u8 map; | |
2216 | ||
2217 | /* ICH6s share the same PCI ID for both piix and ahci | |
2218 | * modes. Enabling ahci mode while MAP indicates | |
2219 | * combined mode is a bad idea. Yield to ata_piix. | |
2220 | */ | |
2221 | pci_read_config_byte(pdev, ICH_MAP, &map); | |
2222 | if (map & 0x3) { | |
2223 | dev_printk(KERN_INFO, &pdev->dev, "controller is in " | |
2224 | "combined mode, can't enable AHCI mode\n"); | |
2225 | return -ENODEV; | |
2226 | } | |
2227 | } | |
2228 | ||
24dc5f33 TH |
2229 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
2230 | if (!hpriv) | |
2231 | return -ENOMEM; | |
417a1a6d TH |
2232 | hpriv->flags |= (unsigned long)pi.private_data; |
2233 | ||
2234 | if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev)) | |
2235 | pci_intx(pdev, 1); | |
1da177e4 | 2236 | |
4447d351 | 2237 | /* save initial config */ |
417a1a6d | 2238 | ahci_save_initial_config(pdev, hpriv); |
1da177e4 | 2239 | |
4447d351 | 2240 | /* prepare host */ |
274c1fde | 2241 | if (hpriv->cap & HOST_CAP_NCQ) |
4447d351 | 2242 | pi.flags |= ATA_FLAG_NCQ; |
1da177e4 | 2243 | |
7d50b60b TH |
2244 | if (hpriv->cap & HOST_CAP_PMP) |
2245 | pi.flags |= ATA_FLAG_PMP; | |
2246 | ||
4447d351 TH |
2247 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map)); |
2248 | if (!host) | |
2249 | return -ENOMEM; | |
2250 | host->iomap = pcim_iomap_table(pdev); | |
2251 | host->private_data = hpriv; | |
2252 | ||
2253 | for (i = 0; i < host->n_ports; i++) { | |
dab632e8 JG |
2254 | struct ata_port *ap = host->ports[i]; |
2255 | void __iomem *port_mmio = ahci_port_base(ap); | |
4447d351 | 2256 | |
cbcdd875 TH |
2257 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar"); |
2258 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, | |
2259 | 0x100 + ap->port_no * 0x80, "port"); | |
2260 | ||
31556594 KCA |
2261 | /* set initial link pm policy */ |
2262 | ap->pm_policy = NOT_AVAILABLE; | |
2263 | ||
dab632e8 | 2264 | /* standard SATA port setup */ |
203ef6c4 | 2265 | if (hpriv->port_map & (1 << i)) |
4447d351 | 2266 | ap->ioaddr.cmd_addr = port_mmio; |
dab632e8 JG |
2267 | |
2268 | /* disabled/not-implemented port */ | |
2269 | else | |
2270 | ap->ops = &ata_dummy_port_ops; | |
4447d351 | 2271 | } |
d447df14 | 2272 | |
edc93052 TH |
2273 | /* apply workaround for ASUS P5W DH Deluxe mainboard */ |
2274 | ahci_p5wdh_workaround(host); | |
2275 | ||
4447d351 TH |
2276 | /* initialize adapter */ |
2277 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); | |
1da177e4 | 2278 | if (rc) |
24dc5f33 | 2279 | return rc; |
1da177e4 | 2280 | |
4447d351 TH |
2281 | rc = ahci_reset_controller(host); |
2282 | if (rc) | |
2283 | return rc; | |
1da177e4 | 2284 | |
4447d351 TH |
2285 | ahci_init_controller(host); |
2286 | ahci_print_info(host); | |
1da177e4 | 2287 | |
4447d351 TH |
2288 | pci_set_master(pdev); |
2289 | return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, | |
2290 | &ahci_sht); | |
907f4678 | 2291 | } |
1da177e4 LT |
2292 | |
2293 | static int __init ahci_init(void) | |
2294 | { | |
b7887196 | 2295 | return pci_register_driver(&ahci_pci_driver); |
1da177e4 LT |
2296 | } |
2297 | ||
1da177e4 LT |
2298 | static void __exit ahci_exit(void) |
2299 | { | |
2300 | pci_unregister_driver(&ahci_pci_driver); | |
2301 | } | |
2302 | ||
2303 | ||
2304 | MODULE_AUTHOR("Jeff Garzik"); | |
2305 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); | |
2306 | MODULE_LICENSE("GPL"); | |
2307 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); | |
6885433c | 2308 | MODULE_VERSION(DRV_VERSION); |
1da177e4 LT |
2309 | |
2310 | module_init(ahci_init); | |
2311 | module_exit(ahci_exit); |