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[PATCH] pci_module_init-convertion-in-ata_genericc fix
[deliverable/linux.git] / drivers / ata / libata-core.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * libata-core.c - helper library for ATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2004 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
1da177e4
LT		 33 */
34
1da177e4
LT		 35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/list.h>
40#include <linux/mm.h>
41#include <linux/highmem.h>
42#include <linux/spinlock.h>
43#include <linux/blkdev.h>
44#include <linux/delay.h>
45#include <linux/timer.h>
46#include <linux/interrupt.h>
47#include <linux/completion.h>
48#include <linux/suspend.h>
49#include <linux/workqueue.h>
67846b30 50#include <linux/jiffies.h>
378f058c 51#include <linux/scatterlist.h>
1da177e4 52#include <scsi/scsi.h>
193515d5 53#include <scsi/scsi_cmnd.h>
1da177e4
LT		 54#include <scsi/scsi_host.h>
55#include <linux/libata.h>
56#include <asm/io.h>
57#include <asm/semaphore.h>
58#include <asm/byteorder.h>
59
60#include "libata.h"
61
d7bb4cc7 62/* debounce timing parameters in msecs { interval, duration, timeout } */
e9c83914
TH		 63const unsigned long sata_deb_timing_normal[] = { 5, 100, 2000 };
64const unsigned long sata_deb_timing_hotplug[] = { 25, 500, 2000 };
65const unsigned long sata_deb_timing_long[] = { 100, 2000, 5000 };
d7bb4cc7 66
3373efd8
TH		 67static unsigned int ata_dev_init_params(struct ata_device *dev,
68 u16 heads, u16 sectors);
69static unsigned int ata_dev_set_xfermode(struct ata_device *dev);
70static void ata_dev_xfermask(struct ata_device *dev);
1da177e4
LT		 71
72static unsigned int ata_unique_id = 1;
73static struct workqueue_struct *ata_wq;
74
453b07ac
TH		 75struct workqueue_struct *ata_aux_wq;
76
418dc1f5 77int atapi_enabled = 1;
1623c81e
JG		 78module_param(atapi_enabled, int, 0444);
79MODULE_PARM_DESC(atapi_enabled, "Enable discovery of ATAPI devices (0=off, 1=on)");
80
95de719a
AL		 81int atapi_dmadir = 0;
82module_param(atapi_dmadir, int, 0444);
83MODULE_PARM_DESC(atapi_dmadir, "Enable ATAPI DMADIR bridge support (0=off, 1=on)");
84
c3c013a2
JG		 85int libata_fua = 0;
86module_param_named(fua, libata_fua, int, 0444);
87MODULE_PARM_DESC(fua, "FUA support (0=off, 1=on)");
88
a8601e5f
AM		 89static int ata_probe_timeout = ATA_TMOUT_INTERNAL / HZ;
90module_param(ata_probe_timeout, int, 0444);
91MODULE_PARM_DESC(ata_probe_timeout, "Set ATA probing timeout (seconds)");
92
1da177e4
LT		 93MODULE_AUTHOR("Jeff Garzik");
94MODULE_DESCRIPTION("Library module for ATA devices");
95MODULE_LICENSE("GPL");
96MODULE_VERSION(DRV_VERSION);
97
0baab86b 98
1da177e4
LT		 99/**
100 * ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure
101 * @tf: Taskfile to convert
102 * @fis: Buffer into which data will output
103 * @pmp: Port multiplier port
104 *
105 * Converts a standard ATA taskfile to a Serial ATA
106 * FIS structure (Register - Host to Device).
107 *
108 * LOCKING:
109 * Inherited from caller.
110 */
111
057ace5e 112void ata_tf_to_fis(const struct ata_taskfile *tf, u8 *fis, u8 pmp)
1da177e4
LT		 113{
114 fis[0] = 0x27; /* Register - Host to Device FIS */
115 fis[1] = (pmp & 0xf) | (1 << 7); /* Port multiplier number,
116 bit 7 indicates Command FIS */
117 fis[2] = tf->command;
118 fis[3] = tf->feature;
119
120 fis[4] = tf->lbal;
121 fis[5] = tf->lbam;
122 fis[6] = tf->lbah;
123 fis[7] = tf->device;
124
125 fis[8] = tf->hob_lbal;
126 fis[9] = tf->hob_lbam;
127 fis[10] = tf->hob_lbah;
128 fis[11] = tf->hob_feature;
129
130 fis[12] = tf->nsect;
131 fis[13] = tf->hob_nsect;
132 fis[14] = 0;
133 fis[15] = tf->ctl;
134
135 fis[16] = 0;
136 fis[17] = 0;
137 fis[18] = 0;
138 fis[19] = 0;
139}
140
141/**
142 * ata_tf_from_fis - Convert SATA FIS to ATA taskfile
143 * @fis: Buffer from which data will be input
144 * @tf: Taskfile to output
145 *
e12a1be6 146 * Converts a serial ATA FIS structure to a standard ATA taskfile.
1da177e4
LT		 147 *
148 * LOCKING:
149 * Inherited from caller.
150 */
151
057ace5e 152void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf)
1da177e4
LT		 153{
154 tf->command = fis[2]; /* status */
155 tf->feature = fis[3]; /* error */
156
157 tf->lbal = fis[4];
158 tf->lbam = fis[5];
159 tf->lbah = fis[6];
160 tf->device = fis[7];
161
162 tf->hob_lbal = fis[8];
163 tf->hob_lbam = fis[9];
164 tf->hob_lbah = fis[10];
165
166 tf->nsect = fis[12];
167 tf->hob_nsect = fis[13];
168}
169
8cbd6df1
AL		 170static const u8 ata_rw_cmds[] = {
171 /* pio multi */
172 ATA_CMD_READ_MULTI,
173 ATA_CMD_WRITE_MULTI,
174 ATA_CMD_READ_MULTI_EXT,
175 ATA_CMD_WRITE_MULTI_EXT,
9a3dccc4
TH		 176 0,
177 0,
178 0,
179 ATA_CMD_WRITE_MULTI_FUA_EXT,
8cbd6df1
AL		 180 /* pio */
181 ATA_CMD_PIO_READ,
182 ATA_CMD_PIO_WRITE,
183 ATA_CMD_PIO_READ_EXT,
184 ATA_CMD_PIO_WRITE_EXT,
9a3dccc4
TH		 185 0,
186 0,
187 0,
188 0,
8cbd6df1
AL		 189 /* dma */
190 ATA_CMD_READ,
191 ATA_CMD_WRITE,
192 ATA_CMD_READ_EXT,
9a3dccc4
TH		 193 ATA_CMD_WRITE_EXT,
194 0,
195 0,
196 0,
197 ATA_CMD_WRITE_FUA_EXT
8cbd6df1 198};
1da177e4
LT		 199
200/**
8cbd6df1
AL		 201 * ata_rwcmd_protocol - set taskfile r/w commands and protocol
202 * @qc: command to examine and configure
1da177e4 203 *
2e9edbf8 204 * Examine the device configuration and tf->flags to calculate
8cbd6df1 205 * the proper read/write commands and protocol to use.
1da177e4
LT		 206 *
207 * LOCKING:
208 * caller.
209 */
9a3dccc4 210int ata_rwcmd_protocol(struct ata_queued_cmd *qc)
1da177e4 211{
8cbd6df1
AL		 212 struct ata_taskfile *tf = &qc->tf;
213 struct ata_device *dev = qc->dev;
9a3dccc4 214 u8 cmd;
1da177e4 215
9a3dccc4 216 int index, fua, lba48, write;
2e9edbf8 217
9a3dccc4 218 fua = (tf->flags & ATA_TFLAG_FUA) ? 4 : 0;
8cbd6df1
AL		 219 lba48 = (tf->flags & ATA_TFLAG_LBA48) ? 2 : 0;
220 write = (tf->flags & ATA_TFLAG_WRITE) ? 1 : 0;
1da177e4 221
8cbd6df1
AL		 222 if (dev->flags & ATA_DFLAG_PIO) {
223 tf->protocol = ATA_PROT_PIO;
9a3dccc4 224 index = dev->multi_count ? 0 : 8;
8d238e01
AC		 225 } else if (lba48 && (qc->ap->flags & ATA_FLAG_PIO_LBA48)) {
226 /* Unable to use DMA due to host limitation */
227 tf->protocol = ATA_PROT_PIO;
0565c26d 228 index = dev->multi_count ? 0 : 8;
8cbd6df1
AL		 229 } else {
230 tf->protocol = ATA_PROT_DMA;
9a3dccc4 231 index = 16;
8cbd6df1 232 }
1da177e4 233
9a3dccc4
TH		 234 cmd = ata_rw_cmds[index + fua + lba48 + write];
235 if (cmd) {
236 tf->command = cmd;
237 return 0;
238 }
239 return -1;
1da177e4
LT		 240}
241
cb95d562
TH		 242/**
243 * ata_pack_xfermask - Pack pio, mwdma and udma masks into xfer_mask
244 * @pio_mask: pio_mask
245 * @mwdma_mask: mwdma_mask
246 * @udma_mask: udma_mask
247 *
248 * Pack @pio_mask, @mwdma_mask and @udma_mask into a single
249 * unsigned int xfer_mask.
250 *
251 * LOCKING:
252 * None.
253 *
254 * RETURNS:
255 * Packed xfer_mask.
256 */
257static unsigned int ata_pack_xfermask(unsigned int pio_mask,
258 unsigned int mwdma_mask,
259 unsigned int udma_mask)
260{
261 return ((pio_mask << ATA_SHIFT_PIO) & ATA_MASK_PIO) |
262 ((mwdma_mask << ATA_SHIFT_MWDMA) & ATA_MASK_MWDMA) |
263 ((udma_mask << ATA_SHIFT_UDMA) & ATA_MASK_UDMA);
264}
265
c0489e4e
TH		 266/**
267 * ata_unpack_xfermask - Unpack xfer_mask into pio, mwdma and udma masks
268 * @xfer_mask: xfer_mask to unpack
269 * @pio_mask: resulting pio_mask
270 * @mwdma_mask: resulting mwdma_mask
271 * @udma_mask: resulting udma_mask
272 *
273 * Unpack @xfer_mask into @pio_mask, @mwdma_mask and @udma_mask.
274 * Any NULL distination masks will be ignored.
275 */
276static void ata_unpack_xfermask(unsigned int xfer_mask,
277 unsigned int *pio_mask,
278 unsigned int *mwdma_mask,
279 unsigned int *udma_mask)
280{
281 if (pio_mask)
282 *pio_mask = (xfer_mask & ATA_MASK_PIO) >> ATA_SHIFT_PIO;
283 if (mwdma_mask)
284 *mwdma_mask = (xfer_mask & ATA_MASK_MWDMA) >> ATA_SHIFT_MWDMA;
285 if (udma_mask)
286 *udma_mask = (xfer_mask & ATA_MASK_UDMA) >> ATA_SHIFT_UDMA;
287}
288
cb95d562 289static const struct ata_xfer_ent {
be9a50c8 290 int shift, bits;
cb95d562
TH		 291 u8 base;
292} ata_xfer_tbl[] = {
293 { ATA_SHIFT_PIO, ATA_BITS_PIO, XFER_PIO_0 },
294 { ATA_SHIFT_MWDMA, ATA_BITS_MWDMA, XFER_MW_DMA_0 },
295 { ATA_SHIFT_UDMA, ATA_BITS_UDMA, XFER_UDMA_0 },
296 { -1, },
297};
298
299/**
300 * ata_xfer_mask2mode - Find matching XFER_* for the given xfer_mask
301 * @xfer_mask: xfer_mask of interest
302 *
303 * Return matching XFER_* value for @xfer_mask. Only the highest
304 * bit of @xfer_mask is considered.
305 *
306 * LOCKING:
307 * None.
308 *
309 * RETURNS:
310 * Matching XFER_* value, 0 if no match found.
311 */
312static u8 ata_xfer_mask2mode(unsigned int xfer_mask)
313{
314 int highbit = fls(xfer_mask) - 1;
315 const struct ata_xfer_ent *ent;
316
317 for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
318 if (highbit >= ent->shift && highbit < ent->shift + ent->bits)
319 return ent->base + highbit - ent->shift;
320 return 0;
321}
322
323/**
324 * ata_xfer_mode2mask - Find matching xfer_mask for XFER_*
325 * @xfer_mode: XFER_* of interest
326 *
327 * Return matching xfer_mask for @xfer_mode.
328 *
329 * LOCKING:
330 * None.
331 *
332 * RETURNS:
333 * Matching xfer_mask, 0 if no match found.
334 */
335static unsigned int ata_xfer_mode2mask(u8 xfer_mode)
336{
337 const struct ata_xfer_ent *ent;
338
339 for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
340 if (xfer_mode >= ent->base && xfer_mode < ent->base + ent->bits)
341 return 1 << (ent->shift + xfer_mode - ent->base);
342 return 0;
343}
344
345/**
346 * ata_xfer_mode2shift - Find matching xfer_shift for XFER_*
347 * @xfer_mode: XFER_* of interest
348 *
349 * Return matching xfer_shift for @xfer_mode.
350 *
351 * LOCKING:
352 * None.
353 *
354 * RETURNS:
355 * Matching xfer_shift, -1 if no match found.
356 */
357static int ata_xfer_mode2shift(unsigned int xfer_mode)
358{
359 const struct ata_xfer_ent *ent;
360
361 for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
362 if (xfer_mode >= ent->base && xfer_mode < ent->base + ent->bits)
363 return ent->shift;
364 return -1;
365}
366
1da177e4 367/**
1da7b0d0
TH		 368 * ata_mode_string - convert xfer_mask to string
369 * @xfer_mask: mask of bits supported; only highest bit counts.
1da177e4
LT		 370 *
371 * Determine string which represents the highest speed
1da7b0d0 372 * (highest bit in @modemask).
1da177e4
LT		 373 *
374 * LOCKING:
375 * None.
376 *
377 * RETURNS:
378 * Constant C string representing highest speed listed in
1da7b0d0 379 * @mode_mask, or the constant C string "<n/a>".
1da177e4 380 */
1da7b0d0 381static const char *ata_mode_string(unsigned int xfer_mask)
1da177e4 382{
75f554bc
TH		 383 static const char * const xfer_mode_str[] = {
384 "PIO0",
385 "PIO1",
386 "PIO2",
387 "PIO3",
388 "PIO4",
b352e57d
AC		 389 "PIO5",
390 "PIO6",
75f554bc
TH		 391 "MWDMA0",
392 "MWDMA1",
393 "MWDMA2",
b352e57d
AC		 394 "MWDMA3",
395 "MWDMA4",
75f554bc
TH		 396 "UDMA/16",
397 "UDMA/25",
398 "UDMA/33",
399 "UDMA/44",
400 "UDMA/66",
401 "UDMA/100",
402 "UDMA/133",
403 "UDMA7",
404 };
1da7b0d0 405 int highbit;
1da177e4 406
1da7b0d0
TH		 407 highbit = fls(xfer_mask) - 1;
408 if (highbit >= 0 && highbit < ARRAY_SIZE(xfer_mode_str))
409 return xfer_mode_str[highbit];
1da177e4 410 return "<n/a>";
1da177e4
LT		 411}
412
4c360c81
TH		 413static const char *sata_spd_string(unsigned int spd)
414{
415 static const char * const spd_str[] = {
416 "1.5 Gbps",
417 "3.0 Gbps",
418 };
419
420 if (spd == 0 || (spd - 1) >= ARRAY_SIZE(spd_str))
421 return "<unknown>";
422 return spd_str[spd - 1];
423}
424
3373efd8 425void ata_dev_disable(struct ata_device *dev)
0b8efb0a 426{
0dd4b21f 427 if (ata_dev_enabled(dev) && ata_msg_drv(dev->ap)) {
f15a1daf 428 ata_dev_printk(dev, KERN_WARNING, "disabled\n");
0b8efb0a
TH		 429 dev->class++;
430 }
431}
432
1da177e4
LT		 433/**
434 * ata_pio_devchk - PATA device presence detection
435 * @ap: ATA channel to examine
436 * @device: Device to examine (starting at zero)
437 *
438 * This technique was originally described in
439 * Hale Landis's ATADRVR (www.ata-atapi.com), and
440 * later found its way into the ATA/ATAPI spec.
441 *
442 * Write a pattern to the ATA shadow registers,
443 * and if a device is present, it will respond by
444 * correctly storing and echoing back the
445 * ATA shadow register contents.
446 *
447 * LOCKING:
448 * caller.
449 */
450
451static unsigned int ata_pio_devchk(struct ata_port *ap,
452 unsigned int device)
453{
454 struct ata_ioports *ioaddr = &ap->ioaddr;
455 u8 nsect, lbal;
456
457 ap->ops->dev_select(ap, device);
458
459 outb(0x55, ioaddr->nsect_addr);
460 outb(0xaa, ioaddr->lbal_addr);
461
462 outb(0xaa, ioaddr->nsect_addr);
463 outb(0x55, ioaddr->lbal_addr);
464
465 outb(0x55, ioaddr->nsect_addr);
466 outb(0xaa, ioaddr->lbal_addr);
467
468 nsect = inb(ioaddr->nsect_addr);
469 lbal = inb(ioaddr->lbal_addr);
470
471 if ((nsect == 0x55) && (lbal == 0xaa))
472 return 1; /* we found a device */
473
474 return 0; /* nothing found */
475}
476
477/**
478 * ata_mmio_devchk - PATA device presence detection
479 * @ap: ATA channel to examine
480 * @device: Device to examine (starting at zero)
481 *
482 * This technique was originally described in
483 * Hale Landis's ATADRVR (www.ata-atapi.com), and
484 * later found its way into the ATA/ATAPI spec.
485 *
486 * Write a pattern to the ATA shadow registers,
487 * and if a device is present, it will respond by
488 * correctly storing and echoing back the
489 * ATA shadow register contents.
490 *
491 * LOCKING:
492 * caller.
493 */
494
495static unsigned int ata_mmio_devchk(struct ata_port *ap,
496 unsigned int device)
497{
498 struct ata_ioports *ioaddr = &ap->ioaddr;
499 u8 nsect, lbal;
500
501 ap->ops->dev_select(ap, device);
502
503 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
504 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
505
506 writeb(0xaa, (void __iomem *) ioaddr->nsect_addr);
507 writeb(0x55, (void __iomem *) ioaddr->lbal_addr);
508
509 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
510 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
511
512 nsect = readb((void __iomem *) ioaddr->nsect_addr);
513 lbal = readb((void __iomem *) ioaddr->lbal_addr);
514
515 if ((nsect == 0x55) && (lbal == 0xaa))
516 return 1; /* we found a device */
517
518 return 0; /* nothing found */
519}
520
521/**
522 * ata_devchk - PATA device presence detection
523 * @ap: ATA channel to examine
524 * @device: Device to examine (starting at zero)
525 *
526 * Dispatch ATA device presence detection, depending
527 * on whether we are using PIO or MMIO to talk to the
528 * ATA shadow registers.
529 *
530 * LOCKING:
531 * caller.
532 */
533
534static unsigned int ata_devchk(struct ata_port *ap,
535 unsigned int device)
536{
537 if (ap->flags & ATA_FLAG_MMIO)
538 return ata_mmio_devchk(ap, device);
539 return ata_pio_devchk(ap, device);
540}
541
542/**
543 * ata_dev_classify - determine device type based on ATA-spec signature
544 * @tf: ATA taskfile register set for device to be identified
545 *
546 * Determine from taskfile register contents whether a device is
547 * ATA or ATAPI, as per "Signature and persistence" section
548 * of ATA/PI spec (volume 1, sect 5.14).
549 *
550 * LOCKING:
551 * None.
552 *
553 * RETURNS:
554 * Device type, %ATA_DEV_ATA, %ATA_DEV_ATAPI, or %ATA_DEV_UNKNOWN
555 * the event of failure.
556 */
557
057ace5e 558unsigned int ata_dev_classify(const struct ata_taskfile *tf)
1da177e4
LT		 559{
560 /* Apple's open source Darwin code hints that some devices only
561 * put a proper signature into the LBA mid/high registers,
562 * So, we only check those. It's sufficient for uniqueness.
563 */
564
565 if (((tf->lbam == 0) && (tf->lbah == 0)) ||
566 ((tf->lbam == 0x3c) && (tf->lbah == 0xc3))) {
567 DPRINTK("found ATA device by sig\n");
568 return ATA_DEV_ATA;
569 }
570
571 if (((tf->lbam == 0x14) && (tf->lbah == 0xeb)) ||
572 ((tf->lbam == 0x69) && (tf->lbah == 0x96))) {
573 DPRINTK("found ATAPI device by sig\n");
574 return ATA_DEV_ATAPI;
575 }
576
577 DPRINTK("unknown device\n");
578 return ATA_DEV_UNKNOWN;
579}
580
581/**
582 * ata_dev_try_classify - Parse returned ATA device signature
583 * @ap: ATA channel to examine
584 * @device: Device to examine (starting at zero)
b4dc7623 585 * @r_err: Value of error register on completion
1da177e4
LT		 586 *
587 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
588 * an ATA/ATAPI-defined set of values is placed in the ATA
589 * shadow registers, indicating the results of device detection
590 * and diagnostics.
591 *
592 * Select the ATA device, and read the values from the ATA shadow
593 * registers. Then parse according to the Error register value,
594 * and the spec-defined values examined by ata_dev_classify().
595 *
596 * LOCKING:
597 * caller.
b4dc7623
TH		 598 *
599 * RETURNS:
600 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1da177e4
LT		 601 */
602
b4dc7623
TH		 603static unsigned int
604ata_dev_try_classify(struct ata_port *ap, unsigned int device, u8 *r_err)
1da177e4 605{
1da177e4
LT		 606 struct ata_taskfile tf;
607 unsigned int class;
608 u8 err;
609
610 ap->ops->dev_select(ap, device);
611
612 memset(&tf, 0, sizeof(tf));
613
1da177e4 614 ap->ops->tf_read(ap, &tf);
0169e284 615 err = tf.feature;
b4dc7623
TH		 616 if (r_err)
617 *r_err = err;
1da177e4 618
93590859
AC		 619 /* see if device passed diags: if master then continue and warn later */
620 if (err == 0 && device == 0)
621 /* diagnostic fail : do nothing _YET_ */
622 ap->device[device].horkage |= ATA_HORKAGE_DIAGNOSTIC;
623 else if (err == 1)
1da177e4
LT		 624 /* do nothing */ ;
625 else if ((device == 0) && (err == 0x81))
626 /* do nothing */ ;
627 else
b4dc7623 628 return ATA_DEV_NONE;
1da177e4 629
b4dc7623 630 /* determine if device is ATA or ATAPI */
1da177e4 631 class = ata_dev_classify(&tf);
b4dc7623 632
1da177e4 633 if (class == ATA_DEV_UNKNOWN)
b4dc7623 634 return ATA_DEV_NONE;
1da177e4 635 if ((class == ATA_DEV_ATA) && (ata_chk_status(ap) == 0))
b4dc7623
TH		 636 return ATA_DEV_NONE;
637 return class;
1da177e4
LT		 638}
639
640/**
6a62a04d 641 * ata_id_string - Convert IDENTIFY DEVICE page into string
1da177e4
LT		 642 * @id: IDENTIFY DEVICE results we will examine
643 * @s: string into which data is output
644 * @ofs: offset into identify device page
645 * @len: length of string to return. must be an even number.
646 *
647 * The strings in the IDENTIFY DEVICE page are broken up into
648 * 16-bit chunks. Run through the string, and output each
649 * 8-bit chunk linearly, regardless of platform.
650 *
651 * LOCKING:
652 * caller.
653 */
654
6a62a04d
TH		 655void ata_id_string(const u16 *id, unsigned char *s,
656 unsigned int ofs, unsigned int len)
1da177e4
LT		 657{
658 unsigned int c;
659
660 while (len > 0) {
661 c = id[ofs] >> 8;
662 *s = c;
663 s++;
664
665 c = id[ofs] & 0xff;
666 *s = c;
667 s++;
668
669 ofs++;
670 len -= 2;
671 }
672}
673
0e949ff3 674/**
6a62a04d 675 * ata_id_c_string - Convert IDENTIFY DEVICE page into C string
0e949ff3
TH		 676 * @id: IDENTIFY DEVICE results we will examine
677 * @s: string into which data is output
678 * @ofs: offset into identify device page
679 * @len: length of string to return. must be an odd number.
680 *
6a62a04d 681 * This function is identical to ata_id_string except that it
0e949ff3
TH		 682 * trims trailing spaces and terminates the resulting string with
683 * null. @len must be actual maximum length (even number) + 1.
684 *
685 * LOCKING:
686 * caller.
687 */
6a62a04d
TH		 688void ata_id_c_string(const u16 *id, unsigned char *s,
689 unsigned int ofs, unsigned int len)
0e949ff3
TH		 690{
691 unsigned char *p;
692
693 WARN_ON(!(len & 1));
694
6a62a04d 695 ata_id_string(id, s, ofs, len - 1);
0e949ff3
TH		 696
697 p = s + strnlen(s, len - 1);
698 while (p > s && p[-1] == ' ')
699 p--;
700 *p = '\0';
701}
0baab86b 702
2940740b
TH		 703static u64 ata_id_n_sectors(const u16 *id)
704{
705 if (ata_id_has_lba(id)) {
706 if (ata_id_has_lba48(id))
707 return ata_id_u64(id, 100);
708 else
709 return ata_id_u32(id, 60);
710 } else {
711 if (ata_id_current_chs_valid(id))
712 return ata_id_u32(id, 57);
713 else
714 return id[1] * id[3] * id[6];
715 }
716}
717
0baab86b
EF		 718/**
719 * ata_noop_dev_select - Select device 0/1 on ATA bus
720 * @ap: ATA channel to manipulate
721 * @device: ATA device (numbered from zero) to select
722 *
723 * This function performs no actual function.
724 *
725 * May be used as the dev_select() entry in ata_port_operations.
726 *
727 * LOCKING:
728 * caller.
729 */
1da177e4
LT		 730void ata_noop_dev_select (struct ata_port *ap, unsigned int device)
731{
732}
733
0baab86b 734
1da177e4
LT		 735/**
736 * ata_std_dev_select - Select device 0/1 on ATA bus
737 * @ap: ATA channel to manipulate
738 * @device: ATA device (numbered from zero) to select
739 *
740 * Use the method defined in the ATA specification to
741 * make either device 0, or device 1, active on the
0baab86b
EF		 742 * ATA channel. Works with both PIO and MMIO.
743 *
744 * May be used as the dev_select() entry in ata_port_operations.
1da177e4
LT		 745 *
746 * LOCKING:
747 * caller.
748 */
749
750void ata_std_dev_select (struct ata_port *ap, unsigned int device)
751{
752 u8 tmp;
753
754 if (device == 0)
755 tmp = ATA_DEVICE_OBS;
756 else
757 tmp = ATA_DEVICE_OBS | ATA_DEV1;
758
759 if (ap->flags & ATA_FLAG_MMIO) {
760 writeb(tmp, (void __iomem *) ap->ioaddr.device_addr);
761 } else {
762 outb(tmp, ap->ioaddr.device_addr);
763 }
764 ata_pause(ap); /* needed; also flushes, for mmio */
765}
766
767/**
768 * ata_dev_select - Select device 0/1 on ATA bus
769 * @ap: ATA channel to manipulate
770 * @device: ATA device (numbered from zero) to select
771 * @wait: non-zero to wait for Status register BSY bit to clear
772 * @can_sleep: non-zero if context allows sleeping
773 *
774 * Use the method defined in the ATA specification to
775 * make either device 0, or device 1, active on the
776 * ATA channel.
777 *
778 * This is a high-level version of ata_std_dev_select(),
779 * which additionally provides the services of inserting
780 * the proper pauses and status polling, where needed.
781 *
782 * LOCKING:
783 * caller.
784 */
785
786void ata_dev_select(struct ata_port *ap, unsigned int device,
787 unsigned int wait, unsigned int can_sleep)
788{
88574551 789 if (ata_msg_probe(ap))
0dd4b21f 790 ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, ata%u: "
88574551 791 "device %u, wait %u\n", ap->id, device, wait);
1da177e4
LT		 792
793 if (wait)
794 ata_wait_idle(ap);
795
796 ap->ops->dev_select(ap, device);
797
798 if (wait) {
799 if (can_sleep && ap->device[device].class == ATA_DEV_ATAPI)
800 msleep(150);
801 ata_wait_idle(ap);
802 }
803}
804
805/**
806 * ata_dump_id - IDENTIFY DEVICE info debugging output
0bd3300a 807 * @id: IDENTIFY DEVICE page to dump
1da177e4 808 *
0bd3300a
TH		 809 * Dump selected 16-bit words from the given IDENTIFY DEVICE
810 * page.
1da177e4
LT		 811 *
812 * LOCKING:
813 * caller.
814 */
815
0bd3300a 816static inline void ata_dump_id(const u16 *id)
1da177e4
LT		 817{
818 DPRINTK("49==0x%04x "
819 "53==0x%04x "
820 "63==0x%04x "
821 "64==0x%04x "
822 "75==0x%04x \n",
0bd3300a
TH		 823 id[49],
824 id[53],
825 id[63],
826 id[64],
827 id[75]);
1da177e4
LT		 828 DPRINTK("80==0x%04x "
829 "81==0x%04x "
830 "82==0x%04x "
831 "83==0x%04x "
832 "84==0x%04x \n",
0bd3300a
TH		 833 id[80],
834 id[81],
835 id[82],
836 id[83],
837 id[84]);
1da177e4
LT		 838 DPRINTK("88==0x%04x "
839 "93==0x%04x\n",
0bd3300a
TH		 840 id[88],
841 id[93]);
1da177e4
LT		 842}
843
cb95d562
TH		 844/**
845 * ata_id_xfermask - Compute xfermask from the given IDENTIFY data
846 * @id: IDENTIFY data to compute xfer mask from
847 *
848 * Compute the xfermask for this device. This is not as trivial
849 * as it seems if we must consider early devices correctly.
850 *
851 * FIXME: pre IDE drive timing (do we care ?).
852 *
853 * LOCKING:
854 * None.
855 *
856 * RETURNS:
857 * Computed xfermask
858 */
859static unsigned int ata_id_xfermask(const u16 *id)
860{
861 unsigned int pio_mask, mwdma_mask, udma_mask;
862
863 /* Usual case. Word 53 indicates word 64 is valid */
864 if (id[ATA_ID_FIELD_VALID] & (1 << 1)) {
865 pio_mask = id[ATA_ID_PIO_MODES] & 0x03;
866 pio_mask <<= 3;
867 pio_mask |= 0x7;
868 } else {
869 /* If word 64 isn't valid then Word 51 high byte holds
870 * the PIO timing number for the maximum. Turn it into
871 * a mask.
872 */
46767aeb
AC		 873 u8 mode = id[ATA_ID_OLD_PIO_MODES] & 0xFF;
874 if (mode < 5) /* Valid PIO range */
875 pio_mask = (2 << mode) - 1;
876 else
877 pio_mask = 1;
cb95d562
TH		 878
879 /* But wait.. there's more. Design your standards by
880 * committee and you too can get a free iordy field to
881 * process. However its the speeds not the modes that
882 * are supported... Note drivers using the timing API
883 * will get this right anyway
884 */
885 }
886
887 mwdma_mask = id[ATA_ID_MWDMA_MODES] & 0x07;
fb21f0d0 888
b352e57d
AC		 889 if (ata_id_is_cfa(id)) {
890 /*
891 * Process compact flash extended modes
892 */
893 int pio = id[163] & 0x7;
894 int dma = (id[163] >> 3) & 7;
895
896 if (pio)
897 pio_mask |= (1 << 5);
898 if (pio > 1)
899 pio_mask |= (1 << 6);
900 if (dma)
901 mwdma_mask |= (1 << 3);
902 if (dma > 1)
903 mwdma_mask |= (1 << 4);
904 }
905
fb21f0d0
TH		 906 udma_mask = 0;
907 if (id[ATA_ID_FIELD_VALID] & (1 << 2))
908 udma_mask = id[ATA_ID_UDMA_MODES] & 0xff;
cb95d562
TH		 909
910 return ata_pack_xfermask(pio_mask, mwdma_mask, udma_mask);
911}
912
86e45b6b
TH		 913/**
914 * ata_port_queue_task - Queue port_task
915 * @ap: The ata_port to queue port_task for
e2a7f77a
RD		 916 * @fn: workqueue function to be scheduled
917 * @data: data value to pass to workqueue function
918 * @delay: delay time for workqueue function
86e45b6b
TH		 919 *
920 * Schedule @fn(@data) for execution after @delay jiffies using
921 * port_task. There is one port_task per port and it's the
922 * user(low level driver)'s responsibility to make sure that only
923 * one task is active at any given time.
924 *
925 * libata core layer takes care of synchronization between
926 * port_task and EH. ata_port_queue_task() may be ignored for EH
927 * synchronization.
928 *
929 * LOCKING:
930 * Inherited from caller.
931 */
932void ata_port_queue_task(struct ata_port *ap, void (*fn)(void *), void *data,
933 unsigned long delay)
934{
935 int rc;
936
b51e9e5d 937 if (ap->pflags & ATA_PFLAG_FLUSH_PORT_TASK)
86e45b6b
TH		 938 return;
939
940 PREPARE_WORK(&ap->port_task, fn, data);
941
942 if (!delay)
943 rc = queue_work(ata_wq, &ap->port_task);
944 else
945 rc = queue_delayed_work(ata_wq, &ap->port_task, delay);
946
947 /* rc == 0 means that another user is using port task */
948 WARN_ON(rc == 0);
949}
950
951/**
952 * ata_port_flush_task - Flush port_task
953 * @ap: The ata_port to flush port_task for
954 *
955 * After this function completes, port_task is guranteed not to
956 * be running or scheduled.
957 *
958 * LOCKING:
959 * Kernel thread context (may sleep)
960 */
961void ata_port_flush_task(struct ata_port *ap)
962{
963 unsigned long flags;
964
965 DPRINTK("ENTER\n");
966
ba6a1308 967 spin_lock_irqsave(ap->lock, flags);
b51e9e5d 968 ap->pflags |= ATA_PFLAG_FLUSH_PORT_TASK;
ba6a1308 969 spin_unlock_irqrestore(ap->lock, flags);
86e45b6b
TH		 970
971 DPRINTK("flush #1\n");
972 flush_workqueue(ata_wq);
973
974 /*
975 * At this point, if a task is running, it's guaranteed to see
976 * the FLUSH flag; thus, it will never queue pio tasks again.
977 * Cancel and flush.
978 */
979 if (!cancel_delayed_work(&ap->port_task)) {
0dd4b21f 980 if (ata_msg_ctl(ap))
88574551
TH		 981 ata_port_printk(ap, KERN_DEBUG, "%s: flush #2\n",
982 __FUNCTION__);
86e45b6b
TH		 983 flush_workqueue(ata_wq);
984 }
985
ba6a1308 986 spin_lock_irqsave(ap->lock, flags);
b51e9e5d 987 ap->pflags &= ~ATA_PFLAG_FLUSH_PORT_TASK;
ba6a1308 988 spin_unlock_irqrestore(ap->lock, flags);
86e45b6b 989
0dd4b21f
BP		 990 if (ata_msg_ctl(ap))
991 ata_port_printk(ap, KERN_DEBUG, "%s: EXIT\n", __FUNCTION__);
86e45b6b
TH		 992}
993
77853bf2 994void ata_qc_complete_internal(struct ata_queued_cmd *qc)
a2a7a662 995{
77853bf2 996 struct completion *waiting = qc->private_data;
a2a7a662 997
a2a7a662 998 complete(waiting);
a2a7a662
TH		 999}
1000
1001/**
1002 * ata_exec_internal - execute libata internal command
a2a7a662
TH		 1003 * @dev: Device to which the command is sent
1004 * @tf: Taskfile registers for the command and the result
d69cf37d 1005 * @cdb: CDB for packet command
a2a7a662
TH		 1006 * @dma_dir: Data tranfer direction of the command
1007 * @buf: Data buffer of the command
1008 * @buflen: Length of data buffer
1009 *
1010 * Executes libata internal command with timeout. @tf contains
1011 * command on entry and result on return. Timeout and error
1012 * conditions are reported via return value. No recovery action
1013 * is taken after a command times out. It's caller's duty to
1014 * clean up after timeout.
1015 *
1016 * LOCKING:
1017 * None. Should be called with kernel context, might sleep.
551e8889
TH		 1018 *
1019 * RETURNS:
1020 * Zero on success, AC_ERR_* mask on failure
a2a7a662 1021 */
3373efd8 1022unsigned ata_exec_internal(struct ata_device *dev,
1ad8e7f9
TH		 1023 struct ata_taskfile *tf, const u8 *cdb,
1024 int dma_dir, void *buf, unsigned int buflen)
a2a7a662 1025{
3373efd8 1026 struct ata_port *ap = dev->ap;
a2a7a662
TH		 1027 u8 command = tf->command;
1028 struct ata_queued_cmd *qc;
2ab7db1f 1029 unsigned int tag, preempted_tag;
dedaf2b0 1030 u32 preempted_sactive, preempted_qc_active;
60be6b9a 1031 DECLARE_COMPLETION_ONSTACK(wait);
a2a7a662 1032 unsigned long flags;
77853bf2 1033 unsigned int err_mask;
d95a717f 1034 int rc;
a2a7a662 1035
ba6a1308 1036 spin_lock_irqsave(ap->lock, flags);
a2a7a662 1037
e3180499 1038 /* no internal command while frozen */
b51e9e5d 1039 if (ap->pflags & ATA_PFLAG_FROZEN) {
ba6a1308 1040 spin_unlock_irqrestore(ap->lock, flags);
e3180499
TH		 1041 return AC_ERR_SYSTEM;
1042 }
1043
2ab7db1f 1044 /* initialize internal qc */
a2a7a662 1045
2ab7db1f
TH		 1046 /* XXX: Tag 0 is used for drivers with legacy EH as some
1047 * drivers choke if any other tag is given. This breaks
1048 * ata_tag_internal() test for those drivers. Don't use new
1049 * EH stuff without converting to it.
1050 */
1051 if (ap->ops->error_handler)
1052 tag = ATA_TAG_INTERNAL;
1053 else
1054 tag = 0;
1055
6cec4a39 1056 if (test_and_set_bit(tag, &ap->qc_allocated))
2ab7db1f 1057 BUG();
f69499f4 1058 qc = __ata_qc_from_tag(ap, tag);
2ab7db1f
TH		 1059
1060 qc->tag = tag;
1061 qc->scsicmd = NULL;
1062 qc->ap = ap;
1063 qc->dev = dev;
1064 ata_qc_reinit(qc);
1065
1066 preempted_tag = ap->active_tag;
dedaf2b0
TH		 1067 preempted_sactive = ap->sactive;
1068 preempted_qc_active = ap->qc_active;
2ab7db1f 1069 ap->active_tag = ATA_TAG_POISON;
dedaf2b0
TH		 1070 ap->sactive = 0;
1071 ap->qc_active = 0;
2ab7db1f
TH		 1072
1073 /* prepare & issue qc */
a2a7a662 1074 qc->tf = *tf;
d69cf37d
TH		 1075 if (cdb)
1076 memcpy(qc->cdb, cdb, ATAPI_CDB_LEN);
e61e0672 1077 qc->flags |= ATA_QCFLAG_RESULT_TF;
a2a7a662
TH		 1078 qc->dma_dir = dma_dir;
1079 if (dma_dir != DMA_NONE) {
1080 ata_sg_init_one(qc, buf, buflen);
1081 qc->nsect = buflen / ATA_SECT_SIZE;
1082 }
1083
77853bf2 1084 qc->private_data = &wait;
a2a7a662
TH		 1085 qc->complete_fn = ata_qc_complete_internal;
1086
8e0e694a 1087 ata_qc_issue(qc);
a2a7a662 1088
ba6a1308 1089 spin_unlock_irqrestore(ap->lock, flags);
a2a7a662 1090
a8601e5f 1091 rc = wait_for_completion_timeout(&wait, ata_probe_timeout);
d95a717f
TH		 1092
1093 ata_port_flush_task(ap);
41ade50c 1094
d95a717f 1095 if (!rc) {
ba6a1308 1096 spin_lock_irqsave(ap->lock, flags);
a2a7a662
TH		 1097
1098 /* We're racing with irq here. If we lose, the
1099 * following test prevents us from completing the qc
d95a717f
TH		 1100 * twice. If we win, the port is frozen and will be
1101 * cleaned up by ->post_internal_cmd().
a2a7a662 1102 */
77853bf2 1103 if (qc->flags & ATA_QCFLAG_ACTIVE) {
d95a717f
TH		 1104 qc->err_mask |= AC_ERR_TIMEOUT;
1105
1106 if (ap->ops->error_handler)
1107 ata_port_freeze(ap);
1108 else
1109 ata_qc_complete(qc);
f15a1daf 1110
0dd4b21f
BP		 1111 if (ata_msg_warn(ap))
1112 ata_dev_printk(dev, KERN_WARNING,
88574551 1113 "qc timeout (cmd 0x%x)\n", command);
a2a7a662
TH		 1114 }
1115
ba6a1308 1116 spin_unlock_irqrestore(ap->lock, flags);
a2a7a662
TH		 1117 }
1118
d95a717f
TH		 1119 /* do post_internal_cmd */
1120 if (ap->ops->post_internal_cmd)
1121 ap->ops->post_internal_cmd(qc);
1122
1123 if (qc->flags & ATA_QCFLAG_FAILED && !qc->err_mask) {
0dd4b21f 1124 if (ata_msg_warn(ap))
88574551 1125 ata_dev_printk(dev, KERN_WARNING,
0dd4b21f 1126 "zero err_mask for failed "
88574551 1127 "internal command, assuming AC_ERR_OTHER\n");
d95a717f
TH		 1128 qc->err_mask |= AC_ERR_OTHER;
1129 }
1130
15869303 1131 /* finish up */
ba6a1308 1132 spin_lock_irqsave(ap->lock, flags);
15869303 1133
e61e0672 1134 *tf = qc->result_tf;
77853bf2
TH		 1135 err_mask = qc->err_mask;
1136
1137 ata_qc_free(qc);
2ab7db1f 1138 ap->active_tag = preempted_tag;
dedaf2b0
TH		 1139 ap->sactive = preempted_sactive;
1140 ap->qc_active = preempted_qc_active;
77853bf2 1141
1f7dd3e9
TH		 1142 /* XXX - Some LLDDs (sata_mv) disable port on command failure.
1143 * Until those drivers are fixed, we detect the condition
1144 * here, fail the command with AC_ERR_SYSTEM and reenable the
1145 * port.
1146 *
1147 * Note that this doesn't change any behavior as internal
1148 * command failure results in disabling the device in the
1149 * higher layer for LLDDs without new reset/EH callbacks.
1150 *
1151 * Kill the following code as soon as those drivers are fixed.
1152 */
198e0fed 1153 if (ap->flags & ATA_FLAG_DISABLED) {
1f7dd3e9
TH		 1154 err_mask |= AC_ERR_SYSTEM;
1155 ata_port_probe(ap);
1156 }
1157
ba6a1308 1158 spin_unlock_irqrestore(ap->lock, flags);
15869303 1159
77853bf2 1160 return err_mask;
a2a7a662
TH		 1161}
1162
977e6b9f
TH		 1163/**
1164 * ata_do_simple_cmd - execute simple internal command
1165 * @dev: Device to which the command is sent
1166 * @cmd: Opcode to execute
1167 *
1168 * Execute a 'simple' command, that only consists of the opcode
1169 * 'cmd' itself, without filling any other registers
1170 *
1171 * LOCKING:
1172 * Kernel thread context (may sleep).
1173 *
1174 * RETURNS:
1175 * Zero on success, AC_ERR_* mask on failure
e58eb583 1176 */
77b08fb5 1177unsigned int ata_do_simple_cmd(struct ata_device *dev, u8 cmd)
e58eb583
TH		 1178{
1179 struct ata_taskfile tf;
e58eb583
TH		 1180
1181 ata_tf_init(dev, &tf);
1182
1183 tf.command = cmd;
1184 tf.flags |= ATA_TFLAG_DEVICE;
1185 tf.protocol = ATA_PROT_NODATA;
1186
977e6b9f 1187 return ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0);
e58eb583
TH		 1188}
1189
1bc4ccff
AC		 1190/**
1191 * ata_pio_need_iordy - check if iordy needed
1192 * @adev: ATA device
1193 *
1194 * Check if the current speed of the device requires IORDY. Used
1195 * by various controllers for chip configuration.
1196 */
1197
1198unsigned int ata_pio_need_iordy(const struct ata_device *adev)
1199{
1200 int pio;
1201 int speed = adev->pio_mode - XFER_PIO_0;
1202
1203 if (speed < 2)
1204 return 0;
1205 if (speed > 2)
1206 return 1;
2e9edbf8 1207
1bc4ccff
AC		 1208 /* If we have no drive specific rule, then PIO 2 is non IORDY */
1209
1210 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE */
1211 pio = adev->id[ATA_ID_EIDE_PIO];
1212 /* Is the speed faster than the drive allows non IORDY ? */
1213 if (pio) {
1214 /* This is cycle times not frequency - watch the logic! */
1215 if (pio > 240) /* PIO2 is 240nS per cycle */
1216 return 1;
1217 return 0;
1218 }
1219 }
1220 return 0;
1221}
1222
1da177e4 1223/**
49016aca 1224 * ata_dev_read_id - Read ID data from the specified device
49016aca
TH		 1225 * @dev: target device
1226 * @p_class: pointer to class of the target device (may be changed)
1227 * @post_reset: is this read ID post-reset?
fe635c7e 1228 * @id: buffer to read IDENTIFY data into
1da177e4 1229 *
49016aca
TH		 1230 * Read ID data from the specified device. ATA_CMD_ID_ATA is
1231 * performed on ATA devices and ATA_CMD_ID_ATAPI on ATAPI
aec5c3c1
TH		 1232 * devices. This function also issues ATA_CMD_INIT_DEV_PARAMS
1233 * for pre-ATA4 drives.
1da177e4
LT		 1234 *
1235 * LOCKING:
49016aca
TH		 1236 * Kernel thread context (may sleep)
1237 *
1238 * RETURNS:
1239 * 0 on success, -errno otherwise.
1da177e4 1240 */
a9beec95
TH		 1241int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
1242 int post_reset, u16 *id)
1da177e4 1243{
3373efd8 1244 struct ata_port *ap = dev->ap;
49016aca 1245 unsigned int class = *p_class;
a0123703 1246 struct ata_taskfile tf;
49016aca
TH		 1247 unsigned int err_mask = 0;
1248 const char *reason;
1249 int rc;
1da177e4 1250
0dd4b21f 1251 if (ata_msg_ctl(ap))
88574551
TH		 1252 ata_dev_printk(dev, KERN_DEBUG, "%s: ENTER, host %u, dev %u\n",
1253 __FUNCTION__, ap->id, dev->devno);
1da177e4 1254
49016aca 1255 ata_dev_select(ap, dev->devno, 1, 1); /* select device 0/1 */
1da177e4 1256
49016aca 1257 retry:
3373efd8 1258 ata_tf_init(dev, &tf);
a0123703 1259
49016aca
TH		 1260 switch (class) {
1261 case ATA_DEV_ATA:
a0123703 1262 tf.command = ATA_CMD_ID_ATA;
49016aca
TH		 1263 break;
1264 case ATA_DEV_ATAPI:
a0123703 1265 tf.command = ATA_CMD_ID_ATAPI;
49016aca
TH		 1266 break;
1267 default:
1268 rc = -ENODEV;
1269 reason = "unsupported class";
1270 goto err_out;
1da177e4
LT		 1271 }
1272
a0123703 1273 tf.protocol = ATA_PROT_PIO;
1da177e4 1274
3373efd8 1275 err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE,
49016aca 1276 id, sizeof(id[0]) * ATA_ID_WORDS);
a0123703 1277 if (err_mask) {
49016aca
TH		 1278 rc = -EIO;
1279 reason = "I/O error";
1da177e4
LT		 1280 goto err_out;
1281 }
1282
49016aca 1283 swap_buf_le16(id, ATA_ID_WORDS);
1da177e4 1284
49016aca 1285 /* sanity check */
a4f5749b
TH		 1286 rc = -EINVAL;
1287 reason = "device reports illegal type";
1288
1289 if (class == ATA_DEV_ATA) {
1290 if (!ata_id_is_ata(id) && !ata_id_is_cfa(id))
1291 goto err_out;
1292 } else {
1293 if (ata_id_is_ata(id))
1294 goto err_out;
49016aca
TH		 1295 }
1296
1297 if (post_reset && class == ATA_DEV_ATA) {
1298 /*
1299 * The exact sequence expected by certain pre-ATA4 drives is:
1300 * SRST RESET
1301 * IDENTIFY
1302 * INITIALIZE DEVICE PARAMETERS
1303 * anything else..
1304 * Some drives were very specific about that exact sequence.
1305 */
1306 if (ata_id_major_version(id) < 4 || !ata_id_has_lba(id)) {
3373efd8 1307 err_mask = ata_dev_init_params(dev, id[3], id[6]);
49016aca
TH		 1308 if (err_mask) {
1309 rc = -EIO;
1310 reason = "INIT_DEV_PARAMS failed";
1311 goto err_out;
1312 }
1313
1314 /* current CHS translation info (id[53-58]) might be
1315 * changed. reread the identify device info.
1316 */
1317 post_reset = 0;
1318 goto retry;
1319 }
1320 }
1321
1322 *p_class = class;
fe635c7e 1323
49016aca
TH		 1324 return 0;
1325
1326 err_out:
88574551 1327 if (ata_msg_warn(ap))
0dd4b21f 1328 ata_dev_printk(dev, KERN_WARNING, "failed to IDENTIFY "
88574551 1329 "(%s, err_mask=0x%x)\n", reason, err_mask);
49016aca
TH		 1330 return rc;
1331}
1332
3373efd8 1333static inline u8 ata_dev_knobble(struct ata_device *dev)
4b2f3ede 1334{
3373efd8 1335 return ((dev->ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(dev->id)));
4b2f3ede
TH		 1336}
1337
a6e6ce8e
TH		 1338static void ata_dev_config_ncq(struct ata_device *dev,
1339 char *desc, size_t desc_sz)
1340{
1341 struct ata_port *ap = dev->ap;
1342 int hdepth = 0, ddepth = ata_id_queue_depth(dev->id);
1343
1344 if (!ata_id_has_ncq(dev->id)) {
1345 desc[0] = '\0';
1346 return;
1347 }
1348
1349 if (ap->flags & ATA_FLAG_NCQ) {
cca3974e 1350 hdepth = min(ap->scsi_host->can_queue, ATA_MAX_QUEUE - 1);
a6e6ce8e
TH		 1351 dev->flags |= ATA_DFLAG_NCQ;
1352 }
1353
1354 if (hdepth >= ddepth)
1355 snprintf(desc, desc_sz, "NCQ (depth %d)", ddepth);
1356 else
1357 snprintf(desc, desc_sz, "NCQ (depth %d/%d)", hdepth, ddepth);
1358}
1359
e6d902a3
BK		 1360static void ata_set_port_max_cmd_len(struct ata_port *ap)
1361{
1362 int i;
1363
cca3974e
JG		 1364 if (ap->scsi_host) {
1365 unsigned int len = 0;
1366
e6d902a3 1367 for (i = 0; i < ATA_MAX_DEVICES; i++)
cca3974e
JG		 1368 len = max(len, ap->device[i].cdb_len);
1369
1370 ap->scsi_host->max_cmd_len = len;
e6d902a3
BK		 1371 }
1372}
1373
49016aca 1374/**
ffeae418 1375 * ata_dev_configure - Configure the specified ATA/ATAPI device
ffeae418 1376 * @dev: Target device to configure
4c2d721a 1377 * @print_info: Enable device info printout
ffeae418
TH		 1378 *
1379 * Configure @dev according to @dev->id. Generic and low-level
1380 * driver specific fixups are also applied.
49016aca
TH		 1381 *
1382 * LOCKING:
ffeae418
TH		 1383 * Kernel thread context (may sleep)
1384 *
1385 * RETURNS:
1386 * 0 on success, -errno otherwise
49016aca 1387 */
a9beec95 1388int ata_dev_configure(struct ata_device *dev, int print_info)
49016aca 1389{
3373efd8 1390 struct ata_port *ap = dev->ap;
1148c3a7 1391 const u16 *id = dev->id;
ff8854b2 1392 unsigned int xfer_mask;
b352e57d 1393 char revbuf[7]; /* XYZ-99\0 */
e6d902a3 1394 int rc;
49016aca 1395
0dd4b21f 1396 if (!ata_dev_enabled(dev) && ata_msg_info(ap)) {
88574551
TH		 1397 ata_dev_printk(dev, KERN_INFO,
1398 "%s: ENTER/EXIT (host %u, dev %u) -- nodev\n",
1399 __FUNCTION__, ap->id, dev->devno);
ffeae418 1400 return 0;
49016aca
TH		 1401 }
1402
0dd4b21f 1403 if (ata_msg_probe(ap))
88574551
TH		 1404 ata_dev_printk(dev, KERN_DEBUG, "%s: ENTER, host %u, dev %u\n",
1405 __FUNCTION__, ap->id, dev->devno);
1da177e4 1406
c39f5ebe 1407 /* print device capabilities */
0dd4b21f 1408 if (ata_msg_probe(ap))
88574551
TH		 1409 ata_dev_printk(dev, KERN_DEBUG,
1410 "%s: cfg 49:%04x 82:%04x 83:%04x 84:%04x "
1411 "85:%04x 86:%04x 87:%04x 88:%04x\n",
0dd4b21f 1412 __FUNCTION__,
f15a1daf
TH		 1413 id[49], id[82], id[83], id[84],
1414 id[85], id[86], id[87], id[88]);
c39f5ebe 1415
208a9933 1416 /* initialize to-be-configured parameters */
ea1dd4e1 1417 dev->flags &= ~ATA_DFLAG_CFG_MASK;
208a9933
TH		 1418 dev->max_sectors = 0;
1419 dev->cdb_len = 0;
1420 dev->n_sectors = 0;
1421 dev->cylinders = 0;
1422 dev->heads = 0;
1423 dev->sectors = 0;
1424
1da177e4
LT		 1425 /*
1426 * common ATA, ATAPI feature tests
1427 */
1428
ff8854b2 1429 /* find max transfer mode; for printk only */
1148c3a7 1430 xfer_mask = ata_id_xfermask(id);
1da177e4 1431
0dd4b21f
BP		 1432 if (ata_msg_probe(ap))
1433 ata_dump_id(id);
1da177e4
LT		 1434
1435 /* ATA-specific feature tests */
1436 if (dev->class == ATA_DEV_ATA) {
b352e57d
AC		 1437 if (ata_id_is_cfa(id)) {
1438 if (id[162] & 1) /* CPRM may make this media unusable */
1439 ata_dev_printk(dev, KERN_WARNING, "ata%u: device %u supports DRM functions and may not be fully accessable.\n",
1440 ap->id, dev->devno);
1441 snprintf(revbuf, 7, "CFA");
1442 }
1443 else
1444 snprintf(revbuf, 7, "ATA-%d", ata_id_major_version(id));
1445
1148c3a7 1446 dev->n_sectors = ata_id_n_sectors(id);
2940740b 1447
1148c3a7 1448 if (ata_id_has_lba(id)) {
4c2d721a 1449 const char *lba_desc;
a6e6ce8e 1450 char ncq_desc[20];
8bf62ece 1451
4c2d721a
TH		 1452 lba_desc = "LBA";
1453 dev->flags |= ATA_DFLAG_LBA;
1148c3a7 1454 if (ata_id_has_lba48(id)) {
8bf62ece 1455 dev->flags |= ATA_DFLAG_LBA48;
4c2d721a
TH		 1456 lba_desc = "LBA48";
1457 }
8bf62ece 1458
a6e6ce8e
TH		 1459 /* config NCQ */
1460 ata_dev_config_ncq(dev, ncq_desc, sizeof(ncq_desc));
1461
8bf62ece 1462 /* print device info to dmesg */
5afc8142 1463 if (ata_msg_drv(ap) && print_info)
b352e57d 1464 ata_dev_printk(dev, KERN_INFO, "%s, "
a6e6ce8e 1465 "max %s, %Lu sectors: %s %s\n",
b352e57d 1466 revbuf,
f15a1daf
TH		 1467 ata_mode_string(xfer_mask),
1468 (unsigned long long)dev->n_sectors,
a6e6ce8e 1469 lba_desc, ncq_desc);
ffeae418 1470 } else {
8bf62ece
AL		 1471 /* CHS */
1472
1473 /* Default translation */
1148c3a7
TH		 1474 dev->cylinders = id[1];
1475 dev->heads = id[3];
1476 dev->sectors = id[6];
8bf62ece 1477
1148c3a7 1478 if (ata_id_current_chs_valid(id)) {
8bf62ece 1479 /* Current CHS translation is valid. */
1148c3a7
TH		 1480 dev->cylinders = id[54];
1481 dev->heads = id[55];
1482 dev->sectors = id[56];
8bf62ece
AL		 1483 }
1484
1485 /* print device info to dmesg */
5afc8142 1486 if (ata_msg_drv(ap) && print_info)
b352e57d 1487 ata_dev_printk(dev, KERN_INFO, "%s, "
f15a1daf 1488 "max %s, %Lu sectors: CHS %u/%u/%u\n",
b352e57d 1489 revbuf,
f15a1daf
TH		 1490 ata_mode_string(xfer_mask),
1491 (unsigned long long)dev->n_sectors,
88574551
TH		 1492 dev->cylinders, dev->heads,
1493 dev->sectors);
1da177e4
LT		 1494 }
1495
07f6f7d0
AL		 1496 if (dev->id[59] & 0x100) {
1497 dev->multi_count = dev->id[59] & 0xff;
5afc8142 1498 if (ata_msg_drv(ap) && print_info)
88574551
TH		 1499 ata_dev_printk(dev, KERN_INFO,
1500 "ata%u: dev %u multi count %u\n",
1501 ap->id, dev->devno, dev->multi_count);
07f6f7d0
AL		 1502 }
1503
6e7846e9 1504 dev->cdb_len = 16;
1da177e4
LT		 1505 }
1506
1507 /* ATAPI-specific feature tests */
2c13b7ce 1508 else if (dev->class == ATA_DEV_ATAPI) {
08a556db
AL		 1509 char *cdb_intr_string = "";
1510
1148c3a7 1511 rc = atapi_cdb_len(id);
1da177e4 1512 if ((rc < 12) || (rc > ATAPI_CDB_LEN)) {
0dd4b21f 1513 if (ata_msg_warn(ap))
88574551
TH		 1514 ata_dev_printk(dev, KERN_WARNING,
1515 "unsupported CDB len\n");
ffeae418 1516 rc = -EINVAL;
1da177e4
LT		 1517 goto err_out_nosup;
1518 }
6e7846e9 1519 dev->cdb_len = (unsigned int) rc;
1da177e4 1520
08a556db 1521 if (ata_id_cdb_intr(dev->id)) {
312f7da2 1522 dev->flags |= ATA_DFLAG_CDB_INTR;
08a556db
AL		 1523 cdb_intr_string = ", CDB intr";
1524 }
312f7da2 1525
1da177e4 1526 /* print device info to dmesg */
5afc8142 1527 if (ata_msg_drv(ap) && print_info)
12436c30
TH		 1528 ata_dev_printk(dev, KERN_INFO, "ATAPI, max %s%s\n",
1529 ata_mode_string(xfer_mask),
1530 cdb_intr_string);
1da177e4
LT		 1531 }
1532
93590859
AC		 1533 if (dev->horkage & ATA_HORKAGE_DIAGNOSTIC) {
1534 /* Let the user know. We don't want to disallow opens for
1535 rescue purposes, or in case the vendor is just a blithering
1536 idiot */
1537 if (print_info) {
1538 ata_dev_printk(dev, KERN_WARNING,
1539"Drive reports diagnostics failure. This may indicate a drive\n");
1540 ata_dev_printk(dev, KERN_WARNING,
1541"fault or invalid emulation. Contact drive vendor for information.\n");
1542 }
1543 }
1544
e6d902a3 1545 ata_set_port_max_cmd_len(ap);
6e7846e9 1546
4b2f3ede 1547 /* limit bridge transfers to udma5, 200 sectors */
3373efd8 1548 if (ata_dev_knobble(dev)) {
5afc8142 1549 if (ata_msg_drv(ap) && print_info)
f15a1daf
TH		 1550 ata_dev_printk(dev, KERN_INFO,
1551 "applying bridge limits\n");
5a529139 1552 dev->udma_mask &= ATA_UDMA5;
4b2f3ede
TH		 1553 dev->max_sectors = ATA_MAX_SECTORS;
1554 }
1555
1556 if (ap->ops->dev_config)
1557 ap->ops->dev_config(ap, dev);
1558
0dd4b21f
BP		 1559 if (ata_msg_probe(ap))
1560 ata_dev_printk(dev, KERN_DEBUG, "%s: EXIT, drv_stat = 0x%x\n",
1561 __FUNCTION__, ata_chk_status(ap));
ffeae418 1562 return 0;
1da177e4
LT		 1563
1564err_out_nosup:
0dd4b21f 1565 if (ata_msg_probe(ap))
88574551
TH		 1566 ata_dev_printk(dev, KERN_DEBUG,
1567 "%s: EXIT, err\n", __FUNCTION__);
ffeae418 1568 return rc;
1da177e4
LT		 1569}
1570
1571/**
1572 * ata_bus_probe - Reset and probe ATA bus
1573 * @ap: Bus to probe
1574 *
0cba632b
JG		 1575 * Master ATA bus probing function. Initiates a hardware-dependent
1576 * bus reset, then attempts to identify any devices found on
1577 * the bus.
1578 *
1da177e4 1579 * LOCKING:
0cba632b 1580 * PCI/etc. bus probe sem.
1da177e4
LT		 1581 *
1582 * RETURNS:
96072e69 1583 * Zero on success, negative errno otherwise.
1da177e4
LT		 1584 */
1585
80289167 1586int ata_bus_probe(struct ata_port *ap)
1da177e4 1587{
28ca5c57 1588 unsigned int classes[ATA_MAX_DEVICES];
14d2bac1
TH		 1589 int tries[ATA_MAX_DEVICES];
1590 int i, rc, down_xfermask;
e82cbdb9 1591 struct ata_device *dev;
1da177e4 1592
28ca5c57 1593 ata_port_probe(ap);
c19ba8af 1594
14d2bac1
TH		 1595 for (i = 0; i < ATA_MAX_DEVICES; i++)
1596 tries[i] = ATA_PROBE_MAX_TRIES;
1597
1598 retry:
1599 down_xfermask = 0;
1600
2044470c 1601 /* reset and determine device classes */
52783c5d 1602 ap->ops->phy_reset(ap);
2061a47a 1603
52783c5d
TH		 1604 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1605 dev = &ap->device[i];
c19ba8af 1606
52783c5d
TH		 1607 if (!(ap->flags & ATA_FLAG_DISABLED) &&
1608 dev->class != ATA_DEV_UNKNOWN)
1609 classes[dev->devno] = dev->class;
1610 else
1611 classes[dev->devno] = ATA_DEV_NONE;
2044470c 1612
52783c5d 1613 dev->class = ATA_DEV_UNKNOWN;
28ca5c57 1614 }
1da177e4 1615
52783c5d 1616 ata_port_probe(ap);
2044470c 1617
b6079ca4
AC		 1618 /* after the reset the device state is PIO 0 and the controller
1619 state is undefined. Record the mode */
1620
1621 for (i = 0; i < ATA_MAX_DEVICES; i++)
1622 ap->device[i].pio_mode = XFER_PIO_0;
1623
28ca5c57 1624 /* read IDENTIFY page and configure devices */
1da177e4 1625 for (i = 0; i < ATA_MAX_DEVICES; i++) {
e82cbdb9 1626 dev = &ap->device[i];
28ca5c57 1627
ec573755
TH		 1628 if (tries[i])
1629 dev->class = classes[i];
ffeae418 1630
14d2bac1 1631 if (!ata_dev_enabled(dev))
ffeae418 1632 continue;
ffeae418 1633
3373efd8 1634 rc = ata_dev_read_id(dev, &dev->class, 1, dev->id);
14d2bac1
TH		 1635 if (rc)
1636 goto fail;
1637
3373efd8 1638 rc = ata_dev_configure(dev, 1);
14d2bac1
TH		 1639 if (rc)
1640 goto fail;
1da177e4
LT		 1641 }
1642
e82cbdb9 1643 /* configure transfer mode */
3adcebb2 1644 rc = ata_set_mode(ap, &dev);
51713d35
TH		 1645 if (rc) {
1646 down_xfermask = 1;
1647 goto fail;
e82cbdb9 1648 }
1da177e4 1649
e82cbdb9
TH		 1650 for (i = 0; i < ATA_MAX_DEVICES; i++)
1651 if (ata_dev_enabled(&ap->device[i]))
1652 return 0;
1da177e4 1653
e82cbdb9
TH		 1654 /* no device present, disable port */
1655 ata_port_disable(ap);
1da177e4 1656 ap->ops->port_disable(ap);
96072e69 1657 return -ENODEV;
14d2bac1
TH		 1658
1659 fail:
1660 switch (rc) {
1661 case -EINVAL:
1662 case -ENODEV:
1663 tries[dev->devno] = 0;
1664 break;
1665 case -EIO:
3c567b7d 1666 sata_down_spd_limit(ap);
14d2bac1
TH		 1667 /* fall through */
1668 default:
1669 tries[dev->devno]--;
1670 if (down_xfermask &&
3373efd8 1671 ata_down_xfermask_limit(dev, tries[dev->devno] == 1))
14d2bac1
TH		 1672 tries[dev->devno] = 0;
1673 }
1674
ec573755 1675 if (!tries[dev->devno]) {
3373efd8
TH		 1676 ata_down_xfermask_limit(dev, 1);
1677 ata_dev_disable(dev);
ec573755
TH		 1678 }
1679
14d2bac1 1680 goto retry;
1da177e4
LT		 1681}
1682
1683/**
0cba632b
JG		 1684 * ata_port_probe - Mark port as enabled
1685 * @ap: Port for which we indicate enablement
1da177e4 1686 *
0cba632b
JG		 1687 * Modify @ap data structure such that the system
1688 * thinks that the entire port is enabled.
1689 *
cca3974e 1690 * LOCKING: host lock, or some other form of
0cba632b 1691 * serialization.
1da177e4
LT		 1692 */
1693
1694void ata_port_probe(struct ata_port *ap)
1695{
198e0fed 1696 ap->flags &= ~ATA_FLAG_DISABLED;
1da177e4
LT		 1697}
1698
3be680b7
TH		 1699/**
1700 * sata_print_link_status - Print SATA link status
1701 * @ap: SATA port to printk link status about
1702 *
1703 * This function prints link speed and status of a SATA link.
1704 *
1705 * LOCKING:
1706 * None.
1707 */
1708static void sata_print_link_status(struct ata_port *ap)
1709{
6d5f9732 1710 u32 sstatus, scontrol, tmp;
3be680b7 1711
81952c54 1712 if (sata_scr_read(ap, SCR_STATUS, &sstatus))
3be680b7 1713 return;
81952c54 1714 sata_scr_read(ap, SCR_CONTROL, &scontrol);
3be680b7 1715
81952c54 1716 if (ata_port_online(ap)) {
3be680b7 1717 tmp = (sstatus >> 4) & 0xf;
f15a1daf
TH		 1718 ata_port_printk(ap, KERN_INFO,
1719 "SATA link up %s (SStatus %X SControl %X)\n",
1720 sata_spd_string(tmp), sstatus, scontrol);
3be680b7 1721 } else {
f15a1daf
TH		 1722 ata_port_printk(ap, KERN_INFO,
1723 "SATA link down (SStatus %X SControl %X)\n",
1724 sstatus, scontrol);
3be680b7
TH		 1725 }
1726}
1727
1da177e4 1728/**
780a87f7
JG		 1729 * __sata_phy_reset - Wake/reset a low-level SATA PHY
1730 * @ap: SATA port associated with target SATA PHY.
1da177e4 1731 *
780a87f7
JG		 1732 * This function issues commands to standard SATA Sxxx
1733 * PHY registers, to wake up the phy (and device), and
1734 * clear any reset condition.
1da177e4
LT		 1735 *
1736 * LOCKING:
0cba632b 1737 * PCI/etc. bus probe sem.
1da177e4
LT		 1738 *
1739 */
1740void __sata_phy_reset(struct ata_port *ap)
1741{
1742 u32 sstatus;
1743 unsigned long timeout = jiffies + (HZ * 5);
1744
1745 if (ap->flags & ATA_FLAG_SATA_RESET) {
cdcca89e 1746 /* issue phy wake/reset */
81952c54 1747 sata_scr_write_flush(ap, SCR_CONTROL, 0x301);
62ba2841
TH		 1748 /* Couldn't find anything in SATA I/II specs, but
1749 * AHCI-1.1 10.4.2 says at least 1 ms. */
1750 mdelay(1);
1da177e4 1751 }
81952c54
TH		 1752 /* phy wake/clear reset */
1753 sata_scr_write_flush(ap, SCR_CONTROL, 0x300);
1da177e4
LT		 1754
1755 /* wait for phy to become ready, if necessary */
1756 do {
1757 msleep(200);
81952c54 1758 sata_scr_read(ap, SCR_STATUS, &sstatus);
1da177e4
LT		 1759 if ((sstatus & 0xf) != 1)
1760 break;
1761 } while (time_before(jiffies, timeout));
1762
3be680b7
TH		 1763 /* print link status */
1764 sata_print_link_status(ap);
656563e3 1765
3be680b7 1766 /* TODO: phy layer with polling, timeouts, etc. */
81952c54 1767 if (!ata_port_offline(ap))
1da177e4 1768 ata_port_probe(ap);
3be680b7 1769 else
1da177e4 1770 ata_port_disable(ap);
1da177e4 1771
198e0fed 1772 if (ap->flags & ATA_FLAG_DISABLED)
1da177e4
LT		 1773 return;
1774
1775 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
1776 ata_port_disable(ap);
1777 return;
1778 }
1779
1780 ap->cbl = ATA_CBL_SATA;
1781}
1782
1783/**
780a87f7
JG		 1784 * sata_phy_reset - Reset SATA bus.
1785 * @ap: SATA port associated with target SATA PHY.
1da177e4 1786 *
780a87f7
JG		 1787 * This function resets the SATA bus, and then probes
1788 * the bus for devices.
1da177e4
LT		 1789 *
1790 * LOCKING:
0cba632b 1791 * PCI/etc. bus probe sem.
1da177e4
LT		 1792 *
1793 */
1794void sata_phy_reset(struct ata_port *ap)
1795{
1796 __sata_phy_reset(ap);
198e0fed 1797 if (ap->flags & ATA_FLAG_DISABLED)
1da177e4
LT		 1798 return;
1799 ata_bus_reset(ap);
1800}
1801
ebdfca6e
AC		 1802/**
1803 * ata_dev_pair - return other device on cable
ebdfca6e
AC		 1804 * @adev: device
1805 *
1806 * Obtain the other device on the same cable, or if none is
1807 * present NULL is returned
1808 */
2e9edbf8 1809
3373efd8 1810struct ata_device *ata_dev_pair(struct ata_device *adev)
ebdfca6e 1811{
3373efd8 1812 struct ata_port *ap = adev->ap;
ebdfca6e 1813 struct ata_device *pair = &ap->device[1 - adev->devno];
e1211e3f 1814 if (!ata_dev_enabled(pair))
ebdfca6e
AC		 1815 return NULL;
1816 return pair;
1817}
1818
1da177e4 1819/**
780a87f7
JG		 1820 * ata_port_disable - Disable port.
1821 * @ap: Port to be disabled.
1da177e4 1822 *
780a87f7
JG		 1823 * Modify @ap data structure such that the system
1824 * thinks that the entire port is disabled, and should
1825 * never attempt to probe or communicate with devices
1826 * on this port.
1827 *
cca3974e 1828 * LOCKING: host lock, or some other form of
780a87f7 1829 * serialization.
1da177e4
LT		 1830 */
1831
1832void ata_port_disable(struct ata_port *ap)
1833{
1834 ap->device[0].class = ATA_DEV_NONE;
1835 ap->device[1].class = ATA_DEV_NONE;
198e0fed 1836 ap->flags |= ATA_FLAG_DISABLED;
1da177e4
LT		 1837}
1838
1c3fae4d 1839/**
3c567b7d 1840 * sata_down_spd_limit - adjust SATA spd limit downward
1c3fae4d
TH		 1841 * @ap: Port to adjust SATA spd limit for
1842 *
1843 * Adjust SATA spd limit of @ap downward. Note that this
1844 * function only adjusts the limit. The change must be applied
3c567b7d 1845 * using sata_set_spd().
1c3fae4d
TH		 1846 *
1847 * LOCKING:
1848 * Inherited from caller.
1849 *
1850 * RETURNS:
1851 * 0 on success, negative errno on failure
1852 */
3c567b7d 1853int sata_down_spd_limit(struct ata_port *ap)
1c3fae4d 1854{
81952c54
TH		 1855 u32 sstatus, spd, mask;
1856 int rc, highbit;
1c3fae4d 1857
81952c54
TH		 1858 rc = sata_scr_read(ap, SCR_STATUS, &sstatus);
1859 if (rc)
1860 return rc;
1c3fae4d
TH		 1861
1862 mask = ap->sata_spd_limit;
1863 if (mask <= 1)
1864 return -EINVAL;
1865 highbit = fls(mask) - 1;
1866 mask &= ~(1 << highbit);
1867
81952c54 1868 spd = (sstatus >> 4) & 0xf;
1c3fae4d
TH		 1869 if (spd <= 1)
1870 return -EINVAL;
1871 spd--;
1872 mask &= (1 << spd) - 1;
1873 if (!mask)
1874 return -EINVAL;
1875
1876 ap->sata_spd_limit = mask;
1877
f15a1daf
TH		 1878 ata_port_printk(ap, KERN_WARNING, "limiting SATA link speed to %s\n",
1879 sata_spd_string(fls(mask)));
1c3fae4d
TH		 1880
1881 return 0;
1882}
1883
3c567b7d 1884static int __sata_set_spd_needed(struct ata_port *ap, u32 *scontrol)
1c3fae4d
TH		 1885{
1886 u32 spd, limit;
1887
1888 if (ap->sata_spd_limit == UINT_MAX)
1889 limit = 0;
1890 else
1891 limit = fls(ap->sata_spd_limit);
1892
1893 spd = (*scontrol >> 4) & 0xf;
1894 *scontrol = (*scontrol & ~0xf0) | ((limit & 0xf) << 4);
1895
1896 return spd != limit;
1897}
1898
1899/**
3c567b7d 1900 * sata_set_spd_needed - is SATA spd configuration needed
1c3fae4d
TH		 1901 * @ap: Port in question
1902 *
1903 * Test whether the spd limit in SControl matches
1904 * @ap->sata_spd_limit. This function is used to determine
1905 * whether hardreset is necessary to apply SATA spd
1906 * configuration.
1907 *
1908 * LOCKING:
1909 * Inherited from caller.
1910 *
1911 * RETURNS:
1912 * 1 if SATA spd configuration is needed, 0 otherwise.
1913 */
3c567b7d 1914int sata_set_spd_needed(struct ata_port *ap)
1c3fae4d
TH		 1915{
1916 u32 scontrol;
1917
81952c54 1918 if (sata_scr_read(ap, SCR_CONTROL, &scontrol))
1c3fae4d
TH		 1919 return 0;
1920
3c567b7d 1921 return __sata_set_spd_needed(ap, &scontrol);
1c3fae4d
TH		 1922}
1923
1924/**
3c567b7d 1925 * sata_set_spd - set SATA spd according to spd limit
1c3fae4d
TH		 1926 * @ap: Port to set SATA spd for
1927 *
1928 * Set SATA spd of @ap according to sata_spd_limit.
1929 *
1930 * LOCKING:
1931 * Inherited from caller.
1932 *
1933 * RETURNS:
1934 * 0 if spd doesn't need to be changed, 1 if spd has been
81952c54 1935 * changed. Negative errno if SCR registers are inaccessible.
1c3fae4d 1936 */
3c567b7d 1937int sata_set_spd(struct ata_port *ap)
1c3fae4d
TH		 1938{
1939 u32 scontrol;
81952c54 1940 int rc;
1c3fae4d 1941
81952c54
TH		 1942 if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
1943 return rc;
1c3fae4d 1944
3c567b7d 1945 if (!__sata_set_spd_needed(ap, &scontrol))
1c3fae4d
TH		 1946 return 0;
1947
81952c54
TH		 1948 if ((rc = sata_scr_write(ap, SCR_CONTROL, scontrol)))
1949 return rc;
1950
1c3fae4d
TH		 1951 return 1;
1952}
1953
452503f9
AC		 1954/*
1955 * This mode timing computation functionality is ported over from
1956 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
1957 */
1958/*
b352e57d 1959 * PIO 0-4, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
452503f9 1960 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
b352e57d
AC		 1961 * for UDMA6, which is currently supported only by Maxtor drives.
1962 *
1963 * For PIO 5/6 MWDMA 3/4 see the CFA specification 3.0.
452503f9
AC		 1964 */
1965
1966static const struct ata_timing ata_timing[] = {
1967
1968 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
1969 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
1970 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
1971 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
1972
b352e57d
AC		 1973 { XFER_MW_DMA_4, 25, 0, 0, 0, 55, 20, 80, 0 },
1974 { XFER_MW_DMA_3, 25, 0, 0, 0, 65, 25, 100, 0 },
452503f9
AC		 1975 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
1976 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
1977 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
1978
1979/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */
2e9edbf8 1980
452503f9
AC		 1981 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
1982 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
1983 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
2e9edbf8 1984
452503f9
AC		 1985 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
1986 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
1987 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
1988
b352e57d
AC		 1989 { XFER_PIO_6, 10, 55, 20, 80, 55, 20, 80, 0 },
1990 { XFER_PIO_5, 15, 65, 25, 100, 65, 25, 100, 0 },
452503f9
AC		 1991 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
1992 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
1993
1994 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
1995 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
1996 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
1997
1998/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */
1999
2000 { 0xFF }
2001};
2002
2003#define ENOUGH(v,unit) (((v)-1)/(unit)+1)
2004#define EZ(v,unit) ((v)?ENOUGH(v,unit):0)
2005
2006static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
2007{
2008 q->setup = EZ(t->setup * 1000, T);
2009 q->act8b = EZ(t->act8b * 1000, T);
2010 q->rec8b = EZ(t->rec8b * 1000, T);
2011 q->cyc8b = EZ(t->cyc8b * 1000, T);
2012 q->active = EZ(t->active * 1000, T);
2013 q->recover = EZ(t->recover * 1000, T);
2014 q->cycle = EZ(t->cycle * 1000, T);
2015 q->udma = EZ(t->udma * 1000, UT);
2016}
2017
2018void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
2019 struct ata_timing *m, unsigned int what)
2020{
2021 if (what & ATA_TIMING_SETUP ) m->setup = max(a->setup, b->setup);
2022 if (what & ATA_TIMING_ACT8B ) m->act8b = max(a->act8b, b->act8b);
2023 if (what & ATA_TIMING_REC8B ) m->rec8b = max(a->rec8b, b->rec8b);
2024 if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b);
2025 if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active);
2026 if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
2027 if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle);
2028 if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma);
2029}
2030
2031static const struct ata_timing* ata_timing_find_mode(unsigned short speed)
2032{
2033 const struct ata_timing *t;
2034
2035 for (t = ata_timing; t->mode != speed; t++)
91190758 2036 if (t->mode == 0xFF)
452503f9 2037 return NULL;
2e9edbf8 2038 return t;
452503f9
AC		 2039}
2040
2041int ata_timing_compute(struct ata_device *adev, unsigned short speed,
2042 struct ata_timing *t, int T, int UT)
2043{
2044 const struct ata_timing *s;
2045 struct ata_timing p;
2046
2047 /*
2e9edbf8 2048 * Find the mode.
75b1f2f8 2049 */
452503f9
AC		 2050
2051 if (!(s = ata_timing_find_mode(speed)))
2052 return -EINVAL;
2053
75b1f2f8
AL		 2054 memcpy(t, s, sizeof(*s));
2055
452503f9
AC		 2056 /*
2057 * If the drive is an EIDE drive, it can tell us it needs extended
2058 * PIO/MW_DMA cycle timing.
2059 */
2060
2061 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
2062 memset(&p, 0, sizeof(p));
2063 if(speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) {
2064 if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO];
2065 else p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO_IORDY];
2066 } else if(speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) {
2067 p.cycle = adev->id[ATA_ID_EIDE_DMA_MIN];
2068 }
2069 ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
2070 }
2071
2072 /*
2073 * Convert the timing to bus clock counts.
2074 */
2075
75b1f2f8 2076 ata_timing_quantize(t, t, T, UT);
452503f9
AC		 2077
2078 /*
c893a3ae
RD		 2079 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
2080 * S.M.A.R.T * and some other commands. We have to ensure that the
2081 * DMA cycle timing is slower/equal than the fastest PIO timing.
452503f9
AC		 2082 */
2083
2084 if (speed > XFER_PIO_4) {
2085 ata_timing_compute(adev, adev->pio_mode, &p, T, UT);
2086 ata_timing_merge(&p, t, t, ATA_TIMING_ALL);
2087 }
2088
2089 /*
c893a3ae 2090 * Lengthen active & recovery time so that cycle time is correct.
452503f9
AC		 2091 */
2092
2093 if (t->act8b + t->rec8b < t->cyc8b) {
2094 t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
2095 t->rec8b = t->cyc8b - t->act8b;
2096 }
2097
2098 if (t->active + t->recover < t->cycle) {
2099 t->active += (t->cycle - (t->active + t->recover)) / 2;
2100 t->recover = t->cycle - t->active;
2101 }
2102
2103 return 0;
2104}
2105
cf176e1a
TH		 2106/**
2107 * ata_down_xfermask_limit - adjust dev xfer masks downward
cf176e1a
TH		 2108 * @dev: Device to adjust xfer masks
2109 * @force_pio0: Force PIO0
2110 *
2111 * Adjust xfer masks of @dev downward. Note that this function
2112 * does not apply the change. Invoking ata_set_mode() afterwards
2113 * will apply the limit.
2114 *
2115 * LOCKING:
2116 * Inherited from caller.
2117 *
2118 * RETURNS:
2119 * 0 on success, negative errno on failure
2120 */
3373efd8 2121int ata_down_xfermask_limit(struct ata_device *dev, int force_pio0)
cf176e1a
TH		 2122{
2123 unsigned long xfer_mask;
2124 int highbit;
2125
2126 xfer_mask = ata_pack_xfermask(dev->pio_mask, dev->mwdma_mask,
2127 dev->udma_mask);
2128
2129 if (!xfer_mask)
2130 goto fail;
2131 /* don't gear down to MWDMA from UDMA, go directly to PIO */
2132 if (xfer_mask & ATA_MASK_UDMA)
2133 xfer_mask &= ~ATA_MASK_MWDMA;
2134
2135 highbit = fls(xfer_mask) - 1;
2136 xfer_mask &= ~(1 << highbit);
2137 if (force_pio0)
2138 xfer_mask &= 1 << ATA_SHIFT_PIO;
2139 if (!xfer_mask)
2140 goto fail;
2141
2142 ata_unpack_xfermask(xfer_mask, &dev->pio_mask, &dev->mwdma_mask,
2143 &dev->udma_mask);
2144
f15a1daf
TH		 2145 ata_dev_printk(dev, KERN_WARNING, "limiting speed to %s\n",
2146 ata_mode_string(xfer_mask));
cf176e1a
TH		 2147
2148 return 0;
2149
2150 fail:
2151 return -EINVAL;
2152}
2153
3373efd8 2154static int ata_dev_set_mode(struct ata_device *dev)
1da177e4 2155{
83206a29
TH		 2156 unsigned int err_mask;
2157 int rc;
1da177e4 2158
e8384607 2159 dev->flags &= ~ATA_DFLAG_PIO;
1da177e4
LT		 2160 if (dev->xfer_shift == ATA_SHIFT_PIO)
2161 dev->flags |= ATA_DFLAG_PIO;
2162
3373efd8 2163 err_mask = ata_dev_set_xfermode(dev);
83206a29 2164 if (err_mask) {
f15a1daf
TH		 2165 ata_dev_printk(dev, KERN_ERR, "failed to set xfermode "
2166 "(err_mask=0x%x)\n", err_mask);
83206a29
TH		 2167 return -EIO;
2168 }
1da177e4 2169
3373efd8 2170 rc = ata_dev_revalidate(dev, 0);
5eb45c02 2171 if (rc)
83206a29 2172 return rc;
48a8a14f 2173
23e71c3d
TH		 2174 DPRINTK("xfer_shift=%u, xfer_mode=0x%x\n",
2175 dev->xfer_shift, (int)dev->xfer_mode);
1da177e4 2176
f15a1daf
TH		 2177 ata_dev_printk(dev, KERN_INFO, "configured for %s\n",
2178 ata_mode_string(ata_xfer_mode2mask(dev->xfer_mode)));
83206a29 2179 return 0;
1da177e4
LT		 2180}
2181
1da177e4
LT		 2182/**
2183 * ata_set_mode - Program timings and issue SET FEATURES - XFER
2184 * @ap: port on which timings will be programmed
e82cbdb9 2185 * @r_failed_dev: out paramter for failed device
1da177e4 2186 *
e82cbdb9
TH		 2187 * Set ATA device disk transfer mode (PIO3, UDMA6, etc.). If
2188 * ata_set_mode() fails, pointer to the failing device is
2189 * returned in @r_failed_dev.
780a87f7 2190 *
1da177e4 2191 * LOCKING:
0cba632b 2192 * PCI/etc. bus probe sem.
e82cbdb9
TH		 2193 *
2194 * RETURNS:
2195 * 0 on success, negative errno otherwise
1da177e4 2196 */
1ad8e7f9 2197int ata_set_mode(struct ata_port *ap, struct ata_device **r_failed_dev)
1da177e4 2198{
e8e0619f 2199 struct ata_device *dev;
e82cbdb9 2200 int i, rc = 0, used_dma = 0, found = 0;
1da177e4 2201
3adcebb2
TH		 2202 /* has private set_mode? */
2203 if (ap->ops->set_mode) {
2204 /* FIXME: make ->set_mode handle no device case and
2205 * return error code and failing device on failure.
2206 */
2207 for (i = 0; i < ATA_MAX_DEVICES; i++) {
02670bf3 2208 if (ata_dev_ready(&ap->device[i])) {
3adcebb2
TH		 2209 ap->ops->set_mode(ap);
2210 break;
2211 }
2212 }
2213 return 0;
2214 }
2215
a6d5a51c
TH		 2216 /* step 1: calculate xfer_mask */
2217 for (i = 0; i < ATA_MAX_DEVICES; i++) {
acf356b1 2218 unsigned int pio_mask, dma_mask;
a6d5a51c 2219
e8e0619f
TH		 2220 dev = &ap->device[i];
2221
e1211e3f 2222 if (!ata_dev_enabled(dev))
a6d5a51c
TH		 2223 continue;
2224
3373efd8 2225 ata_dev_xfermask(dev);
1da177e4 2226
acf356b1
TH		 2227 pio_mask = ata_pack_xfermask(dev->pio_mask, 0, 0);
2228 dma_mask = ata_pack_xfermask(0, dev->mwdma_mask, dev->udma_mask);
2229 dev->pio_mode = ata_xfer_mask2mode(pio_mask);
2230 dev->dma_mode = ata_xfer_mask2mode(dma_mask);
5444a6f4 2231
4f65977d 2232 found = 1;
5444a6f4
AC		 2233 if (dev->dma_mode)
2234 used_dma = 1;
a6d5a51c 2235 }
4f65977d 2236 if (!found)
e82cbdb9 2237 goto out;
a6d5a51c
TH		 2238
2239 /* step 2: always set host PIO timings */
e8e0619f
TH		 2240 for (i = 0; i < ATA_MAX_DEVICES; i++) {
2241 dev = &ap->device[i];
2242 if (!ata_dev_enabled(dev))
2243 continue;
2244
2245 if (!dev->pio_mode) {
f15a1daf 2246 ata_dev_printk(dev, KERN_WARNING, "no PIO support\n");
e8e0619f 2247 rc = -EINVAL;
e82cbdb9 2248 goto out;
e8e0619f
TH		 2249 }
2250
2251 dev->xfer_mode = dev->pio_mode;
2252 dev->xfer_shift = ATA_SHIFT_PIO;
2253 if (ap->ops->set_piomode)
2254 ap->ops->set_piomode(ap, dev);
2255 }
1da177e4 2256
a6d5a51c 2257 /* step 3: set host DMA timings */
e8e0619f
TH		 2258 for (i = 0; i < ATA_MAX_DEVICES; i++) {
2259 dev = &ap->device[i];
2260
2261 if (!ata_dev_enabled(dev) || !dev->dma_mode)
2262 continue;
2263
2264 dev->xfer_mode = dev->dma_mode;
2265 dev->xfer_shift = ata_xfer_mode2shift(dev->dma_mode);
2266 if (ap->ops->set_dmamode)
2267 ap->ops->set_dmamode(ap, dev);
2268 }
1da177e4
LT		 2269
2270 /* step 4: update devices' xfer mode */
83206a29 2271 for (i = 0; i < ATA_MAX_DEVICES; i++) {
e8e0619f 2272 dev = &ap->device[i];
1da177e4 2273
02670bf3
TH		 2274 /* don't udpate suspended devices' xfer mode */
2275 if (!ata_dev_ready(dev))
83206a29
TH		 2276 continue;
2277
3373efd8 2278 rc = ata_dev_set_mode(dev);
5bbc53f4 2279 if (rc)
e82cbdb9 2280 goto out;
83206a29 2281 }
1da177e4 2282
e8e0619f
TH		 2283 /* Record simplex status. If we selected DMA then the other
2284 * host channels are not permitted to do so.
5444a6f4 2285 */
cca3974e
JG		 2286 if (used_dma && (ap->host->flags & ATA_HOST_SIMPLEX))
2287 ap->host->simplex_claimed = 1;
5444a6f4 2288
e8e0619f 2289 /* step5: chip specific finalisation */
1da177e4
LT		 2290 if (ap->ops->post_set_mode)
2291 ap->ops->post_set_mode(ap);
2292
e82cbdb9
TH		 2293 out:
2294 if (rc)
2295 *r_failed_dev = dev;
2296 return rc;
1da177e4
LT		 2297}
2298
1fdffbce
JG		 2299/**
2300 * ata_tf_to_host - issue ATA taskfile to host controller
2301 * @ap: port to which command is being issued
2302 * @tf: ATA taskfile register set
2303 *
2304 * Issues ATA taskfile register set to ATA host controller,
2305 * with proper synchronization with interrupt handler and
2306 * other threads.
2307 *
2308 * LOCKING:
cca3974e 2309 * spin_lock_irqsave(host lock)
1fdffbce
JG		 2310 */
2311
2312static inline void ata_tf_to_host(struct ata_port *ap,
2313 const struct ata_taskfile *tf)
2314{
2315 ap->ops->tf_load(ap, tf);
2316 ap->ops->exec_command(ap, tf);
2317}
2318
1da177e4
LT		 2319/**
2320 * ata_busy_sleep - sleep until BSY clears, or timeout
2321 * @ap: port containing status register to be polled
2322 * @tmout_pat: impatience timeout
2323 * @tmout: overall timeout
2324 *
780a87f7
JG		 2325 * Sleep until ATA Status register bit BSY clears,
2326 * or a timeout occurs.
2327 *
2328 * LOCKING: None.
1da177e4
LT		 2329 */
2330
6f8b9958
TH		 2331unsigned int ata_busy_sleep (struct ata_port *ap,
2332 unsigned long tmout_pat, unsigned long tmout)
1da177e4
LT		 2333{
2334 unsigned long timer_start, timeout;
2335 u8 status;
2336
2337 status = ata_busy_wait(ap, ATA_BUSY, 300);
2338 timer_start = jiffies;
2339 timeout = timer_start + tmout_pat;
2340 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
2341 msleep(50);
2342 status = ata_busy_wait(ap, ATA_BUSY, 3);
2343 }
2344
2345 if (status & ATA_BUSY)
f15a1daf 2346 ata_port_printk(ap, KERN_WARNING,
35aa7a43
JG		 2347 "port is slow to respond, please be patient "
2348 "(Status 0x%x)\n", status);
1da177e4
LT		 2349
2350 timeout = timer_start + tmout;
2351 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
2352 msleep(50);
2353 status = ata_chk_status(ap);
2354 }
2355
2356 if (status & ATA_BUSY) {
f15a1daf 2357 ata_port_printk(ap, KERN_ERR, "port failed to respond "
35aa7a43
JG		 2358 "(%lu secs, Status 0x%x)\n",
2359 tmout / HZ, status);
1da177e4
LT		 2360 return 1;
2361 }
2362
2363 return 0;
2364}
2365
2366static void ata_bus_post_reset(struct ata_port *ap, unsigned int devmask)
2367{
2368 struct ata_ioports *ioaddr = &ap->ioaddr;
2369 unsigned int dev0 = devmask & (1 << 0);
2370 unsigned int dev1 = devmask & (1 << 1);
2371 unsigned long timeout;
2372
2373 /* if device 0 was found in ata_devchk, wait for its
2374 * BSY bit to clear
2375 */
2376 if (dev0)
2377 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
2378
2379 /* if device 1 was found in ata_devchk, wait for
2380 * register access, then wait for BSY to clear
2381 */
2382 timeout = jiffies + ATA_TMOUT_BOOT;
2383 while (dev1) {
2384 u8 nsect, lbal;
2385
2386 ap->ops->dev_select(ap, 1);
2387 if (ap->flags & ATA_FLAG_MMIO) {
2388 nsect = readb((void __iomem *) ioaddr->nsect_addr);
2389 lbal = readb((void __iomem *) ioaddr->lbal_addr);
2390 } else {
2391 nsect = inb(ioaddr->nsect_addr);
2392 lbal = inb(ioaddr->lbal_addr);
2393 }
2394 if ((nsect == 1) && (lbal == 1))
2395 break;
2396 if (time_after(jiffies, timeout)) {
2397 dev1 = 0;
2398 break;
2399 }
2400 msleep(50); /* give drive a breather */
2401 }
2402 if (dev1)
2403 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
2404
2405 /* is all this really necessary? */
2406 ap->ops->dev_select(ap, 0);
2407 if (dev1)
2408 ap->ops->dev_select(ap, 1);
2409 if (dev0)
2410 ap->ops->dev_select(ap, 0);
2411}
2412
1da177e4
LT		 2413static unsigned int ata_bus_softreset(struct ata_port *ap,
2414 unsigned int devmask)
2415{
2416 struct ata_ioports *ioaddr = &ap->ioaddr;
2417
2418 DPRINTK("ata%u: bus reset via SRST\n", ap->id);
2419
2420 /* software reset. causes dev0 to be selected */
2421 if (ap->flags & ATA_FLAG_MMIO) {
2422 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2423 udelay(20); /* FIXME: flush */
2424 writeb(ap->ctl | ATA_SRST, (void __iomem *) ioaddr->ctl_addr);
2425 udelay(20); /* FIXME: flush */
2426 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2427 } else {
2428 outb(ap->ctl, ioaddr->ctl_addr);
2429 udelay(10);
2430 outb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
2431 udelay(10);
2432 outb(ap->ctl, ioaddr->ctl_addr);
2433 }
2434
2435 /* spec mandates ">= 2ms" before checking status.
2436 * We wait 150ms, because that was the magic delay used for
2437 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
2438 * between when the ATA command register is written, and then
2439 * status is checked. Because waiting for "a while" before
2440 * checking status is fine, post SRST, we perform this magic
2441 * delay here as well.
09c7ad79
AC		 2442 *
2443 * Old drivers/ide uses the 2mS rule and then waits for ready
1da177e4
LT		 2444 */
2445 msleep(150);
2446
2e9edbf8 2447 /* Before we perform post reset processing we want to see if
298a41ca
TH		 2448 * the bus shows 0xFF because the odd clown forgets the D7
2449 * pulldown resistor.
2450 */
987d2f05 2451 if (ata_check_status(ap) == 0xFF) {
f15a1daf 2452 ata_port_printk(ap, KERN_ERR, "SRST failed (status 0xFF)\n");
298a41ca 2453 return AC_ERR_OTHER;
987d2f05 2454 }
09c7ad79 2455
1da177e4
LT		 2456 ata_bus_post_reset(ap, devmask);
2457
2458 return 0;
2459}
2460
2461/**
2462 * ata_bus_reset - reset host port and associated ATA channel
2463 * @ap: port to reset
2464 *
2465 * This is typically the first time we actually start issuing
2466 * commands to the ATA channel. We wait for BSY to clear, then
2467 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
2468 * result. Determine what devices, if any, are on the channel
2469 * by looking at the device 0/1 error register. Look at the signature
2470 * stored in each device's taskfile registers, to determine if
2471 * the device is ATA or ATAPI.
2472 *
2473 * LOCKING:
0cba632b 2474 * PCI/etc. bus probe sem.
cca3974e 2475 * Obtains host lock.
1da177e4
LT		 2476 *
2477 * SIDE EFFECTS:
198e0fed 2478 * Sets ATA_FLAG_DISABLED if bus reset fails.
1da177e4
LT		 2479 */
2480
2481void ata_bus_reset(struct ata_port *ap)
2482{
2483 struct ata_ioports *ioaddr = &ap->ioaddr;
2484 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2485 u8 err;
aec5c3c1 2486 unsigned int dev0, dev1 = 0, devmask = 0;
1da177e4
LT		 2487
2488 DPRINTK("ENTER, host %u, port %u\n", ap->id, ap->port_no);
2489
2490 /* determine if device 0/1 are present */
2491 if (ap->flags & ATA_FLAG_SATA_RESET)
2492 dev0 = 1;
2493 else {
2494 dev0 = ata_devchk(ap, 0);
2495 if (slave_possible)
2496 dev1 = ata_devchk(ap, 1);
2497 }
2498
2499 if (dev0)
2500 devmask |= (1 << 0);
2501 if (dev1)
2502 devmask |= (1 << 1);
2503
2504 /* select device 0 again */
2505 ap->ops->dev_select(ap, 0);
2506
2507 /* issue bus reset */
2508 if (ap->flags & ATA_FLAG_SRST)
aec5c3c1
TH		 2509 if (ata_bus_softreset(ap, devmask))
2510 goto err_out;
1da177e4
LT		 2511
2512 /*
2513 * determine by signature whether we have ATA or ATAPI devices
2514 */
b4dc7623 2515 ap->device[0].class = ata_dev_try_classify(ap, 0, &err);
1da177e4 2516 if ((slave_possible) && (err != 0x81))
b4dc7623 2517 ap->device[1].class = ata_dev_try_classify(ap, 1, &err);
1da177e4
LT		 2518
2519 /* re-enable interrupts */
2520 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
2521 ata_irq_on(ap);
2522
2523 /* is double-select really necessary? */
2524 if (ap->device[1].class != ATA_DEV_NONE)
2525 ap->ops->dev_select(ap, 1);
2526 if (ap->device[0].class != ATA_DEV_NONE)
2527 ap->ops->dev_select(ap, 0);
2528
2529 /* if no devices were detected, disable this port */
2530 if ((ap->device[0].class == ATA_DEV_NONE) &&
2531 (ap->device[1].class == ATA_DEV_NONE))
2532 goto err_out;
2533
2534 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2535 /* set up device control for ATA_FLAG_SATA_RESET */
2536 if (ap->flags & ATA_FLAG_MMIO)
2537 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2538 else
2539 outb(ap->ctl, ioaddr->ctl_addr);
2540 }
2541
2542 DPRINTK("EXIT\n");
2543 return;
2544
2545err_out:
f15a1daf 2546 ata_port_printk(ap, KERN_ERR, "disabling port\n");
1da177e4
LT		 2547 ap->ops->port_disable(ap);
2548
2549 DPRINTK("EXIT\n");
2550}
2551
d7bb4cc7
TH		 2552/**
2553 * sata_phy_debounce - debounce SATA phy status
2554 * @ap: ATA port to debounce SATA phy status for
2555 * @params: timing parameters { interval, duratinon, timeout } in msec
2556 *
2557 * Make sure SStatus of @ap reaches stable state, determined by
2558 * holding the same value where DET is not 1 for @duration polled
2559 * every @interval, before @timeout. Timeout constraints the
2560 * beginning of the stable state. Because, after hot unplugging,
2561 * DET gets stuck at 1 on some controllers, this functions waits
2562 * until timeout then returns 0 if DET is stable at 1.
2563 *
2564 * LOCKING:
2565 * Kernel thread context (may sleep)
2566 *
2567 * RETURNS:
2568 * 0 on success, -errno on failure.
2569 */
2570int sata_phy_debounce(struct ata_port *ap, const unsigned long *params)
7a7921e8 2571{
d7bb4cc7
TH		 2572 unsigned long interval_msec = params[0];
2573 unsigned long duration = params[1] * HZ / 1000;
2574 unsigned long timeout = jiffies + params[2] * HZ / 1000;
2575 unsigned long last_jiffies;
2576 u32 last, cur;
2577 int rc;
2578
2579 if ((rc = sata_scr_read(ap, SCR_STATUS, &cur)))
2580 return rc;
2581 cur &= 0xf;
2582
2583 last = cur;
2584 last_jiffies = jiffies;
2585
2586 while (1) {
2587 msleep(interval_msec);
2588 if ((rc = sata_scr_read(ap, SCR_STATUS, &cur)))
2589 return rc;
2590 cur &= 0xf;
2591
2592 /* DET stable? */
2593 if (cur == last) {
2594 if (cur == 1 && time_before(jiffies, timeout))
2595 continue;
2596 if (time_after(jiffies, last_jiffies + duration))
2597 return 0;
2598 continue;
2599 }
2600
2601 /* unstable, start over */
2602 last = cur;
2603 last_jiffies = jiffies;
2604
2605 /* check timeout */
2606 if (time_after(jiffies, timeout))
2607 return -EBUSY;
2608 }
2609}
2610
2611/**
2612 * sata_phy_resume - resume SATA phy
2613 * @ap: ATA port to resume SATA phy for
2614 * @params: timing parameters { interval, duratinon, timeout } in msec
2615 *
2616 * Resume SATA phy of @ap and debounce it.
2617 *
2618 * LOCKING:
2619 * Kernel thread context (may sleep)
2620 *
2621 * RETURNS:
2622 * 0 on success, -errno on failure.
2623 */
2624int sata_phy_resume(struct ata_port *ap, const unsigned long *params)
2625{
2626 u32 scontrol;
81952c54
TH		 2627 int rc;
2628
2629 if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
2630 return rc;
7a7921e8 2631
852ee16a 2632 scontrol = (scontrol & 0x0f0) | 0x300;
81952c54
TH		 2633
2634 if ((rc = sata_scr_write(ap, SCR_CONTROL, scontrol)))
2635 return rc;
7a7921e8 2636
d7bb4cc7
TH		 2637 /* Some PHYs react badly if SStatus is pounded immediately
2638 * after resuming. Delay 200ms before debouncing.
2639 */
2640 msleep(200);
7a7921e8 2641
d7bb4cc7 2642 return sata_phy_debounce(ap, params);
7a7921e8
TH		 2643}
2644
f5914a46
TH		 2645static void ata_wait_spinup(struct ata_port *ap)
2646{
2647 struct ata_eh_context *ehc = &ap->eh_context;
2648 unsigned long end, secs;
2649 int rc;
2650
2651 /* first, debounce phy if SATA */
2652 if (ap->cbl == ATA_CBL_SATA) {
e9c83914 2653 rc = sata_phy_debounce(ap, sata_deb_timing_hotplug);
f5914a46
TH		 2654
2655 /* if debounced successfully and offline, no need to wait */
2656 if ((rc == 0 || rc == -EOPNOTSUPP) && ata_port_offline(ap))
2657 return;
2658 }
2659
2660 /* okay, let's give the drive time to spin up */
2661 end = ehc->i.hotplug_timestamp + ATA_SPINUP_WAIT * HZ / 1000;
2662 secs = ((end - jiffies) + HZ - 1) / HZ;
2663
2664 if (time_after(jiffies, end))
2665 return;
2666
2667 if (secs > 5)
2668 ata_port_printk(ap, KERN_INFO, "waiting for device to spin up "
2669 "(%lu secs)\n", secs);
2670
2671 schedule_timeout_uninterruptible(end - jiffies);
2672}
2673
2674/**
2675 * ata_std_prereset - prepare for reset
2676 * @ap: ATA port to be reset
2677 *
2678 * @ap is about to be reset. Initialize it.
2679 *
2680 * LOCKING:
2681 * Kernel thread context (may sleep)
2682 *
2683 * RETURNS:
2684 * 0 on success, -errno otherwise.
2685 */
2686int ata_std_prereset(struct ata_port *ap)
2687{
2688 struct ata_eh_context *ehc = &ap->eh_context;
e9c83914 2689 const unsigned long *timing = sata_ehc_deb_timing(ehc);
f5914a46
TH		 2690 int rc;
2691
28324304
TH		 2692 /* handle link resume & hotplug spinup */
2693 if ((ehc->i.flags & ATA_EHI_RESUME_LINK) &&
2694 (ap->flags & ATA_FLAG_HRST_TO_RESUME))
2695 ehc->i.action |= ATA_EH_HARDRESET;
2696
2697 if ((ehc->i.flags & ATA_EHI_HOTPLUGGED) &&
2698 (ap->flags & ATA_FLAG_SKIP_D2H_BSY))
2699 ata_wait_spinup(ap);
f5914a46
TH		 2700
2701 /* if we're about to do hardreset, nothing more to do */
2702 if (ehc->i.action & ATA_EH_HARDRESET)
2703 return 0;
2704
2705 /* if SATA, resume phy */
2706 if (ap->cbl == ATA_CBL_SATA) {
f5914a46
TH		 2707 rc = sata_phy_resume(ap, timing);
2708 if (rc && rc != -EOPNOTSUPP) {
2709 /* phy resume failed */
2710 ata_port_printk(ap, KERN_WARNING, "failed to resume "
2711 "link for reset (errno=%d)\n", rc);
2712 return rc;
2713 }
2714 }
2715
2716 /* Wait for !BSY if the controller can wait for the first D2H
2717 * Reg FIS and we don't know that no device is attached.
2718 */
2719 if (!(ap->flags & ATA_FLAG_SKIP_D2H_BSY) && !ata_port_offline(ap))
2720 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
2721
2722 return 0;
2723}
2724
c2bd5804
TH		 2725/**
2726 * ata_std_softreset - reset host port via ATA SRST
2727 * @ap: port to reset
c2bd5804
TH		 2728 * @classes: resulting classes of attached devices
2729 *
52783c5d 2730 * Reset host port using ATA SRST.
c2bd5804
TH		 2731 *
2732 * LOCKING:
2733 * Kernel thread context (may sleep)
2734 *
2735 * RETURNS:
2736 * 0 on success, -errno otherwise.
2737 */
2bf2cb26 2738int ata_std_softreset(struct ata_port *ap, unsigned int *classes)
c2bd5804
TH		 2739{
2740 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2741 unsigned int devmask = 0, err_mask;
2742 u8 err;
2743
2744 DPRINTK("ENTER\n");
2745
81952c54 2746 if (ata_port_offline(ap)) {
3a39746a
TH		 2747 classes[0] = ATA_DEV_NONE;
2748 goto out;
2749 }
2750
c2bd5804
TH		 2751 /* determine if device 0/1 are present */
2752 if (ata_devchk(ap, 0))
2753 devmask |= (1 << 0);
2754 if (slave_possible && ata_devchk(ap, 1))
2755 devmask |= (1 << 1);
2756
c2bd5804
TH		 2757 /* select device 0 again */
2758 ap->ops->dev_select(ap, 0);
2759
2760 /* issue bus reset */
2761 DPRINTK("about to softreset, devmask=%x\n", devmask);
2762 err_mask = ata_bus_softreset(ap, devmask);
2763 if (err_mask) {
f15a1daf
TH		 2764 ata_port_printk(ap, KERN_ERR, "SRST failed (err_mask=0x%x)\n",
2765 err_mask);
c2bd5804
TH		 2766 return -EIO;
2767 }
2768
2769 /* determine by signature whether we have ATA or ATAPI devices */
2770 classes[0] = ata_dev_try_classify(ap, 0, &err);
2771 if (slave_possible && err != 0x81)
2772 classes[1] = ata_dev_try_classify(ap, 1, &err);
2773
3a39746a 2774 out:
c2bd5804
TH		 2775 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2776 return 0;
2777}
2778
2779/**
2780 * sata_std_hardreset - reset host port via SATA phy reset
2781 * @ap: port to reset
c2bd5804
TH		 2782 * @class: resulting class of attached device
2783 *
2784 * SATA phy-reset host port using DET bits of SControl register.
c2bd5804
TH		 2785 *
2786 * LOCKING:
2787 * Kernel thread context (may sleep)
2788 *
2789 * RETURNS:
2790 * 0 on success, -errno otherwise.
2791 */
2bf2cb26 2792int sata_std_hardreset(struct ata_port *ap, unsigned int *class)
c2bd5804 2793{
e9c83914
TH		 2794 struct ata_eh_context *ehc = &ap->eh_context;
2795 const unsigned long *timing = sata_ehc_deb_timing(ehc);
852ee16a 2796 u32 scontrol;
81952c54 2797 int rc;
852ee16a 2798
c2bd5804
TH		 2799 DPRINTK("ENTER\n");
2800
3c567b7d 2801 if (sata_set_spd_needed(ap)) {
1c3fae4d
TH		 2802 /* SATA spec says nothing about how to reconfigure
2803 * spd. To be on the safe side, turn off phy during
2804 * reconfiguration. This works for at least ICH7 AHCI
2805 * and Sil3124.
2806 */
81952c54
TH		 2807 if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
2808 return rc;
2809
a34b6fc0 2810 scontrol = (scontrol & 0x0f0) | 0x304;
81952c54
TH		 2811
2812 if ((rc = sata_scr_write(ap, SCR_CONTROL, scontrol)))
2813 return rc;
1c3fae4d 2814
3c567b7d 2815 sata_set_spd(ap);
1c3fae4d
TH		 2816 }
2817
2818 /* issue phy wake/reset */
81952c54
TH		 2819 if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
2820 return rc;
2821
852ee16a 2822 scontrol = (scontrol & 0x0f0) | 0x301;
81952c54
TH		 2823
2824 if ((rc = sata_scr_write_flush(ap, SCR_CONTROL, scontrol)))
2825 return rc;
c2bd5804 2826
1c3fae4d 2827 /* Couldn't find anything in SATA I/II specs, but AHCI-1.1
c2bd5804
TH		 2828 * 10.4.2 says at least 1 ms.
2829 */
2830 msleep(1);
2831
1c3fae4d 2832 /* bring phy back */
e9c83914 2833 sata_phy_resume(ap, timing);
c2bd5804 2834
c2bd5804 2835 /* TODO: phy layer with polling, timeouts, etc. */
81952c54 2836 if (ata_port_offline(ap)) {
c2bd5804
TH		 2837 *class = ATA_DEV_NONE;
2838 DPRINTK("EXIT, link offline\n");
2839 return 0;
2840 }
2841
2842 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
f15a1daf
TH		 2843 ata_port_printk(ap, KERN_ERR,
2844 "COMRESET failed (device not ready)\n");
c2bd5804
TH		 2845 return -EIO;
2846 }
2847
3a39746a
TH		 2848 ap->ops->dev_select(ap, 0); /* probably unnecessary */
2849
c2bd5804
TH		 2850 *class = ata_dev_try_classify(ap, 0, NULL);
2851
2852 DPRINTK("EXIT, class=%u\n", *class);
2853 return 0;
2854}
2855
2856/**
2857 * ata_std_postreset - standard postreset callback
2858 * @ap: the target ata_port
2859 * @classes: classes of attached devices
2860 *
2861 * This function is invoked after a successful reset. Note that
2862 * the device might have been reset more than once using
2863 * different reset methods before postreset is invoked.
c2bd5804 2864 *
c2bd5804
TH		 2865 * LOCKING:
2866 * Kernel thread context (may sleep)
2867 */
2868void ata_std_postreset(struct ata_port *ap, unsigned int *classes)
2869{
dc2b3515
TH		 2870 u32 serror;
2871
c2bd5804
TH		 2872 DPRINTK("ENTER\n");
2873
c2bd5804 2874 /* print link status */
81952c54 2875 sata_print_link_status(ap);
c2bd5804 2876
dc2b3515
TH		 2877 /* clear SError */
2878 if (sata_scr_read(ap, SCR_ERROR, &serror) == 0)
2879 sata_scr_write(ap, SCR_ERROR, serror);
2880
3a39746a 2881 /* re-enable interrupts */
e3180499
TH		 2882 if (!ap->ops->error_handler) {
2883 /* FIXME: hack. create a hook instead */
2884 if (ap->ioaddr.ctl_addr)
2885 ata_irq_on(ap);
2886 }
c2bd5804
TH		 2887
2888 /* is double-select really necessary? */
2889 if (classes[0] != ATA_DEV_NONE)
2890 ap->ops->dev_select(ap, 1);
2891 if (classes[1] != ATA_DEV_NONE)
2892 ap->ops->dev_select(ap, 0);
2893
3a39746a
TH		 2894 /* bail out if no device is present */
2895 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2896 DPRINTK("EXIT, no device\n");
2897 return;
2898 }
2899
2900 /* set up device control */
2901 if (ap->ioaddr.ctl_addr) {
2902 if (ap->flags & ATA_FLAG_MMIO)
2903 writeb(ap->ctl, (void __iomem *) ap->ioaddr.ctl_addr);
2904 else
2905 outb(ap->ctl, ap->ioaddr.ctl_addr);
2906 }
c2bd5804
TH		 2907
2908 DPRINTK("EXIT\n");
2909}
2910
623a3128
TH		 2911/**
2912 * ata_dev_same_device - Determine whether new ID matches configured device
623a3128
TH		 2913 * @dev: device to compare against
2914 * @new_class: class of the new device
2915 * @new_id: IDENTIFY page of the new device
2916 *
2917 * Compare @new_class and @new_id against @dev and determine
2918 * whether @dev is the device indicated by @new_class and
2919 * @new_id.
2920 *
2921 * LOCKING:
2922 * None.
2923 *
2924 * RETURNS:
2925 * 1 if @dev matches @new_class and @new_id, 0 otherwise.
2926 */
3373efd8
TH		 2927static int ata_dev_same_device(struct ata_device *dev, unsigned int new_class,
2928 const u16 *new_id)
623a3128
TH		 2929{
2930 const u16 *old_id = dev->id;
2931 unsigned char model[2][41], serial[2][21];
2932 u64 new_n_sectors;
2933
2934 if (dev->class != new_class) {
f15a1daf
TH		 2935 ata_dev_printk(dev, KERN_INFO, "class mismatch %d != %d\n",
2936 dev->class, new_class);
623a3128
TH		 2937 return 0;
2938 }
2939
2940 ata_id_c_string(old_id, model[0], ATA_ID_PROD_OFS, sizeof(model[0]));
2941 ata_id_c_string(new_id, model[1], ATA_ID_PROD_OFS, sizeof(model[1]));
2942 ata_id_c_string(old_id, serial[0], ATA_ID_SERNO_OFS, sizeof(serial[0]));
2943 ata_id_c_string(new_id, serial[1], ATA_ID_SERNO_OFS, sizeof(serial[1]));
2944 new_n_sectors = ata_id_n_sectors(new_id);
2945
2946 if (strcmp(model[0], model[1])) {
f15a1daf
TH		 2947 ata_dev_printk(dev, KERN_INFO, "model number mismatch "
2948 "'%s' != '%s'\n", model[0], model[1]);
623a3128
TH		 2949 return 0;
2950 }
2951
2952 if (strcmp(serial[0], serial[1])) {
f15a1daf
TH		 2953 ata_dev_printk(dev, KERN_INFO, "serial number mismatch "
2954 "'%s' != '%s'\n", serial[0], serial[1]);
623a3128
TH		 2955 return 0;
2956 }
2957
2958 if (dev->class == ATA_DEV_ATA && dev->n_sectors != new_n_sectors) {
f15a1daf
TH		 2959 ata_dev_printk(dev, KERN_INFO, "n_sectors mismatch "
2960 "%llu != %llu\n",
2961 (unsigned long long)dev->n_sectors,
2962 (unsigned long long)new_n_sectors);
623a3128
TH		 2963 return 0;
2964 }
2965
2966 return 1;
2967}
2968
2969/**
2970 * ata_dev_revalidate - Revalidate ATA device
623a3128
TH		 2971 * @dev: device to revalidate
2972 * @post_reset: is this revalidation after reset?
2973 *
2974 * Re-read IDENTIFY page and make sure @dev is still attached to
2975 * the port.
2976 *
2977 * LOCKING:
2978 * Kernel thread context (may sleep)
2979 *
2980 * RETURNS:
2981 * 0 on success, negative errno otherwise
2982 */
3373efd8 2983int ata_dev_revalidate(struct ata_device *dev, int post_reset)
623a3128 2984{
5eb45c02 2985 unsigned int class = dev->class;
f15a1daf 2986 u16 *id = (void *)dev->ap->sector_buf;
623a3128
TH		 2987 int rc;
2988
5eb45c02
TH		 2989 if (!ata_dev_enabled(dev)) {
2990 rc = -ENODEV;
2991 goto fail;
2992 }
623a3128 2993
fe635c7e 2994 /* read ID data */
3373efd8 2995 rc = ata_dev_read_id(dev, &class, post_reset, id);
623a3128
TH		 2996 if (rc)
2997 goto fail;
2998
2999 /* is the device still there? */
3373efd8 3000 if (!ata_dev_same_device(dev, class, id)) {
623a3128
TH		 3001 rc = -ENODEV;
3002 goto fail;
3003 }
3004
fe635c7e 3005 memcpy(dev->id, id, sizeof(id[0]) * ATA_ID_WORDS);
623a3128
TH		 3006
3007 /* configure device according to the new ID */
3373efd8 3008 rc = ata_dev_configure(dev, 0);
5eb45c02
TH		 3009 if (rc == 0)
3010 return 0;
623a3128
TH		 3011
3012 fail:
f15a1daf 3013 ata_dev_printk(dev, KERN_ERR, "revalidation failed (errno=%d)\n", rc);
623a3128
TH		 3014 return rc;
3015}
3016
98ac62de 3017static const char * const ata_dma_blacklist [] = {
f4b15fef
AC		 3018 "WDC AC11000H", NULL,
3019 "WDC AC22100H", NULL,
3020 "WDC AC32500H", NULL,
3021 "WDC AC33100H", NULL,
3022 "WDC AC31600H", NULL,
3023 "WDC AC32100H", "24.09P07",
3024 "WDC AC23200L", "21.10N21",
3025 "Compaq CRD-8241B", NULL,
3026 "CRD-8400B", NULL,
3027 "CRD-8480B", NULL,
3028 "CRD-8482B", NULL,
3029 "CRD-84", NULL,
3030 "SanDisk SDP3B", NULL,
3031 "SanDisk SDP3B-64", NULL,
3032 "SANYO CD-ROM CRD", NULL,
3033 "HITACHI CDR-8", NULL,
2e9edbf8 3034 "HITACHI CDR-8335", NULL,
f4b15fef 3035 "HITACHI CDR-8435", NULL,
2e9edbf8
JG		 3036 "Toshiba CD-ROM XM-6202B", NULL,
3037 "TOSHIBA CD-ROM XM-1702BC", NULL,
3038 "CD-532E-A", NULL,
3039 "E-IDE CD-ROM CR-840", NULL,
3040 "CD-ROM Drive/F5A", NULL,
3041 "WPI CDD-820", NULL,
f4b15fef 3042 "SAMSUNG CD-ROM SC-148C", NULL,
2e9edbf8 3043 "SAMSUNG CD-ROM SC", NULL,
f4b15fef
AC		 3044 "SanDisk SDP3B-64", NULL,
3045 "ATAPI CD-ROM DRIVE 40X MAXIMUM",NULL,
3046 "_NEC DV5800A", NULL,
3047 "SAMSUNG CD-ROM SN-124", "N001"
1da177e4 3048};
2e9edbf8 3049
f4b15fef
AC		 3050static int ata_strim(char *s, size_t len)
3051{
3052 len = strnlen(s, len);
3053
3054 /* ATAPI specifies that empty space is blank-filled; remove blanks */
3055 while ((len > 0) && (s[len - 1] == ' ')) {
3056 len--;
3057 s[len] = 0;
3058 }
3059 return len;
3060}
1da177e4 3061
057ace5e 3062static int ata_dma_blacklisted(const struct ata_device *dev)
1da177e4 3063{
f4b15fef
AC		 3064 unsigned char model_num[40];
3065 unsigned char model_rev[16];
3066 unsigned int nlen, rlen;
1da177e4
LT		 3067 int i;
3068
3a778275
AL		 3069 /* We don't support polling DMA.
3070 * DMA blacklist those ATAPI devices with CDB-intr (and use PIO)
3071 * if the LLDD handles only interrupts in the HSM_ST_LAST state.
3072 */
3073 if ((dev->ap->flags & ATA_FLAG_PIO_POLLING) &&
3074 (dev->flags & ATA_DFLAG_CDB_INTR))
3075 return 1;
3076
f4b15fef
AC		 3077 ata_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
3078 sizeof(model_num));
3079 ata_id_string(dev->id, model_rev, ATA_ID_FW_REV_OFS,
3080 sizeof(model_rev));
3081 nlen = ata_strim(model_num, sizeof(model_num));
3082 rlen = ata_strim(model_rev, sizeof(model_rev));
1da177e4 3083
f4b15fef
AC		 3084 for (i = 0; i < ARRAY_SIZE(ata_dma_blacklist); i += 2) {
3085 if (!strncmp(ata_dma_blacklist[i], model_num, nlen)) {
3086 if (ata_dma_blacklist[i+1] == NULL)
3087 return 1;
3088 if (!strncmp(ata_dma_blacklist[i], model_rev, rlen))
3089 return 1;
3090 }
3091 }
1da177e4
LT		 3092 return 0;
3093}
3094
a6d5a51c
TH		 3095/**
3096 * ata_dev_xfermask - Compute supported xfermask of the given device
a6d5a51c
TH		 3097 * @dev: Device to compute xfermask for
3098 *
acf356b1
TH		 3099 * Compute supported xfermask of @dev and store it in
3100 * dev->*_mask. This function is responsible for applying all
3101 * known limits including host controller limits, device
3102 * blacklist, etc...
a6d5a51c
TH		 3103 *
3104 * LOCKING:
3105 * None.
a6d5a51c 3106 */
3373efd8 3107static void ata_dev_xfermask(struct ata_device *dev)
1da177e4 3108{
3373efd8 3109 struct ata_port *ap = dev->ap;
cca3974e 3110 struct ata_host *host = ap->host;
a6d5a51c 3111 unsigned long xfer_mask;
1da177e4 3112
37deecb5 3113 /* controller modes available */
565083e1
TH		 3114 xfer_mask = ata_pack_xfermask(ap->pio_mask,
3115 ap->mwdma_mask, ap->udma_mask);
3116
3117 /* Apply cable rule here. Don't apply it early because when
3118 * we handle hot plug the cable type can itself change.
3119 */
3120 if (ap->cbl == ATA_CBL_PATA40)
3121 xfer_mask &= ~(0xF8 << ATA_SHIFT_UDMA);
1da177e4 3122
37deecb5
TH		 3123 xfer_mask &= ata_pack_xfermask(dev->pio_mask,
3124 dev->mwdma_mask, dev->udma_mask);
3125 xfer_mask &= ata_id_xfermask(dev->id);
565083e1 3126
b352e57d
AC		 3127 /*
3128 * CFA Advanced TrueIDE timings are not allowed on a shared
3129 * cable
3130 */
3131 if (ata_dev_pair(dev)) {
3132 /* No PIO5 or PIO6 */
3133 xfer_mask &= ~(0x03 << (ATA_SHIFT_PIO + 5));
3134 /* No MWDMA3 or MWDMA 4 */
3135 xfer_mask &= ~(0x03 << (ATA_SHIFT_MWDMA + 3));
3136 }
3137
37deecb5
TH		 3138 if (ata_dma_blacklisted(dev)) {
3139 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
f15a1daf
TH		 3140 ata_dev_printk(dev, KERN_WARNING,
3141 "device is on DMA blacklist, disabling DMA\n");
37deecb5 3142 }
a6d5a51c 3143
cca3974e 3144 if ((host->flags & ATA_HOST_SIMPLEX) && host->simplex_claimed) {
37deecb5
TH		 3145 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
3146 ata_dev_printk(dev, KERN_WARNING, "simplex DMA is claimed by "
3147 "other device, disabling DMA\n");
5444a6f4 3148 }
565083e1 3149
5444a6f4
AC		 3150 if (ap->ops->mode_filter)
3151 xfer_mask = ap->ops->mode_filter(ap, dev, xfer_mask);
3152
565083e1
TH		 3153 ata_unpack_xfermask(xfer_mask, &dev->pio_mask,
3154 &dev->mwdma_mask, &dev->udma_mask);
1da177e4
LT		 3155}
3156
1da177e4
LT		 3157/**
3158 * ata_dev_set_xfermode - Issue SET FEATURES - XFER MODE command
1da177e4
LT		 3159 * @dev: Device to which command will be sent
3160 *
780a87f7
JG		 3161 * Issue SET FEATURES - XFER MODE command to device @dev
3162 * on port @ap.
3163 *
1da177e4 3164 * LOCKING:
0cba632b 3165 * PCI/etc. bus probe sem.
83206a29
TH		 3166 *
3167 * RETURNS:
3168 * 0 on success, AC_ERR_* mask otherwise.
1da177e4
LT		 3169 */
3170
3373efd8 3171static unsigned int ata_dev_set_xfermode(struct ata_device *dev)
1da177e4 3172{
a0123703 3173 struct ata_taskfile tf;
83206a29 3174 unsigned int err_mask;
1da177e4
LT		 3175
3176 /* set up set-features taskfile */
3177 DPRINTK("set features - xfer mode\n");
3178
3373efd8 3179 ata_tf_init(dev, &tf);
a0123703
TH		 3180 tf.command = ATA_CMD_SET_FEATURES;
3181 tf.feature = SETFEATURES_XFER;
3182 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
3183 tf.protocol = ATA_PROT_NODATA;
3184 tf.nsect = dev->xfer_mode;
1da177e4 3185
3373efd8 3186 err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0);
1da177e4 3187
83206a29
TH		 3188 DPRINTK("EXIT, err_mask=%x\n", err_mask);
3189 return err_mask;
1da177e4
LT		 3190}
3191
8bf62ece
AL		 3192/**
3193 * ata_dev_init_params - Issue INIT DEV PARAMS command
8bf62ece 3194 * @dev: Device to which command will be sent
e2a7f77a
RD		 3195 * @heads: Number of heads (taskfile parameter)
3196 * @sectors: Number of sectors (taskfile parameter)
8bf62ece
AL		 3197 *
3198 * LOCKING:
6aff8f1f
TH		 3199 * Kernel thread context (may sleep)
3200 *
3201 * RETURNS:
3202 * 0 on success, AC_ERR_* mask otherwise.
8bf62ece 3203 */
3373efd8
TH		 3204static unsigned int ata_dev_init_params(struct ata_device *dev,
3205 u16 heads, u16 sectors)
8bf62ece 3206{
a0123703 3207 struct ata_taskfile tf;
6aff8f1f 3208 unsigned int err_mask;
8bf62ece
AL		 3209
3210 /* Number of sectors per track 1-255. Number of heads 1-16 */
3211 if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
00b6f5e9 3212 return AC_ERR_INVALID;
8bf62ece
AL		 3213
3214 /* set up init dev params taskfile */
3215 DPRINTK("init dev params \n");
3216
3373efd8 3217 ata_tf_init(dev, &tf);
a0123703
TH		 3218 tf.command = ATA_CMD_INIT_DEV_PARAMS;
3219 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
3220 tf.protocol = ATA_PROT_NODATA;
3221 tf.nsect = sectors;
3222 tf.device |= (heads - 1) & 0x0f; /* max head = num. of heads - 1 */
8bf62ece 3223
3373efd8 3224 err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0);
8bf62ece 3225
6aff8f1f
TH		 3226 DPRINTK("EXIT, err_mask=%x\n", err_mask);
3227 return err_mask;
8bf62ece
AL		 3228}
3229
1da177e4 3230/**
0cba632b
JG		 3231 * ata_sg_clean - Unmap DMA memory associated with command
3232 * @qc: Command containing DMA memory to be released
3233 *
3234 * Unmap all mapped DMA memory associated with this command.
1da177e4
LT		 3235 *
3236 * LOCKING:
cca3974e 3237 * spin_lock_irqsave(host lock)
1da177e4
LT		 3238 */
3239
3240static void ata_sg_clean(struct ata_queued_cmd *qc)
3241{
3242 struct ata_port *ap = qc->ap;
cedc9a47 3243 struct scatterlist *sg = qc->__sg;
1da177e4 3244 int dir = qc->dma_dir;
cedc9a47 3245 void *pad_buf = NULL;
1da177e4 3246
a4631474
TH		 3247 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
3248 WARN_ON(sg == NULL);
1da177e4
LT		 3249
3250 if (qc->flags & ATA_QCFLAG_SINGLE)
f131883e 3251 WARN_ON(qc->n_elem > 1);
1da177e4 3252
2c13b7ce 3253 VPRINTK("unmapping %u sg elements\n", qc->n_elem);
1da177e4 3254
cedc9a47
JG		 3255 /* if we padded the buffer out to 32-bit bound, and data
3256 * xfer direction is from-device, we must copy from the
3257 * pad buffer back into the supplied buffer
3258 */
3259 if (qc->pad_len && !(qc->tf.flags & ATA_TFLAG_WRITE))
3260 pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
3261
3262 if (qc->flags & ATA_QCFLAG_SG) {
e1410f2d 3263 if (qc->n_elem)
2f1f610b 3264 dma_unmap_sg(ap->dev, sg, qc->n_elem, dir);
cedc9a47
JG		 3265 /* restore last sg */
3266 sg[qc->orig_n_elem - 1].length += qc->pad_len;
3267 if (pad_buf) {
3268 struct scatterlist *psg = &qc->pad_sgent;
3269 void *addr = kmap_atomic(psg->page, KM_IRQ0);
3270 memcpy(addr + psg->offset, pad_buf, qc->pad_len);
dfa15988 3271 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 3272 }
3273 } else {
2e242fa9 3274 if (qc->n_elem)
2f1f610b 3275 dma_unmap_single(ap->dev,
e1410f2d
JG		 3276 sg_dma_address(&sg[0]), sg_dma_len(&sg[0]),
3277 dir);
cedc9a47
JG		 3278 /* restore sg */
3279 sg->length += qc->pad_len;
3280 if (pad_buf)
3281 memcpy(qc->buf_virt + sg->length - qc->pad_len,
3282 pad_buf, qc->pad_len);
3283 }
1da177e4
LT		 3284
3285 qc->flags &= ~ATA_QCFLAG_DMAMAP;
cedc9a47 3286 qc->__sg = NULL;
1da177e4
LT		 3287}
3288
3289/**
3290 * ata_fill_sg - Fill PCI IDE PRD table
3291 * @qc: Metadata associated with taskfile to be transferred
3292 *
780a87f7
JG		 3293 * Fill PCI IDE PRD (scatter-gather) table with segments
3294 * associated with the current disk command.
3295 *
1da177e4 3296 * LOCKING:
cca3974e 3297 * spin_lock_irqsave(host lock)
1da177e4
LT		 3298 *
3299 */
3300static void ata_fill_sg(struct ata_queued_cmd *qc)
3301{
1da177e4 3302 struct ata_port *ap = qc->ap;
cedc9a47
JG		 3303 struct scatterlist *sg;
3304 unsigned int idx;
1da177e4 3305
a4631474 3306 WARN_ON(qc->__sg == NULL);
f131883e 3307 WARN_ON(qc->n_elem == 0 && qc->pad_len == 0);
1da177e4
LT		 3308
3309 idx = 0;
cedc9a47 3310 ata_for_each_sg(sg, qc) {
1da177e4
LT		 3311 u32 addr, offset;
3312 u32 sg_len, len;
3313
3314 /* determine if physical DMA addr spans 64K boundary.
3315 * Note h/w doesn't support 64-bit, so we unconditionally
3316 * truncate dma_addr_t to u32.
3317 */
3318 addr = (u32) sg_dma_address(sg);
3319 sg_len = sg_dma_len(sg);
3320
3321 while (sg_len) {
3322 offset = addr & 0xffff;
3323 len = sg_len;
3324 if ((offset + sg_len) > 0x10000)
3325 len = 0x10000 - offset;
3326
3327 ap->prd[idx].addr = cpu_to_le32(addr);
3328 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
3329 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
3330
3331 idx++;
3332 sg_len -= len;
3333 addr += len;
3334 }
3335 }
3336
3337 if (idx)
3338 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
3339}
3340/**
3341 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported
3342 * @qc: Metadata associated with taskfile to check
3343 *
780a87f7
JG		 3344 * Allow low-level driver to filter ATA PACKET commands, returning
3345 * a status indicating whether or not it is OK to use DMA for the
3346 * supplied PACKET command.
3347 *
1da177e4 3348 * LOCKING:
cca3974e 3349 * spin_lock_irqsave(host lock)
0cba632b 3350 *
1da177e4
LT		 3351 * RETURNS: 0 when ATAPI DMA can be used
3352 * nonzero otherwise
3353 */
3354int ata_check_atapi_dma(struct ata_queued_cmd *qc)
3355{
3356 struct ata_port *ap = qc->ap;
3357 int rc = 0; /* Assume ATAPI DMA is OK by default */
3358
3359 if (ap->ops->check_atapi_dma)
3360 rc = ap->ops->check_atapi_dma(qc);
3361
3362 return rc;
3363}
3364/**
3365 * ata_qc_prep - Prepare taskfile for submission
3366 * @qc: Metadata associated with taskfile to be prepared
3367 *
780a87f7
JG		 3368 * Prepare ATA taskfile for submission.
3369 *
1da177e4 3370 * LOCKING:
cca3974e 3371 * spin_lock_irqsave(host lock)
1da177e4
LT		 3372 */
3373void ata_qc_prep(struct ata_queued_cmd *qc)
3374{
3375 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
3376 return;
3377
3378 ata_fill_sg(qc);
3379}
3380
e46834cd
BK		 3381void ata_noop_qc_prep(struct ata_queued_cmd *qc) { }
3382
0cba632b
JG		 3383/**
3384 * ata_sg_init_one - Associate command with memory buffer
3385 * @qc: Command to be associated
3386 * @buf: Memory buffer
3387 * @buflen: Length of memory buffer, in bytes.
3388 *
3389 * Initialize the data-related elements of queued_cmd @qc
3390 * to point to a single memory buffer, @buf of byte length @buflen.
3391 *
3392 * LOCKING:
cca3974e 3393 * spin_lock_irqsave(host lock)
0cba632b
JG		 3394 */
3395
1da177e4
LT		 3396void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf, unsigned int buflen)
3397{
3398 struct scatterlist *sg;
3399
3400 qc->flags |= ATA_QCFLAG_SINGLE;
3401
3402 memset(&qc->sgent, 0, sizeof(qc->sgent));
cedc9a47 3403 qc->__sg = &qc->sgent;
1da177e4 3404 qc->n_elem = 1;
cedc9a47 3405 qc->orig_n_elem = 1;
1da177e4 3406 qc->buf_virt = buf;
233277ca 3407 qc->nbytes = buflen;
1da177e4 3408
cedc9a47 3409 sg = qc->__sg;
f0612bbc 3410 sg_init_one(sg, buf, buflen);
1da177e4
LT		 3411}
3412
0cba632b
JG		 3413/**
3414 * ata_sg_init - Associate command with scatter-gather table.
3415 * @qc: Command to be associated
3416 * @sg: Scatter-gather table.
3417 * @n_elem: Number of elements in s/g table.
3418 *
3419 * Initialize the data-related elements of queued_cmd @qc
3420 * to point to a scatter-gather table @sg, containing @n_elem
3421 * elements.
3422 *
3423 * LOCKING:
cca3974e 3424 * spin_lock_irqsave(host lock)
0cba632b
JG		 3425 */
3426
1da177e4
LT		 3427void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
3428 unsigned int n_elem)
3429{
3430 qc->flags |= ATA_QCFLAG_SG;
cedc9a47 3431 qc->__sg = sg;
1da177e4 3432 qc->n_elem = n_elem;
cedc9a47 3433 qc->orig_n_elem = n_elem;
1da177e4
LT		 3434}
3435
3436/**
0cba632b
JG		 3437 * ata_sg_setup_one - DMA-map the memory buffer associated with a command.
3438 * @qc: Command with memory buffer to be mapped.
3439 *
3440 * DMA-map the memory buffer associated with queued_cmd @qc.
1da177e4
LT		 3441 *
3442 * LOCKING:
cca3974e 3443 * spin_lock_irqsave(host lock)
1da177e4
LT		 3444 *
3445 * RETURNS:
0cba632b 3446 * Zero on success, negative on error.
1da177e4
LT		 3447 */
3448
3449static int ata_sg_setup_one(struct ata_queued_cmd *qc)
3450{
3451 struct ata_port *ap = qc->ap;
3452 int dir = qc->dma_dir;
cedc9a47 3453 struct scatterlist *sg = qc->__sg;
1da177e4 3454 dma_addr_t dma_address;
2e242fa9 3455 int trim_sg = 0;
1da177e4 3456
cedc9a47
JG		 3457 /* we must lengthen transfers to end on a 32-bit boundary */
3458 qc->pad_len = sg->length & 3;
3459 if (qc->pad_len) {
3460 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
3461 struct scatterlist *psg = &qc->pad_sgent;
3462
a4631474 3463 WARN_ON(qc->dev->class != ATA_DEV_ATAPI);
cedc9a47
JG		 3464
3465 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
3466
3467 if (qc->tf.flags & ATA_TFLAG_WRITE)
3468 memcpy(pad_buf, qc->buf_virt + sg->length - qc->pad_len,
3469 qc->pad_len);
3470
3471 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
3472 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
3473 /* trim sg */
3474 sg->length -= qc->pad_len;
2e242fa9
TH		 3475 if (sg->length == 0)
3476 trim_sg = 1;
cedc9a47
JG		 3477
3478 DPRINTK("padding done, sg->length=%u pad_len=%u\n",
3479 sg->length, qc->pad_len);
3480 }
3481
2e242fa9
TH		 3482 if (trim_sg) {
3483 qc->n_elem--;
e1410f2d
JG		 3484 goto skip_map;
3485 }
3486
2f1f610b 3487 dma_address = dma_map_single(ap->dev, qc->buf_virt,
32529e01 3488 sg->length, dir);
537a95d9
TH		 3489 if (dma_mapping_error(dma_address)) {
3490 /* restore sg */
3491 sg->length += qc->pad_len;
1da177e4 3492 return -1;
537a95d9 3493 }
1da177e4
LT		 3494
3495 sg_dma_address(sg) = dma_address;
32529e01 3496 sg_dma_len(sg) = sg->length;
1da177e4 3497
2e242fa9 3498skip_map:
1da177e4
LT		 3499 DPRINTK("mapped buffer of %d bytes for %s\n", sg_dma_len(sg),
3500 qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3501
3502 return 0;
3503}
3504
3505/**
0cba632b
JG		 3506 * ata_sg_setup - DMA-map the scatter-gather table associated with a command.
3507 * @qc: Command with scatter-gather table to be mapped.
3508 *
3509 * DMA-map the scatter-gather table associated with queued_cmd @qc.
1da177e4
LT		 3510 *
3511 * LOCKING:
cca3974e 3512 * spin_lock_irqsave(host lock)
1da177e4
LT		 3513 *
3514 * RETURNS:
0cba632b 3515 * Zero on success, negative on error.
1da177e4
LT		 3516 *
3517 */
3518
3519static int ata_sg_setup(struct ata_queued_cmd *qc)
3520{
3521 struct ata_port *ap = qc->ap;
cedc9a47
JG		 3522 struct scatterlist *sg = qc->__sg;
3523 struct scatterlist *lsg = &sg[qc->n_elem - 1];
e1410f2d 3524 int n_elem, pre_n_elem, dir, trim_sg = 0;
1da177e4
LT		 3525
3526 VPRINTK("ENTER, ata%u\n", ap->id);
a4631474 3527 WARN_ON(!(qc->flags & ATA_QCFLAG_SG));
1da177e4 3528
cedc9a47
JG		 3529 /* we must lengthen transfers to end on a 32-bit boundary */
3530 qc->pad_len = lsg->length & 3;
3531 if (qc->pad_len) {
3532 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
3533 struct scatterlist *psg = &qc->pad_sgent;
3534 unsigned int offset;
3535
a4631474 3536 WARN_ON(qc->dev->class != ATA_DEV_ATAPI);
cedc9a47
JG		 3537
3538 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
3539
3540 /*
3541 * psg->page/offset are used to copy to-be-written
3542 * data in this function or read data in ata_sg_clean.
3543 */
3544 offset = lsg->offset + lsg->length - qc->pad_len;
3545 psg->page = nth_page(lsg->page, offset >> PAGE_SHIFT);
3546 psg->offset = offset_in_page(offset);
3547
3548 if (qc->tf.flags & ATA_TFLAG_WRITE) {
3549 void *addr = kmap_atomic(psg->page, KM_IRQ0);
3550 memcpy(pad_buf, addr + psg->offset, qc->pad_len);
dfa15988 3551 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 3552 }
3553
3554 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
3555 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
3556 /* trim last sg */
3557 lsg->length -= qc->pad_len;
e1410f2d
JG		 3558 if (lsg->length == 0)
3559 trim_sg = 1;
cedc9a47
JG		 3560
3561 DPRINTK("padding done, sg[%d].length=%u pad_len=%u\n",
3562 qc->n_elem - 1, lsg->length, qc->pad_len);
3563 }
3564
e1410f2d
JG		 3565 pre_n_elem = qc->n_elem;
3566 if (trim_sg && pre_n_elem)
3567 pre_n_elem--;
3568
3569 if (!pre_n_elem) {
3570 n_elem = 0;
3571 goto skip_map;
3572 }
3573
1da177e4 3574 dir = qc->dma_dir;
2f1f610b 3575 n_elem = dma_map_sg(ap->dev, sg, pre_n_elem, dir);
537a95d9
TH		 3576 if (n_elem < 1) {
3577 /* restore last sg */
3578 lsg->length += qc->pad_len;
1da177e4 3579 return -1;
537a95d9 3580 }
1da177e4
LT		 3581
3582 DPRINTK("%d sg elements mapped\n", n_elem);
3583
e1410f2d 3584skip_map:
1da177e4
LT		 3585 qc->n_elem = n_elem;
3586
3587 return 0;
3588}
3589
0baab86b 3590/**
c893a3ae 3591 * swap_buf_le16 - swap halves of 16-bit words in place
0baab86b
EF		 3592 * @buf: Buffer to swap
3593 * @buf_words: Number of 16-bit words in buffer.
3594 *
3595 * Swap halves of 16-bit words if needed to convert from
3596 * little-endian byte order to native cpu byte order, or
3597 * vice-versa.
3598 *
3599 * LOCKING:
6f0ef4fa 3600 * Inherited from caller.
0baab86b 3601 */
1da177e4
LT		 3602void swap_buf_le16(u16 *buf, unsigned int buf_words)
3603{
3604#ifdef __BIG_ENDIAN
3605 unsigned int i;
3606
3607 for (i = 0; i < buf_words; i++)
3608 buf[i] = le16_to_cpu(buf[i]);
3609#endif /* __BIG_ENDIAN */
3610}
3611
6ae4cfb5
AL		 3612/**
3613 * ata_mmio_data_xfer - Transfer data by MMIO
bf717b11 3614 * @adev: device for this I/O
6ae4cfb5
AL		 3615 * @buf: data buffer
3616 * @buflen: buffer length
344babaa 3617 * @write_data: read/write
6ae4cfb5
AL		 3618 *
3619 * Transfer data from/to the device data register by MMIO.
3620 *
3621 * LOCKING:
3622 * Inherited from caller.
6ae4cfb5
AL		 3623 */
3624
88574551 3625void ata_mmio_data_xfer(struct ata_device *adev, unsigned char *buf,
a6b2c5d4 3626 unsigned int buflen, int write_data)
1da177e4 3627{
a6b2c5d4 3628 struct ata_port *ap = adev->ap;
1da177e4
LT		 3629 unsigned int i;
3630 unsigned int words = buflen >> 1;
3631 u16 *buf16 = (u16 *) buf;
3632 void __iomem *mmio = (void __iomem *)ap->ioaddr.data_addr;
3633
6ae4cfb5 3634 /* Transfer multiple of 2 bytes */
1da177e4
LT		 3635 if (write_data) {
3636 for (i = 0; i < words; i++)
3637 writew(le16_to_cpu(buf16[i]), mmio);
3638 } else {
3639 for (i = 0; i < words; i++)
3640 buf16[i] = cpu_to_le16(readw(mmio));
3641 }
6ae4cfb5
AL		 3642
3643 /* Transfer trailing 1 byte, if any. */
3644 if (unlikely(buflen & 0x01)) {
3645 u16 align_buf[1] = { 0 };
3646 unsigned char *trailing_buf = buf + buflen - 1;
3647
3648 if (write_data) {
3649 memcpy(align_buf, trailing_buf, 1);
3650 writew(le16_to_cpu(align_buf[0]), mmio);
3651 } else {
3652 align_buf[0] = cpu_to_le16(readw(mmio));
3653 memcpy(trailing_buf, align_buf, 1);
3654 }
3655 }
1da177e4
LT		 3656}
3657
6ae4cfb5
AL		 3658/**
3659 * ata_pio_data_xfer - Transfer data by PIO
a6b2c5d4 3660 * @adev: device to target
6ae4cfb5
AL		 3661 * @buf: data buffer
3662 * @buflen: buffer length
344babaa 3663 * @write_data: read/write
6ae4cfb5
AL		 3664 *
3665 * Transfer data from/to the device data register by PIO.
3666 *
3667 * LOCKING:
3668 * Inherited from caller.
6ae4cfb5
AL		 3669 */
3670
88574551 3671void ata_pio_data_xfer(struct ata_device *adev, unsigned char *buf,
a6b2c5d4 3672 unsigned int buflen, int write_data)
1da177e4 3673{
a6b2c5d4 3674 struct ata_port *ap = adev->ap;
6ae4cfb5 3675 unsigned int words = buflen >> 1;
1da177e4 3676
6ae4cfb5 3677 /* Transfer multiple of 2 bytes */
1da177e4 3678 if (write_data)
6ae4cfb5 3679 outsw(ap->ioaddr.data_addr, buf, words);
1da177e4 3680 else
6ae4cfb5
AL		 3681 insw(ap->ioaddr.data_addr, buf, words);
3682
3683 /* Transfer trailing 1 byte, if any. */
3684 if (unlikely(buflen & 0x01)) {
3685 u16 align_buf[1] = { 0 };
3686 unsigned char *trailing_buf = buf + buflen - 1;
3687
3688 if (write_data) {
3689 memcpy(align_buf, trailing_buf, 1);
3690 outw(le16_to_cpu(align_buf[0]), ap->ioaddr.data_addr);
3691 } else {
3692 align_buf[0] = cpu_to_le16(inw(ap->ioaddr.data_addr));
3693 memcpy(trailing_buf, align_buf, 1);
3694 }
3695 }
1da177e4
LT		 3696}
3697
75e99585
AC		 3698/**
3699 * ata_pio_data_xfer_noirq - Transfer data by PIO
3700 * @adev: device to target
3701 * @buf: data buffer
3702 * @buflen: buffer length
3703 * @write_data: read/write
3704 *
88574551 3705 * Transfer data from/to the device data register by PIO. Do the
75e99585
AC		 3706 * transfer with interrupts disabled.
3707 *
3708 * LOCKING:
3709 * Inherited from caller.
3710 */
3711
3712void ata_pio_data_xfer_noirq(struct ata_device *adev, unsigned char *buf,
3713 unsigned int buflen, int write_data)
3714{
3715 unsigned long flags;
3716 local_irq_save(flags);
3717 ata_pio_data_xfer(adev, buf, buflen, write_data);
3718 local_irq_restore(flags);
3719}
3720
3721
6ae4cfb5
AL		 3722/**
3723 * ata_pio_sector - Transfer ATA_SECT_SIZE (512 bytes) of data.
3724 * @qc: Command on going
3725 *
3726 * Transfer ATA_SECT_SIZE of data from/to the ATA device.
3727 *
3728 * LOCKING:
3729 * Inherited from caller.
3730 */
3731
1da177e4
LT		 3732static void ata_pio_sector(struct ata_queued_cmd *qc)
3733{
3734 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3735 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3736 struct ata_port *ap = qc->ap;
3737 struct page *page;
3738 unsigned int offset;
3739 unsigned char *buf;
3740
3741 if (qc->cursect == (qc->nsect - 1))
14be71f4 3742 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3743
3744 page = sg[qc->cursg].page;
3745 offset = sg[qc->cursg].offset + qc->cursg_ofs * ATA_SECT_SIZE;
3746
3747 /* get the current page and offset */
3748 page = nth_page(page, (offset >> PAGE_SHIFT));
3749 offset %= PAGE_SIZE;
3750
1da177e4
LT		 3751 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3752
91b8b313
AL		 3753 if (PageHighMem(page)) {
3754 unsigned long flags;
3755
a6b2c5d4 3756 /* FIXME: use a bounce buffer */
91b8b313
AL		 3757 local_irq_save(flags);
3758 buf = kmap_atomic(page, KM_IRQ0);
083958d3 3759
91b8b313 3760 /* do the actual data transfer */
a6b2c5d4 3761 ap->ops->data_xfer(qc->dev, buf + offset, ATA_SECT_SIZE, do_write);
1da177e4 3762
91b8b313
AL		 3763 kunmap_atomic(buf, KM_IRQ0);
3764 local_irq_restore(flags);
3765 } else {
3766 buf = page_address(page);
a6b2c5d4 3767 ap->ops->data_xfer(qc->dev, buf + offset, ATA_SECT_SIZE, do_write);
91b8b313 3768 }
1da177e4
LT		 3769
3770 qc->cursect++;
3771 qc->cursg_ofs++;
3772
32529e01 3773 if ((qc->cursg_ofs * ATA_SECT_SIZE) == (&sg[qc->cursg])->length) {
1da177e4
LT		 3774 qc->cursg++;
3775 qc->cursg_ofs = 0;
3776 }
1da177e4 3777}
1da177e4 3778
07f6f7d0
AL		 3779/**
3780 * ata_pio_sectors - Transfer one or many 512-byte sectors.
3781 * @qc: Command on going
3782 *
c81e29b4 3783 * Transfer one or many ATA_SECT_SIZE of data from/to the
07f6f7d0
AL		 3784 * ATA device for the DRQ request.
3785 *
3786 * LOCKING:
3787 * Inherited from caller.
3788 */
1da177e4 3789
07f6f7d0
AL		 3790static void ata_pio_sectors(struct ata_queued_cmd *qc)
3791{
3792 if (is_multi_taskfile(&qc->tf)) {
3793 /* READ/WRITE MULTIPLE */
3794 unsigned int nsect;
3795
587005de 3796 WARN_ON(qc->dev->multi_count == 0);
1da177e4 3797
07f6f7d0
AL		 3798 nsect = min(qc->nsect - qc->cursect, qc->dev->multi_count);
3799 while (nsect--)
3800 ata_pio_sector(qc);
3801 } else
3802 ata_pio_sector(qc);
3803}
3804
c71c1857
AL		 3805/**
3806 * atapi_send_cdb - Write CDB bytes to hardware
3807 * @ap: Port to which ATAPI device is attached.
3808 * @qc: Taskfile currently active
3809 *
3810 * When device has indicated its readiness to accept
3811 * a CDB, this function is called. Send the CDB.
3812 *
3813 * LOCKING:
3814 * caller.
3815 */
3816
3817static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
3818{
3819 /* send SCSI cdb */
3820 DPRINTK("send cdb\n");
db024d53 3821 WARN_ON(qc->dev->cdb_len < 12);
c71c1857 3822
a6b2c5d4 3823 ap->ops->data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
c71c1857
AL		 3824 ata_altstatus(ap); /* flush */
3825
3826 switch (qc->tf.protocol) {
3827 case ATA_PROT_ATAPI:
3828 ap->hsm_task_state = HSM_ST;
3829 break;
3830 case ATA_PROT_ATAPI_NODATA:
3831 ap->hsm_task_state = HSM_ST_LAST;
3832 break;
3833 case ATA_PROT_ATAPI_DMA:
3834 ap->hsm_task_state = HSM_ST_LAST;
3835 /* initiate bmdma */
3836 ap->ops->bmdma_start(qc);
3837 break;
3838 }
1da177e4
LT		 3839}
3840
6ae4cfb5
AL		 3841/**
3842 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
3843 * @qc: Command on going
3844 * @bytes: number of bytes
3845 *
3846 * Transfer Transfer data from/to the ATAPI device.
3847 *
3848 * LOCKING:
3849 * Inherited from caller.
3850 *
3851 */
3852
1da177e4
LT		 3853static void __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
3854{
3855 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3856 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3857 struct ata_port *ap = qc->ap;
3858 struct page *page;
3859 unsigned char *buf;
3860 unsigned int offset, count;
3861
563a6e1f 3862 if (qc->curbytes + bytes >= qc->nbytes)
14be71f4 3863 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3864
3865next_sg:
563a6e1f 3866 if (unlikely(qc->cursg >= qc->n_elem)) {
7fb6ec28 3867 /*
563a6e1f
AL		 3868 * The end of qc->sg is reached and the device expects
3869 * more data to transfer. In order not to overrun qc->sg
3870 * and fulfill length specified in the byte count register,
3871 * - for read case, discard trailing data from the device
3872 * - for write case, padding zero data to the device
3873 */
3874 u16 pad_buf[1] = { 0 };
3875 unsigned int words = bytes >> 1;
3876 unsigned int i;
3877
3878 if (words) /* warning if bytes > 1 */
f15a1daf
TH		 3879 ata_dev_printk(qc->dev, KERN_WARNING,
3880 "%u bytes trailing data\n", bytes);
563a6e1f
AL		 3881
3882 for (i = 0; i < words; i++)
a6b2c5d4 3883 ap->ops->data_xfer(qc->dev, (unsigned char*)pad_buf, 2, do_write);
563a6e1f 3884
14be71f4 3885 ap->hsm_task_state = HSM_ST_LAST;
563a6e1f
AL		 3886 return;
3887 }
3888
cedc9a47 3889 sg = &qc->__sg[qc->cursg];
1da177e4 3890
1da177e4
LT		 3891 page = sg->page;
3892 offset = sg->offset + qc->cursg_ofs;
3893
3894 /* get the current page and offset */
3895 page = nth_page(page, (offset >> PAGE_SHIFT));
3896 offset %= PAGE_SIZE;
3897
6952df03 3898 /* don't overrun current sg */
32529e01 3899 count = min(sg->length - qc->cursg_ofs, bytes);
1da177e4
LT		 3900
3901 /* don't cross page boundaries */
3902 count = min(count, (unsigned int)PAGE_SIZE - offset);
3903
7282aa4b
AL		 3904 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3905
91b8b313
AL		 3906 if (PageHighMem(page)) {
3907 unsigned long flags;
3908
a6b2c5d4 3909 /* FIXME: use bounce buffer */
91b8b313
AL		 3910 local_irq_save(flags);
3911 buf = kmap_atomic(page, KM_IRQ0);
083958d3 3912
91b8b313 3913 /* do the actual data transfer */
a6b2c5d4 3914 ap->ops->data_xfer(qc->dev, buf + offset, count, do_write);
7282aa4b 3915
91b8b313
AL		 3916 kunmap_atomic(buf, KM_IRQ0);
3917 local_irq_restore(flags);
3918 } else {
3919 buf = page_address(page);
a6b2c5d4 3920 ap->ops->data_xfer(qc->dev, buf + offset, count, do_write);
91b8b313 3921 }
1da177e4
LT		 3922
3923 bytes -= count;
3924 qc->curbytes += count;
3925 qc->cursg_ofs += count;
3926
32529e01 3927 if (qc->cursg_ofs == sg->length) {
1da177e4
LT		 3928 qc->cursg++;
3929 qc->cursg_ofs = 0;
3930 }
3931
563a6e1f 3932 if (bytes)
1da177e4 3933 goto next_sg;
1da177e4
LT		 3934}
3935
6ae4cfb5
AL		 3936/**
3937 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
3938 * @qc: Command on going
3939 *
3940 * Transfer Transfer data from/to the ATAPI device.
3941 *
3942 * LOCKING:
3943 * Inherited from caller.
6ae4cfb5
AL		 3944 */
3945
1da177e4
LT		 3946static void atapi_pio_bytes(struct ata_queued_cmd *qc)
3947{
3948 struct ata_port *ap = qc->ap;
3949 struct ata_device *dev = qc->dev;
3950 unsigned int ireason, bc_lo, bc_hi, bytes;
3951 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
3952
eec4c3f3
AL		 3953 /* Abuse qc->result_tf for temp storage of intermediate TF
3954 * here to save some kernel stack usage.
3955 * For normal completion, qc->result_tf is not relevant. For
3956 * error, qc->result_tf is later overwritten by ata_qc_complete().
3957 * So, the correctness of qc->result_tf is not affected.
3958 */
3959 ap->ops->tf_read(ap, &qc->result_tf);
3960 ireason = qc->result_tf.nsect;
3961 bc_lo = qc->result_tf.lbam;
3962 bc_hi = qc->result_tf.lbah;
1da177e4
LT		 3963 bytes = (bc_hi << 8) | bc_lo;
3964
3965 /* shall be cleared to zero, indicating xfer of data */
3966 if (ireason & (1 << 0))
3967 goto err_out;
3968
3969 /* make sure transfer direction matches expected */
3970 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
3971 if (do_write != i_write)
3972 goto err_out;
3973
312f7da2
AL		 3974 VPRINTK("ata%u: xfering %d bytes\n", ap->id, bytes);
3975
1da177e4
LT		 3976 __atapi_pio_bytes(qc, bytes);
3977
3978 return;
3979
3980err_out:
f15a1daf 3981 ata_dev_printk(dev, KERN_INFO, "ATAPI check failed\n");
11a56d24 3982 qc->err_mask |= AC_ERR_HSM;
14be71f4 3983 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3984}
3985
3986/**
c234fb00
AL		 3987 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
3988 * @ap: the target ata_port
3989 * @qc: qc on going
1da177e4 3990 *
c234fb00
AL		 3991 * RETURNS:
3992 * 1 if ok in workqueue, 0 otherwise.
1da177e4 3993 */
c234fb00
AL		 3994
3995static inline int ata_hsm_ok_in_wq(struct ata_port *ap, struct ata_queued_cmd *qc)
1da177e4 3996{
c234fb00
AL		 3997 if (qc->tf.flags & ATA_TFLAG_POLLING)
3998 return 1;
1da177e4 3999
c234fb00
AL		 4000 if (ap->hsm_task_state == HSM_ST_FIRST) {
4001 if (qc->tf.protocol == ATA_PROT_PIO &&
4002 (qc->tf.flags & ATA_TFLAG_WRITE))
4003 return 1;
1da177e4 4004
c234fb00
AL		 4005 if (is_atapi_taskfile(&qc->tf) &&
4006 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
4007 return 1;
fe79e683
AL		 4008 }
4009
c234fb00
AL		 4010 return 0;
4011}
1da177e4 4012
c17ea20d
TH		 4013/**
4014 * ata_hsm_qc_complete - finish a qc running on standard HSM
4015 * @qc: Command to complete
4016 * @in_wq: 1 if called from workqueue, 0 otherwise
4017 *
4018 * Finish @qc which is running on standard HSM.
4019 *
4020 * LOCKING:
cca3974e 4021 * If @in_wq is zero, spin_lock_irqsave(host lock).
c17ea20d
TH		 4022 * Otherwise, none on entry and grabs host lock.
4023 */
4024static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
4025{
4026 struct ata_port *ap = qc->ap;
4027 unsigned long flags;
4028
4029 if (ap->ops->error_handler) {
4030 if (in_wq) {
ba6a1308 4031 spin_lock_irqsave(ap->lock, flags);
c17ea20d 4032
cca3974e
JG		 4033 /* EH might have kicked in while host lock is
4034 * released.
c17ea20d
TH		 4035 */
4036 qc = ata_qc_from_tag(ap, qc->tag);
4037 if (qc) {
4038 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
4039 ata_irq_on(ap);
4040 ata_qc_complete(qc);
4041 } else
4042 ata_port_freeze(ap);
4043 }
4044
ba6a1308 4045 spin_unlock_irqrestore(ap->lock, flags);
c17ea20d
TH		 4046 } else {
4047 if (likely(!(qc->err_mask & AC_ERR_HSM)))
4048 ata_qc_complete(qc);
4049 else
4050 ata_port_freeze(ap);
4051 }
4052 } else {
4053 if (in_wq) {
ba6a1308 4054 spin_lock_irqsave(ap->lock, flags);
c17ea20d
TH		 4055 ata_irq_on(ap);
4056 ata_qc_complete(qc);
ba6a1308 4057 spin_unlock_irqrestore(ap->lock, flags);
c17ea20d
TH		 4058 } else
4059 ata_qc_complete(qc);
4060 }
1da177e4 4061
c81e29b4 4062 ata_altstatus(ap); /* flush */
c17ea20d
TH		 4063}
4064
bb5cb290
AL		 4065/**
4066 * ata_hsm_move - move the HSM to the next state.
4067 * @ap: the target ata_port
4068 * @qc: qc on going
4069 * @status: current device status
4070 * @in_wq: 1 if called from workqueue, 0 otherwise
4071 *
4072 * RETURNS:
4073 * 1 when poll next status needed, 0 otherwise.
4074 */
9a1004d0
TH		 4075int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
4076 u8 status, int in_wq)
e2cec771 4077{
bb5cb290
AL		 4078 unsigned long flags = 0;
4079 int poll_next;
4080
6912ccd5
AL		 4081 WARN_ON((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
4082
bb5cb290
AL		 4083 /* Make sure ata_qc_issue_prot() does not throw things
4084 * like DMA polling into the workqueue. Notice that
4085 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
4086 */
c234fb00 4087 WARN_ON(in_wq != ata_hsm_ok_in_wq(ap, qc));
bb5cb290 4088
e2cec771 4089fsm_start:
999bb6f4
AL		 4090 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
4091 ap->id, qc->tf.protocol, ap->hsm_task_state, status);
4092
e2cec771
AL		 4093 switch (ap->hsm_task_state) {
4094 case HSM_ST_FIRST:
bb5cb290
AL		 4095 /* Send first data block or PACKET CDB */
4096
4097 /* If polling, we will stay in the work queue after
4098 * sending the data. Otherwise, interrupt handler
4099 * takes over after sending the data.
4100 */
4101 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
4102
e2cec771 4103 /* check device status */
3655d1d3
AL		 4104 if (unlikely((status & ATA_DRQ) == 0)) {
4105 /* handle BSY=0, DRQ=0 as error */
4106 if (likely(status & (ATA_ERR | ATA_DF)))
4107 /* device stops HSM for abort/error */
4108 qc->err_mask |= AC_ERR_DEV;
4109 else
4110 /* HSM violation. Let EH handle this */
4111 qc->err_mask |= AC_ERR_HSM;
4112
14be71f4 4113 ap->hsm_task_state = HSM_ST_ERR;
e2cec771 4114 goto fsm_start;
1da177e4
LT		 4115 }
4116
71601958
AL		 4117 /* Device should not ask for data transfer (DRQ=1)
4118 * when it finds something wrong.
eee6c32f
AL		 4119 * We ignore DRQ here and stop the HSM by
4120 * changing hsm_task_state to HSM_ST_ERR and
4121 * let the EH abort the command or reset the device.
71601958
AL		 4122 */
4123 if (unlikely(status & (ATA_ERR | ATA_DF))) {
4124 printk(KERN_WARNING "ata%d: DRQ=1 with device error, dev_stat 0x%X\n",
4125 ap->id, status);
3655d1d3 4126 qc->err_mask |= AC_ERR_HSM;
eee6c32f
AL		 4127 ap->hsm_task_state = HSM_ST_ERR;
4128 goto fsm_start;
71601958 4129 }
1da177e4 4130
bb5cb290
AL		 4131 /* Send the CDB (atapi) or the first data block (ata pio out).
4132 * During the state transition, interrupt handler shouldn't
4133 * be invoked before the data transfer is complete and
4134 * hsm_task_state is changed. Hence, the following locking.
4135 */
4136 if (in_wq)
ba6a1308 4137 spin_lock_irqsave(ap->lock, flags);
1da177e4 4138
bb5cb290
AL		 4139 if (qc->tf.protocol == ATA_PROT_PIO) {
4140 /* PIO data out protocol.
4141 * send first data block.
4142 */
0565c26d 4143
bb5cb290
AL		 4144 /* ata_pio_sectors() might change the state
4145 * to HSM_ST_LAST. so, the state is changed here
4146 * before ata_pio_sectors().
4147 */
4148 ap->hsm_task_state = HSM_ST;
4149 ata_pio_sectors(qc);
4150 ata_altstatus(ap); /* flush */
4151 } else
4152 /* send CDB */
4153 atapi_send_cdb(ap, qc);
4154
4155 if (in_wq)
ba6a1308 4156 spin_unlock_irqrestore(ap->lock, flags);
bb5cb290
AL		 4157
4158 /* if polling, ata_pio_task() handles the rest.
4159 * otherwise, interrupt handler takes over from here.
4160 */
e2cec771 4161 break;
1c848984 4162
e2cec771
AL		 4163 case HSM_ST:
4164 /* complete command or read/write the data register */
4165 if (qc->tf.protocol == ATA_PROT_ATAPI) {
4166 /* ATAPI PIO protocol */
4167 if ((status & ATA_DRQ) == 0) {
3655d1d3
AL		 4168 /* No more data to transfer or device error.
4169 * Device error will be tagged in HSM_ST_LAST.
4170 */
e2cec771
AL		 4171 ap->hsm_task_state = HSM_ST_LAST;
4172 goto fsm_start;
4173 }
1da177e4 4174
71601958
AL		 4175 /* Device should not ask for data transfer (DRQ=1)
4176 * when it finds something wrong.
eee6c32f
AL		 4177 * We ignore DRQ here and stop the HSM by
4178 * changing hsm_task_state to HSM_ST_ERR and
4179 * let the EH abort the command or reset the device.
71601958
AL		 4180 */
4181 if (unlikely(status & (ATA_ERR | ATA_DF))) {
4182 printk(KERN_WARNING "ata%d: DRQ=1 with device error, dev_stat 0x%X\n",
4183 ap->id, status);
3655d1d3 4184 qc->err_mask |= AC_ERR_HSM;
eee6c32f
AL		 4185 ap->hsm_task_state = HSM_ST_ERR;
4186 goto fsm_start;
71601958 4187 }
1da177e4 4188
e2cec771 4189 atapi_pio_bytes(qc);
7fb6ec28 4190
e2cec771
AL		 4191 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
4192 /* bad ireason reported by device */
4193 goto fsm_start;
1da177e4 4194
e2cec771
AL		 4195 } else {
4196 /* ATA PIO protocol */
4197 if (unlikely((status & ATA_DRQ) == 0)) {
4198 /* handle BSY=0, DRQ=0 as error */
3655d1d3
AL		 4199 if (likely(status & (ATA_ERR | ATA_DF)))
4200 /* device stops HSM for abort/error */
4201 qc->err_mask |= AC_ERR_DEV;
4202 else
4203 /* HSM violation. Let EH handle this */
4204 qc->err_mask |= AC_ERR_HSM;
4205
e2cec771
AL		 4206 ap->hsm_task_state = HSM_ST_ERR;
4207 goto fsm_start;
4208 }
1da177e4 4209
eee6c32f
AL		 4210 /* For PIO reads, some devices may ask for
4211 * data transfer (DRQ=1) alone with ERR=1.
4212 * We respect DRQ here and transfer one
4213 * block of junk data before changing the
4214 * hsm_task_state to HSM_ST_ERR.
4215 *
4216 * For PIO writes, ERR=1 DRQ=1 doesn't make
4217 * sense since the data block has been
4218 * transferred to the device.
71601958
AL		 4219 */
4220 if (unlikely(status & (ATA_ERR | ATA_DF))) {
71601958
AL		 4221 /* data might be corrputed */
4222 qc->err_mask |= AC_ERR_DEV;
eee6c32f
AL		 4223
4224 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
4225 ata_pio_sectors(qc);
4226 ata_altstatus(ap);
4227 status = ata_wait_idle(ap);
4228 }
4229
3655d1d3
AL		 4230 if (status & (ATA_BUSY | ATA_DRQ))
4231 qc->err_mask |= AC_ERR_HSM;
4232
eee6c32f
AL		 4233 /* ata_pio_sectors() might change the
4234 * state to HSM_ST_LAST. so, the state
4235 * is changed after ata_pio_sectors().
4236 */
4237 ap->hsm_task_state = HSM_ST_ERR;
4238 goto fsm_start;
71601958
AL		 4239 }
4240
e2cec771
AL		 4241 ata_pio_sectors(qc);
4242
4243 if (ap->hsm_task_state == HSM_ST_LAST &&
4244 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
4245 /* all data read */
4246 ata_altstatus(ap);
52a32205 4247 status = ata_wait_idle(ap);
e2cec771
AL		 4248 goto fsm_start;
4249 }
4250 }
4251
4252 ata_altstatus(ap); /* flush */
bb5cb290 4253 poll_next = 1;
1da177e4
LT		 4254 break;
4255
14be71f4 4256 case HSM_ST_LAST:
6912ccd5
AL		 4257 if (unlikely(!ata_ok(status))) {
4258 qc->err_mask |= __ac_err_mask(status);
e2cec771
AL		 4259 ap->hsm_task_state = HSM_ST_ERR;
4260 goto fsm_start;
4261 }
4262
4263 /* no more data to transfer */
4332a771
AL		 4264 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
4265 ap->id, qc->dev->devno, status);
e2cec771 4266
6912ccd5
AL		 4267 WARN_ON(qc->err_mask);
4268
e2cec771 4269 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 4270
e2cec771 4271 /* complete taskfile transaction */
c17ea20d 4272 ata_hsm_qc_complete(qc, in_wq);
bb5cb290
AL		 4273
4274 poll_next = 0;
1da177e4
LT		 4275 break;
4276
14be71f4 4277 case HSM_ST_ERR:
e2cec771
AL		 4278 /* make sure qc->err_mask is available to
4279 * know what's wrong and recover
4280 */
4281 WARN_ON(qc->err_mask == 0);
4282
4283 ap->hsm_task_state = HSM_ST_IDLE;
bb5cb290 4284
999bb6f4 4285 /* complete taskfile transaction */
c17ea20d 4286 ata_hsm_qc_complete(qc, in_wq);
bb5cb290
AL		 4287
4288 poll_next = 0;
e2cec771
AL		 4289 break;
4290 default:
bb5cb290 4291 poll_next = 0;
6912ccd5 4292 BUG();
1da177e4
LT		 4293 }
4294
bb5cb290 4295 return poll_next;
1da177e4
LT		 4296}
4297
1da177e4 4298static void ata_pio_task(void *_data)
8061f5f0 4299{
c91af2c8
TH		 4300 struct ata_queued_cmd *qc = _data;
4301 struct ata_port *ap = qc->ap;
8061f5f0 4302 u8 status;
a1af3734 4303 int poll_next;
8061f5f0 4304
7fb6ec28 4305fsm_start:
a1af3734 4306 WARN_ON(ap->hsm_task_state == HSM_ST_IDLE);
8061f5f0 4307
a1af3734
AL		 4308 /*
4309 * This is purely heuristic. This is a fast path.
4310 * Sometimes when we enter, BSY will be cleared in
4311 * a chk-status or two. If not, the drive is probably seeking
4312 * or something. Snooze for a couple msecs, then
4313 * chk-status again. If still busy, queue delayed work.
4314 */
4315 status = ata_busy_wait(ap, ATA_BUSY, 5);
4316 if (status & ATA_BUSY) {
4317 msleep(2);
4318 status = ata_busy_wait(ap, ATA_BUSY, 10);
4319 if (status & ATA_BUSY) {
31ce6dae 4320 ata_port_queue_task(ap, ata_pio_task, qc, ATA_SHORT_PAUSE);
a1af3734
AL		 4321 return;
4322 }
8061f5f0
TH		 4323 }
4324
a1af3734
AL		 4325 /* move the HSM */
4326 poll_next = ata_hsm_move(ap, qc, status, 1);
8061f5f0 4327
a1af3734
AL		 4328 /* another command or interrupt handler
4329 * may be running at this point.
4330 */
4331 if (poll_next)
7fb6ec28 4332 goto fsm_start;
8061f5f0
TH		 4333}
4334
1da177e4
LT		 4335/**
4336 * ata_qc_new - Request an available ATA command, for queueing
4337 * @ap: Port associated with device @dev
4338 * @dev: Device from whom we request an available command structure
4339 *
4340 * LOCKING:
0cba632b 4341 * None.
1da177e4
LT		 4342 */
4343
4344static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap)
4345{
4346 struct ata_queued_cmd *qc = NULL;
4347 unsigned int i;
4348
e3180499 4349 /* no command while frozen */
b51e9e5d 4350 if (unlikely(ap->pflags & ATA_PFLAG_FROZEN))
e3180499
TH		 4351 return NULL;
4352
2ab7db1f
TH		 4353 /* the last tag is reserved for internal command. */
4354 for (i = 0; i < ATA_MAX_QUEUE - 1; i++)
6cec4a39 4355 if (!test_and_set_bit(i, &ap->qc_allocated)) {
f69499f4 4356 qc = __ata_qc_from_tag(ap, i);
1da177e4
LT		 4357 break;
4358 }
4359
4360 if (qc)
4361 qc->tag = i;
4362
4363 return qc;
4364}
4365
4366/**
4367 * ata_qc_new_init - Request an available ATA command, and initialize it
1da177e4
LT		 4368 * @dev: Device from whom we request an available command structure
4369 *
4370 * LOCKING:
0cba632b 4371 * None.
1da177e4
LT		 4372 */
4373
3373efd8 4374struct ata_queued_cmd *ata_qc_new_init(struct ata_device *dev)
1da177e4 4375{
3373efd8 4376 struct ata_port *ap = dev->ap;
1da177e4
LT		 4377 struct ata_queued_cmd *qc;
4378
4379 qc = ata_qc_new(ap);
4380 if (qc) {
1da177e4
LT		 4381 qc->scsicmd = NULL;
4382 qc->ap = ap;
4383 qc->dev = dev;
1da177e4 4384
2c13b7ce 4385 ata_qc_reinit(qc);
1da177e4
LT		 4386 }
4387
4388 return qc;
4389}
4390
1da177e4
LT		 4391/**
4392 * ata_qc_free - free unused ata_queued_cmd
4393 * @qc: Command to complete
4394 *
4395 * Designed to free unused ata_queued_cmd object
4396 * in case something prevents using it.
4397 *
4398 * LOCKING:
cca3974e 4399 * spin_lock_irqsave(host lock)
1da177e4
LT		 4400 */
4401void ata_qc_free(struct ata_queued_cmd *qc)
4402{
4ba946e9
TH		 4403 struct ata_port *ap = qc->ap;
4404 unsigned int tag;
4405
a4631474 4406 WARN_ON(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
1da177e4 4407
4ba946e9
TH		 4408 qc->flags = 0;
4409 tag = qc->tag;
4410 if (likely(ata_tag_valid(tag))) {
4ba946e9 4411 qc->tag = ATA_TAG_POISON;
6cec4a39 4412 clear_bit(tag, &ap->qc_allocated);
4ba946e9 4413 }
1da177e4
LT		 4414}
4415
76014427 4416void __ata_qc_complete(struct ata_queued_cmd *qc)
1da177e4 4417{
dedaf2b0
TH		 4418 struct ata_port *ap = qc->ap;
4419
a4631474
TH		 4420 WARN_ON(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
4421 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
1da177e4
LT		 4422
4423 if (likely(qc->flags & ATA_QCFLAG_DMAMAP))
4424 ata_sg_clean(qc);
4425
7401abf2 4426 /* command should be marked inactive atomically with qc completion */
dedaf2b0
TH		 4427 if (qc->tf.protocol == ATA_PROT_NCQ)
4428 ap->sactive &= ~(1 << qc->tag);
4429 else
4430 ap->active_tag = ATA_TAG_POISON;
7401abf2 4431
3f3791d3
AL		 4432 /* atapi: mark qc as inactive to prevent the interrupt handler
4433 * from completing the command twice later, before the error handler
4434 * is called. (when rc != 0 and atapi request sense is needed)
4435 */
4436 qc->flags &= ~ATA_QCFLAG_ACTIVE;
dedaf2b0 4437 ap->qc_active &= ~(1 << qc->tag);
3f3791d3 4438
1da177e4 4439 /* call completion callback */
77853bf2 4440 qc->complete_fn(qc);
1da177e4
LT		 4441}
4442
f686bcb8
TH		 4443/**
4444 * ata_qc_complete - Complete an active ATA command
4445 * @qc: Command to complete
4446 * @err_mask: ATA Status register contents
4447 *
4448 * Indicate to the mid and upper layers that an ATA
4449 * command has completed, with either an ok or not-ok status.
4450 *
4451 * LOCKING:
cca3974e 4452 * spin_lock_irqsave(host lock)
f686bcb8
TH		 4453 */
4454void ata_qc_complete(struct ata_queued_cmd *qc)
4455{
4456 struct ata_port *ap = qc->ap;
4457
4458 /* XXX: New EH and old EH use different mechanisms to
4459 * synchronize EH with regular execution path.
4460 *
4461 * In new EH, a failed qc is marked with ATA_QCFLAG_FAILED.
4462 * Normal execution path is responsible for not accessing a
4463 * failed qc. libata core enforces the rule by returning NULL
4464 * from ata_qc_from_tag() for failed qcs.
4465 *
4466 * Old EH depends on ata_qc_complete() nullifying completion
4467 * requests if ATA_QCFLAG_EH_SCHEDULED is set. Old EH does
4468 * not synchronize with interrupt handler. Only PIO task is
4469 * taken care of.
4470 */
4471 if (ap->ops->error_handler) {
b51e9e5d 4472 WARN_ON(ap->pflags & ATA_PFLAG_FROZEN);
f686bcb8
TH		 4473
4474 if (unlikely(qc->err_mask))
4475 qc->flags |= ATA_QCFLAG_FAILED;
4476
4477 if (unlikely(qc->flags & ATA_QCFLAG_FAILED)) {
4478 if (!ata_tag_internal(qc->tag)) {
4479 /* always fill result TF for failed qc */
4480 ap->ops->tf_read(ap, &qc->result_tf);
4481 ata_qc_schedule_eh(qc);
4482 return;
4483 }
4484 }
4485
4486 /* read result TF if requested */
4487 if (qc->flags & ATA_QCFLAG_RESULT_TF)
4488 ap->ops->tf_read(ap, &qc->result_tf);
4489
4490 __ata_qc_complete(qc);
4491 } else {
4492 if (qc->flags & ATA_QCFLAG_EH_SCHEDULED)
4493 return;
4494
4495 /* read result TF if failed or requested */
4496 if (qc->err_mask || qc->flags & ATA_QCFLAG_RESULT_TF)
4497 ap->ops->tf_read(ap, &qc->result_tf);
4498
4499 __ata_qc_complete(qc);
4500 }
4501}
4502
dedaf2b0
TH		 4503/**
4504 * ata_qc_complete_multiple - Complete multiple qcs successfully
4505 * @ap: port in question
4506 * @qc_active: new qc_active mask
4507 * @finish_qc: LLDD callback invoked before completing a qc
4508 *
4509 * Complete in-flight commands. This functions is meant to be
4510 * called from low-level driver's interrupt routine to complete
4511 * requests normally. ap->qc_active and @qc_active is compared
4512 * and commands are completed accordingly.
4513 *
4514 * LOCKING:
cca3974e 4515 * spin_lock_irqsave(host lock)
dedaf2b0
TH		 4516 *
4517 * RETURNS:
4518 * Number of completed commands on success, -errno otherwise.
4519 */
4520int ata_qc_complete_multiple(struct ata_port *ap, u32 qc_active,
4521 void (*finish_qc)(struct ata_queued_cmd *))
4522{
4523 int nr_done = 0;
4524 u32 done_mask;
4525 int i;
4526
4527 done_mask = ap->qc_active ^ qc_active;
4528
4529 if (unlikely(done_mask & qc_active)) {
4530 ata_port_printk(ap, KERN_ERR, "illegal qc_active transition "
4531 "(%08x->%08x)\n", ap->qc_active, qc_active);
4532 return -EINVAL;
4533 }
4534
4535 for (i = 0; i < ATA_MAX_QUEUE; i++) {
4536 struct ata_queued_cmd *qc;
4537
4538 if (!(done_mask & (1 << i)))
4539 continue;
4540
4541 if ((qc = ata_qc_from_tag(ap, i))) {
4542 if (finish_qc)
4543 finish_qc(qc);
4544 ata_qc_complete(qc);
4545 nr_done++;
4546 }
4547 }
4548
4549 return nr_done;
4550}
4551
1da177e4
LT		 4552static inline int ata_should_dma_map(struct ata_queued_cmd *qc)
4553{
4554 struct ata_port *ap = qc->ap;
4555
4556 switch (qc->tf.protocol) {
3dc1d881 4557 case ATA_PROT_NCQ:
1da177e4
LT		 4558 case ATA_PROT_DMA:
4559 case ATA_PROT_ATAPI_DMA:
4560 return 1;
4561
4562 case ATA_PROT_ATAPI:
4563 case ATA_PROT_PIO:
1da177e4
LT		 4564 if (ap->flags & ATA_FLAG_PIO_DMA)
4565 return 1;
4566
4567 /* fall through */
4568
4569 default:
4570 return 0;
4571 }
4572
4573 /* never reached */
4574}
4575
4576/**
4577 * ata_qc_issue - issue taskfile to device
4578 * @qc: command to issue to device
4579 *
4580 * Prepare an ATA command to submission to device.
4581 * This includes mapping the data into a DMA-able
4582 * area, filling in the S/G table, and finally
4583 * writing the taskfile to hardware, starting the command.
4584 *
4585 * LOCKING:
cca3974e 4586 * spin_lock_irqsave(host lock)
1da177e4 4587 */
8e0e694a 4588void ata_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 4589{
4590 struct ata_port *ap = qc->ap;
4591
dedaf2b0
TH		 4592 /* Make sure only one non-NCQ command is outstanding. The
4593 * check is skipped for old EH because it reuses active qc to
4594 * request ATAPI sense.
4595 */
4596 WARN_ON(ap->ops->error_handler && ata_tag_valid(ap->active_tag));
4597
4598 if (qc->tf.protocol == ATA_PROT_NCQ) {
4599 WARN_ON(ap->sactive & (1 << qc->tag));
4600 ap->sactive |= 1 << qc->tag;
4601 } else {
4602 WARN_ON(ap->sactive);
4603 ap->active_tag = qc->tag;
4604 }
4605
e4a70e76 4606 qc->flags |= ATA_QCFLAG_ACTIVE;
dedaf2b0 4607 ap->qc_active |= 1 << qc->tag;
e4a70e76 4608
1da177e4
LT		 4609 if (ata_should_dma_map(qc)) {
4610 if (qc->flags & ATA_QCFLAG_SG) {
4611 if (ata_sg_setup(qc))
8e436af9 4612 goto sg_err;
1da177e4
LT		 4613 } else if (qc->flags & ATA_QCFLAG_SINGLE) {
4614 if (ata_sg_setup_one(qc))
8e436af9 4615 goto sg_err;
1da177e4
LT		 4616 }
4617 } else {
4618 qc->flags &= ~ATA_QCFLAG_DMAMAP;
4619 }
4620
4621 ap->ops->qc_prep(qc);
4622
8e0e694a
TH		 4623 qc->err_mask |= ap->ops->qc_issue(qc);
4624 if (unlikely(qc->err_mask))
4625 goto err;
4626 return;
1da177e4 4627
8e436af9
TH		 4628sg_err:
4629 qc->flags &= ~ATA_QCFLAG_DMAMAP;
8e0e694a
TH		 4630 qc->err_mask |= AC_ERR_SYSTEM;
4631err:
4632 ata_qc_complete(qc);
1da177e4
LT		 4633}
4634
4635/**
4636 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
4637 * @qc: command to issue to device
4638 *
4639 * Using various libata functions and hooks, this function
4640 * starts an ATA command. ATA commands are grouped into
4641 * classes called "protocols", and issuing each type of protocol
4642 * is slightly different.
4643 *
0baab86b
EF		 4644 * May be used as the qc_issue() entry in ata_port_operations.
4645 *
1da177e4 4646 * LOCKING:
cca3974e 4647 * spin_lock_irqsave(host lock)
1da177e4
LT		 4648 *
4649 * RETURNS:
9a3d9eb0 4650 * Zero on success, AC_ERR_* mask on failure
1da177e4
LT		 4651 */
4652
9a3d9eb0 4653unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
1da177e4
LT		 4654{
4655 struct ata_port *ap = qc->ap;
4656
e50362ec
AL		 4657 /* Use polling pio if the LLD doesn't handle
4658 * interrupt driven pio and atapi CDB interrupt.
4659 */
4660 if (ap->flags & ATA_FLAG_PIO_POLLING) {
4661 switch (qc->tf.protocol) {
4662 case ATA_PROT_PIO:
4663 case ATA_PROT_ATAPI:
4664 case ATA_PROT_ATAPI_NODATA:
4665 qc->tf.flags |= ATA_TFLAG_POLLING;
4666 break;
4667 case ATA_PROT_ATAPI_DMA:
4668 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
3a778275 4669 /* see ata_dma_blacklisted() */
e50362ec
AL		 4670 BUG();
4671 break;
4672 default:
4673 break;
4674 }
4675 }
4676
312f7da2 4677 /* select the device */
1da177e4
LT		 4678 ata_dev_select(ap, qc->dev->devno, 1, 0);
4679
312f7da2 4680 /* start the command */
1da177e4
LT		 4681 switch (qc->tf.protocol) {
4682 case ATA_PROT_NODATA:
312f7da2
AL		 4683 if (qc->tf.flags & ATA_TFLAG_POLLING)
4684 ata_qc_set_polling(qc);
4685
e5338254 4686 ata_tf_to_host(ap, &qc->tf);
312f7da2
AL		 4687 ap->hsm_task_state = HSM_ST_LAST;
4688
4689 if (qc->tf.flags & ATA_TFLAG_POLLING)
31ce6dae 4690 ata_port_queue_task(ap, ata_pio_task, qc, 0);
312f7da2 4691
1da177e4
LT		 4692 break;
4693
4694 case ATA_PROT_DMA:
587005de 4695 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
312f7da2 4696
1da177e4
LT		 4697 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
4698 ap->ops->bmdma_setup(qc); /* set up bmdma */
4699 ap->ops->bmdma_start(qc); /* initiate bmdma */
312f7da2 4700 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 4701 break;
4702
312f7da2
AL		 4703 case ATA_PROT_PIO:
4704 if (qc->tf.flags & ATA_TFLAG_POLLING)
4705 ata_qc_set_polling(qc);
1da177e4 4706
e5338254 4707 ata_tf_to_host(ap, &qc->tf);
312f7da2 4708
54f00389
AL		 4709 if (qc->tf.flags & ATA_TFLAG_WRITE) {
4710 /* PIO data out protocol */
4711 ap->hsm_task_state = HSM_ST_FIRST;
31ce6dae 4712 ata_port_queue_task(ap, ata_pio_task, qc, 0);
54f00389
AL		 4713
4714 /* always send first data block using
e27486db 4715 * the ata_pio_task() codepath.
54f00389 4716 */
312f7da2 4717 } else {
54f00389
AL		 4718 /* PIO data in protocol */
4719 ap->hsm_task_state = HSM_ST;
4720
4721 if (qc->tf.flags & ATA_TFLAG_POLLING)
31ce6dae 4722 ata_port_queue_task(ap, ata_pio_task, qc, 0);
54f00389
AL		 4723
4724 /* if polling, ata_pio_task() handles the rest.
4725 * otherwise, interrupt handler takes over from here.
4726 */
312f7da2
AL		 4727 }
4728
1da177e4
LT		 4729 break;
4730
1da177e4 4731 case ATA_PROT_ATAPI:
1da177e4 4732 case ATA_PROT_ATAPI_NODATA:
312f7da2
AL		 4733 if (qc->tf.flags & ATA_TFLAG_POLLING)
4734 ata_qc_set_polling(qc);
4735
e5338254 4736 ata_tf_to_host(ap, &qc->tf);
f6ef65e6 4737
312f7da2
AL		 4738 ap->hsm_task_state = HSM_ST_FIRST;
4739
4740 /* send cdb by polling if no cdb interrupt */
4741 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
4742 (qc->tf.flags & ATA_TFLAG_POLLING))
31ce6dae 4743 ata_port_queue_task(ap, ata_pio_task, qc, 0);
1da177e4
LT		 4744 break;
4745
4746 case ATA_PROT_ATAPI_DMA:
587005de 4747 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
312f7da2 4748
1da177e4
LT		 4749 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
4750 ap->ops->bmdma_setup(qc); /* set up bmdma */
312f7da2
AL		 4751 ap->hsm_task_state = HSM_ST_FIRST;
4752
4753 /* send cdb by polling if no cdb interrupt */
4754 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
31ce6dae 4755 ata_port_queue_task(ap, ata_pio_task, qc, 0);
1da177e4
LT		 4756 break;
4757
4758 default:
4759 WARN_ON(1);
9a3d9eb0 4760 return AC_ERR_SYSTEM;
1da177e4
LT		 4761 }
4762
4763 return 0;
4764}
4765
1da177e4
LT		 4766/**
4767 * ata_host_intr - Handle host interrupt for given (port, task)
4768 * @ap: Port on which interrupt arrived (possibly...)
4769 * @qc: Taskfile currently active in engine
4770 *
4771 * Handle host interrupt for given queued command. Currently,
4772 * only DMA interrupts are handled. All other commands are
4773 * handled via polling with interrupts disabled (nIEN bit).
4774 *
4775 * LOCKING:
cca3974e 4776 * spin_lock_irqsave(host lock)
1da177e4
LT		 4777 *
4778 * RETURNS:
4779 * One if interrupt was handled, zero if not (shared irq).
4780 */
4781
4782inline unsigned int ata_host_intr (struct ata_port *ap,
4783 struct ata_queued_cmd *qc)
4784{
312f7da2 4785 u8 status, host_stat = 0;
1da177e4 4786
312f7da2
AL		 4787 VPRINTK("ata%u: protocol %d task_state %d\n",
4788 ap->id, qc->tf.protocol, ap->hsm_task_state);
1da177e4 4789
312f7da2
AL		 4790 /* Check whether we are expecting interrupt in this state */
4791 switch (ap->hsm_task_state) {
4792 case HSM_ST_FIRST:
6912ccd5
AL		 4793 /* Some pre-ATAPI-4 devices assert INTRQ
4794 * at this state when ready to receive CDB.
4795 */
1da177e4 4796
312f7da2
AL		 4797 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
4798 * The flag was turned on only for atapi devices.
4799 * No need to check is_atapi_taskfile(&qc->tf) again.
4800 */
4801 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1da177e4 4802 goto idle_irq;
1da177e4 4803 break;
312f7da2
AL		 4804 case HSM_ST_LAST:
4805 if (qc->tf.protocol == ATA_PROT_DMA ||
4806 qc->tf.protocol == ATA_PROT_ATAPI_DMA) {
4807 /* check status of DMA engine */
4808 host_stat = ap->ops->bmdma_status(ap);
4809 VPRINTK("ata%u: host_stat 0x%X\n", ap->id, host_stat);
4810
4811 /* if it's not our irq... */
4812 if (!(host_stat & ATA_DMA_INTR))
4813 goto idle_irq;
4814
4815 /* before we do anything else, clear DMA-Start bit */
4816 ap->ops->bmdma_stop(qc);
a4f16610
AL		 4817
4818 if (unlikely(host_stat & ATA_DMA_ERR)) {
4819 /* error when transfering data to/from memory */
4820 qc->err_mask |= AC_ERR_HOST_BUS;
4821 ap->hsm_task_state = HSM_ST_ERR;
4822 }
312f7da2
AL		 4823 }
4824 break;
4825 case HSM_ST:
4826 break;
1da177e4
LT		 4827 default:
4828 goto idle_irq;
4829 }
4830
312f7da2
AL		 4831 /* check altstatus */
4832 status = ata_altstatus(ap);
4833 if (status & ATA_BUSY)
4834 goto idle_irq;
1da177e4 4835
312f7da2
AL		 4836 /* check main status, clearing INTRQ */
4837 status = ata_chk_status(ap);
4838 if (unlikely(status & ATA_BUSY))
4839 goto idle_irq;
1da177e4 4840
312f7da2
AL		 4841 /* ack bmdma irq events */
4842 ap->ops->irq_clear(ap);
1da177e4 4843
bb5cb290 4844 ata_hsm_move(ap, qc, status, 0);
1da177e4
LT		 4845 return 1; /* irq handled */
4846
4847idle_irq:
4848 ap->stats.idle_irq++;
4849
4850#ifdef ATA_IRQ_TRAP
4851 if ((ap->stats.idle_irq % 1000) == 0) {
1da177e4 4852 ata_irq_ack(ap, 0); /* debug trap */
f15a1daf 4853 ata_port_printk(ap, KERN_WARNING, "irq trap\n");
23cfce89 4854 return 1;
1da177e4
LT		 4855 }
4856#endif
4857 return 0; /* irq not handled */
4858}
4859
4860/**
4861 * ata_interrupt - Default ATA host interrupt handler
0cba632b 4862 * @irq: irq line (unused)
cca3974e 4863 * @dev_instance: pointer to our ata_host information structure
1da177e4 4864 *
0cba632b
JG		 4865 * Default interrupt handler for PCI IDE devices. Calls
4866 * ata_host_intr() for each port that is not disabled.
4867 *
1da177e4 4868 * LOCKING:
cca3974e 4869 * Obtains host lock during operation.
1da177e4
LT		 4870 *
4871 * RETURNS:
0cba632b 4872 * IRQ_NONE or IRQ_HANDLED.
1da177e4
LT		 4873 */
4874
7d12e780 4875irqreturn_t ata_interrupt (int irq, void *dev_instance)
1da177e4 4876{
cca3974e 4877 struct ata_host *host = dev_instance;
1da177e4
LT		 4878 unsigned int i;
4879 unsigned int handled = 0;
4880 unsigned long flags;
4881
4882 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
cca3974e 4883 spin_lock_irqsave(&host->lock, flags);
1da177e4 4884
cca3974e 4885 for (i = 0; i < host->n_ports; i++) {
1da177e4
LT		 4886 struct ata_port *ap;
4887
cca3974e 4888 ap = host->ports[i];
c1389503 4889 if (ap &&
029f5468 4890 !(ap->flags & ATA_FLAG_DISABLED)) {
1da177e4
LT		 4891 struct ata_queued_cmd *qc;
4892
4893 qc = ata_qc_from_tag(ap, ap->active_tag);
312f7da2 4894 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
21b1ed74 4895 (qc->flags & ATA_QCFLAG_ACTIVE))
1da177e4
LT		 4896 handled |= ata_host_intr(ap, qc);
4897 }
4898 }
4899
cca3974e 4900 spin_unlock_irqrestore(&host->lock, flags);
1da177e4
LT		 4901
4902 return IRQ_RETVAL(handled);
4903}
4904
34bf2170
TH		 4905/**
4906 * sata_scr_valid - test whether SCRs are accessible
4907 * @ap: ATA port to test SCR accessibility for
4908 *
4909 * Test whether SCRs are accessible for @ap.
4910 *
4911 * LOCKING:
4912 * None.
4913 *
4914 * RETURNS:
4915 * 1 if SCRs are accessible, 0 otherwise.
4916 */
4917int sata_scr_valid(struct ata_port *ap)
4918{
4919 return ap->cbl == ATA_CBL_SATA && ap->ops->scr_read;
4920}
4921
4922/**
4923 * sata_scr_read - read SCR register of the specified port
4924 * @ap: ATA port to read SCR for
4925 * @reg: SCR to read
4926 * @val: Place to store read value
4927 *
4928 * Read SCR register @reg of @ap into *@val. This function is
4929 * guaranteed to succeed if the cable type of the port is SATA
4930 * and the port implements ->scr_read.
4931 *
4932 * LOCKING:
4933 * None.
4934 *
4935 * RETURNS:
4936 * 0 on success, negative errno on failure.
4937 */
4938int sata_scr_read(struct ata_port *ap, int reg, u32 *val)
4939{
4940 if (sata_scr_valid(ap)) {
4941 *val = ap->ops->scr_read(ap, reg);
4942 return 0;
4943 }
4944 return -EOPNOTSUPP;
4945}
4946
4947/**
4948 * sata_scr_write - write SCR register of the specified port
4949 * @ap: ATA port to write SCR for
4950 * @reg: SCR to write
4951 * @val: value to write
4952 *
4953 * Write @val to SCR register @reg of @ap. This function is
4954 * guaranteed to succeed if the cable type of the port is SATA
4955 * and the port implements ->scr_read.
4956 *
4957 * LOCKING:
4958 * None.
4959 *
4960 * RETURNS:
4961 * 0 on success, negative errno on failure.
4962 */
4963int sata_scr_write(struct ata_port *ap, int reg, u32 val)
4964{
4965 if (sata_scr_valid(ap)) {
4966 ap->ops->scr_write(ap, reg, val);
4967 return 0;
4968 }
4969 return -EOPNOTSUPP;
4970}
4971
4972/**
4973 * sata_scr_write_flush - write SCR register of the specified port and flush
4974 * @ap: ATA port to write SCR for
4975 * @reg: SCR to write
4976 * @val: value to write
4977 *
4978 * This function is identical to sata_scr_write() except that this
4979 * function performs flush after writing to the register.
4980 *
4981 * LOCKING:
4982 * None.
4983 *
4984 * RETURNS:
4985 * 0 on success, negative errno on failure.
4986 */
4987int sata_scr_write_flush(struct ata_port *ap, int reg, u32 val)
4988{
4989 if (sata_scr_valid(ap)) {
4990 ap->ops->scr_write(ap, reg, val);
4991 ap->ops->scr_read(ap, reg);
4992 return 0;
4993 }
4994 return -EOPNOTSUPP;
4995}
4996
4997/**
4998 * ata_port_online - test whether the given port is online
4999 * @ap: ATA port to test
5000 *
5001 * Test whether @ap is online. Note that this function returns 0
5002 * if online status of @ap cannot be obtained, so
5003 * ata_port_online(ap) != !ata_port_offline(ap).
5004 *
5005 * LOCKING:
5006 * None.
5007 *
5008 * RETURNS:
5009 * 1 if the port online status is available and online.
5010 */
5011int ata_port_online(struct ata_port *ap)
5012{
5013 u32 sstatus;
5014
5015 if (!sata_scr_read(ap, SCR_STATUS, &sstatus) && (sstatus & 0xf) == 0x3)
5016 return 1;
5017 return 0;
5018}
5019
5020/**
5021 * ata_port_offline - test whether the given port is offline
5022 * @ap: ATA port to test
5023 *
5024 * Test whether @ap is offline. Note that this function returns
5025 * 0 if offline status of @ap cannot be obtained, so
5026 * ata_port_online(ap) != !ata_port_offline(ap).
5027 *
5028 * LOCKING:
5029 * None.
5030 *
5031 * RETURNS:
5032 * 1 if the port offline status is available and offline.
5033 */
5034int ata_port_offline(struct ata_port *ap)
5035{
5036 u32 sstatus;
5037
5038 if (!sata_scr_read(ap, SCR_STATUS, &sstatus) && (sstatus & 0xf) != 0x3)
5039 return 1;
5040 return 0;
5041}
0baab86b 5042
77b08fb5 5043int ata_flush_cache(struct ata_device *dev)
9b847548 5044{
977e6b9f 5045 unsigned int err_mask;
9b847548
JA		 5046 u8 cmd;
5047
5048 if (!ata_try_flush_cache(dev))
5049 return 0;
5050
5051 if (ata_id_has_flush_ext(dev->id))
5052 cmd = ATA_CMD_FLUSH_EXT;
5053 else
5054 cmd = ATA_CMD_FLUSH;
5055
977e6b9f
TH		 5056 err_mask = ata_do_simple_cmd(dev, cmd);
5057 if (err_mask) {
5058 ata_dev_printk(dev, KERN_ERR, "failed to flush cache\n");
5059 return -EIO;
5060 }
5061
5062 return 0;
9b847548
JA		 5063}
5064
cca3974e
JG		 5065static int ata_host_request_pm(struct ata_host *host, pm_message_t mesg,
5066 unsigned int action, unsigned int ehi_flags,
5067 int wait)
500530f6
TH		 5068{
5069 unsigned long flags;
5070 int i, rc;
5071
cca3974e
JG		 5072 for (i = 0; i < host->n_ports; i++) {
5073 struct ata_port *ap = host->ports[i];
500530f6
TH		 5074
5075 /* Previous resume operation might still be in
5076 * progress. Wait for PM_PENDING to clear.
5077 */
5078 if (ap->pflags & ATA_PFLAG_PM_PENDING) {
5079 ata_port_wait_eh(ap);
5080 WARN_ON(ap->pflags & ATA_PFLAG_PM_PENDING);
5081 }
5082
5083 /* request PM ops to EH */
5084 spin_lock_irqsave(ap->lock, flags);
5085
5086 ap->pm_mesg = mesg;
5087 if (wait) {
5088 rc = 0;
5089 ap->pm_result = &rc;
5090 }
5091
5092 ap->pflags |= ATA_PFLAG_PM_PENDING;
5093 ap->eh_info.action |= action;
5094 ap->eh_info.flags |= ehi_flags;
5095
5096 ata_port_schedule_eh(ap);
5097
5098 spin_unlock_irqrestore(ap->lock, flags);
5099
5100 /* wait and check result */
5101 if (wait) {
5102 ata_port_wait_eh(ap);
5103 WARN_ON(ap->pflags & ATA_PFLAG_PM_PENDING);
5104 if (rc)
5105 return rc;
5106 }
5107 }
5108
5109 return 0;
5110}
5111
5112/**
cca3974e
JG		 5113 * ata_host_suspend - suspend host
5114 * @host: host to suspend
500530f6
TH		 5115 * @mesg: PM message
5116 *
cca3974e 5117 * Suspend @host. Actual operation is performed by EH. This
500530f6
TH		 5118 * function requests EH to perform PM operations and waits for EH
5119 * to finish.
5120 *
5121 * LOCKING:
5122 * Kernel thread context (may sleep).
5123 *
5124 * RETURNS:
5125 * 0 on success, -errno on failure.
5126 */
cca3974e 5127int ata_host_suspend(struct ata_host *host, pm_message_t mesg)
500530f6
TH		 5128{
5129 int i, j, rc;
5130
cca3974e 5131 rc = ata_host_request_pm(host, mesg, 0, ATA_EHI_QUIET, 1);
500530f6
TH		 5132 if (rc)
5133 goto fail;
5134
5135 /* EH is quiescent now. Fail if we have any ready device.
5136 * This happens if hotplug occurs between completion of device
5137 * suspension and here.
5138 */
cca3974e
JG		 5139 for (i = 0; i < host->n_ports; i++) {
5140 struct ata_port *ap = host->ports[i];
500530f6
TH		 5141
5142 for (j = 0; j < ATA_MAX_DEVICES; j++) {
5143 struct ata_device *dev = &ap->device[j];
5144
5145 if (ata_dev_ready(dev)) {
5146 ata_port_printk(ap, KERN_WARNING,
5147 "suspend failed, device %d "
5148 "still active\n", dev->devno);
5149 rc = -EBUSY;
5150 goto fail;
5151 }
5152 }
5153 }
5154
cca3974e 5155 host->dev->power.power_state = mesg;
500530f6
TH		 5156 return 0;
5157
5158 fail:
cca3974e 5159 ata_host_resume(host);
500530f6
TH		 5160 return rc;
5161}
5162
5163/**
cca3974e
JG		 5164 * ata_host_resume - resume host
5165 * @host: host to resume
500530f6 5166 *
cca3974e 5167 * Resume @host. Actual operation is performed by EH. This
500530f6
TH		 5168 * function requests EH to perform PM operations and returns.
5169 * Note that all resume operations are performed parallely.
5170 *
5171 * LOCKING:
5172 * Kernel thread context (may sleep).
5173 */
cca3974e 5174void ata_host_resume(struct ata_host *host)
500530f6 5175{
cca3974e
JG		 5176 ata_host_request_pm(host, PMSG_ON, ATA_EH_SOFTRESET,
5177 ATA_EHI_NO_AUTOPSY | ATA_EHI_QUIET, 0);
5178 host->dev->power.power_state = PMSG_ON;
500530f6
TH		 5179}
5180
c893a3ae
RD		 5181/**
5182 * ata_port_start - Set port up for dma.
5183 * @ap: Port to initialize
5184 *
5185 * Called just after data structures for each port are
5186 * initialized. Allocates space for PRD table.
5187 *
5188 * May be used as the port_start() entry in ata_port_operations.
5189 *
5190 * LOCKING:
5191 * Inherited from caller.
5192 */
5193
1da177e4
LT		 5194int ata_port_start (struct ata_port *ap)
5195{
2f1f610b 5196 struct device *dev = ap->dev;
6037d6bb 5197 int rc;
1da177e4
LT		 5198
5199 ap->prd = dma_alloc_coherent(dev, ATA_PRD_TBL_SZ, &ap->prd_dma, GFP_KERNEL);
5200 if (!ap->prd)
5201 return -ENOMEM;
5202
6037d6bb
JG		 5203 rc = ata_pad_alloc(ap, dev);
5204 if (rc) {
cedc9a47 5205 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 5206 return rc;
cedc9a47
JG		 5207 }
5208
1da177e4
LT		 5209 DPRINTK("prd alloc, virt %p, dma %llx\n", ap->prd, (unsigned long long) ap->prd_dma);
5210
5211 return 0;
5212}
5213
0baab86b
EF		 5214
5215/**
5216 * ata_port_stop - Undo ata_port_start()
5217 * @ap: Port to shut down
5218 *
5219 * Frees the PRD table.
5220 *
5221 * May be used as the port_stop() entry in ata_port_operations.
5222 *
5223 * LOCKING:
6f0ef4fa 5224 * Inherited from caller.
0baab86b
EF		 5225 */
5226
1da177e4
LT		 5227void ata_port_stop (struct ata_port *ap)
5228{
2f1f610b 5229 struct device *dev = ap->dev;
1da177e4
LT		 5230
5231 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 5232 ata_pad_free(ap, dev);
1da177e4
LT		 5233}
5234
cca3974e 5235void ata_host_stop (struct ata_host *host)
aa8f0dc6 5236{
cca3974e
JG		 5237 if (host->mmio_base)
5238 iounmap(host->mmio_base);
aa8f0dc6
JG		 5239}
5240
3ef3b43d
TH		 5241/**
5242 * ata_dev_init - Initialize an ata_device structure
5243 * @dev: Device structure to initialize
5244 *
5245 * Initialize @dev in preparation for probing.
5246 *
5247 * LOCKING:
5248 * Inherited from caller.
5249 */
5250void ata_dev_init(struct ata_device *dev)
5251{
5252 struct ata_port *ap = dev->ap;
72fa4b74
TH		 5253 unsigned long flags;
5254
5a04bf4b
TH		 5255 /* SATA spd limit is bound to the first device */
5256 ap->sata_spd_limit = ap->hw_sata_spd_limit;
5257
72fa4b74
TH		 5258 /* High bits of dev->flags are used to record warm plug
5259 * requests which occur asynchronously. Synchronize using
cca3974e 5260 * host lock.
72fa4b74 5261 */
ba6a1308 5262 spin_lock_irqsave(ap->lock, flags);
72fa4b74 5263 dev->flags &= ~ATA_DFLAG_INIT_MASK;
ba6a1308 5264 spin_unlock_irqrestore(ap->lock, flags);
3ef3b43d 5265
72fa4b74
TH		 5266 memset((void *)dev + ATA_DEVICE_CLEAR_OFFSET, 0,
5267 sizeof(*dev) - ATA_DEVICE_CLEAR_OFFSET);
3ef3b43d
TH		 5268 dev->pio_mask = UINT_MAX;
5269 dev->mwdma_mask = UINT_MAX;
5270 dev->udma_mask = UINT_MAX;
5271}
5272
1da177e4 5273/**
155a8a9c 5274 * ata_port_init - Initialize an ata_port structure
1da177e4 5275 * @ap: Structure to initialize
cca3974e 5276 * @host: Collection of hosts to which @ap belongs
1da177e4
LT		 5277 * @ent: Probe information provided by low-level driver
5278 * @port_no: Port number associated with this ata_port
5279 *
155a8a9c 5280 * Initialize a new ata_port structure.
0cba632b 5281 *
1da177e4 5282 * LOCKING:
0cba632b 5283 * Inherited from caller.
1da177e4 5284 */
cca3974e 5285void ata_port_init(struct ata_port *ap, struct ata_host *host,
155a8a9c 5286 const struct ata_probe_ent *ent, unsigned int port_no)
1da177e4
LT		 5287{
5288 unsigned int i;
5289
cca3974e 5290 ap->lock = &host->lock;
198e0fed 5291 ap->flags = ATA_FLAG_DISABLED;
155a8a9c 5292 ap->id = ata_unique_id++;
1da177e4 5293 ap->ctl = ATA_DEVCTL_OBS;
cca3974e 5294 ap->host = host;
2f1f610b 5295 ap->dev = ent->dev;
1da177e4 5296 ap->port_no = port_no;
fea63e38
TH		 5297 if (port_no == 1 && ent->pinfo2) {
5298 ap->pio_mask = ent->pinfo2->pio_mask;
5299 ap->mwdma_mask = ent->pinfo2->mwdma_mask;
5300 ap->udma_mask = ent->pinfo2->udma_mask;
5301 ap->flags |= ent->pinfo2->flags;
5302 ap->ops = ent->pinfo2->port_ops;
5303 } else {
5304 ap->pio_mask = ent->pio_mask;
5305 ap->mwdma_mask = ent->mwdma_mask;
5306 ap->udma_mask = ent->udma_mask;
5307 ap->flags |= ent->port_flags;
5308 ap->ops = ent->port_ops;
5309 }
5a04bf4b 5310 ap->hw_sata_spd_limit = UINT_MAX;
1da177e4
LT		 5311 ap->active_tag = ATA_TAG_POISON;
5312 ap->last_ctl = 0xFF;
bd5d825c
BP		 5313
5314#if defined(ATA_VERBOSE_DEBUG)
5315 /* turn on all debugging levels */
5316 ap->msg_enable = 0x00FF;
5317#elif defined(ATA_DEBUG)
5318 ap->msg_enable = ATA_MSG_DRV | ATA_MSG_INFO | ATA_MSG_CTL | ATA_MSG_WARN | ATA_MSG_ERR;
88574551 5319#else
0dd4b21f 5320 ap->msg_enable = ATA_MSG_DRV | ATA_MSG_ERR | ATA_MSG_WARN;
bd5d825c 5321#endif
1da177e4 5322
86e45b6b 5323 INIT_WORK(&ap->port_task, NULL, NULL);
580b2102 5324 INIT_WORK(&ap->hotplug_task, ata_scsi_hotplug, ap);
3057ac3c 5325 INIT_WORK(&ap->scsi_rescan_task, ata_scsi_dev_rescan, ap);
a72ec4ce 5326 INIT_LIST_HEAD(&ap->eh_done_q);
c6cf9e99 5327 init_waitqueue_head(&ap->eh_wait_q);
1da177e4 5328
838df628
TH		 5329 /* set cable type */
5330 ap->cbl = ATA_CBL_NONE;
5331 if (ap->flags & ATA_FLAG_SATA)
5332 ap->cbl = ATA_CBL_SATA;
5333
acf356b1
TH		 5334 for (i = 0; i < ATA_MAX_DEVICES; i++) {
5335 struct ata_device *dev = &ap->device[i];
38d87234 5336 dev->ap = ap;
72fa4b74 5337 dev->devno = i;
3ef3b43d 5338 ata_dev_init(dev);
acf356b1 5339 }
1da177e4
LT		 5340
5341#ifdef ATA_IRQ_TRAP
5342 ap->stats.unhandled_irq = 1;
5343 ap->stats.idle_irq = 1;
5344#endif
5345
5346 memcpy(&ap->ioaddr, &ent->port[port_no], sizeof(struct ata_ioports));
5347}
5348
155a8a9c 5349/**
4608c160
TH		 5350 * ata_port_init_shost - Initialize SCSI host associated with ATA port
5351 * @ap: ATA port to initialize SCSI host for
5352 * @shost: SCSI host associated with @ap
155a8a9c 5353 *
4608c160 5354 * Initialize SCSI host @shost associated with ATA port @ap.
155a8a9c
BK		 5355 *
5356 * LOCKING:
5357 * Inherited from caller.
5358 */
4608c160 5359static void ata_port_init_shost(struct ata_port *ap, struct Scsi_Host *shost)
155a8a9c 5360{
cca3974e 5361 ap->scsi_host = shost;
155a8a9c 5362
4608c160
TH		 5363 shost->unique_id = ap->id;
5364 shost->max_id = 16;
5365 shost->max_lun = 1;
5366 shost->max_channel = 1;
5367 shost->max_cmd_len = 12;
155a8a9c
BK		 5368}
5369
1da177e4 5370/**
996139f1 5371 * ata_port_add - Attach low-level ATA driver to system
1da177e4 5372 * @ent: Information provided by low-level driver
cca3974e 5373 * @host: Collections of ports to which we add
1da177e4
LT		 5374 * @port_no: Port number associated with this host
5375 *
0cba632b
JG		 5376 * Attach low-level ATA driver to system.
5377 *
1da177e4 5378 * LOCKING:
0cba632b 5379 * PCI/etc. bus probe sem.
1da177e4
LT		 5380 *
5381 * RETURNS:
0cba632b 5382 * New ata_port on success, for NULL on error.
1da177e4 5383 */
996139f1 5384static struct ata_port * ata_port_add(const struct ata_probe_ent *ent,
cca3974e 5385 struct ata_host *host,
1da177e4
LT		 5386 unsigned int port_no)
5387{
996139f1 5388 struct Scsi_Host *shost;
1da177e4 5389 struct ata_port *ap;
1da177e4
LT		 5390
5391 DPRINTK("ENTER\n");
aec5c3c1 5392
52783c5d 5393 if (!ent->port_ops->error_handler &&
cca3974e 5394 !(ent->port_flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST))) {
aec5c3c1
TH		 5395 printk(KERN_ERR "ata%u: no reset mechanism available\n",
5396 port_no);
5397 return NULL;
5398 }
5399
996139f1
JG		 5400 shost = scsi_host_alloc(ent->sht, sizeof(struct ata_port));
5401 if (!shost)
1da177e4
LT		 5402 return NULL;
5403
996139f1 5404 shost->transportt = &ata_scsi_transport_template;
30afc84c 5405
996139f1 5406 ap = ata_shost_to_port(shost);
1da177e4 5407
cca3974e 5408 ata_port_init(ap, host, ent, port_no);
996139f1 5409 ata_port_init_shost(ap, shost);
1da177e4 5410
1da177e4 5411 return ap;
1da177e4
LT		 5412}
5413
b03732f0 5414/**
cca3974e
JG		 5415 * ata_sas_host_init - Initialize a host struct
5416 * @host: host to initialize
5417 * @dev: device host is attached to
5418 * @flags: host flags
5419 * @ops: port_ops
b03732f0
BK		 5420 *
5421 * LOCKING:
5422 * PCI/etc. bus probe sem.
5423 *
5424 */
5425
cca3974e
JG		 5426void ata_host_init(struct ata_host *host, struct device *dev,
5427 unsigned long flags, const struct ata_port_operations *ops)
b03732f0 5428{
cca3974e
JG		 5429 spin_lock_init(&host->lock);
5430 host->dev = dev;
5431 host->flags = flags;
5432 host->ops = ops;
b03732f0
BK		 5433}
5434
1da177e4 5435/**
0cba632b
JG		 5436 * ata_device_add - Register hardware device with ATA and SCSI layers
5437 * @ent: Probe information describing hardware device to be registered
5438 *
5439 * This function processes the information provided in the probe
5440 * information struct @ent, allocates the necessary ATA and SCSI
5441 * host information structures, initializes them, and registers
5442 * everything with requisite kernel subsystems.
5443 *
5444 * This function requests irqs, probes the ATA bus, and probes
5445 * the SCSI bus.
1da177e4
LT		 5446 *
5447 * LOCKING:
0cba632b 5448 * PCI/etc. bus probe sem.
1da177e4
LT		 5449 *
5450 * RETURNS:
0cba632b 5451 * Number of ports registered. Zero on error (no ports registered).
1da177e4 5452 */
057ace5e 5453int ata_device_add(const struct ata_probe_ent *ent)
1da177e4 5454{
6d0500df 5455 unsigned int i;
1da177e4 5456 struct device *dev = ent->dev;
cca3974e 5457 struct ata_host *host;
39b07ce6 5458 int rc;
1da177e4
LT		 5459
5460 DPRINTK("ENTER\n");
02f076aa
AC		 5461
5462 if (ent->irq == 0) {
5463 dev_printk(KERN_ERR, dev, "is not available: No interrupt assigned.\n");
5464 return 0;
5465 }
1da177e4 5466 /* alloc a container for our list of ATA ports (buses) */
cca3974e
JG		 5467 host = kzalloc(sizeof(struct ata_host) +
5468 (ent->n_ports * sizeof(void *)), GFP_KERNEL);
5469 if (!host)
1da177e4 5470 return 0;
1da177e4 5471
cca3974e
JG		 5472 ata_host_init(host, dev, ent->_host_flags, ent->port_ops);
5473 host->n_ports = ent->n_ports;
5474 host->irq = ent->irq;
5475 host->irq2 = ent->irq2;
5476 host->mmio_base = ent->mmio_base;
5477 host->private_data = ent->private_data;
1da177e4
LT		 5478
5479 /* register each port bound to this device */
cca3974e 5480 for (i = 0; i < host->n_ports; i++) {
1da177e4
LT		 5481 struct ata_port *ap;
5482 unsigned long xfer_mode_mask;
2ec7df04 5483 int irq_line = ent->irq;
1da177e4 5484
cca3974e 5485 ap = ata_port_add(ent, host, i);
c38778c3 5486 host->ports[i] = ap;
1da177e4
LT		 5487 if (!ap)
5488 goto err_out;
5489
dd5b06c4
TH		 5490 /* dummy? */
5491 if (ent->dummy_port_mask & (1 << i)) {
5492 ata_port_printk(ap, KERN_INFO, "DUMMY\n");
5493 ap->ops = &ata_dummy_port_ops;
5494 continue;
5495 }
5496
5497 /* start port */
5498 rc = ap->ops->port_start(ap);
5499 if (rc) {
cca3974e
JG		 5500 host->ports[i] = NULL;
5501 scsi_host_put(ap->scsi_host);
dd5b06c4
TH		 5502 goto err_out;
5503 }
5504
2ec7df04
AC		 5505 /* Report the secondary IRQ for second channel legacy */
5506 if (i == 1 && ent->irq2)
5507 irq_line = ent->irq2;
5508
1da177e4
LT		 5509 xfer_mode_mask =(ap->udma_mask << ATA_SHIFT_UDMA) |
5510 (ap->mwdma_mask << ATA_SHIFT_MWDMA) |
5511 (ap->pio_mask << ATA_SHIFT_PIO);
5512
5513 /* print per-port info to dmesg */
f15a1daf 5514 ata_port_printk(ap, KERN_INFO, "%cATA max %s cmd 0x%lX "
2ec7df04 5515 "ctl 0x%lX bmdma 0x%lX irq %d\n",
f15a1daf
TH		 5516 ap->flags & ATA_FLAG_SATA ? 'S' : 'P',
5517 ata_mode_string(xfer_mode_mask),
5518 ap->ioaddr.cmd_addr,
5519 ap->ioaddr.ctl_addr,
5520 ap->ioaddr.bmdma_addr,
2ec7df04 5521 irq_line);
1da177e4
LT		 5522
5523 ata_chk_status(ap);
cca3974e 5524 host->ops->irq_clear(ap);
e3180499 5525 ata_eh_freeze_port(ap); /* freeze port before requesting IRQ */
1da177e4
LT		 5526 }
5527
2ec7df04 5528 /* obtain irq, that may be shared between channels */
39b07ce6 5529 rc = request_irq(ent->irq, ent->port_ops->irq_handler, ent->irq_flags,
cca3974e 5530 DRV_NAME, host);
39b07ce6
JG		 5531 if (rc) {
5532 dev_printk(KERN_ERR, dev, "irq %lu request failed: %d\n",
5533 ent->irq, rc);
1da177e4 5534 goto err_out;
39b07ce6 5535 }
1da177e4 5536
2ec7df04
AC		 5537 /* do we have a second IRQ for the other channel, eg legacy mode */
5538 if (ent->irq2) {
5539 /* We will get weird core code crashes later if this is true
5540 so trap it now */
5541 BUG_ON(ent->irq == ent->irq2);
5542
5543 rc = request_irq(ent->irq2, ent->port_ops->irq_handler, ent->irq_flags,
cca3974e 5544 DRV_NAME, host);
2ec7df04
AC		 5545 if (rc) {
5546 dev_printk(KERN_ERR, dev, "irq %lu request failed: %d\n",
5547 ent->irq2, rc);
5548 goto err_out_free_irq;
5549 }
5550 }
5551
1da177e4
LT		 5552 /* perform each probe synchronously */
5553 DPRINTK("probe begin\n");
cca3974e
JG		 5554 for (i = 0; i < host->n_ports; i++) {
5555 struct ata_port *ap = host->ports[i];
5a04bf4b 5556 u32 scontrol;
1da177e4
LT		 5557 int rc;
5558
5a04bf4b
TH		 5559 /* init sata_spd_limit to the current value */
5560 if (sata_scr_read(ap, SCR_CONTROL, &scontrol) == 0) {
5561 int spd = (scontrol >> 4) & 0xf;
5562 ap->hw_sata_spd_limit &= (1 << spd) - 1;
5563 }
5564 ap->sata_spd_limit = ap->hw_sata_spd_limit;
5565
cca3974e 5566 rc = scsi_add_host(ap->scsi_host, dev);
1da177e4 5567 if (rc) {
f15a1daf 5568 ata_port_printk(ap, KERN_ERR, "scsi_add_host failed\n");
1da177e4
LT		 5569 /* FIXME: do something useful here */
5570 /* FIXME: handle unconditional calls to
5571 * scsi_scan_host and ata_host_remove, below,
5572 * at the very least
5573 */
5574 }
3e706399 5575
52783c5d 5576 if (ap->ops->error_handler) {
1cdaf534 5577 struct ata_eh_info *ehi = &ap->eh_info;
3e706399
TH		 5578 unsigned long flags;
5579
5580 ata_port_probe(ap);
5581
5582 /* kick EH for boot probing */
ba6a1308 5583 spin_lock_irqsave(ap->lock, flags);
3e706399 5584
1cdaf534
TH		 5585 ehi->probe_mask = (1 << ATA_MAX_DEVICES) - 1;
5586 ehi->action |= ATA_EH_SOFTRESET;
5587 ehi->flags |= ATA_EHI_NO_AUTOPSY | ATA_EHI_QUIET;
3e706399 5588
b51e9e5d 5589 ap->pflags |= ATA_PFLAG_LOADING;
3e706399
TH		 5590 ata_port_schedule_eh(ap);
5591
ba6a1308 5592 spin_unlock_irqrestore(ap->lock, flags);
3e706399
TH		 5593
5594 /* wait for EH to finish */
5595 ata_port_wait_eh(ap);
5596 } else {
5597 DPRINTK("ata%u: bus probe begin\n", ap->id);
5598 rc = ata_bus_probe(ap);
5599 DPRINTK("ata%u: bus probe end\n", ap->id);
5600
5601 if (rc) {
5602 /* FIXME: do something useful here?
5603 * Current libata behavior will
5604 * tear down everything when
5605 * the module is removed
5606 * or the h/w is unplugged.
5607 */
5608 }
5609 }
1da177e4
LT		 5610 }
5611
5612 /* probes are done, now scan each port's disk(s) */
c893a3ae 5613 DPRINTK("host probe begin\n");
cca3974e
JG		 5614 for (i = 0; i < host->n_ports; i++) {
5615 struct ata_port *ap = host->ports[i];
1da177e4 5616
644dd0cc 5617 ata_scsi_scan_host(ap);
1da177e4
LT		 5618 }
5619
cca3974e 5620 dev_set_drvdata(dev, host);
1da177e4
LT		 5621
5622 VPRINTK("EXIT, returning %u\n", ent->n_ports);
5623 return ent->n_ports; /* success */
5624
2ec7df04 5625err_out_free_irq:
cca3974e 5626 free_irq(ent->irq, host);
1da177e4 5627err_out:
cca3974e
JG		 5628 for (i = 0; i < host->n_ports; i++) {
5629 struct ata_port *ap = host->ports[i];
77f3f879
TH		 5630 if (ap) {
5631 ap->ops->port_stop(ap);
cca3974e 5632 scsi_host_put(ap->scsi_host);
77f3f879 5633 }
1da177e4 5634 }
6d0500df 5635
cca3974e 5636 kfree(host);
1da177e4
LT		 5637 VPRINTK("EXIT, returning 0\n");
5638 return 0;
5639}
5640
720ba126
TH		 5641/**
5642 * ata_port_detach - Detach ATA port in prepration of device removal
5643 * @ap: ATA port to be detached
5644 *
5645 * Detach all ATA devices and the associated SCSI devices of @ap;
5646 * then, remove the associated SCSI host. @ap is guaranteed to
5647 * be quiescent on return from this function.
5648 *
5649 * LOCKING:
5650 * Kernel thread context (may sleep).
5651 */
5652void ata_port_detach(struct ata_port *ap)
5653{
5654 unsigned long flags;
5655 int i;
5656
5657 if (!ap->ops->error_handler)
c3cf30a9 5658 goto skip_eh;
720ba126
TH		 5659
5660 /* tell EH we're leaving & flush EH */
ba6a1308 5661 spin_lock_irqsave(ap->lock, flags);
b51e9e5d 5662 ap->pflags |= ATA_PFLAG_UNLOADING;
ba6a1308 5663 spin_unlock_irqrestore(ap->lock, flags);
720ba126
TH		 5664
5665 ata_port_wait_eh(ap);
5666
5667 /* EH is now guaranteed to see UNLOADING, so no new device
5668 * will be attached. Disable all existing devices.
5669 */
ba6a1308 5670 spin_lock_irqsave(ap->lock, flags);
720ba126
TH		 5671
5672 for (i = 0; i < ATA_MAX_DEVICES; i++)
5673 ata_dev_disable(&ap->device[i]);
5674
ba6a1308 5675 spin_unlock_irqrestore(ap->lock, flags);
720ba126
TH		 5676
5677 /* Final freeze & EH. All in-flight commands are aborted. EH
5678 * will be skipped and retrials will be terminated with bad
5679 * target.
5680 */
ba6a1308 5681 spin_lock_irqsave(ap->lock, flags);
720ba126 5682 ata_port_freeze(ap); /* won't be thawed */
ba6a1308 5683 spin_unlock_irqrestore(ap->lock, flags);
720ba126
TH		 5684
5685 ata_port_wait_eh(ap);
5686
5687 /* Flush hotplug task. The sequence is similar to
5688 * ata_port_flush_task().
5689 */
5690 flush_workqueue(ata_aux_wq);
5691 cancel_delayed_work(&ap->hotplug_task);
5692 flush_workqueue(ata_aux_wq);
5693
c3cf30a9 5694 skip_eh:
720ba126 5695 /* remove the associated SCSI host */
cca3974e 5696 scsi_remove_host(ap->scsi_host);
720ba126
TH		 5697}
5698
17b14451 5699/**
cca3974e
JG		 5700 * ata_host_remove - PCI layer callback for device removal
5701 * @host: ATA host set that was removed
17b14451 5702 *
2e9edbf8 5703 * Unregister all objects associated with this host set. Free those
17b14451
AC		 5704 * objects.
5705 *
5706 * LOCKING:
5707 * Inherited from calling layer (may sleep).
5708 */
5709
cca3974e 5710void ata_host_remove(struct ata_host *host)
17b14451 5711{
17b14451
AC		 5712 unsigned int i;
5713
cca3974e
JG		 5714 for (i = 0; i < host->n_ports; i++)
5715 ata_port_detach(host->ports[i]);
17b14451 5716
cca3974e
JG		 5717 free_irq(host->irq, host);
5718 if (host->irq2)
5719 free_irq(host->irq2, host);
17b14451 5720
cca3974e
JG		 5721 for (i = 0; i < host->n_ports; i++) {
5722 struct ata_port *ap = host->ports[i];
17b14451 5723
cca3974e 5724 ata_scsi_release(ap->scsi_host);
17b14451
AC		 5725
5726 if ((ap->flags & ATA_FLAG_NO_LEGACY) == 0) {
5727 struct ata_ioports *ioaddr = &ap->ioaddr;
5728
2ec7df04
AC		 5729 /* FIXME: Add -ac IDE pci mods to remove these special cases */
5730 if (ioaddr->cmd_addr == ATA_PRIMARY_CMD)
5731 release_region(ATA_PRIMARY_CMD, 8);
5732 else if (ioaddr->cmd_addr == ATA_SECONDARY_CMD)
5733 release_region(ATA_SECONDARY_CMD, 8);
17b14451
AC		 5734 }
5735
cca3974e 5736 scsi_host_put(ap->scsi_host);
17b14451
AC		 5737 }
5738
cca3974e
JG		 5739 if (host->ops->host_stop)
5740 host->ops->host_stop(host);
17b14451 5741
cca3974e 5742 kfree(host);
17b14451
AC		 5743}
5744
1da177e4
LT		 5745/**
5746 * ata_scsi_release - SCSI layer callback hook for host unload
4f931374 5747 * @shost: libata host to be unloaded
1da177e4
LT		 5748 *
5749 * Performs all duties necessary to shut down a libata port...
5750 * Kill port kthread, disable port, and release resources.
5751 *
5752 * LOCKING:
5753 * Inherited from SCSI layer.
5754 *
5755 * RETURNS:
5756 * One.
5757 */
5758
cca3974e 5759int ata_scsi_release(struct Scsi_Host *shost)
1da177e4 5760{
cca3974e 5761 struct ata_port *ap = ata_shost_to_port(shost);
1da177e4
LT		 5762
5763 DPRINTK("ENTER\n");
5764
5765 ap->ops->port_disable(ap);
6543bc07 5766 ap->ops->port_stop(ap);
1da177e4
LT		 5767
5768 DPRINTK("EXIT\n");
5769 return 1;
5770}
5771
f6d950e2
BK		 5772struct ata_probe_ent *
5773ata_probe_ent_alloc(struct device *dev, const struct ata_port_info *port)
5774{
5775 struct ata_probe_ent *probe_ent;
5776
5777 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
5778 if (!probe_ent) {
5779 printk(KERN_ERR DRV_NAME "(%s): out of memory\n",
5780 kobject_name(&(dev->kobj)));
5781 return NULL;
5782 }
5783
5784 INIT_LIST_HEAD(&probe_ent->node);
5785 probe_ent->dev = dev;
5786
5787 probe_ent->sht = port->sht;
cca3974e 5788 probe_ent->port_flags = port->flags;
f6d950e2
BK		 5789 probe_ent->pio_mask = port->pio_mask;
5790 probe_ent->mwdma_mask = port->mwdma_mask;
5791 probe_ent->udma_mask = port->udma_mask;
5792 probe_ent->port_ops = port->port_ops;
d639ca94 5793 probe_ent->private_data = port->private_data;
f6d950e2
BK		 5794
5795 return probe_ent;
5796}
5797
1da177e4
LT		 5798/**
5799 * ata_std_ports - initialize ioaddr with standard port offsets.
5800 * @ioaddr: IO address structure to be initialized
0baab86b
EF		 5801 *
5802 * Utility function which initializes data_addr, error_addr,
5803 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
5804 * device_addr, status_addr, and command_addr to standard offsets
5805 * relative to cmd_addr.
5806 *
5807 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
1da177e4 5808 */
0baab86b 5809
1da177e4
LT		 5810void ata_std_ports(struct ata_ioports *ioaddr)
5811{
5812 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
5813 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
5814 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
5815 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
5816 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
5817 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
5818 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
5819 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
5820 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
5821 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
5822}
5823
0baab86b 5824
374b1873
JG		 5825#ifdef CONFIG_PCI
5826
cca3974e 5827void ata_pci_host_stop (struct ata_host *host)
374b1873 5828{
cca3974e 5829 struct pci_dev *pdev = to_pci_dev(host->dev);
374b1873 5830
cca3974e 5831 pci_iounmap(pdev, host->mmio_base);
374b1873
JG		 5832}
5833
1da177e4
LT		 5834/**
5835 * ata_pci_remove_one - PCI layer callback for device removal
5836 * @pdev: PCI device that was removed
5837 *
5838 * PCI layer indicates to libata via this hook that
6f0ef4fa 5839 * hot-unplug or module unload event has occurred.
1da177e4
LT		 5840 * Handle this by unregistering all objects associated
5841 * with this PCI device. Free those objects. Then finally
5842 * release PCI resources and disable device.
5843 *
5844 * LOCKING:
5845 * Inherited from PCI layer (may sleep).
5846 */
5847
5848void ata_pci_remove_one (struct pci_dev *pdev)
5849{
5850 struct device *dev = pci_dev_to_dev(pdev);
cca3974e 5851 struct ata_host *host = dev_get_drvdata(dev);
1da177e4 5852
cca3974e 5853 ata_host_remove(host);
f0eb62b8 5854
1da177e4
LT		 5855 pci_release_regions(pdev);
5856 pci_disable_device(pdev);
5857 dev_set_drvdata(dev, NULL);
5858}
5859
5860/* move to PCI subsystem */
057ace5e 5861int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits)
1da177e4
LT		 5862{
5863 unsigned long tmp = 0;
5864
5865 switch (bits->width) {
5866 case 1: {
5867 u8 tmp8 = 0;
5868 pci_read_config_byte(pdev, bits->reg, &tmp8);
5869 tmp = tmp8;
5870 break;
5871 }
5872 case 2: {
5873 u16 tmp16 = 0;
5874 pci_read_config_word(pdev, bits->reg, &tmp16);
5875 tmp = tmp16;
5876 break;
5877 }
5878 case 4: {
5879 u32 tmp32 = 0;
5880 pci_read_config_dword(pdev, bits->reg, &tmp32);
5881 tmp = tmp32;
5882 break;
5883 }
5884
5885 default:
5886 return -EINVAL;
5887 }
5888
5889 tmp &= bits->mask;
5890
5891 return (tmp == bits->val) ? 1 : 0;
5892}
9b847548 5893
3c5100c1 5894void ata_pci_device_do_suspend(struct pci_dev *pdev, pm_message_t mesg)
9b847548
JA		 5895{
5896 pci_save_state(pdev);
500530f6 5897
3c5100c1 5898 if (mesg.event == PM_EVENT_SUSPEND) {
500530f6
TH		 5899 pci_disable_device(pdev);
5900 pci_set_power_state(pdev, PCI_D3hot);
5901 }
9b847548
JA		 5902}
5903
500530f6 5904void ata_pci_device_do_resume(struct pci_dev *pdev)
9b847548
JA		 5905{
5906 pci_set_power_state(pdev, PCI_D0);
5907 pci_restore_state(pdev);
5908 pci_enable_device(pdev);
5909 pci_set_master(pdev);
500530f6
TH		 5910}
5911
3c5100c1 5912int ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
500530f6 5913{
cca3974e 5914 struct ata_host *host = dev_get_drvdata(&pdev->dev);
500530f6
TH		 5915 int rc = 0;
5916
cca3974e 5917 rc = ata_host_suspend(host, mesg);
500530f6
TH		 5918 if (rc)
5919 return rc;
5920
3c5100c1 5921 ata_pci_device_do_suspend(pdev, mesg);
500530f6
TH		 5922
5923 return 0;
5924}
5925
5926int ata_pci_device_resume(struct pci_dev *pdev)
5927{
cca3974e 5928 struct ata_host *host = dev_get_drvdata(&pdev->dev);
500530f6
TH		 5929
5930 ata_pci_device_do_resume(pdev);
cca3974e 5931 ata_host_resume(host);
9b847548
JA		 5932 return 0;
5933}
1da177e4
LT		 5934#endif /* CONFIG_PCI */
5935
5936
1da177e4
LT		 5937static int __init ata_init(void)
5938{
a8601e5f 5939 ata_probe_timeout *= HZ;
1da177e4
LT		 5940 ata_wq = create_workqueue("ata");
5941 if (!ata_wq)
5942 return -ENOMEM;
5943
453b07ac
TH		 5944 ata_aux_wq = create_singlethread_workqueue("ata_aux");
5945 if (!ata_aux_wq) {
5946 destroy_workqueue(ata_wq);
5947 return -ENOMEM;
5948 }
5949
1da177e4
LT		 5950 printk(KERN_DEBUG "libata version " DRV_VERSION " loaded.\n");
5951 return 0;
5952}
5953
5954static void __exit ata_exit(void)
5955{
5956 destroy_workqueue(ata_wq);
453b07ac 5957 destroy_workqueue(ata_aux_wq);
1da177e4
LT		 5958}
5959
a4625085 5960subsys_initcall(ata_init);
1da177e4
LT		 5961module_exit(ata_exit);
5962
67846b30 5963static unsigned long ratelimit_time;
34af946a 5964static DEFINE_SPINLOCK(ata_ratelimit_lock);
67846b30
JG		 5965
5966int ata_ratelimit(void)
5967{
5968 int rc;
5969 unsigned long flags;
5970
5971 spin_lock_irqsave(&ata_ratelimit_lock, flags);
5972
5973 if (time_after(jiffies, ratelimit_time)) {
5974 rc = 1;
5975 ratelimit_time = jiffies + (HZ/5);
5976 } else
5977 rc = 0;
5978
5979 spin_unlock_irqrestore(&ata_ratelimit_lock, flags);
5980
5981 return rc;
5982}
5983
c22daff4
TH		 5984/**
5985 * ata_wait_register - wait until register value changes
5986 * @reg: IO-mapped register
5987 * @mask: Mask to apply to read register value
5988 * @val: Wait condition
5989 * @interval_msec: polling interval in milliseconds
5990 * @timeout_msec: timeout in milliseconds
5991 *
5992 * Waiting for some bits of register to change is a common
5993 * operation for ATA controllers. This function reads 32bit LE
5994 * IO-mapped register @reg and tests for the following condition.
5995 *
5996 * (*@reg & mask) != val
5997 *
5998 * If the condition is met, it returns; otherwise, the process is
5999 * repeated after @interval_msec until timeout.
6000 *
6001 * LOCKING:
6002 * Kernel thread context (may sleep)
6003 *
6004 * RETURNS:
6005 * The final register value.
6006 */
6007u32 ata_wait_register(void __iomem *reg, u32 mask, u32 val,
6008 unsigned long interval_msec,
6009 unsigned long timeout_msec)
6010{
6011 unsigned long timeout;
6012 u32 tmp;
6013
6014 tmp = ioread32(reg);
6015
6016 /* Calculate timeout _after_ the first read to make sure
6017 * preceding writes reach the controller before starting to
6018 * eat away the timeout.
6019 */
6020 timeout = jiffies + (timeout_msec * HZ) / 1000;
6021
6022 while ((tmp & mask) == val && time_before(jiffies, timeout)) {
6023 msleep(interval_msec);
6024 tmp = ioread32(reg);
6025 }
6026
6027 return tmp;
6028}
6029
dd5b06c4
TH		 6030/*
6031 * Dummy port_ops
6032 */
6033static void ata_dummy_noret(struct ata_port *ap) { }
6034static int ata_dummy_ret0(struct ata_port *ap) { return 0; }
6035static void ata_dummy_qc_noret(struct ata_queued_cmd *qc) { }
6036
6037static u8 ata_dummy_check_status(struct ata_port *ap)
6038{
6039 return ATA_DRDY;
6040}
6041
6042static unsigned int ata_dummy_qc_issue(struct ata_queued_cmd *qc)
6043{
6044 return AC_ERR_SYSTEM;
6045}
6046
6047const struct ata_port_operations ata_dummy_port_ops = {
6048 .port_disable = ata_port_disable,
6049 .check_status = ata_dummy_check_status,
6050 .check_altstatus = ata_dummy_check_status,
6051 .dev_select = ata_noop_dev_select,
6052 .qc_prep = ata_noop_qc_prep,
6053 .qc_issue = ata_dummy_qc_issue,
6054 .freeze = ata_dummy_noret,
6055 .thaw = ata_dummy_noret,
6056 .error_handler = ata_dummy_noret,
6057 .post_internal_cmd = ata_dummy_qc_noret,
6058 .irq_clear = ata_dummy_noret,
6059 .port_start = ata_dummy_ret0,
6060 .port_stop = ata_dummy_noret,
6061};
6062
1da177e4
LT		 6063/*
6064 * libata is essentially a library of internal helper functions for
6065 * low-level ATA host controller drivers. As such, the API/ABI is
6066 * likely to change as new drivers are added and updated.
6067 * Do not depend on ABI/API stability.
6068 */
6069
e9c83914
TH		 6070EXPORT_SYMBOL_GPL(sata_deb_timing_normal);
6071EXPORT_SYMBOL_GPL(sata_deb_timing_hotplug);
6072EXPORT_SYMBOL_GPL(sata_deb_timing_long);
dd5b06c4 6073EXPORT_SYMBOL_GPL(ata_dummy_port_ops);
1da177e4
LT		 6074EXPORT_SYMBOL_GPL(ata_std_bios_param);
6075EXPORT_SYMBOL_GPL(ata_std_ports);
cca3974e 6076EXPORT_SYMBOL_GPL(ata_host_init);
1da177e4 6077EXPORT_SYMBOL_GPL(ata_device_add);
720ba126 6078EXPORT_SYMBOL_GPL(ata_port_detach);
cca3974e 6079EXPORT_SYMBOL_GPL(ata_host_remove);
1da177e4
LT		 6080EXPORT_SYMBOL_GPL(ata_sg_init);
6081EXPORT_SYMBOL_GPL(ata_sg_init_one);
9a1004d0 6082EXPORT_SYMBOL_GPL(ata_hsm_move);
f686bcb8 6083EXPORT_SYMBOL_GPL(ata_qc_complete);
dedaf2b0 6084EXPORT_SYMBOL_GPL(ata_qc_complete_multiple);
1da177e4 6085EXPORT_SYMBOL_GPL(ata_qc_issue_prot);
1da177e4
LT		 6086EXPORT_SYMBOL_GPL(ata_tf_load);
6087EXPORT_SYMBOL_GPL(ata_tf_read);
6088EXPORT_SYMBOL_GPL(ata_noop_dev_select);
6089EXPORT_SYMBOL_GPL(ata_std_dev_select);
6090EXPORT_SYMBOL_GPL(ata_tf_to_fis);
6091EXPORT_SYMBOL_GPL(ata_tf_from_fis);
6092EXPORT_SYMBOL_GPL(ata_check_status);
6093EXPORT_SYMBOL_GPL(ata_altstatus);
1da177e4
LT		 6094EXPORT_SYMBOL_GPL(ata_exec_command);
6095EXPORT_SYMBOL_GPL(ata_port_start);
6096EXPORT_SYMBOL_GPL(ata_port_stop);
aa8f0dc6 6097EXPORT_SYMBOL_GPL(ata_host_stop);
1da177e4 6098EXPORT_SYMBOL_GPL(ata_interrupt);
a6b2c5d4
AC		 6099EXPORT_SYMBOL_GPL(ata_mmio_data_xfer);
6100EXPORT_SYMBOL_GPL(ata_pio_data_xfer);
75e99585 6101EXPORT_SYMBOL_GPL(ata_pio_data_xfer_noirq);
1da177e4 6102EXPORT_SYMBOL_GPL(ata_qc_prep);
e46834cd 6103EXPORT_SYMBOL_GPL(ata_noop_qc_prep);
1da177e4
LT		 6104EXPORT_SYMBOL_GPL(ata_bmdma_setup);
6105EXPORT_SYMBOL_GPL(ata_bmdma_start);
6106EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
6107EXPORT_SYMBOL_GPL(ata_bmdma_status);
6108EXPORT_SYMBOL_GPL(ata_bmdma_stop);
6d97dbd7
TH		 6109EXPORT_SYMBOL_GPL(ata_bmdma_freeze);
6110EXPORT_SYMBOL_GPL(ata_bmdma_thaw);
6111EXPORT_SYMBOL_GPL(ata_bmdma_drive_eh);
6112EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
6113EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
1da177e4 6114EXPORT_SYMBOL_GPL(ata_port_probe);
3c567b7d 6115EXPORT_SYMBOL_GPL(sata_set_spd);
d7bb4cc7
TH		 6116EXPORT_SYMBOL_GPL(sata_phy_debounce);
6117EXPORT_SYMBOL_GPL(sata_phy_resume);
1da177e4
LT		 6118EXPORT_SYMBOL_GPL(sata_phy_reset);
6119EXPORT_SYMBOL_GPL(__sata_phy_reset);
6120EXPORT_SYMBOL_GPL(ata_bus_reset);
f5914a46 6121EXPORT_SYMBOL_GPL(ata_std_prereset);
c2bd5804
TH		 6122EXPORT_SYMBOL_GPL(ata_std_softreset);
6123EXPORT_SYMBOL_GPL(sata_std_hardreset);
6124EXPORT_SYMBOL_GPL(ata_std_postreset);
2e9edbf8
JG		 6125EXPORT_SYMBOL_GPL(ata_dev_classify);
6126EXPORT_SYMBOL_GPL(ata_dev_pair);
1da177e4 6127EXPORT_SYMBOL_GPL(ata_port_disable);
67846b30 6128EXPORT_SYMBOL_GPL(ata_ratelimit);
c22daff4 6129EXPORT_SYMBOL_GPL(ata_wait_register);
6f8b9958 6130EXPORT_SYMBOL_GPL(ata_busy_sleep);
86e45b6b 6131EXPORT_SYMBOL_GPL(ata_port_queue_task);
1da177e4
LT		 6132EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
6133EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
1da177e4 6134EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
83c47bcb 6135EXPORT_SYMBOL_GPL(ata_scsi_slave_destroy);
a6e6ce8e 6136EXPORT_SYMBOL_GPL(ata_scsi_change_queue_depth);
1da177e4
LT		 6137EXPORT_SYMBOL_GPL(ata_scsi_release);
6138EXPORT_SYMBOL_GPL(ata_host_intr);
34bf2170
TH		 6139EXPORT_SYMBOL_GPL(sata_scr_valid);
6140EXPORT_SYMBOL_GPL(sata_scr_read);
6141EXPORT_SYMBOL_GPL(sata_scr_write);
6142EXPORT_SYMBOL_GPL(sata_scr_write_flush);
6143EXPORT_SYMBOL_GPL(ata_port_online);
6144EXPORT_SYMBOL_GPL(ata_port_offline);
cca3974e
JG		 6145EXPORT_SYMBOL_GPL(ata_host_suspend);
6146EXPORT_SYMBOL_GPL(ata_host_resume);
6a62a04d
TH		 6147EXPORT_SYMBOL_GPL(ata_id_string);
6148EXPORT_SYMBOL_GPL(ata_id_c_string);
1da177e4
LT		 6149EXPORT_SYMBOL_GPL(ata_scsi_simulate);
6150
1bc4ccff 6151EXPORT_SYMBOL_GPL(ata_pio_need_iordy);
452503f9
AC		 6152EXPORT_SYMBOL_GPL(ata_timing_compute);
6153EXPORT_SYMBOL_GPL(ata_timing_merge);
6154
1da177e4
LT		 6155#ifdef CONFIG_PCI
6156EXPORT_SYMBOL_GPL(pci_test_config_bits);
374b1873 6157EXPORT_SYMBOL_GPL(ata_pci_host_stop);
1da177e4
LT		 6158EXPORT_SYMBOL_GPL(ata_pci_init_native_mode);
6159EXPORT_SYMBOL_GPL(ata_pci_init_one);
6160EXPORT_SYMBOL_GPL(ata_pci_remove_one);
500530f6
TH		 6161EXPORT_SYMBOL_GPL(ata_pci_device_do_suspend);
6162EXPORT_SYMBOL_GPL(ata_pci_device_do_resume);
9b847548
JA		 6163EXPORT_SYMBOL_GPL(ata_pci_device_suspend);
6164EXPORT_SYMBOL_GPL(ata_pci_device_resume);
67951ade
AC		 6165EXPORT_SYMBOL_GPL(ata_pci_default_filter);
6166EXPORT_SYMBOL_GPL(ata_pci_clear_simplex);
1da177e4 6167#endif /* CONFIG_PCI */
9b847548 6168
9b847548
JA		 6169EXPORT_SYMBOL_GPL(ata_scsi_device_suspend);
6170EXPORT_SYMBOL_GPL(ata_scsi_device_resume);
ece1d636 6171
ece1d636 6172EXPORT_SYMBOL_GPL(ata_eng_timeout);
7b70fc03
TH		 6173EXPORT_SYMBOL_GPL(ata_port_schedule_eh);
6174EXPORT_SYMBOL_GPL(ata_port_abort);
e3180499
TH		 6175EXPORT_SYMBOL_GPL(ata_port_freeze);
6176EXPORT_SYMBOL_GPL(ata_eh_freeze_port);
6177EXPORT_SYMBOL_GPL(ata_eh_thaw_port);
ece1d636
TH		 6178EXPORT_SYMBOL_GPL(ata_eh_qc_complete);
6179EXPORT_SYMBOL_GPL(ata_eh_qc_retry);
022bdb07 6180EXPORT_SYMBOL_GPL(ata_do_eh);
Linux kernel - Deliverables
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