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Merge branch 'master' into upstream
[deliverable/linux.git] / drivers / ata / libata-core.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * libata-core.c - helper library for ATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2004 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
1da177e4
LT		 33 */
34
1da177e4
LT		 35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/list.h>
40#include <linux/mm.h>
41#include <linux/highmem.h>
42#include <linux/spinlock.h>
43#include <linux/blkdev.h>
44#include <linux/delay.h>
45#include <linux/timer.h>
46#include <linux/interrupt.h>
47#include <linux/completion.h>
48#include <linux/suspend.h>
49#include <linux/workqueue.h>
67846b30 50#include <linux/jiffies.h>
378f058c 51#include <linux/scatterlist.h>
1da177e4 52#include <scsi/scsi.h>
193515d5 53#include <scsi/scsi_cmnd.h>
1da177e4
LT		 54#include <scsi/scsi_host.h>
55#include <linux/libata.h>
56#include <asm/io.h>
57#include <asm/semaphore.h>
58#include <asm/byteorder.h>
59
60#include "libata.h"
61
d7bb4cc7 62/* debounce timing parameters in msecs { interval, duration, timeout } */
e9c83914
TH		 63const unsigned long sata_deb_timing_normal[] = { 5, 100, 2000 };
64const unsigned long sata_deb_timing_hotplug[] = { 25, 500, 2000 };
65const unsigned long sata_deb_timing_long[] = { 100, 2000, 5000 };
d7bb4cc7 66
3373efd8
TH		 67static unsigned int ata_dev_init_params(struct ata_device *dev,
68 u16 heads, u16 sectors);
69static unsigned int ata_dev_set_xfermode(struct ata_device *dev);
70static void ata_dev_xfermask(struct ata_device *dev);
1da177e4
LT		 71
72static unsigned int ata_unique_id = 1;
73static struct workqueue_struct *ata_wq;
74
453b07ac
TH		 75struct workqueue_struct *ata_aux_wq;
76
418dc1f5 77int atapi_enabled = 1;
1623c81e
JG		 78module_param(atapi_enabled, int, 0444);
79MODULE_PARM_DESC(atapi_enabled, "Enable discovery of ATAPI devices (0=off, 1=on)");
80
95de719a
AL		 81int atapi_dmadir = 0;
82module_param(atapi_dmadir, int, 0444);
83MODULE_PARM_DESC(atapi_dmadir, "Enable ATAPI DMADIR bridge support (0=off, 1=on)");
84
c3c013a2
JG		 85int libata_fua = 0;
86module_param_named(fua, libata_fua, int, 0444);
87MODULE_PARM_DESC(fua, "FUA support (0=off, 1=on)");
88
a8601e5f
AM		 89static int ata_probe_timeout = ATA_TMOUT_INTERNAL / HZ;
90module_param(ata_probe_timeout, int, 0444);
91MODULE_PARM_DESC(ata_probe_timeout, "Set ATA probing timeout (seconds)");
92
1da177e4
LT		 93MODULE_AUTHOR("Jeff Garzik");
94MODULE_DESCRIPTION("Library module for ATA devices");
95MODULE_LICENSE("GPL");
96MODULE_VERSION(DRV_VERSION);
97
0baab86b 98
1da177e4
LT		 99/**
100 * ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure
101 * @tf: Taskfile to convert
102 * @fis: Buffer into which data will output
103 * @pmp: Port multiplier port
104 *
105 * Converts a standard ATA taskfile to a Serial ATA
106 * FIS structure (Register - Host to Device).
107 *
108 * LOCKING:
109 * Inherited from caller.
110 */
111
057ace5e 112void ata_tf_to_fis(const struct ata_taskfile *tf, u8 *fis, u8 pmp)
1da177e4
LT		 113{
114 fis[0] = 0x27; /* Register - Host to Device FIS */
115 fis[1] = (pmp & 0xf) | (1 << 7); /* Port multiplier number,
116 bit 7 indicates Command FIS */
117 fis[2] = tf->command;
118 fis[3] = tf->feature;
119
120 fis[4] = tf->lbal;
121 fis[5] = tf->lbam;
122 fis[6] = tf->lbah;
123 fis[7] = tf->device;
124
125 fis[8] = tf->hob_lbal;
126 fis[9] = tf->hob_lbam;
127 fis[10] = tf->hob_lbah;
128 fis[11] = tf->hob_feature;
129
130 fis[12] = tf->nsect;
131 fis[13] = tf->hob_nsect;
132 fis[14] = 0;
133 fis[15] = tf->ctl;
134
135 fis[16] = 0;
136 fis[17] = 0;
137 fis[18] = 0;
138 fis[19] = 0;
139}
140
141/**
142 * ata_tf_from_fis - Convert SATA FIS to ATA taskfile
143 * @fis: Buffer from which data will be input
144 * @tf: Taskfile to output
145 *
e12a1be6 146 * Converts a serial ATA FIS structure to a standard ATA taskfile.
1da177e4
LT		 147 *
148 * LOCKING:
149 * Inherited from caller.
150 */
151
057ace5e 152void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf)
1da177e4
LT		 153{
154 tf->command = fis[2]; /* status */
155 tf->feature = fis[3]; /* error */
156
157 tf->lbal = fis[4];
158 tf->lbam = fis[5];
159 tf->lbah = fis[6];
160 tf->device = fis[7];
161
162 tf->hob_lbal = fis[8];
163 tf->hob_lbam = fis[9];
164 tf->hob_lbah = fis[10];
165
166 tf->nsect = fis[12];
167 tf->hob_nsect = fis[13];
168}
169
8cbd6df1
AL		 170static const u8 ata_rw_cmds[] = {
171 /* pio multi */
172 ATA_CMD_READ_MULTI,
173 ATA_CMD_WRITE_MULTI,
174 ATA_CMD_READ_MULTI_EXT,
175 ATA_CMD_WRITE_MULTI_EXT,
9a3dccc4
TH		 176 0,
177 0,
178 0,
179 ATA_CMD_WRITE_MULTI_FUA_EXT,
8cbd6df1
AL		 180 /* pio */
181 ATA_CMD_PIO_READ,
182 ATA_CMD_PIO_WRITE,
183 ATA_CMD_PIO_READ_EXT,
184 ATA_CMD_PIO_WRITE_EXT,
9a3dccc4
TH		 185 0,
186 0,
187 0,
188 0,
8cbd6df1
AL		 189 /* dma */
190 ATA_CMD_READ,
191 ATA_CMD_WRITE,
192 ATA_CMD_READ_EXT,
9a3dccc4
TH		 193 ATA_CMD_WRITE_EXT,
194 0,
195 0,
196 0,
197 ATA_CMD_WRITE_FUA_EXT
8cbd6df1 198};
1da177e4
LT		 199
200/**
8cbd6df1
AL		 201 * ata_rwcmd_protocol - set taskfile r/w commands and protocol
202 * @qc: command to examine and configure
1da177e4 203 *
2e9edbf8 204 * Examine the device configuration and tf->flags to calculate
8cbd6df1 205 * the proper read/write commands and protocol to use.
1da177e4
LT		 206 *
207 * LOCKING:
208 * caller.
209 */
9a3dccc4 210int ata_rwcmd_protocol(struct ata_queued_cmd *qc)
1da177e4 211{
8cbd6df1
AL		 212 struct ata_taskfile *tf = &qc->tf;
213 struct ata_device *dev = qc->dev;
9a3dccc4 214 u8 cmd;
1da177e4 215
9a3dccc4 216 int index, fua, lba48, write;
2e9edbf8 217
9a3dccc4 218 fua = (tf->flags & ATA_TFLAG_FUA) ? 4 : 0;
8cbd6df1
AL		 219 lba48 = (tf->flags & ATA_TFLAG_LBA48) ? 2 : 0;
220 write = (tf->flags & ATA_TFLAG_WRITE) ? 1 : 0;
1da177e4 221
8cbd6df1
AL		 222 if (dev->flags & ATA_DFLAG_PIO) {
223 tf->protocol = ATA_PROT_PIO;
9a3dccc4 224 index = dev->multi_count ? 0 : 8;
8d238e01
AC		 225 } else if (lba48 && (qc->ap->flags & ATA_FLAG_PIO_LBA48)) {
226 /* Unable to use DMA due to host limitation */
227 tf->protocol = ATA_PROT_PIO;
0565c26d 228 index = dev->multi_count ? 0 : 8;
8cbd6df1
AL		 229 } else {
230 tf->protocol = ATA_PROT_DMA;
9a3dccc4 231 index = 16;
8cbd6df1 232 }
1da177e4 233
9a3dccc4
TH		 234 cmd = ata_rw_cmds[index + fua + lba48 + write];
235 if (cmd) {
236 tf->command = cmd;
237 return 0;
238 }
239 return -1;
1da177e4
LT		 240}
241
cb95d562
TH		 242/**
243 * ata_pack_xfermask - Pack pio, mwdma and udma masks into xfer_mask
244 * @pio_mask: pio_mask
245 * @mwdma_mask: mwdma_mask
246 * @udma_mask: udma_mask
247 *
248 * Pack @pio_mask, @mwdma_mask and @udma_mask into a single
249 * unsigned int xfer_mask.
250 *
251 * LOCKING:
252 * None.
253 *
254 * RETURNS:
255 * Packed xfer_mask.
256 */
257static unsigned int ata_pack_xfermask(unsigned int pio_mask,
258 unsigned int mwdma_mask,
259 unsigned int udma_mask)
260{
261 return ((pio_mask << ATA_SHIFT_PIO) & ATA_MASK_PIO) |
262 ((mwdma_mask << ATA_SHIFT_MWDMA) & ATA_MASK_MWDMA) |
263 ((udma_mask << ATA_SHIFT_UDMA) & ATA_MASK_UDMA);
264}
265
c0489e4e
TH		 266/**
267 * ata_unpack_xfermask - Unpack xfer_mask into pio, mwdma and udma masks
268 * @xfer_mask: xfer_mask to unpack
269 * @pio_mask: resulting pio_mask
270 * @mwdma_mask: resulting mwdma_mask
271 * @udma_mask: resulting udma_mask
272 *
273 * Unpack @xfer_mask into @pio_mask, @mwdma_mask and @udma_mask.
274 * Any NULL distination masks will be ignored.
275 */
276static void ata_unpack_xfermask(unsigned int xfer_mask,
277 unsigned int *pio_mask,
278 unsigned int *mwdma_mask,
279 unsigned int *udma_mask)
280{
281 if (pio_mask)
282 *pio_mask = (xfer_mask & ATA_MASK_PIO) >> ATA_SHIFT_PIO;
283 if (mwdma_mask)
284 *mwdma_mask = (xfer_mask & ATA_MASK_MWDMA) >> ATA_SHIFT_MWDMA;
285 if (udma_mask)
286 *udma_mask = (xfer_mask & ATA_MASK_UDMA) >> ATA_SHIFT_UDMA;
287}
288
cb95d562 289static const struct ata_xfer_ent {
be9a50c8 290 int shift, bits;
cb95d562
TH		 291 u8 base;
292} ata_xfer_tbl[] = {
293 { ATA_SHIFT_PIO, ATA_BITS_PIO, XFER_PIO_0 },
294 { ATA_SHIFT_MWDMA, ATA_BITS_MWDMA, XFER_MW_DMA_0 },
295 { ATA_SHIFT_UDMA, ATA_BITS_UDMA, XFER_UDMA_0 },
296 { -1, },
297};
298
299/**
300 * ata_xfer_mask2mode - Find matching XFER_* for the given xfer_mask
301 * @xfer_mask: xfer_mask of interest
302 *
303 * Return matching XFER_* value for @xfer_mask. Only the highest
304 * bit of @xfer_mask is considered.
305 *
306 * LOCKING:
307 * None.
308 *
309 * RETURNS:
310 * Matching XFER_* value, 0 if no match found.
311 */
312static u8 ata_xfer_mask2mode(unsigned int xfer_mask)
313{
314 int highbit = fls(xfer_mask) - 1;
315 const struct ata_xfer_ent *ent;
316
317 for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
318 if (highbit >= ent->shift && highbit < ent->shift + ent->bits)
319 return ent->base + highbit - ent->shift;
320 return 0;
321}
322
323/**
324 * ata_xfer_mode2mask - Find matching xfer_mask for XFER_*
325 * @xfer_mode: XFER_* of interest
326 *
327 * Return matching xfer_mask for @xfer_mode.
328 *
329 * LOCKING:
330 * None.
331 *
332 * RETURNS:
333 * Matching xfer_mask, 0 if no match found.
334 */
335static unsigned int ata_xfer_mode2mask(u8 xfer_mode)
336{
337 const struct ata_xfer_ent *ent;
338
339 for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
340 if (xfer_mode >= ent->base && xfer_mode < ent->base + ent->bits)
341 return 1 << (ent->shift + xfer_mode - ent->base);
342 return 0;
343}
344
345/**
346 * ata_xfer_mode2shift - Find matching xfer_shift for XFER_*
347 * @xfer_mode: XFER_* of interest
348 *
349 * Return matching xfer_shift for @xfer_mode.
350 *
351 * LOCKING:
352 * None.
353 *
354 * RETURNS:
355 * Matching xfer_shift, -1 if no match found.
356 */
357static int ata_xfer_mode2shift(unsigned int xfer_mode)
358{
359 const struct ata_xfer_ent *ent;
360
361 for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
362 if (xfer_mode >= ent->base && xfer_mode < ent->base + ent->bits)
363 return ent->shift;
364 return -1;
365}
366
1da177e4 367/**
1da7b0d0
TH		 368 * ata_mode_string - convert xfer_mask to string
369 * @xfer_mask: mask of bits supported; only highest bit counts.
1da177e4
LT		 370 *
371 * Determine string which represents the highest speed
1da7b0d0 372 * (highest bit in @modemask).
1da177e4
LT		 373 *
374 * LOCKING:
375 * None.
376 *
377 * RETURNS:
378 * Constant C string representing highest speed listed in
1da7b0d0 379 * @mode_mask, or the constant C string "<n/a>".
1da177e4 380 */
1da7b0d0 381static const char *ata_mode_string(unsigned int xfer_mask)
1da177e4 382{
75f554bc
TH		 383 static const char * const xfer_mode_str[] = {
384 "PIO0",
385 "PIO1",
386 "PIO2",
387 "PIO3",
388 "PIO4",
b352e57d
AC		 389 "PIO5",
390 "PIO6",
75f554bc
TH		 391 "MWDMA0",
392 "MWDMA1",
393 "MWDMA2",
b352e57d
AC		 394 "MWDMA3",
395 "MWDMA4",
75f554bc
TH		 396 "UDMA/16",
397 "UDMA/25",
398 "UDMA/33",
399 "UDMA/44",
400 "UDMA/66",
401 "UDMA/100",
402 "UDMA/133",
403 "UDMA7",
404 };
1da7b0d0 405 int highbit;
1da177e4 406
1da7b0d0
TH		 407 highbit = fls(xfer_mask) - 1;
408 if (highbit >= 0 && highbit < ARRAY_SIZE(xfer_mode_str))
409 return xfer_mode_str[highbit];
1da177e4 410 return "<n/a>";
1da177e4
LT		 411}
412
4c360c81
TH		 413static const char *sata_spd_string(unsigned int spd)
414{
415 static const char * const spd_str[] = {
416 "1.5 Gbps",
417 "3.0 Gbps",
418 };
419
420 if (spd == 0 || (spd - 1) >= ARRAY_SIZE(spd_str))
421 return "<unknown>";
422 return spd_str[spd - 1];
423}
424
3373efd8 425void ata_dev_disable(struct ata_device *dev)
0b8efb0a 426{
0dd4b21f 427 if (ata_dev_enabled(dev) && ata_msg_drv(dev->ap)) {
f15a1daf 428 ata_dev_printk(dev, KERN_WARNING, "disabled\n");
0b8efb0a
TH		 429 dev->class++;
430 }
431}
432
1da177e4
LT		 433/**
434 * ata_pio_devchk - PATA device presence detection
435 * @ap: ATA channel to examine
436 * @device: Device to examine (starting at zero)
437 *
438 * This technique was originally described in
439 * Hale Landis's ATADRVR (www.ata-atapi.com), and
440 * later found its way into the ATA/ATAPI spec.
441 *
442 * Write a pattern to the ATA shadow registers,
443 * and if a device is present, it will respond by
444 * correctly storing and echoing back the
445 * ATA shadow register contents.
446 *
447 * LOCKING:
448 * caller.
449 */
450
451static unsigned int ata_pio_devchk(struct ata_port *ap,
452 unsigned int device)
453{
454 struct ata_ioports *ioaddr = &ap->ioaddr;
455 u8 nsect, lbal;
456
457 ap->ops->dev_select(ap, device);
458
459 outb(0x55, ioaddr->nsect_addr);
460 outb(0xaa, ioaddr->lbal_addr);
461
462 outb(0xaa, ioaddr->nsect_addr);
463 outb(0x55, ioaddr->lbal_addr);
464
465 outb(0x55, ioaddr->nsect_addr);
466 outb(0xaa, ioaddr->lbal_addr);
467
468 nsect = inb(ioaddr->nsect_addr);
469 lbal = inb(ioaddr->lbal_addr);
470
471 if ((nsect == 0x55) && (lbal == 0xaa))
472 return 1; /* we found a device */
473
474 return 0; /* nothing found */
475}
476
477/**
478 * ata_mmio_devchk - PATA device presence detection
479 * @ap: ATA channel to examine
480 * @device: Device to examine (starting at zero)
481 *
482 * This technique was originally described in
483 * Hale Landis's ATADRVR (www.ata-atapi.com), and
484 * later found its way into the ATA/ATAPI spec.
485 *
486 * Write a pattern to the ATA shadow registers,
487 * and if a device is present, it will respond by
488 * correctly storing and echoing back the
489 * ATA shadow register contents.
490 *
491 * LOCKING:
492 * caller.
493 */
494
495static unsigned int ata_mmio_devchk(struct ata_port *ap,
496 unsigned int device)
497{
498 struct ata_ioports *ioaddr = &ap->ioaddr;
499 u8 nsect, lbal;
500
501 ap->ops->dev_select(ap, device);
502
503 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
504 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
505
506 writeb(0xaa, (void __iomem *) ioaddr->nsect_addr);
507 writeb(0x55, (void __iomem *) ioaddr->lbal_addr);
508
509 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
510 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
511
512 nsect = readb((void __iomem *) ioaddr->nsect_addr);
513 lbal = readb((void __iomem *) ioaddr->lbal_addr);
514
515 if ((nsect == 0x55) && (lbal == 0xaa))
516 return 1; /* we found a device */
517
518 return 0; /* nothing found */
519}
520
521/**
522 * ata_devchk - PATA device presence detection
523 * @ap: ATA channel to examine
524 * @device: Device to examine (starting at zero)
525 *
526 * Dispatch ATA device presence detection, depending
527 * on whether we are using PIO or MMIO to talk to the
528 * ATA shadow registers.
529 *
530 * LOCKING:
531 * caller.
532 */
533
534static unsigned int ata_devchk(struct ata_port *ap,
535 unsigned int device)
536{
537 if (ap->flags & ATA_FLAG_MMIO)
538 return ata_mmio_devchk(ap, device);
539 return ata_pio_devchk(ap, device);
540}
541
542/**
543 * ata_dev_classify - determine device type based on ATA-spec signature
544 * @tf: ATA taskfile register set for device to be identified
545 *
546 * Determine from taskfile register contents whether a device is
547 * ATA or ATAPI, as per "Signature and persistence" section
548 * of ATA/PI spec (volume 1, sect 5.14).
549 *
550 * LOCKING:
551 * None.
552 *
553 * RETURNS:
554 * Device type, %ATA_DEV_ATA, %ATA_DEV_ATAPI, or %ATA_DEV_UNKNOWN
555 * the event of failure.
556 */
557
057ace5e 558unsigned int ata_dev_classify(const struct ata_taskfile *tf)
1da177e4
LT		 559{
560 /* Apple's open source Darwin code hints that some devices only
561 * put a proper signature into the LBA mid/high registers,
562 * So, we only check those. It's sufficient for uniqueness.
563 */
564
565 if (((tf->lbam == 0) && (tf->lbah == 0)) ||
566 ((tf->lbam == 0x3c) && (tf->lbah == 0xc3))) {
567 DPRINTK("found ATA device by sig\n");
568 return ATA_DEV_ATA;
569 }
570
571 if (((tf->lbam == 0x14) && (tf->lbah == 0xeb)) ||
572 ((tf->lbam == 0x69) && (tf->lbah == 0x96))) {
573 DPRINTK("found ATAPI device by sig\n");
574 return ATA_DEV_ATAPI;
575 }
576
577 DPRINTK("unknown device\n");
578 return ATA_DEV_UNKNOWN;
579}
580
581/**
582 * ata_dev_try_classify - Parse returned ATA device signature
583 * @ap: ATA channel to examine
584 * @device: Device to examine (starting at zero)
b4dc7623 585 * @r_err: Value of error register on completion
1da177e4
LT		 586 *
587 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
588 * an ATA/ATAPI-defined set of values is placed in the ATA
589 * shadow registers, indicating the results of device detection
590 * and diagnostics.
591 *
592 * Select the ATA device, and read the values from the ATA shadow
593 * registers. Then parse according to the Error register value,
594 * and the spec-defined values examined by ata_dev_classify().
595 *
596 * LOCKING:
597 * caller.
b4dc7623
TH		 598 *
599 * RETURNS:
600 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1da177e4
LT		 601 */
602
b4dc7623
TH		 603static unsigned int
604ata_dev_try_classify(struct ata_port *ap, unsigned int device, u8 *r_err)
1da177e4 605{
1da177e4
LT		 606 struct ata_taskfile tf;
607 unsigned int class;
608 u8 err;
609
610 ap->ops->dev_select(ap, device);
611
612 memset(&tf, 0, sizeof(tf));
613
1da177e4 614 ap->ops->tf_read(ap, &tf);
0169e284 615 err = tf.feature;
b4dc7623
TH		 616 if (r_err)
617 *r_err = err;
1da177e4
LT		 618
619 /* see if device passed diags */
620 if (err == 1)
621 /* do nothing */ ;
622 else if ((device == 0) && (err == 0x81))
623 /* do nothing */ ;
624 else
b4dc7623 625 return ATA_DEV_NONE;
1da177e4 626
b4dc7623 627 /* determine if device is ATA or ATAPI */
1da177e4 628 class = ata_dev_classify(&tf);
b4dc7623 629
1da177e4 630 if (class == ATA_DEV_UNKNOWN)
b4dc7623 631 return ATA_DEV_NONE;
1da177e4 632 if ((class == ATA_DEV_ATA) && (ata_chk_status(ap) == 0))
b4dc7623
TH		 633 return ATA_DEV_NONE;
634 return class;
1da177e4
LT		 635}
636
637/**
6a62a04d 638 * ata_id_string - Convert IDENTIFY DEVICE page into string
1da177e4
LT		 639 * @id: IDENTIFY DEVICE results we will examine
640 * @s: string into which data is output
641 * @ofs: offset into identify device page
642 * @len: length of string to return. must be an even number.
643 *
644 * The strings in the IDENTIFY DEVICE page are broken up into
645 * 16-bit chunks. Run through the string, and output each
646 * 8-bit chunk linearly, regardless of platform.
647 *
648 * LOCKING:
649 * caller.
650 */
651
6a62a04d
TH		 652void ata_id_string(const u16 *id, unsigned char *s,
653 unsigned int ofs, unsigned int len)
1da177e4
LT		 654{
655 unsigned int c;
656
657 while (len > 0) {
658 c = id[ofs] >> 8;
659 *s = c;
660 s++;
661
662 c = id[ofs] & 0xff;
663 *s = c;
664 s++;
665
666 ofs++;
667 len -= 2;
668 }
669}
670
0e949ff3 671/**
6a62a04d 672 * ata_id_c_string - Convert IDENTIFY DEVICE page into C string
0e949ff3
TH		 673 * @id: IDENTIFY DEVICE results we will examine
674 * @s: string into which data is output
675 * @ofs: offset into identify device page
676 * @len: length of string to return. must be an odd number.
677 *
6a62a04d 678 * This function is identical to ata_id_string except that it
0e949ff3
TH		 679 * trims trailing spaces and terminates the resulting string with
680 * null. @len must be actual maximum length (even number) + 1.
681 *
682 * LOCKING:
683 * caller.
684 */
6a62a04d
TH		 685void ata_id_c_string(const u16 *id, unsigned char *s,
686 unsigned int ofs, unsigned int len)
0e949ff3
TH		 687{
688 unsigned char *p;
689
690 WARN_ON(!(len & 1));
691
6a62a04d 692 ata_id_string(id, s, ofs, len - 1);
0e949ff3
TH		 693
694 p = s + strnlen(s, len - 1);
695 while (p > s && p[-1] == ' ')
696 p--;
697 *p = '\0';
698}
0baab86b 699
2940740b
TH		 700static u64 ata_id_n_sectors(const u16 *id)
701{
702 if (ata_id_has_lba(id)) {
703 if (ata_id_has_lba48(id))
704 return ata_id_u64(id, 100);
705 else
706 return ata_id_u32(id, 60);
707 } else {
708 if (ata_id_current_chs_valid(id))
709 return ata_id_u32(id, 57);
710 else
711 return id[1] * id[3] * id[6];
712 }
713}
714
0baab86b
EF		 715/**
716 * ata_noop_dev_select - Select device 0/1 on ATA bus
717 * @ap: ATA channel to manipulate
718 * @device: ATA device (numbered from zero) to select
719 *
720 * This function performs no actual function.
721 *
722 * May be used as the dev_select() entry in ata_port_operations.
723 *
724 * LOCKING:
725 * caller.
726 */
1da177e4
LT		 727void ata_noop_dev_select (struct ata_port *ap, unsigned int device)
728{
729}
730
0baab86b 731
1da177e4
LT		 732/**
733 * ata_std_dev_select - Select device 0/1 on ATA bus
734 * @ap: ATA channel to manipulate
735 * @device: ATA device (numbered from zero) to select
736 *
737 * Use the method defined in the ATA specification to
738 * make either device 0, or device 1, active on the
0baab86b
EF		 739 * ATA channel. Works with both PIO and MMIO.
740 *
741 * May be used as the dev_select() entry in ata_port_operations.
1da177e4
LT		 742 *
743 * LOCKING:
744 * caller.
745 */
746
747void ata_std_dev_select (struct ata_port *ap, unsigned int device)
748{
749 u8 tmp;
750
751 if (device == 0)
752 tmp = ATA_DEVICE_OBS;
753 else
754 tmp = ATA_DEVICE_OBS | ATA_DEV1;
755
756 if (ap->flags & ATA_FLAG_MMIO) {
757 writeb(tmp, (void __iomem *) ap->ioaddr.device_addr);
758 } else {
759 outb(tmp, ap->ioaddr.device_addr);
760 }
761 ata_pause(ap); /* needed; also flushes, for mmio */
762}
763
764/**
765 * ata_dev_select - Select device 0/1 on ATA bus
766 * @ap: ATA channel to manipulate
767 * @device: ATA device (numbered from zero) to select
768 * @wait: non-zero to wait for Status register BSY bit to clear
769 * @can_sleep: non-zero if context allows sleeping
770 *
771 * Use the method defined in the ATA specification to
772 * make either device 0, or device 1, active on the
773 * ATA channel.
774 *
775 * This is a high-level version of ata_std_dev_select(),
776 * which additionally provides the services of inserting
777 * the proper pauses and status polling, where needed.
778 *
779 * LOCKING:
780 * caller.
781 */
782
783void ata_dev_select(struct ata_port *ap, unsigned int device,
784 unsigned int wait, unsigned int can_sleep)
785{
88574551 786 if (ata_msg_probe(ap))
0dd4b21f 787 ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, ata%u: "
88574551 788 "device %u, wait %u\n", ap->id, device, wait);
1da177e4
LT		 789
790 if (wait)
791 ata_wait_idle(ap);
792
793 ap->ops->dev_select(ap, device);
794
795 if (wait) {
796 if (can_sleep && ap->device[device].class == ATA_DEV_ATAPI)
797 msleep(150);
798 ata_wait_idle(ap);
799 }
800}
801
802/**
803 * ata_dump_id - IDENTIFY DEVICE info debugging output
0bd3300a 804 * @id: IDENTIFY DEVICE page to dump
1da177e4 805 *
0bd3300a
TH		 806 * Dump selected 16-bit words from the given IDENTIFY DEVICE
807 * page.
1da177e4
LT		 808 *
809 * LOCKING:
810 * caller.
811 */
812
0bd3300a 813static inline void ata_dump_id(const u16 *id)
1da177e4
LT		 814{
815 DPRINTK("49==0x%04x "
816 "53==0x%04x "
817 "63==0x%04x "
818 "64==0x%04x "
819 "75==0x%04x \n",
0bd3300a
TH		 820 id[49],
821 id[53],
822 id[63],
823 id[64],
824 id[75]);
1da177e4
LT		 825 DPRINTK("80==0x%04x "
826 "81==0x%04x "
827 "82==0x%04x "
828 "83==0x%04x "
829 "84==0x%04x \n",
0bd3300a
TH		 830 id[80],
831 id[81],
832 id[82],
833 id[83],
834 id[84]);
1da177e4
LT		 835 DPRINTK("88==0x%04x "
836 "93==0x%04x\n",
0bd3300a
TH		 837 id[88],
838 id[93]);
1da177e4
LT		 839}
840
cb95d562
TH		 841/**
842 * ata_id_xfermask - Compute xfermask from the given IDENTIFY data
843 * @id: IDENTIFY data to compute xfer mask from
844 *
845 * Compute the xfermask for this device. This is not as trivial
846 * as it seems if we must consider early devices correctly.
847 *
848 * FIXME: pre IDE drive timing (do we care ?).
849 *
850 * LOCKING:
851 * None.
852 *
853 * RETURNS:
854 * Computed xfermask
855 */
856static unsigned int ata_id_xfermask(const u16 *id)
857{
858 unsigned int pio_mask, mwdma_mask, udma_mask;
859
860 /* Usual case. Word 53 indicates word 64 is valid */
861 if (id[ATA_ID_FIELD_VALID] & (1 << 1)) {
862 pio_mask = id[ATA_ID_PIO_MODES] & 0x03;
863 pio_mask <<= 3;
864 pio_mask |= 0x7;
865 } else {
866 /* If word 64 isn't valid then Word 51 high byte holds
867 * the PIO timing number for the maximum. Turn it into
868 * a mask.
869 */
870 pio_mask = (2 << (id[ATA_ID_OLD_PIO_MODES] & 0xFF)) - 1 ;
871
872 /* But wait.. there's more. Design your standards by
873 * committee and you too can get a free iordy field to
874 * process. However its the speeds not the modes that
875 * are supported... Note drivers using the timing API
876 * will get this right anyway
877 */
878 }
879
880 mwdma_mask = id[ATA_ID_MWDMA_MODES] & 0x07;
fb21f0d0 881
b352e57d
AC		 882 if (ata_id_is_cfa(id)) {
883 /*
884 * Process compact flash extended modes
885 */
886 int pio = id[163] & 0x7;
887 int dma = (id[163] >> 3) & 7;
888
889 if (pio)
890 pio_mask |= (1 << 5);
891 if (pio > 1)
892 pio_mask |= (1 << 6);
893 if (dma)
894 mwdma_mask |= (1 << 3);
895 if (dma > 1)
896 mwdma_mask |= (1 << 4);
897 }
898
fb21f0d0
TH		 899 udma_mask = 0;
900 if (id[ATA_ID_FIELD_VALID] & (1 << 2))
901 udma_mask = id[ATA_ID_UDMA_MODES] & 0xff;
cb95d562
TH		 902
903 return ata_pack_xfermask(pio_mask, mwdma_mask, udma_mask);
904}
905
86e45b6b
TH		 906/**
907 * ata_port_queue_task - Queue port_task
908 * @ap: The ata_port to queue port_task for
e2a7f77a
RD		 909 * @fn: workqueue function to be scheduled
910 * @data: data value to pass to workqueue function
911 * @delay: delay time for workqueue function
86e45b6b
TH		 912 *
913 * Schedule @fn(@data) for execution after @delay jiffies using
914 * port_task. There is one port_task per port and it's the
915 * user(low level driver)'s responsibility to make sure that only
916 * one task is active at any given time.
917 *
918 * libata core layer takes care of synchronization between
919 * port_task and EH. ata_port_queue_task() may be ignored for EH
920 * synchronization.
921 *
922 * LOCKING:
923 * Inherited from caller.
924 */
925void ata_port_queue_task(struct ata_port *ap, void (*fn)(void *), void *data,
926 unsigned long delay)
927{
928 int rc;
929
b51e9e5d 930 if (ap->pflags & ATA_PFLAG_FLUSH_PORT_TASK)
86e45b6b
TH		 931 return;
932
933 PREPARE_WORK(&ap->port_task, fn, data);
934
935 if (!delay)
936 rc = queue_work(ata_wq, &ap->port_task);
937 else
938 rc = queue_delayed_work(ata_wq, &ap->port_task, delay);
939
940 /* rc == 0 means that another user is using port task */
941 WARN_ON(rc == 0);
942}
943
944/**
945 * ata_port_flush_task - Flush port_task
946 * @ap: The ata_port to flush port_task for
947 *
948 * After this function completes, port_task is guranteed not to
949 * be running or scheduled.
950 *
951 * LOCKING:
952 * Kernel thread context (may sleep)
953 */
954void ata_port_flush_task(struct ata_port *ap)
955{
956 unsigned long flags;
957
958 DPRINTK("ENTER\n");
959
ba6a1308 960 spin_lock_irqsave(ap->lock, flags);
b51e9e5d 961 ap->pflags |= ATA_PFLAG_FLUSH_PORT_TASK;
ba6a1308 962 spin_unlock_irqrestore(ap->lock, flags);
86e45b6b
TH		 963
964 DPRINTK("flush #1\n");
965 flush_workqueue(ata_wq);
966
967 /*
968 * At this point, if a task is running, it's guaranteed to see
969 * the FLUSH flag; thus, it will never queue pio tasks again.
970 * Cancel and flush.
971 */
972 if (!cancel_delayed_work(&ap->port_task)) {
0dd4b21f 973 if (ata_msg_ctl(ap))
88574551
TH		 974 ata_port_printk(ap, KERN_DEBUG, "%s: flush #2\n",
975 __FUNCTION__);
86e45b6b
TH		 976 flush_workqueue(ata_wq);
977 }
978
ba6a1308 979 spin_lock_irqsave(ap->lock, flags);
b51e9e5d 980 ap->pflags &= ~ATA_PFLAG_FLUSH_PORT_TASK;
ba6a1308 981 spin_unlock_irqrestore(ap->lock, flags);
86e45b6b 982
0dd4b21f
BP		 983 if (ata_msg_ctl(ap))
984 ata_port_printk(ap, KERN_DEBUG, "%s: EXIT\n", __FUNCTION__);
86e45b6b
TH		 985}
986
77853bf2 987void ata_qc_complete_internal(struct ata_queued_cmd *qc)
a2a7a662 988{
77853bf2 989 struct completion *waiting = qc->private_data;
a2a7a662 990
a2a7a662 991 complete(waiting);
a2a7a662
TH		 992}
993
994/**
995 * ata_exec_internal - execute libata internal command
a2a7a662
TH		 996 * @dev: Device to which the command is sent
997 * @tf: Taskfile registers for the command and the result
d69cf37d 998 * @cdb: CDB for packet command
a2a7a662
TH		 999 * @dma_dir: Data tranfer direction of the command
1000 * @buf: Data buffer of the command
1001 * @buflen: Length of data buffer
1002 *
1003 * Executes libata internal command with timeout. @tf contains
1004 * command on entry and result on return. Timeout and error
1005 * conditions are reported via return value. No recovery action
1006 * is taken after a command times out. It's caller's duty to
1007 * clean up after timeout.
1008 *
1009 * LOCKING:
1010 * None. Should be called with kernel context, might sleep.
551e8889
TH		 1011 *
1012 * RETURNS:
1013 * Zero on success, AC_ERR_* mask on failure
a2a7a662 1014 */
3373efd8 1015unsigned ata_exec_internal(struct ata_device *dev,
1ad8e7f9
TH		 1016 struct ata_taskfile *tf, const u8 *cdb,
1017 int dma_dir, void *buf, unsigned int buflen)
a2a7a662 1018{
3373efd8 1019 struct ata_port *ap = dev->ap;
a2a7a662
TH		 1020 u8 command = tf->command;
1021 struct ata_queued_cmd *qc;
2ab7db1f 1022 unsigned int tag, preempted_tag;
dedaf2b0 1023 u32 preempted_sactive, preempted_qc_active;
60be6b9a 1024 DECLARE_COMPLETION_ONSTACK(wait);
a2a7a662 1025 unsigned long flags;
77853bf2 1026 unsigned int err_mask;
d95a717f 1027 int rc;
a2a7a662 1028
ba6a1308 1029 spin_lock_irqsave(ap->lock, flags);
a2a7a662 1030
e3180499 1031 /* no internal command while frozen */
b51e9e5d 1032 if (ap->pflags & ATA_PFLAG_FROZEN) {
ba6a1308 1033 spin_unlock_irqrestore(ap->lock, flags);
e3180499
TH		 1034 return AC_ERR_SYSTEM;
1035 }
1036
2ab7db1f 1037 /* initialize internal qc */
a2a7a662 1038
2ab7db1f
TH		 1039 /* XXX: Tag 0 is used for drivers with legacy EH as some
1040 * drivers choke if any other tag is given. This breaks
1041 * ata_tag_internal() test for those drivers. Don't use new
1042 * EH stuff without converting to it.
1043 */
1044 if (ap->ops->error_handler)
1045 tag = ATA_TAG_INTERNAL;
1046 else
1047 tag = 0;
1048
6cec4a39 1049 if (test_and_set_bit(tag, &ap->qc_allocated))
2ab7db1f 1050 BUG();
f69499f4 1051 qc = __ata_qc_from_tag(ap, tag);
2ab7db1f
TH		 1052
1053 qc->tag = tag;
1054 qc->scsicmd = NULL;
1055 qc->ap = ap;
1056 qc->dev = dev;
1057 ata_qc_reinit(qc);
1058
1059 preempted_tag = ap->active_tag;
dedaf2b0
TH		 1060 preempted_sactive = ap->sactive;
1061 preempted_qc_active = ap->qc_active;
2ab7db1f 1062 ap->active_tag = ATA_TAG_POISON;
dedaf2b0
TH		 1063 ap->sactive = 0;
1064 ap->qc_active = 0;
2ab7db1f
TH		 1065
1066 /* prepare & issue qc */
a2a7a662 1067 qc->tf = *tf;
d69cf37d
TH		 1068 if (cdb)
1069 memcpy(qc->cdb, cdb, ATAPI_CDB_LEN);
e61e0672 1070 qc->flags |= ATA_QCFLAG_RESULT_TF;
a2a7a662
TH		 1071 qc->dma_dir = dma_dir;
1072 if (dma_dir != DMA_NONE) {
1073 ata_sg_init_one(qc, buf, buflen);
1074 qc->nsect = buflen / ATA_SECT_SIZE;
1075 }
1076
77853bf2 1077 qc->private_data = &wait;
a2a7a662
TH		 1078 qc->complete_fn = ata_qc_complete_internal;
1079
8e0e694a 1080 ata_qc_issue(qc);
a2a7a662 1081
ba6a1308 1082 spin_unlock_irqrestore(ap->lock, flags);
a2a7a662 1083
a8601e5f 1084 rc = wait_for_completion_timeout(&wait, ata_probe_timeout);
d95a717f
TH		 1085
1086 ata_port_flush_task(ap);
41ade50c 1087
d95a717f 1088 if (!rc) {
ba6a1308 1089 spin_lock_irqsave(ap->lock, flags);
a2a7a662
TH		 1090
1091 /* We're racing with irq here. If we lose, the
1092 * following test prevents us from completing the qc
d95a717f
TH		 1093 * twice. If we win, the port is frozen and will be
1094 * cleaned up by ->post_internal_cmd().
a2a7a662 1095 */
77853bf2 1096 if (qc->flags & ATA_QCFLAG_ACTIVE) {
d95a717f
TH		 1097 qc->err_mask |= AC_ERR_TIMEOUT;
1098
1099 if (ap->ops->error_handler)
1100 ata_port_freeze(ap);
1101 else
1102 ata_qc_complete(qc);
f15a1daf 1103
0dd4b21f
BP		 1104 if (ata_msg_warn(ap))
1105 ata_dev_printk(dev, KERN_WARNING,
88574551 1106 "qc timeout (cmd 0x%x)\n", command);
a2a7a662
TH		 1107 }
1108
ba6a1308 1109 spin_unlock_irqrestore(ap->lock, flags);
a2a7a662
TH		 1110 }
1111
d95a717f
TH		 1112 /* do post_internal_cmd */
1113 if (ap->ops->post_internal_cmd)
1114 ap->ops->post_internal_cmd(qc);
1115
1116 if (qc->flags & ATA_QCFLAG_FAILED && !qc->err_mask) {
0dd4b21f 1117 if (ata_msg_warn(ap))
88574551 1118 ata_dev_printk(dev, KERN_WARNING,
0dd4b21f 1119 "zero err_mask for failed "
88574551 1120 "internal command, assuming AC_ERR_OTHER\n");
d95a717f
TH		 1121 qc->err_mask |= AC_ERR_OTHER;
1122 }
1123
15869303 1124 /* finish up */
ba6a1308 1125 spin_lock_irqsave(ap->lock, flags);
15869303 1126
e61e0672 1127 *tf = qc->result_tf;
77853bf2
TH		 1128 err_mask = qc->err_mask;
1129
1130 ata_qc_free(qc);
2ab7db1f 1131 ap->active_tag = preempted_tag;
dedaf2b0
TH		 1132 ap->sactive = preempted_sactive;
1133 ap->qc_active = preempted_qc_active;
77853bf2 1134
1f7dd3e9
TH		 1135 /* XXX - Some LLDDs (sata_mv) disable port on command failure.
1136 * Until those drivers are fixed, we detect the condition
1137 * here, fail the command with AC_ERR_SYSTEM and reenable the
1138 * port.
1139 *
1140 * Note that this doesn't change any behavior as internal
1141 * command failure results in disabling the device in the
1142 * higher layer for LLDDs without new reset/EH callbacks.
1143 *
1144 * Kill the following code as soon as those drivers are fixed.
1145 */
198e0fed 1146 if (ap->flags & ATA_FLAG_DISABLED) {
1f7dd3e9
TH		 1147 err_mask |= AC_ERR_SYSTEM;
1148 ata_port_probe(ap);
1149 }
1150
ba6a1308 1151 spin_unlock_irqrestore(ap->lock, flags);
15869303 1152
77853bf2 1153 return err_mask;
a2a7a662
TH		 1154}
1155
977e6b9f
TH		 1156/**
1157 * ata_do_simple_cmd - execute simple internal command
1158 * @dev: Device to which the command is sent
1159 * @cmd: Opcode to execute
1160 *
1161 * Execute a 'simple' command, that only consists of the opcode
1162 * 'cmd' itself, without filling any other registers
1163 *
1164 * LOCKING:
1165 * Kernel thread context (may sleep).
1166 *
1167 * RETURNS:
1168 * Zero on success, AC_ERR_* mask on failure
e58eb583 1169 */
77b08fb5 1170unsigned int ata_do_simple_cmd(struct ata_device *dev, u8 cmd)
e58eb583
TH		 1171{
1172 struct ata_taskfile tf;
e58eb583
TH		 1173
1174 ata_tf_init(dev, &tf);
1175
1176 tf.command = cmd;
1177 tf.flags |= ATA_TFLAG_DEVICE;
1178 tf.protocol = ATA_PROT_NODATA;
1179
977e6b9f 1180 return ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0);
e58eb583
TH		 1181}
1182
1bc4ccff
AC		 1183/**
1184 * ata_pio_need_iordy - check if iordy needed
1185 * @adev: ATA device
1186 *
1187 * Check if the current speed of the device requires IORDY. Used
1188 * by various controllers for chip configuration.
1189 */
1190
1191unsigned int ata_pio_need_iordy(const struct ata_device *adev)
1192{
1193 int pio;
1194 int speed = adev->pio_mode - XFER_PIO_0;
1195
1196 if (speed < 2)
1197 return 0;
1198 if (speed > 2)
1199 return 1;
2e9edbf8 1200
1bc4ccff
AC		 1201 /* If we have no drive specific rule, then PIO 2 is non IORDY */
1202
1203 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE */
1204 pio = adev->id[ATA_ID_EIDE_PIO];
1205 /* Is the speed faster than the drive allows non IORDY ? */
1206 if (pio) {
1207 /* This is cycle times not frequency - watch the logic! */
1208 if (pio > 240) /* PIO2 is 240nS per cycle */
1209 return 1;
1210 return 0;
1211 }
1212 }
1213 return 0;
1214}
1215
1da177e4 1216/**
49016aca 1217 * ata_dev_read_id - Read ID data from the specified device
49016aca
TH		 1218 * @dev: target device
1219 * @p_class: pointer to class of the target device (may be changed)
1220 * @post_reset: is this read ID post-reset?
fe635c7e 1221 * @id: buffer to read IDENTIFY data into
1da177e4 1222 *
49016aca
TH		 1223 * Read ID data from the specified device. ATA_CMD_ID_ATA is
1224 * performed on ATA devices and ATA_CMD_ID_ATAPI on ATAPI
aec5c3c1
TH		 1225 * devices. This function also issues ATA_CMD_INIT_DEV_PARAMS
1226 * for pre-ATA4 drives.
1da177e4
LT		 1227 *
1228 * LOCKING:
49016aca
TH		 1229 * Kernel thread context (may sleep)
1230 *
1231 * RETURNS:
1232 * 0 on success, -errno otherwise.
1da177e4 1233 */
a9beec95
TH		 1234int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
1235 int post_reset, u16 *id)
1da177e4 1236{
3373efd8 1237 struct ata_port *ap = dev->ap;
49016aca 1238 unsigned int class = *p_class;
a0123703 1239 struct ata_taskfile tf;
49016aca
TH		 1240 unsigned int err_mask = 0;
1241 const char *reason;
1242 int rc;
1da177e4 1243
0dd4b21f 1244 if (ata_msg_ctl(ap))
88574551
TH		 1245 ata_dev_printk(dev, KERN_DEBUG, "%s: ENTER, host %u, dev %u\n",
1246 __FUNCTION__, ap->id, dev->devno);
1da177e4 1247
49016aca 1248 ata_dev_select(ap, dev->devno, 1, 1); /* select device 0/1 */
1da177e4 1249
49016aca 1250 retry:
3373efd8 1251 ata_tf_init(dev, &tf);
a0123703 1252
49016aca
TH		 1253 switch (class) {
1254 case ATA_DEV_ATA:
a0123703 1255 tf.command = ATA_CMD_ID_ATA;
49016aca
TH		 1256 break;
1257 case ATA_DEV_ATAPI:
a0123703 1258 tf.command = ATA_CMD_ID_ATAPI;
49016aca
TH		 1259 break;
1260 default:
1261 rc = -ENODEV;
1262 reason = "unsupported class";
1263 goto err_out;
1da177e4
LT		 1264 }
1265
a0123703 1266 tf.protocol = ATA_PROT_PIO;
1da177e4 1267
3373efd8 1268 err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE,
49016aca 1269 id, sizeof(id[0]) * ATA_ID_WORDS);
a0123703 1270 if (err_mask) {
49016aca
TH		 1271 rc = -EIO;
1272 reason = "I/O error";
1da177e4
LT		 1273 goto err_out;
1274 }
1275
49016aca 1276 swap_buf_le16(id, ATA_ID_WORDS);
1da177e4 1277
49016aca 1278 /* sanity check */
a4f5749b
TH		 1279 rc = -EINVAL;
1280 reason = "device reports illegal type";
1281
1282 if (class == ATA_DEV_ATA) {
1283 if (!ata_id_is_ata(id) && !ata_id_is_cfa(id))
1284 goto err_out;
1285 } else {
1286 if (ata_id_is_ata(id))
1287 goto err_out;
49016aca
TH		 1288 }
1289
1290 if (post_reset && class == ATA_DEV_ATA) {
1291 /*
1292 * The exact sequence expected by certain pre-ATA4 drives is:
1293 * SRST RESET
1294 * IDENTIFY
1295 * INITIALIZE DEVICE PARAMETERS
1296 * anything else..
1297 * Some drives were very specific about that exact sequence.
1298 */
1299 if (ata_id_major_version(id) < 4 || !ata_id_has_lba(id)) {
3373efd8 1300 err_mask = ata_dev_init_params(dev, id[3], id[6]);
49016aca
TH		 1301 if (err_mask) {
1302 rc = -EIO;
1303 reason = "INIT_DEV_PARAMS failed";
1304 goto err_out;
1305 }
1306
1307 /* current CHS translation info (id[53-58]) might be
1308 * changed. reread the identify device info.
1309 */
1310 post_reset = 0;
1311 goto retry;
1312 }
1313 }
1314
1315 *p_class = class;
fe635c7e 1316
49016aca
TH		 1317 return 0;
1318
1319 err_out:
88574551 1320 if (ata_msg_warn(ap))
0dd4b21f 1321 ata_dev_printk(dev, KERN_WARNING, "failed to IDENTIFY "
88574551 1322 "(%s, err_mask=0x%x)\n", reason, err_mask);
49016aca
TH		 1323 return rc;
1324}
1325
3373efd8 1326static inline u8 ata_dev_knobble(struct ata_device *dev)
4b2f3ede 1327{
3373efd8 1328 return ((dev->ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(dev->id)));
4b2f3ede
TH		 1329}
1330
a6e6ce8e
TH		 1331static void ata_dev_config_ncq(struct ata_device *dev,
1332 char *desc, size_t desc_sz)
1333{
1334 struct ata_port *ap = dev->ap;
1335 int hdepth = 0, ddepth = ata_id_queue_depth(dev->id);
1336
1337 if (!ata_id_has_ncq(dev->id)) {
1338 desc[0] = '\0';
1339 return;
1340 }
1341
1342 if (ap->flags & ATA_FLAG_NCQ) {
cca3974e 1343 hdepth = min(ap->scsi_host->can_queue, ATA_MAX_QUEUE - 1);
a6e6ce8e
TH		 1344 dev->flags |= ATA_DFLAG_NCQ;
1345 }
1346
1347 if (hdepth >= ddepth)
1348 snprintf(desc, desc_sz, "NCQ (depth %d)", ddepth);
1349 else
1350 snprintf(desc, desc_sz, "NCQ (depth %d/%d)", hdepth, ddepth);
1351}
1352
e6d902a3
BK		 1353static void ata_set_port_max_cmd_len(struct ata_port *ap)
1354{
1355 int i;
1356
cca3974e
JG		 1357 if (ap->scsi_host) {
1358 unsigned int len = 0;
1359
e6d902a3 1360 for (i = 0; i < ATA_MAX_DEVICES; i++)
cca3974e
JG		 1361 len = max(len, ap->device[i].cdb_len);
1362
1363 ap->scsi_host->max_cmd_len = len;
e6d902a3
BK		 1364 }
1365}
1366
49016aca 1367/**
ffeae418 1368 * ata_dev_configure - Configure the specified ATA/ATAPI device
ffeae418 1369 * @dev: Target device to configure
4c2d721a 1370 * @print_info: Enable device info printout
ffeae418
TH		 1371 *
1372 * Configure @dev according to @dev->id. Generic and low-level
1373 * driver specific fixups are also applied.
49016aca
TH		 1374 *
1375 * LOCKING:
ffeae418
TH		 1376 * Kernel thread context (may sleep)
1377 *
1378 * RETURNS:
1379 * 0 on success, -errno otherwise
49016aca 1380 */
a9beec95 1381int ata_dev_configure(struct ata_device *dev, int print_info)
49016aca 1382{
3373efd8 1383 struct ata_port *ap = dev->ap;
1148c3a7 1384 const u16 *id = dev->id;
ff8854b2 1385 unsigned int xfer_mask;
b352e57d 1386 char revbuf[7]; /* XYZ-99\0 */
e6d902a3 1387 int rc;
49016aca 1388
0dd4b21f 1389 if (!ata_dev_enabled(dev) && ata_msg_info(ap)) {
88574551
TH		 1390 ata_dev_printk(dev, KERN_INFO,
1391 "%s: ENTER/EXIT (host %u, dev %u) -- nodev\n",
1392 __FUNCTION__, ap->id, dev->devno);
ffeae418 1393 return 0;
49016aca
TH		 1394 }
1395
0dd4b21f 1396 if (ata_msg_probe(ap))
88574551
TH		 1397 ata_dev_printk(dev, KERN_DEBUG, "%s: ENTER, host %u, dev %u\n",
1398 __FUNCTION__, ap->id, dev->devno);
1da177e4 1399
c39f5ebe 1400 /* print device capabilities */
0dd4b21f 1401 if (ata_msg_probe(ap))
88574551
TH		 1402 ata_dev_printk(dev, KERN_DEBUG,
1403 "%s: cfg 49:%04x 82:%04x 83:%04x 84:%04x "
1404 "85:%04x 86:%04x 87:%04x 88:%04x\n",
0dd4b21f 1405 __FUNCTION__,
f15a1daf
TH		 1406 id[49], id[82], id[83], id[84],
1407 id[85], id[86], id[87], id[88]);
c39f5ebe 1408
208a9933 1409 /* initialize to-be-configured parameters */
ea1dd4e1 1410 dev->flags &= ~ATA_DFLAG_CFG_MASK;
208a9933
TH		 1411 dev->max_sectors = 0;
1412 dev->cdb_len = 0;
1413 dev->n_sectors = 0;
1414 dev->cylinders = 0;
1415 dev->heads = 0;
1416 dev->sectors = 0;
1417
1da177e4
LT		 1418 /*
1419 * common ATA, ATAPI feature tests
1420 */
1421
ff8854b2 1422 /* find max transfer mode; for printk only */
1148c3a7 1423 xfer_mask = ata_id_xfermask(id);
1da177e4 1424
0dd4b21f
BP		 1425 if (ata_msg_probe(ap))
1426 ata_dump_id(id);
1da177e4
LT		 1427
1428 /* ATA-specific feature tests */
1429 if (dev->class == ATA_DEV_ATA) {
b352e57d
AC		 1430 if (ata_id_is_cfa(id)) {
1431 if (id[162] & 1) /* CPRM may make this media unusable */
1432 ata_dev_printk(dev, KERN_WARNING, "ata%u: device %u supports DRM functions and may not be fully accessable.\n",
1433 ap->id, dev->devno);
1434 snprintf(revbuf, 7, "CFA");
1435 }
1436 else
1437 snprintf(revbuf, 7, "ATA-%d", ata_id_major_version(id));
1438
1148c3a7 1439 dev->n_sectors = ata_id_n_sectors(id);
2940740b 1440
1148c3a7 1441 if (ata_id_has_lba(id)) {
4c2d721a 1442 const char *lba_desc;
a6e6ce8e 1443 char ncq_desc[20];
8bf62ece 1444
4c2d721a
TH		 1445 lba_desc = "LBA";
1446 dev->flags |= ATA_DFLAG_LBA;
1148c3a7 1447 if (ata_id_has_lba48(id)) {
8bf62ece 1448 dev->flags |= ATA_DFLAG_LBA48;
4c2d721a
TH		 1449 lba_desc = "LBA48";
1450 }
8bf62ece 1451
a6e6ce8e
TH		 1452 /* config NCQ */
1453 ata_dev_config_ncq(dev, ncq_desc, sizeof(ncq_desc));
1454
8bf62ece 1455 /* print device info to dmesg */
5afc8142 1456 if (ata_msg_drv(ap) && print_info)
b352e57d 1457 ata_dev_printk(dev, KERN_INFO, "%s, "
a6e6ce8e 1458 "max %s, %Lu sectors: %s %s\n",
b352e57d 1459 revbuf,
f15a1daf
TH		 1460 ata_mode_string(xfer_mask),
1461 (unsigned long long)dev->n_sectors,
a6e6ce8e 1462 lba_desc, ncq_desc);
ffeae418 1463 } else {
8bf62ece
AL		 1464 /* CHS */
1465
1466 /* Default translation */
1148c3a7
TH		 1467 dev->cylinders = id[1];
1468 dev->heads = id[3];
1469 dev->sectors = id[6];
8bf62ece 1470
1148c3a7 1471 if (ata_id_current_chs_valid(id)) {
8bf62ece 1472 /* Current CHS translation is valid. */
1148c3a7
TH		 1473 dev->cylinders = id[54];
1474 dev->heads = id[55];
1475 dev->sectors = id[56];
8bf62ece
AL		 1476 }
1477
1478 /* print device info to dmesg */
5afc8142 1479 if (ata_msg_drv(ap) && print_info)
b352e57d 1480 ata_dev_printk(dev, KERN_INFO, "%s, "
f15a1daf 1481 "max %s, %Lu sectors: CHS %u/%u/%u\n",
b352e57d 1482 revbuf,
f15a1daf
TH		 1483 ata_mode_string(xfer_mask),
1484 (unsigned long long)dev->n_sectors,
88574551
TH		 1485 dev->cylinders, dev->heads,
1486 dev->sectors);
1da177e4
LT		 1487 }
1488
07f6f7d0
AL		 1489 if (dev->id[59] & 0x100) {
1490 dev->multi_count = dev->id[59] & 0xff;
5afc8142 1491 if (ata_msg_drv(ap) && print_info)
88574551
TH		 1492 ata_dev_printk(dev, KERN_INFO,
1493 "ata%u: dev %u multi count %u\n",
1494 ap->id, dev->devno, dev->multi_count);
07f6f7d0
AL		 1495 }
1496
6e7846e9 1497 dev->cdb_len = 16;
1da177e4
LT		 1498 }
1499
1500 /* ATAPI-specific feature tests */
2c13b7ce 1501 else if (dev->class == ATA_DEV_ATAPI) {
08a556db
AL		 1502 char *cdb_intr_string = "";
1503
1148c3a7 1504 rc = atapi_cdb_len(id);
1da177e4 1505 if ((rc < 12) || (rc > ATAPI_CDB_LEN)) {
0dd4b21f 1506 if (ata_msg_warn(ap))
88574551
TH		 1507 ata_dev_printk(dev, KERN_WARNING,
1508 "unsupported CDB len\n");
ffeae418 1509 rc = -EINVAL;
1da177e4
LT		 1510 goto err_out_nosup;
1511 }
6e7846e9 1512 dev->cdb_len = (unsigned int) rc;
1da177e4 1513
08a556db 1514 if (ata_id_cdb_intr(dev->id)) {
312f7da2 1515 dev->flags |= ATA_DFLAG_CDB_INTR;
08a556db
AL		 1516 cdb_intr_string = ", CDB intr";
1517 }
312f7da2 1518
1da177e4 1519 /* print device info to dmesg */
5afc8142 1520 if (ata_msg_drv(ap) && print_info)
12436c30
TH		 1521 ata_dev_printk(dev, KERN_INFO, "ATAPI, max %s%s\n",
1522 ata_mode_string(xfer_mask),
1523 cdb_intr_string);
1da177e4
LT		 1524 }
1525
e6d902a3 1526 ata_set_port_max_cmd_len(ap);
6e7846e9 1527
4b2f3ede 1528 /* limit bridge transfers to udma5, 200 sectors */
3373efd8 1529 if (ata_dev_knobble(dev)) {
5afc8142 1530 if (ata_msg_drv(ap) && print_info)
f15a1daf
TH		 1531 ata_dev_printk(dev, KERN_INFO,
1532 "applying bridge limits\n");
5a529139 1533 dev->udma_mask &= ATA_UDMA5;
4b2f3ede
TH		 1534 dev->max_sectors = ATA_MAX_SECTORS;
1535 }
1536
1537 if (ap->ops->dev_config)
1538 ap->ops->dev_config(ap, dev);
1539
0dd4b21f
BP		 1540 if (ata_msg_probe(ap))
1541 ata_dev_printk(dev, KERN_DEBUG, "%s: EXIT, drv_stat = 0x%x\n",
1542 __FUNCTION__, ata_chk_status(ap));
ffeae418 1543 return 0;
1da177e4
LT		 1544
1545err_out_nosup:
0dd4b21f 1546 if (ata_msg_probe(ap))
88574551
TH		 1547 ata_dev_printk(dev, KERN_DEBUG,
1548 "%s: EXIT, err\n", __FUNCTION__);
ffeae418 1549 return rc;
1da177e4
LT		 1550}
1551
1552/**
1553 * ata_bus_probe - Reset and probe ATA bus
1554 * @ap: Bus to probe
1555 *
0cba632b
JG		 1556 * Master ATA bus probing function. Initiates a hardware-dependent
1557 * bus reset, then attempts to identify any devices found on
1558 * the bus.
1559 *
1da177e4 1560 * LOCKING:
0cba632b 1561 * PCI/etc. bus probe sem.
1da177e4
LT		 1562 *
1563 * RETURNS:
96072e69 1564 * Zero on success, negative errno otherwise.
1da177e4
LT		 1565 */
1566
80289167 1567int ata_bus_probe(struct ata_port *ap)
1da177e4 1568{
28ca5c57 1569 unsigned int classes[ATA_MAX_DEVICES];
14d2bac1
TH		 1570 int tries[ATA_MAX_DEVICES];
1571 int i, rc, down_xfermask;
e82cbdb9 1572 struct ata_device *dev;
1da177e4 1573
28ca5c57 1574 ata_port_probe(ap);
c19ba8af 1575
14d2bac1
TH		 1576 for (i = 0; i < ATA_MAX_DEVICES; i++)
1577 tries[i] = ATA_PROBE_MAX_TRIES;
1578
1579 retry:
1580 down_xfermask = 0;
1581
2044470c 1582 /* reset and determine device classes */
52783c5d 1583 ap->ops->phy_reset(ap);
2061a47a 1584
52783c5d
TH		 1585 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1586 dev = &ap->device[i];
c19ba8af 1587
52783c5d
TH		 1588 if (!(ap->flags & ATA_FLAG_DISABLED) &&
1589 dev->class != ATA_DEV_UNKNOWN)
1590 classes[dev->devno] = dev->class;
1591 else
1592 classes[dev->devno] = ATA_DEV_NONE;
2044470c 1593
52783c5d 1594 dev->class = ATA_DEV_UNKNOWN;
28ca5c57 1595 }
1da177e4 1596
52783c5d 1597 ata_port_probe(ap);
2044470c 1598
b6079ca4
AC		 1599 /* after the reset the device state is PIO 0 and the controller
1600 state is undefined. Record the mode */
1601
1602 for (i = 0; i < ATA_MAX_DEVICES; i++)
1603 ap->device[i].pio_mode = XFER_PIO_0;
1604
28ca5c57 1605 /* read IDENTIFY page and configure devices */
1da177e4 1606 for (i = 0; i < ATA_MAX_DEVICES; i++) {
e82cbdb9 1607 dev = &ap->device[i];
28ca5c57 1608
ec573755
TH		 1609 if (tries[i])
1610 dev->class = classes[i];
ffeae418 1611
14d2bac1 1612 if (!ata_dev_enabled(dev))
ffeae418 1613 continue;
ffeae418 1614
3373efd8 1615 rc = ata_dev_read_id(dev, &dev->class, 1, dev->id);
14d2bac1
TH		 1616 if (rc)
1617 goto fail;
1618
3373efd8 1619 rc = ata_dev_configure(dev, 1);
14d2bac1
TH		 1620 if (rc)
1621 goto fail;
1da177e4
LT		 1622 }
1623
e82cbdb9 1624 /* configure transfer mode */
3adcebb2 1625 rc = ata_set_mode(ap, &dev);
51713d35
TH		 1626 if (rc) {
1627 down_xfermask = 1;
1628 goto fail;
e82cbdb9 1629 }
1da177e4 1630
e82cbdb9
TH		 1631 for (i = 0; i < ATA_MAX_DEVICES; i++)
1632 if (ata_dev_enabled(&ap->device[i]))
1633 return 0;
1da177e4 1634
e82cbdb9
TH		 1635 /* no device present, disable port */
1636 ata_port_disable(ap);
1da177e4 1637 ap->ops->port_disable(ap);
96072e69 1638 return -ENODEV;
14d2bac1
TH		 1639
1640 fail:
1641 switch (rc) {
1642 case -EINVAL:
1643 case -ENODEV:
1644 tries[dev->devno] = 0;
1645 break;
1646 case -EIO:
3c567b7d 1647 sata_down_spd_limit(ap);
14d2bac1
TH		 1648 /* fall through */
1649 default:
1650 tries[dev->devno]--;
1651 if (down_xfermask &&
3373efd8 1652 ata_down_xfermask_limit(dev, tries[dev->devno] == 1))
14d2bac1
TH		 1653 tries[dev->devno] = 0;
1654 }
1655
ec573755 1656 if (!tries[dev->devno]) {
3373efd8
TH		 1657 ata_down_xfermask_limit(dev, 1);
1658 ata_dev_disable(dev);
ec573755
TH		 1659 }
1660
14d2bac1 1661 goto retry;
1da177e4
LT		 1662}
1663
1664/**
0cba632b
JG		 1665 * ata_port_probe - Mark port as enabled
1666 * @ap: Port for which we indicate enablement
1da177e4 1667 *
0cba632b
JG		 1668 * Modify @ap data structure such that the system
1669 * thinks that the entire port is enabled.
1670 *
cca3974e 1671 * LOCKING: host lock, or some other form of
0cba632b 1672 * serialization.
1da177e4
LT		 1673 */
1674
1675void ata_port_probe(struct ata_port *ap)
1676{
198e0fed 1677 ap->flags &= ~ATA_FLAG_DISABLED;
1da177e4
LT		 1678}
1679
3be680b7
TH		 1680/**
1681 * sata_print_link_status - Print SATA link status
1682 * @ap: SATA port to printk link status about
1683 *
1684 * This function prints link speed and status of a SATA link.
1685 *
1686 * LOCKING:
1687 * None.
1688 */
1689static void sata_print_link_status(struct ata_port *ap)
1690{
6d5f9732 1691 u32 sstatus, scontrol, tmp;
3be680b7 1692
81952c54 1693 if (sata_scr_read(ap, SCR_STATUS, &sstatus))
3be680b7 1694 return;
81952c54 1695 sata_scr_read(ap, SCR_CONTROL, &scontrol);
3be680b7 1696
81952c54 1697 if (ata_port_online(ap)) {
3be680b7 1698 tmp = (sstatus >> 4) & 0xf;
f15a1daf
TH		 1699 ata_port_printk(ap, KERN_INFO,
1700 "SATA link up %s (SStatus %X SControl %X)\n",
1701 sata_spd_string(tmp), sstatus, scontrol);
3be680b7 1702 } else {
f15a1daf
TH		 1703 ata_port_printk(ap, KERN_INFO,
1704 "SATA link down (SStatus %X SControl %X)\n",
1705 sstatus, scontrol);
3be680b7
TH		 1706 }
1707}
1708
1da177e4 1709/**
780a87f7
JG		 1710 * __sata_phy_reset - Wake/reset a low-level SATA PHY
1711 * @ap: SATA port associated with target SATA PHY.
1da177e4 1712 *
780a87f7
JG		 1713 * This function issues commands to standard SATA Sxxx
1714 * PHY registers, to wake up the phy (and device), and
1715 * clear any reset condition.
1da177e4
LT		 1716 *
1717 * LOCKING:
0cba632b 1718 * PCI/etc. bus probe sem.
1da177e4
LT		 1719 *
1720 */
1721void __sata_phy_reset(struct ata_port *ap)
1722{
1723 u32 sstatus;
1724 unsigned long timeout = jiffies + (HZ * 5);
1725
1726 if (ap->flags & ATA_FLAG_SATA_RESET) {
cdcca89e 1727 /* issue phy wake/reset */
81952c54 1728 sata_scr_write_flush(ap, SCR_CONTROL, 0x301);
62ba2841
TH		 1729 /* Couldn't find anything in SATA I/II specs, but
1730 * AHCI-1.1 10.4.2 says at least 1 ms. */
1731 mdelay(1);
1da177e4 1732 }
81952c54
TH		 1733 /* phy wake/clear reset */
1734 sata_scr_write_flush(ap, SCR_CONTROL, 0x300);
1da177e4
LT		 1735
1736 /* wait for phy to become ready, if necessary */
1737 do {
1738 msleep(200);
81952c54 1739 sata_scr_read(ap, SCR_STATUS, &sstatus);
1da177e4
LT		 1740 if ((sstatus & 0xf) != 1)
1741 break;
1742 } while (time_before(jiffies, timeout));
1743
3be680b7
TH		 1744 /* print link status */
1745 sata_print_link_status(ap);
656563e3 1746
3be680b7 1747 /* TODO: phy layer with polling, timeouts, etc. */
81952c54 1748 if (!ata_port_offline(ap))
1da177e4 1749 ata_port_probe(ap);
3be680b7 1750 else
1da177e4 1751 ata_port_disable(ap);
1da177e4 1752
198e0fed 1753 if (ap->flags & ATA_FLAG_DISABLED)
1da177e4
LT		 1754 return;
1755
1756 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
1757 ata_port_disable(ap);
1758 return;
1759 }
1760
1761 ap->cbl = ATA_CBL_SATA;
1762}
1763
1764/**
780a87f7
JG		 1765 * sata_phy_reset - Reset SATA bus.
1766 * @ap: SATA port associated with target SATA PHY.
1da177e4 1767 *
780a87f7
JG		 1768 * This function resets the SATA bus, and then probes
1769 * the bus for devices.
1da177e4
LT		 1770 *
1771 * LOCKING:
0cba632b 1772 * PCI/etc. bus probe sem.
1da177e4
LT		 1773 *
1774 */
1775void sata_phy_reset(struct ata_port *ap)
1776{
1777 __sata_phy_reset(ap);
198e0fed 1778 if (ap->flags & ATA_FLAG_DISABLED)
1da177e4
LT		 1779 return;
1780 ata_bus_reset(ap);
1781}
1782
ebdfca6e
AC		 1783/**
1784 * ata_dev_pair - return other device on cable
ebdfca6e
AC		 1785 * @adev: device
1786 *
1787 * Obtain the other device on the same cable, or if none is
1788 * present NULL is returned
1789 */
2e9edbf8 1790
3373efd8 1791struct ata_device *ata_dev_pair(struct ata_device *adev)
ebdfca6e 1792{
3373efd8 1793 struct ata_port *ap = adev->ap;
ebdfca6e 1794 struct ata_device *pair = &ap->device[1 - adev->devno];
e1211e3f 1795 if (!ata_dev_enabled(pair))
ebdfca6e
AC		 1796 return NULL;
1797 return pair;
1798}
1799
1da177e4 1800/**
780a87f7
JG		 1801 * ata_port_disable - Disable port.
1802 * @ap: Port to be disabled.
1da177e4 1803 *
780a87f7
JG		 1804 * Modify @ap data structure such that the system
1805 * thinks that the entire port is disabled, and should
1806 * never attempt to probe or communicate with devices
1807 * on this port.
1808 *
cca3974e 1809 * LOCKING: host lock, or some other form of
780a87f7 1810 * serialization.
1da177e4
LT		 1811 */
1812
1813void ata_port_disable(struct ata_port *ap)
1814{
1815 ap->device[0].class = ATA_DEV_NONE;
1816 ap->device[1].class = ATA_DEV_NONE;
198e0fed 1817 ap->flags |= ATA_FLAG_DISABLED;
1da177e4
LT		 1818}
1819
1c3fae4d 1820/**
3c567b7d 1821 * sata_down_spd_limit - adjust SATA spd limit downward
1c3fae4d
TH		 1822 * @ap: Port to adjust SATA spd limit for
1823 *
1824 * Adjust SATA spd limit of @ap downward. Note that this
1825 * function only adjusts the limit. The change must be applied
3c567b7d 1826 * using sata_set_spd().
1c3fae4d
TH		 1827 *
1828 * LOCKING:
1829 * Inherited from caller.
1830 *
1831 * RETURNS:
1832 * 0 on success, negative errno on failure
1833 */
3c567b7d 1834int sata_down_spd_limit(struct ata_port *ap)
1c3fae4d 1835{
81952c54
TH		 1836 u32 sstatus, spd, mask;
1837 int rc, highbit;
1c3fae4d 1838
81952c54
TH		 1839 rc = sata_scr_read(ap, SCR_STATUS, &sstatus);
1840 if (rc)
1841 return rc;
1c3fae4d
TH		 1842
1843 mask = ap->sata_spd_limit;
1844 if (mask <= 1)
1845 return -EINVAL;
1846 highbit = fls(mask) - 1;
1847 mask &= ~(1 << highbit);
1848
81952c54 1849 spd = (sstatus >> 4) & 0xf;
1c3fae4d
TH		 1850 if (spd <= 1)
1851 return -EINVAL;
1852 spd--;
1853 mask &= (1 << spd) - 1;
1854 if (!mask)
1855 return -EINVAL;
1856
1857 ap->sata_spd_limit = mask;
1858
f15a1daf
TH		 1859 ata_port_printk(ap, KERN_WARNING, "limiting SATA link speed to %s\n",
1860 sata_spd_string(fls(mask)));
1c3fae4d
TH		 1861
1862 return 0;
1863}
1864
3c567b7d 1865static int __sata_set_spd_needed(struct ata_port *ap, u32 *scontrol)
1c3fae4d
TH		 1866{
1867 u32 spd, limit;
1868
1869 if (ap->sata_spd_limit == UINT_MAX)
1870 limit = 0;
1871 else
1872 limit = fls(ap->sata_spd_limit);
1873
1874 spd = (*scontrol >> 4) & 0xf;
1875 *scontrol = (*scontrol & ~0xf0) | ((limit & 0xf) << 4);
1876
1877 return spd != limit;
1878}
1879
1880/**
3c567b7d 1881 * sata_set_spd_needed - is SATA spd configuration needed
1c3fae4d
TH		 1882 * @ap: Port in question
1883 *
1884 * Test whether the spd limit in SControl matches
1885 * @ap->sata_spd_limit. This function is used to determine
1886 * whether hardreset is necessary to apply SATA spd
1887 * configuration.
1888 *
1889 * LOCKING:
1890 * Inherited from caller.
1891 *
1892 * RETURNS:
1893 * 1 if SATA spd configuration is needed, 0 otherwise.
1894 */
3c567b7d 1895int sata_set_spd_needed(struct ata_port *ap)
1c3fae4d
TH		 1896{
1897 u32 scontrol;
1898
81952c54 1899 if (sata_scr_read(ap, SCR_CONTROL, &scontrol))
1c3fae4d
TH		 1900 return 0;
1901
3c567b7d 1902 return __sata_set_spd_needed(ap, &scontrol);
1c3fae4d
TH		 1903}
1904
1905/**
3c567b7d 1906 * sata_set_spd - set SATA spd according to spd limit
1c3fae4d
TH		 1907 * @ap: Port to set SATA spd for
1908 *
1909 * Set SATA spd of @ap according to sata_spd_limit.
1910 *
1911 * LOCKING:
1912 * Inherited from caller.
1913 *
1914 * RETURNS:
1915 * 0 if spd doesn't need to be changed, 1 if spd has been
81952c54 1916 * changed. Negative errno if SCR registers are inaccessible.
1c3fae4d 1917 */
3c567b7d 1918int sata_set_spd(struct ata_port *ap)
1c3fae4d
TH		 1919{
1920 u32 scontrol;
81952c54 1921 int rc;
1c3fae4d 1922
81952c54
TH		 1923 if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
1924 return rc;
1c3fae4d 1925
3c567b7d 1926 if (!__sata_set_spd_needed(ap, &scontrol))
1c3fae4d
TH		 1927 return 0;
1928
81952c54
TH		 1929 if ((rc = sata_scr_write(ap, SCR_CONTROL, scontrol)))
1930 return rc;
1931
1c3fae4d
TH		 1932 return 1;
1933}
1934
452503f9
AC		 1935/*
1936 * This mode timing computation functionality is ported over from
1937 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
1938 */
1939/*
b352e57d 1940 * PIO 0-4, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
452503f9 1941 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
b352e57d
AC		 1942 * for UDMA6, which is currently supported only by Maxtor drives.
1943 *
1944 * For PIO 5/6 MWDMA 3/4 see the CFA specification 3.0.
452503f9
AC		 1945 */
1946
1947static const struct ata_timing ata_timing[] = {
1948
1949 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
1950 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
1951 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
1952 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
1953
b352e57d
AC		 1954 { XFER_MW_DMA_4, 25, 0, 0, 0, 55, 20, 80, 0 },
1955 { XFER_MW_DMA_3, 25, 0, 0, 0, 65, 25, 100, 0 },
452503f9
AC		 1956 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
1957 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
1958 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
1959
1960/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */
2e9edbf8 1961
452503f9
AC		 1962 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
1963 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
1964 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
2e9edbf8 1965
452503f9
AC		 1966 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
1967 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
1968 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
1969
b352e57d
AC		 1970 { XFER_PIO_6, 10, 55, 20, 80, 55, 20, 80, 0 },
1971 { XFER_PIO_5, 15, 65, 25, 100, 65, 25, 100, 0 },
452503f9
AC		 1972 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
1973 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
1974
1975 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
1976 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
1977 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
1978
1979/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */
1980
1981 { 0xFF }
1982};
1983
1984#define ENOUGH(v,unit) (((v)-1)/(unit)+1)
1985#define EZ(v,unit) ((v)?ENOUGH(v,unit):0)
1986
1987static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
1988{
1989 q->setup = EZ(t->setup * 1000, T);
1990 q->act8b = EZ(t->act8b * 1000, T);
1991 q->rec8b = EZ(t->rec8b * 1000, T);
1992 q->cyc8b = EZ(t->cyc8b * 1000, T);
1993 q->active = EZ(t->active * 1000, T);
1994 q->recover = EZ(t->recover * 1000, T);
1995 q->cycle = EZ(t->cycle * 1000, T);
1996 q->udma = EZ(t->udma * 1000, UT);
1997}
1998
1999void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
2000 struct ata_timing *m, unsigned int what)
2001{
2002 if (what & ATA_TIMING_SETUP ) m->setup = max(a->setup, b->setup);
2003 if (what & ATA_TIMING_ACT8B ) m->act8b = max(a->act8b, b->act8b);
2004 if (what & ATA_TIMING_REC8B ) m->rec8b = max(a->rec8b, b->rec8b);
2005 if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b);
2006 if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active);
2007 if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
2008 if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle);
2009 if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma);
2010}
2011
2012static const struct ata_timing* ata_timing_find_mode(unsigned short speed)
2013{
2014 const struct ata_timing *t;
2015
2016 for (t = ata_timing; t->mode != speed; t++)
91190758 2017 if (t->mode == 0xFF)
452503f9 2018 return NULL;
2e9edbf8 2019 return t;
452503f9
AC		 2020}
2021
2022int ata_timing_compute(struct ata_device *adev, unsigned short speed,
2023 struct ata_timing *t, int T, int UT)
2024{
2025 const struct ata_timing *s;
2026 struct ata_timing p;
2027
2028 /*
2e9edbf8 2029 * Find the mode.
75b1f2f8 2030 */
452503f9
AC		 2031
2032 if (!(s = ata_timing_find_mode(speed)))
2033 return -EINVAL;
2034
75b1f2f8
AL		 2035 memcpy(t, s, sizeof(*s));
2036
452503f9
AC		 2037 /*
2038 * If the drive is an EIDE drive, it can tell us it needs extended
2039 * PIO/MW_DMA cycle timing.
2040 */
2041
2042 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
2043 memset(&p, 0, sizeof(p));
2044 if(speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) {
2045 if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO];
2046 else p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO_IORDY];
2047 } else if(speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) {
2048 p.cycle = adev->id[ATA_ID_EIDE_DMA_MIN];
2049 }
2050 ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
2051 }
2052
2053 /*
2054 * Convert the timing to bus clock counts.
2055 */
2056
75b1f2f8 2057 ata_timing_quantize(t, t, T, UT);
452503f9
AC		 2058
2059 /*
c893a3ae
RD		 2060 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
2061 * S.M.A.R.T * and some other commands. We have to ensure that the
2062 * DMA cycle timing is slower/equal than the fastest PIO timing.
452503f9
AC		 2063 */
2064
2065 if (speed > XFER_PIO_4) {
2066 ata_timing_compute(adev, adev->pio_mode, &p, T, UT);
2067 ata_timing_merge(&p, t, t, ATA_TIMING_ALL);
2068 }
2069
2070 /*
c893a3ae 2071 * Lengthen active & recovery time so that cycle time is correct.
452503f9
AC		 2072 */
2073
2074 if (t->act8b + t->rec8b < t->cyc8b) {
2075 t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
2076 t->rec8b = t->cyc8b - t->act8b;
2077 }
2078
2079 if (t->active + t->recover < t->cycle) {
2080 t->active += (t->cycle - (t->active + t->recover)) / 2;
2081 t->recover = t->cycle - t->active;
2082 }
2083
2084 return 0;
2085}
2086
cf176e1a
TH		 2087/**
2088 * ata_down_xfermask_limit - adjust dev xfer masks downward
cf176e1a
TH		 2089 * @dev: Device to adjust xfer masks
2090 * @force_pio0: Force PIO0
2091 *
2092 * Adjust xfer masks of @dev downward. Note that this function
2093 * does not apply the change. Invoking ata_set_mode() afterwards
2094 * will apply the limit.
2095 *
2096 * LOCKING:
2097 * Inherited from caller.
2098 *
2099 * RETURNS:
2100 * 0 on success, negative errno on failure
2101 */
3373efd8 2102int ata_down_xfermask_limit(struct ata_device *dev, int force_pio0)
cf176e1a
TH		 2103{
2104 unsigned long xfer_mask;
2105 int highbit;
2106
2107 xfer_mask = ata_pack_xfermask(dev->pio_mask, dev->mwdma_mask,
2108 dev->udma_mask);
2109
2110 if (!xfer_mask)
2111 goto fail;
2112 /* don't gear down to MWDMA from UDMA, go directly to PIO */
2113 if (xfer_mask & ATA_MASK_UDMA)
2114 xfer_mask &= ~ATA_MASK_MWDMA;
2115
2116 highbit = fls(xfer_mask) - 1;
2117 xfer_mask &= ~(1 << highbit);
2118 if (force_pio0)
2119 xfer_mask &= 1 << ATA_SHIFT_PIO;
2120 if (!xfer_mask)
2121 goto fail;
2122
2123 ata_unpack_xfermask(xfer_mask, &dev->pio_mask, &dev->mwdma_mask,
2124 &dev->udma_mask);
2125
f15a1daf
TH		 2126 ata_dev_printk(dev, KERN_WARNING, "limiting speed to %s\n",
2127 ata_mode_string(xfer_mask));
cf176e1a
TH		 2128
2129 return 0;
2130
2131 fail:
2132 return -EINVAL;
2133}
2134
3373efd8 2135static int ata_dev_set_mode(struct ata_device *dev)
1da177e4 2136{
83206a29
TH		 2137 unsigned int err_mask;
2138 int rc;
1da177e4 2139
e8384607 2140 dev->flags &= ~ATA_DFLAG_PIO;
1da177e4
LT		 2141 if (dev->xfer_shift == ATA_SHIFT_PIO)
2142 dev->flags |= ATA_DFLAG_PIO;
2143
3373efd8 2144 err_mask = ata_dev_set_xfermode(dev);
83206a29 2145 if (err_mask) {
f15a1daf
TH		 2146 ata_dev_printk(dev, KERN_ERR, "failed to set xfermode "
2147 "(err_mask=0x%x)\n", err_mask);
83206a29
TH		 2148 return -EIO;
2149 }
1da177e4 2150
3373efd8 2151 rc = ata_dev_revalidate(dev, 0);
5eb45c02 2152 if (rc)
83206a29 2153 return rc;
48a8a14f 2154
23e71c3d
TH		 2155 DPRINTK("xfer_shift=%u, xfer_mode=0x%x\n",
2156 dev->xfer_shift, (int)dev->xfer_mode);
1da177e4 2157
f15a1daf
TH		 2158 ata_dev_printk(dev, KERN_INFO, "configured for %s\n",
2159 ata_mode_string(ata_xfer_mode2mask(dev->xfer_mode)));
83206a29 2160 return 0;
1da177e4
LT		 2161}
2162
1da177e4
LT		 2163/**
2164 * ata_set_mode - Program timings and issue SET FEATURES - XFER
2165 * @ap: port on which timings will be programmed
e82cbdb9 2166 * @r_failed_dev: out paramter for failed device
1da177e4 2167 *
e82cbdb9
TH		 2168 * Set ATA device disk transfer mode (PIO3, UDMA6, etc.). If
2169 * ata_set_mode() fails, pointer to the failing device is
2170 * returned in @r_failed_dev.
780a87f7 2171 *
1da177e4 2172 * LOCKING:
0cba632b 2173 * PCI/etc. bus probe sem.
e82cbdb9
TH		 2174 *
2175 * RETURNS:
2176 * 0 on success, negative errno otherwise
1da177e4 2177 */
1ad8e7f9 2178int ata_set_mode(struct ata_port *ap, struct ata_device **r_failed_dev)
1da177e4 2179{
e8e0619f 2180 struct ata_device *dev;
e82cbdb9 2181 int i, rc = 0, used_dma = 0, found = 0;
1da177e4 2182
3adcebb2
TH		 2183 /* has private set_mode? */
2184 if (ap->ops->set_mode) {
2185 /* FIXME: make ->set_mode handle no device case and
2186 * return error code and failing device on failure.
2187 */
2188 for (i = 0; i < ATA_MAX_DEVICES; i++) {
02670bf3 2189 if (ata_dev_ready(&ap->device[i])) {
3adcebb2
TH		 2190 ap->ops->set_mode(ap);
2191 break;
2192 }
2193 }
2194 return 0;
2195 }
2196
a6d5a51c
TH		 2197 /* step 1: calculate xfer_mask */
2198 for (i = 0; i < ATA_MAX_DEVICES; i++) {
acf356b1 2199 unsigned int pio_mask, dma_mask;
a6d5a51c 2200
e8e0619f
TH		 2201 dev = &ap->device[i];
2202
e1211e3f 2203 if (!ata_dev_enabled(dev))
a6d5a51c
TH		 2204 continue;
2205
3373efd8 2206 ata_dev_xfermask(dev);
1da177e4 2207
acf356b1
TH		 2208 pio_mask = ata_pack_xfermask(dev->pio_mask, 0, 0);
2209 dma_mask = ata_pack_xfermask(0, dev->mwdma_mask, dev->udma_mask);
2210 dev->pio_mode = ata_xfer_mask2mode(pio_mask);
2211 dev->dma_mode = ata_xfer_mask2mode(dma_mask);
5444a6f4 2212
4f65977d 2213 found = 1;
5444a6f4
AC		 2214 if (dev->dma_mode)
2215 used_dma = 1;
a6d5a51c 2216 }
4f65977d 2217 if (!found)
e82cbdb9 2218 goto out;
a6d5a51c
TH		 2219
2220 /* step 2: always set host PIO timings */
e8e0619f
TH		 2221 for (i = 0; i < ATA_MAX_DEVICES; i++) {
2222 dev = &ap->device[i];
2223 if (!ata_dev_enabled(dev))
2224 continue;
2225
2226 if (!dev->pio_mode) {
f15a1daf 2227 ata_dev_printk(dev, KERN_WARNING, "no PIO support\n");
e8e0619f 2228 rc = -EINVAL;
e82cbdb9 2229 goto out;
e8e0619f
TH		 2230 }
2231
2232 dev->xfer_mode = dev->pio_mode;
2233 dev->xfer_shift = ATA_SHIFT_PIO;
2234 if (ap->ops->set_piomode)
2235 ap->ops->set_piomode(ap, dev);
2236 }
1da177e4 2237
a6d5a51c 2238 /* step 3: set host DMA timings */
e8e0619f
TH		 2239 for (i = 0; i < ATA_MAX_DEVICES; i++) {
2240 dev = &ap->device[i];
2241
2242 if (!ata_dev_enabled(dev) || !dev->dma_mode)
2243 continue;
2244
2245 dev->xfer_mode = dev->dma_mode;
2246 dev->xfer_shift = ata_xfer_mode2shift(dev->dma_mode);
2247 if (ap->ops->set_dmamode)
2248 ap->ops->set_dmamode(ap, dev);
2249 }
1da177e4
LT		 2250
2251 /* step 4: update devices' xfer mode */
83206a29 2252 for (i = 0; i < ATA_MAX_DEVICES; i++) {
e8e0619f 2253 dev = &ap->device[i];
1da177e4 2254
02670bf3
TH		 2255 /* don't udpate suspended devices' xfer mode */
2256 if (!ata_dev_ready(dev))
83206a29
TH		 2257 continue;
2258
3373efd8 2259 rc = ata_dev_set_mode(dev);
5bbc53f4 2260 if (rc)
e82cbdb9 2261 goto out;
83206a29 2262 }
1da177e4 2263
e8e0619f
TH		 2264 /* Record simplex status. If we selected DMA then the other
2265 * host channels are not permitted to do so.
5444a6f4 2266 */
cca3974e
JG		 2267 if (used_dma && (ap->host->flags & ATA_HOST_SIMPLEX))
2268 ap->host->simplex_claimed = 1;
5444a6f4 2269
e8e0619f 2270 /* step5: chip specific finalisation */
1da177e4
LT		 2271 if (ap->ops->post_set_mode)
2272 ap->ops->post_set_mode(ap);
2273
e82cbdb9
TH		 2274 out:
2275 if (rc)
2276 *r_failed_dev = dev;
2277 return rc;
1da177e4
LT		 2278}
2279
1fdffbce
JG		 2280/**
2281 * ata_tf_to_host - issue ATA taskfile to host controller
2282 * @ap: port to which command is being issued
2283 * @tf: ATA taskfile register set
2284 *
2285 * Issues ATA taskfile register set to ATA host controller,
2286 * with proper synchronization with interrupt handler and
2287 * other threads.
2288 *
2289 * LOCKING:
cca3974e 2290 * spin_lock_irqsave(host lock)
1fdffbce
JG		 2291 */
2292
2293static inline void ata_tf_to_host(struct ata_port *ap,
2294 const struct ata_taskfile *tf)
2295{
2296 ap->ops->tf_load(ap, tf);
2297 ap->ops->exec_command(ap, tf);
2298}
2299
1da177e4
LT		 2300/**
2301 * ata_busy_sleep - sleep until BSY clears, or timeout
2302 * @ap: port containing status register to be polled
2303 * @tmout_pat: impatience timeout
2304 * @tmout: overall timeout
2305 *
780a87f7
JG		 2306 * Sleep until ATA Status register bit BSY clears,
2307 * or a timeout occurs.
2308 *
2309 * LOCKING: None.
1da177e4
LT		 2310 */
2311
6f8b9958
TH		 2312unsigned int ata_busy_sleep (struct ata_port *ap,
2313 unsigned long tmout_pat, unsigned long tmout)
1da177e4
LT		 2314{
2315 unsigned long timer_start, timeout;
2316 u8 status;
2317
2318 status = ata_busy_wait(ap, ATA_BUSY, 300);
2319 timer_start = jiffies;
2320 timeout = timer_start + tmout_pat;
2321 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
2322 msleep(50);
2323 status = ata_busy_wait(ap, ATA_BUSY, 3);
2324 }
2325
2326 if (status & ATA_BUSY)
f15a1daf
TH		 2327 ata_port_printk(ap, KERN_WARNING,
2328 "port is slow to respond, please be patient\n");
1da177e4
LT		 2329
2330 timeout = timer_start + tmout;
2331 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
2332 msleep(50);
2333 status = ata_chk_status(ap);
2334 }
2335
2336 if (status & ATA_BUSY) {
f15a1daf
TH		 2337 ata_port_printk(ap, KERN_ERR, "port failed to respond "
2338 "(%lu secs)\n", tmout / HZ);
1da177e4
LT		 2339 return 1;
2340 }
2341
2342 return 0;
2343}
2344
2345static void ata_bus_post_reset(struct ata_port *ap, unsigned int devmask)
2346{
2347 struct ata_ioports *ioaddr = &ap->ioaddr;
2348 unsigned int dev0 = devmask & (1 << 0);
2349 unsigned int dev1 = devmask & (1 << 1);
2350 unsigned long timeout;
2351
2352 /* if device 0 was found in ata_devchk, wait for its
2353 * BSY bit to clear
2354 */
2355 if (dev0)
2356 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
2357
2358 /* if device 1 was found in ata_devchk, wait for
2359 * register access, then wait for BSY to clear
2360 */
2361 timeout = jiffies + ATA_TMOUT_BOOT;
2362 while (dev1) {
2363 u8 nsect, lbal;
2364
2365 ap->ops->dev_select(ap, 1);
2366 if (ap->flags & ATA_FLAG_MMIO) {
2367 nsect = readb((void __iomem *) ioaddr->nsect_addr);
2368 lbal = readb((void __iomem *) ioaddr->lbal_addr);
2369 } else {
2370 nsect = inb(ioaddr->nsect_addr);
2371 lbal = inb(ioaddr->lbal_addr);
2372 }
2373 if ((nsect == 1) && (lbal == 1))
2374 break;
2375 if (time_after(jiffies, timeout)) {
2376 dev1 = 0;
2377 break;
2378 }
2379 msleep(50); /* give drive a breather */
2380 }
2381 if (dev1)
2382 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
2383
2384 /* is all this really necessary? */
2385 ap->ops->dev_select(ap, 0);
2386 if (dev1)
2387 ap->ops->dev_select(ap, 1);
2388 if (dev0)
2389 ap->ops->dev_select(ap, 0);
2390}
2391
1da177e4
LT		 2392static unsigned int ata_bus_softreset(struct ata_port *ap,
2393 unsigned int devmask)
2394{
2395 struct ata_ioports *ioaddr = &ap->ioaddr;
2396
2397 DPRINTK("ata%u: bus reset via SRST\n", ap->id);
2398
2399 /* software reset. causes dev0 to be selected */
2400 if (ap->flags & ATA_FLAG_MMIO) {
2401 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2402 udelay(20); /* FIXME: flush */
2403 writeb(ap->ctl | ATA_SRST, (void __iomem *) ioaddr->ctl_addr);
2404 udelay(20); /* FIXME: flush */
2405 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2406 } else {
2407 outb(ap->ctl, ioaddr->ctl_addr);
2408 udelay(10);
2409 outb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
2410 udelay(10);
2411 outb(ap->ctl, ioaddr->ctl_addr);
2412 }
2413
2414 /* spec mandates ">= 2ms" before checking status.
2415 * We wait 150ms, because that was the magic delay used for
2416 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
2417 * between when the ATA command register is written, and then
2418 * status is checked. Because waiting for "a while" before
2419 * checking status is fine, post SRST, we perform this magic
2420 * delay here as well.
09c7ad79
AC		 2421 *
2422 * Old drivers/ide uses the 2mS rule and then waits for ready
1da177e4
LT		 2423 */
2424 msleep(150);
2425
2e9edbf8 2426 /* Before we perform post reset processing we want to see if
298a41ca
TH		 2427 * the bus shows 0xFF because the odd clown forgets the D7
2428 * pulldown resistor.
2429 */
987d2f05 2430 if (ata_check_status(ap) == 0xFF) {
f15a1daf 2431 ata_port_printk(ap, KERN_ERR, "SRST failed (status 0xFF)\n");
298a41ca 2432 return AC_ERR_OTHER;
987d2f05 2433 }
09c7ad79 2434
1da177e4
LT		 2435 ata_bus_post_reset(ap, devmask);
2436
2437 return 0;
2438}
2439
2440/**
2441 * ata_bus_reset - reset host port and associated ATA channel
2442 * @ap: port to reset
2443 *
2444 * This is typically the first time we actually start issuing
2445 * commands to the ATA channel. We wait for BSY to clear, then
2446 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
2447 * result. Determine what devices, if any, are on the channel
2448 * by looking at the device 0/1 error register. Look at the signature
2449 * stored in each device's taskfile registers, to determine if
2450 * the device is ATA or ATAPI.
2451 *
2452 * LOCKING:
0cba632b 2453 * PCI/etc. bus probe sem.
cca3974e 2454 * Obtains host lock.
1da177e4
LT		 2455 *
2456 * SIDE EFFECTS:
198e0fed 2457 * Sets ATA_FLAG_DISABLED if bus reset fails.
1da177e4
LT		 2458 */
2459
2460void ata_bus_reset(struct ata_port *ap)
2461{
2462 struct ata_ioports *ioaddr = &ap->ioaddr;
2463 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2464 u8 err;
aec5c3c1 2465 unsigned int dev0, dev1 = 0, devmask = 0;
1da177e4
LT		 2466
2467 DPRINTK("ENTER, host %u, port %u\n", ap->id, ap->port_no);
2468
2469 /* determine if device 0/1 are present */
2470 if (ap->flags & ATA_FLAG_SATA_RESET)
2471 dev0 = 1;
2472 else {
2473 dev0 = ata_devchk(ap, 0);
2474 if (slave_possible)
2475 dev1 = ata_devchk(ap, 1);
2476 }
2477
2478 if (dev0)
2479 devmask |= (1 << 0);
2480 if (dev1)
2481 devmask |= (1 << 1);
2482
2483 /* select device 0 again */
2484 ap->ops->dev_select(ap, 0);
2485
2486 /* issue bus reset */
2487 if (ap->flags & ATA_FLAG_SRST)
aec5c3c1
TH		 2488 if (ata_bus_softreset(ap, devmask))
2489 goto err_out;
1da177e4
LT		 2490
2491 /*
2492 * determine by signature whether we have ATA or ATAPI devices
2493 */
b4dc7623 2494 ap->device[0].class = ata_dev_try_classify(ap, 0, &err);
1da177e4 2495 if ((slave_possible) && (err != 0x81))
b4dc7623 2496 ap->device[1].class = ata_dev_try_classify(ap, 1, &err);
1da177e4
LT		 2497
2498 /* re-enable interrupts */
2499 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
2500 ata_irq_on(ap);
2501
2502 /* is double-select really necessary? */
2503 if (ap->device[1].class != ATA_DEV_NONE)
2504 ap->ops->dev_select(ap, 1);
2505 if (ap->device[0].class != ATA_DEV_NONE)
2506 ap->ops->dev_select(ap, 0);
2507
2508 /* if no devices were detected, disable this port */
2509 if ((ap->device[0].class == ATA_DEV_NONE) &&
2510 (ap->device[1].class == ATA_DEV_NONE))
2511 goto err_out;
2512
2513 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2514 /* set up device control for ATA_FLAG_SATA_RESET */
2515 if (ap->flags & ATA_FLAG_MMIO)
2516 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2517 else
2518 outb(ap->ctl, ioaddr->ctl_addr);
2519 }
2520
2521 DPRINTK("EXIT\n");
2522 return;
2523
2524err_out:
f15a1daf 2525 ata_port_printk(ap, KERN_ERR, "disabling port\n");
1da177e4
LT		 2526 ap->ops->port_disable(ap);
2527
2528 DPRINTK("EXIT\n");
2529}
2530
d7bb4cc7
TH		 2531/**
2532 * sata_phy_debounce - debounce SATA phy status
2533 * @ap: ATA port to debounce SATA phy status for
2534 * @params: timing parameters { interval, duratinon, timeout } in msec
2535 *
2536 * Make sure SStatus of @ap reaches stable state, determined by
2537 * holding the same value where DET is not 1 for @duration polled
2538 * every @interval, before @timeout. Timeout constraints the
2539 * beginning of the stable state. Because, after hot unplugging,
2540 * DET gets stuck at 1 on some controllers, this functions waits
2541 * until timeout then returns 0 if DET is stable at 1.
2542 *
2543 * LOCKING:
2544 * Kernel thread context (may sleep)
2545 *
2546 * RETURNS:
2547 * 0 on success, -errno on failure.
2548 */
2549int sata_phy_debounce(struct ata_port *ap, const unsigned long *params)
7a7921e8 2550{
d7bb4cc7
TH		 2551 unsigned long interval_msec = params[0];
2552 unsigned long duration = params[1] * HZ / 1000;
2553 unsigned long timeout = jiffies + params[2] * HZ / 1000;
2554 unsigned long last_jiffies;
2555 u32 last, cur;
2556 int rc;
2557
2558 if ((rc = sata_scr_read(ap, SCR_STATUS, &cur)))
2559 return rc;
2560 cur &= 0xf;
2561
2562 last = cur;
2563 last_jiffies = jiffies;
2564
2565 while (1) {
2566 msleep(interval_msec);
2567 if ((rc = sata_scr_read(ap, SCR_STATUS, &cur)))
2568 return rc;
2569 cur &= 0xf;
2570
2571 /* DET stable? */
2572 if (cur == last) {
2573 if (cur == 1 && time_before(jiffies, timeout))
2574 continue;
2575 if (time_after(jiffies, last_jiffies + duration))
2576 return 0;
2577 continue;
2578 }
2579
2580 /* unstable, start over */
2581 last = cur;
2582 last_jiffies = jiffies;
2583
2584 /* check timeout */
2585 if (time_after(jiffies, timeout))
2586 return -EBUSY;
2587 }
2588}
2589
2590/**
2591 * sata_phy_resume - resume SATA phy
2592 * @ap: ATA port to resume SATA phy for
2593 * @params: timing parameters { interval, duratinon, timeout } in msec
2594 *
2595 * Resume SATA phy of @ap and debounce it.
2596 *
2597 * LOCKING:
2598 * Kernel thread context (may sleep)
2599 *
2600 * RETURNS:
2601 * 0 on success, -errno on failure.
2602 */
2603int sata_phy_resume(struct ata_port *ap, const unsigned long *params)
2604{
2605 u32 scontrol;
81952c54
TH		 2606 int rc;
2607
2608 if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
2609 return rc;
7a7921e8 2610
852ee16a 2611 scontrol = (scontrol & 0x0f0) | 0x300;
81952c54
TH		 2612
2613 if ((rc = sata_scr_write(ap, SCR_CONTROL, scontrol)))
2614 return rc;
7a7921e8 2615
d7bb4cc7
TH		 2616 /* Some PHYs react badly if SStatus is pounded immediately
2617 * after resuming. Delay 200ms before debouncing.
2618 */
2619 msleep(200);
7a7921e8 2620
d7bb4cc7 2621 return sata_phy_debounce(ap, params);
7a7921e8
TH		 2622}
2623
f5914a46
TH		 2624static void ata_wait_spinup(struct ata_port *ap)
2625{
2626 struct ata_eh_context *ehc = &ap->eh_context;
2627 unsigned long end, secs;
2628 int rc;
2629
2630 /* first, debounce phy if SATA */
2631 if (ap->cbl == ATA_CBL_SATA) {
e9c83914 2632 rc = sata_phy_debounce(ap, sata_deb_timing_hotplug);
f5914a46
TH		 2633
2634 /* if debounced successfully and offline, no need to wait */
2635 if ((rc == 0 || rc == -EOPNOTSUPP) && ata_port_offline(ap))
2636 return;
2637 }
2638
2639 /* okay, let's give the drive time to spin up */
2640 end = ehc->i.hotplug_timestamp + ATA_SPINUP_WAIT * HZ / 1000;
2641 secs = ((end - jiffies) + HZ - 1) / HZ;
2642
2643 if (time_after(jiffies, end))
2644 return;
2645
2646 if (secs > 5)
2647 ata_port_printk(ap, KERN_INFO, "waiting for device to spin up "
2648 "(%lu secs)\n", secs);
2649
2650 schedule_timeout_uninterruptible(end - jiffies);
2651}
2652
2653/**
2654 * ata_std_prereset - prepare for reset
2655 * @ap: ATA port to be reset
2656 *
2657 * @ap is about to be reset. Initialize it.
2658 *
2659 * LOCKING:
2660 * Kernel thread context (may sleep)
2661 *
2662 * RETURNS:
2663 * 0 on success, -errno otherwise.
2664 */
2665int ata_std_prereset(struct ata_port *ap)
2666{
2667 struct ata_eh_context *ehc = &ap->eh_context;
e9c83914 2668 const unsigned long *timing = sata_ehc_deb_timing(ehc);
f5914a46
TH		 2669 int rc;
2670
28324304
TH		 2671 /* handle link resume & hotplug spinup */
2672 if ((ehc->i.flags & ATA_EHI_RESUME_LINK) &&
2673 (ap->flags & ATA_FLAG_HRST_TO_RESUME))
2674 ehc->i.action |= ATA_EH_HARDRESET;
2675
2676 if ((ehc->i.flags & ATA_EHI_HOTPLUGGED) &&
2677 (ap->flags & ATA_FLAG_SKIP_D2H_BSY))
2678 ata_wait_spinup(ap);
f5914a46
TH		 2679
2680 /* if we're about to do hardreset, nothing more to do */
2681 if (ehc->i.action & ATA_EH_HARDRESET)
2682 return 0;
2683
2684 /* if SATA, resume phy */
2685 if (ap->cbl == ATA_CBL_SATA) {
f5914a46
TH		 2686 rc = sata_phy_resume(ap, timing);
2687 if (rc && rc != -EOPNOTSUPP) {
2688 /* phy resume failed */
2689 ata_port_printk(ap, KERN_WARNING, "failed to resume "
2690 "link for reset (errno=%d)\n", rc);
2691 return rc;
2692 }
2693 }
2694
2695 /* Wait for !BSY if the controller can wait for the first D2H
2696 * Reg FIS and we don't know that no device is attached.
2697 */
2698 if (!(ap->flags & ATA_FLAG_SKIP_D2H_BSY) && !ata_port_offline(ap))
2699 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
2700
2701 return 0;
2702}
2703
c2bd5804
TH		 2704/**
2705 * ata_std_softreset - reset host port via ATA SRST
2706 * @ap: port to reset
c2bd5804
TH		 2707 * @classes: resulting classes of attached devices
2708 *
52783c5d 2709 * Reset host port using ATA SRST.
c2bd5804
TH		 2710 *
2711 * LOCKING:
2712 * Kernel thread context (may sleep)
2713 *
2714 * RETURNS:
2715 * 0 on success, -errno otherwise.
2716 */
2bf2cb26 2717int ata_std_softreset(struct ata_port *ap, unsigned int *classes)
c2bd5804
TH		 2718{
2719 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2720 unsigned int devmask = 0, err_mask;
2721 u8 err;
2722
2723 DPRINTK("ENTER\n");
2724
81952c54 2725 if (ata_port_offline(ap)) {
3a39746a
TH		 2726 classes[0] = ATA_DEV_NONE;
2727 goto out;
2728 }
2729
c2bd5804
TH		 2730 /* determine if device 0/1 are present */
2731 if (ata_devchk(ap, 0))
2732 devmask |= (1 << 0);
2733 if (slave_possible && ata_devchk(ap, 1))
2734 devmask |= (1 << 1);
2735
c2bd5804
TH		 2736 /* select device 0 again */
2737 ap->ops->dev_select(ap, 0);
2738
2739 /* issue bus reset */
2740 DPRINTK("about to softreset, devmask=%x\n", devmask);
2741 err_mask = ata_bus_softreset(ap, devmask);
2742 if (err_mask) {
f15a1daf
TH		 2743 ata_port_printk(ap, KERN_ERR, "SRST failed (err_mask=0x%x)\n",
2744 err_mask);
c2bd5804
TH		 2745 return -EIO;
2746 }
2747
2748 /* determine by signature whether we have ATA or ATAPI devices */
2749 classes[0] = ata_dev_try_classify(ap, 0, &err);
2750 if (slave_possible && err != 0x81)
2751 classes[1] = ata_dev_try_classify(ap, 1, &err);
2752
3a39746a 2753 out:
c2bd5804
TH		 2754 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2755 return 0;
2756}
2757
2758/**
2759 * sata_std_hardreset - reset host port via SATA phy reset
2760 * @ap: port to reset
c2bd5804
TH		 2761 * @class: resulting class of attached device
2762 *
2763 * SATA phy-reset host port using DET bits of SControl register.
c2bd5804
TH		 2764 *
2765 * LOCKING:
2766 * Kernel thread context (may sleep)
2767 *
2768 * RETURNS:
2769 * 0 on success, -errno otherwise.
2770 */
2bf2cb26 2771int sata_std_hardreset(struct ata_port *ap, unsigned int *class)
c2bd5804 2772{
e9c83914
TH		 2773 struct ata_eh_context *ehc = &ap->eh_context;
2774 const unsigned long *timing = sata_ehc_deb_timing(ehc);
852ee16a 2775 u32 scontrol;
81952c54 2776 int rc;
852ee16a 2777
c2bd5804
TH		 2778 DPRINTK("ENTER\n");
2779
3c567b7d 2780 if (sata_set_spd_needed(ap)) {
1c3fae4d
TH		 2781 /* SATA spec says nothing about how to reconfigure
2782 * spd. To be on the safe side, turn off phy during
2783 * reconfiguration. This works for at least ICH7 AHCI
2784 * and Sil3124.
2785 */
81952c54
TH		 2786 if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
2787 return rc;
2788
a34b6fc0 2789 scontrol = (scontrol & 0x0f0) | 0x304;
81952c54
TH		 2790
2791 if ((rc = sata_scr_write(ap, SCR_CONTROL, scontrol)))
2792 return rc;
1c3fae4d 2793
3c567b7d 2794 sata_set_spd(ap);
1c3fae4d
TH		 2795 }
2796
2797 /* issue phy wake/reset */
81952c54
TH		 2798 if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
2799 return rc;
2800
852ee16a 2801 scontrol = (scontrol & 0x0f0) | 0x301;
81952c54
TH		 2802
2803 if ((rc = sata_scr_write_flush(ap, SCR_CONTROL, scontrol)))
2804 return rc;
c2bd5804 2805
1c3fae4d 2806 /* Couldn't find anything in SATA I/II specs, but AHCI-1.1
c2bd5804
TH		 2807 * 10.4.2 says at least 1 ms.
2808 */
2809 msleep(1);
2810
1c3fae4d 2811 /* bring phy back */
e9c83914 2812 sata_phy_resume(ap, timing);
c2bd5804 2813
c2bd5804 2814 /* TODO: phy layer with polling, timeouts, etc. */
81952c54 2815 if (ata_port_offline(ap)) {
c2bd5804
TH		 2816 *class = ATA_DEV_NONE;
2817 DPRINTK("EXIT, link offline\n");
2818 return 0;
2819 }
2820
2821 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
f15a1daf
TH		 2822 ata_port_printk(ap, KERN_ERR,
2823 "COMRESET failed (device not ready)\n");
c2bd5804
TH		 2824 return -EIO;
2825 }
2826
3a39746a
TH		 2827 ap->ops->dev_select(ap, 0); /* probably unnecessary */
2828
c2bd5804
TH		 2829 *class = ata_dev_try_classify(ap, 0, NULL);
2830
2831 DPRINTK("EXIT, class=%u\n", *class);
2832 return 0;
2833}
2834
2835/**
2836 * ata_std_postreset - standard postreset callback
2837 * @ap: the target ata_port
2838 * @classes: classes of attached devices
2839 *
2840 * This function is invoked after a successful reset. Note that
2841 * the device might have been reset more than once using
2842 * different reset methods before postreset is invoked.
c2bd5804 2843 *
c2bd5804
TH		 2844 * LOCKING:
2845 * Kernel thread context (may sleep)
2846 */
2847void ata_std_postreset(struct ata_port *ap, unsigned int *classes)
2848{
dc2b3515
TH		 2849 u32 serror;
2850
c2bd5804
TH		 2851 DPRINTK("ENTER\n");
2852
c2bd5804 2853 /* print link status */
81952c54 2854 sata_print_link_status(ap);
c2bd5804 2855
dc2b3515
TH		 2856 /* clear SError */
2857 if (sata_scr_read(ap, SCR_ERROR, &serror) == 0)
2858 sata_scr_write(ap, SCR_ERROR, serror);
2859
3a39746a 2860 /* re-enable interrupts */
e3180499
TH		 2861 if (!ap->ops->error_handler) {
2862 /* FIXME: hack. create a hook instead */
2863 if (ap->ioaddr.ctl_addr)
2864 ata_irq_on(ap);
2865 }
c2bd5804
TH		 2866
2867 /* is double-select really necessary? */
2868 if (classes[0] != ATA_DEV_NONE)
2869 ap->ops->dev_select(ap, 1);
2870 if (classes[1] != ATA_DEV_NONE)
2871 ap->ops->dev_select(ap, 0);
2872
3a39746a
TH		 2873 /* bail out if no device is present */
2874 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2875 DPRINTK("EXIT, no device\n");
2876 return;
2877 }
2878
2879 /* set up device control */
2880 if (ap->ioaddr.ctl_addr) {
2881 if (ap->flags & ATA_FLAG_MMIO)
2882 writeb(ap->ctl, (void __iomem *) ap->ioaddr.ctl_addr);
2883 else
2884 outb(ap->ctl, ap->ioaddr.ctl_addr);
2885 }
c2bd5804
TH		 2886
2887 DPRINTK("EXIT\n");
2888}
2889
623a3128
TH		 2890/**
2891 * ata_dev_same_device - Determine whether new ID matches configured device
623a3128
TH		 2892 * @dev: device to compare against
2893 * @new_class: class of the new device
2894 * @new_id: IDENTIFY page of the new device
2895 *
2896 * Compare @new_class and @new_id against @dev and determine
2897 * whether @dev is the device indicated by @new_class and
2898 * @new_id.
2899 *
2900 * LOCKING:
2901 * None.
2902 *
2903 * RETURNS:
2904 * 1 if @dev matches @new_class and @new_id, 0 otherwise.
2905 */
3373efd8
TH		 2906static int ata_dev_same_device(struct ata_device *dev, unsigned int new_class,
2907 const u16 *new_id)
623a3128
TH		 2908{
2909 const u16 *old_id = dev->id;
2910 unsigned char model[2][41], serial[2][21];
2911 u64 new_n_sectors;
2912
2913 if (dev->class != new_class) {
f15a1daf
TH		 2914 ata_dev_printk(dev, KERN_INFO, "class mismatch %d != %d\n",
2915 dev->class, new_class);
623a3128
TH		 2916 return 0;
2917 }
2918
2919 ata_id_c_string(old_id, model[0], ATA_ID_PROD_OFS, sizeof(model[0]));
2920 ata_id_c_string(new_id, model[1], ATA_ID_PROD_OFS, sizeof(model[1]));
2921 ata_id_c_string(old_id, serial[0], ATA_ID_SERNO_OFS, sizeof(serial[0]));
2922 ata_id_c_string(new_id, serial[1], ATA_ID_SERNO_OFS, sizeof(serial[1]));
2923 new_n_sectors = ata_id_n_sectors(new_id);
2924
2925 if (strcmp(model[0], model[1])) {
f15a1daf
TH		 2926 ata_dev_printk(dev, KERN_INFO, "model number mismatch "
2927 "'%s' != '%s'\n", model[0], model[1]);
623a3128
TH		 2928 return 0;
2929 }
2930
2931 if (strcmp(serial[0], serial[1])) {
f15a1daf
TH		 2932 ata_dev_printk(dev, KERN_INFO, "serial number mismatch "
2933 "'%s' != '%s'\n", serial[0], serial[1]);
623a3128
TH		 2934 return 0;
2935 }
2936
2937 if (dev->class == ATA_DEV_ATA && dev->n_sectors != new_n_sectors) {
f15a1daf
TH		 2938 ata_dev_printk(dev, KERN_INFO, "n_sectors mismatch "
2939 "%llu != %llu\n",
2940 (unsigned long long)dev->n_sectors,
2941 (unsigned long long)new_n_sectors);
623a3128
TH		 2942 return 0;
2943 }
2944
2945 return 1;
2946}
2947
2948/**
2949 * ata_dev_revalidate - Revalidate ATA device
623a3128
TH		 2950 * @dev: device to revalidate
2951 * @post_reset: is this revalidation after reset?
2952 *
2953 * Re-read IDENTIFY page and make sure @dev is still attached to
2954 * the port.
2955 *
2956 * LOCKING:
2957 * Kernel thread context (may sleep)
2958 *
2959 * RETURNS:
2960 * 0 on success, negative errno otherwise
2961 */
3373efd8 2962int ata_dev_revalidate(struct ata_device *dev, int post_reset)
623a3128 2963{
5eb45c02 2964 unsigned int class = dev->class;
f15a1daf 2965 u16 *id = (void *)dev->ap->sector_buf;
623a3128
TH		 2966 int rc;
2967
5eb45c02
TH		 2968 if (!ata_dev_enabled(dev)) {
2969 rc = -ENODEV;
2970 goto fail;
2971 }
623a3128 2972
fe635c7e 2973 /* read ID data */
3373efd8 2974 rc = ata_dev_read_id(dev, &class, post_reset, id);
623a3128
TH		 2975 if (rc)
2976 goto fail;
2977
2978 /* is the device still there? */
3373efd8 2979 if (!ata_dev_same_device(dev, class, id)) {
623a3128
TH		 2980 rc = -ENODEV;
2981 goto fail;
2982 }
2983
fe635c7e 2984 memcpy(dev->id, id, sizeof(id[0]) * ATA_ID_WORDS);
623a3128
TH		 2985
2986 /* configure device according to the new ID */
3373efd8 2987 rc = ata_dev_configure(dev, 0);
5eb45c02
TH		 2988 if (rc == 0)
2989 return 0;
623a3128
TH		 2990
2991 fail:
f15a1daf 2992 ata_dev_printk(dev, KERN_ERR, "revalidation failed (errno=%d)\n", rc);
623a3128
TH		 2993 return rc;
2994}
2995
98ac62de 2996static const char * const ata_dma_blacklist [] = {
f4b15fef
AC		 2997 "WDC AC11000H", NULL,
2998 "WDC AC22100H", NULL,
2999 "WDC AC32500H", NULL,
3000 "WDC AC33100H", NULL,
3001 "WDC AC31600H", NULL,
3002 "WDC AC32100H", "24.09P07",
3003 "WDC AC23200L", "21.10N21",
3004 "Compaq CRD-8241B", NULL,
3005 "CRD-8400B", NULL,
3006 "CRD-8480B", NULL,
3007 "CRD-8482B", NULL,
3008 "CRD-84", NULL,
3009 "SanDisk SDP3B", NULL,
3010 "SanDisk SDP3B-64", NULL,
3011 "SANYO CD-ROM CRD", NULL,
3012 "HITACHI CDR-8", NULL,
2e9edbf8 3013 "HITACHI CDR-8335", NULL,
f4b15fef 3014 "HITACHI CDR-8435", NULL,
2e9edbf8
JG		 3015 "Toshiba CD-ROM XM-6202B", NULL,
3016 "TOSHIBA CD-ROM XM-1702BC", NULL,
3017 "CD-532E-A", NULL,
3018 "E-IDE CD-ROM CR-840", NULL,
3019 "CD-ROM Drive/F5A", NULL,
3020 "WPI CDD-820", NULL,
f4b15fef 3021 "SAMSUNG CD-ROM SC-148C", NULL,
2e9edbf8 3022 "SAMSUNG CD-ROM SC", NULL,
f4b15fef
AC		 3023 "SanDisk SDP3B-64", NULL,
3024 "ATAPI CD-ROM DRIVE 40X MAXIMUM",NULL,
3025 "_NEC DV5800A", NULL,
3026 "SAMSUNG CD-ROM SN-124", "N001"
1da177e4 3027};
2e9edbf8 3028
f4b15fef
AC		 3029static int ata_strim(char *s, size_t len)
3030{
3031 len = strnlen(s, len);
3032
3033 /* ATAPI specifies that empty space is blank-filled; remove blanks */
3034 while ((len > 0) && (s[len - 1] == ' ')) {
3035 len--;
3036 s[len] = 0;
3037 }
3038 return len;
3039}
1da177e4 3040
057ace5e 3041static int ata_dma_blacklisted(const struct ata_device *dev)
1da177e4 3042{
f4b15fef
AC		 3043 unsigned char model_num[40];
3044 unsigned char model_rev[16];
3045 unsigned int nlen, rlen;
1da177e4
LT		 3046 int i;
3047
3a778275
AL		 3048 /* We don't support polling DMA.
3049 * DMA blacklist those ATAPI devices with CDB-intr (and use PIO)
3050 * if the LLDD handles only interrupts in the HSM_ST_LAST state.
3051 */
3052 if ((dev->ap->flags & ATA_FLAG_PIO_POLLING) &&
3053 (dev->flags & ATA_DFLAG_CDB_INTR))
3054 return 1;
3055
f4b15fef
AC		 3056 ata_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
3057 sizeof(model_num));
3058 ata_id_string(dev->id, model_rev, ATA_ID_FW_REV_OFS,
3059 sizeof(model_rev));
3060 nlen = ata_strim(model_num, sizeof(model_num));
3061 rlen = ata_strim(model_rev, sizeof(model_rev));
1da177e4 3062
f4b15fef
AC		 3063 for (i = 0; i < ARRAY_SIZE(ata_dma_blacklist); i += 2) {
3064 if (!strncmp(ata_dma_blacklist[i], model_num, nlen)) {
3065 if (ata_dma_blacklist[i+1] == NULL)
3066 return 1;
3067 if (!strncmp(ata_dma_blacklist[i], model_rev, rlen))
3068 return 1;
3069 }
3070 }
1da177e4
LT		 3071 return 0;
3072}
3073
a6d5a51c
TH		 3074/**
3075 * ata_dev_xfermask - Compute supported xfermask of the given device
a6d5a51c
TH		 3076 * @dev: Device to compute xfermask for
3077 *
acf356b1
TH		 3078 * Compute supported xfermask of @dev and store it in
3079 * dev->*_mask. This function is responsible for applying all
3080 * known limits including host controller limits, device
3081 * blacklist, etc...
a6d5a51c
TH		 3082 *
3083 * LOCKING:
3084 * None.
a6d5a51c 3085 */
3373efd8 3086static void ata_dev_xfermask(struct ata_device *dev)
1da177e4 3087{
3373efd8 3088 struct ata_port *ap = dev->ap;
cca3974e 3089 struct ata_host *host = ap->host;
a6d5a51c 3090 unsigned long xfer_mask;
1da177e4 3091
37deecb5 3092 /* controller modes available */
565083e1
TH		 3093 xfer_mask = ata_pack_xfermask(ap->pio_mask,
3094 ap->mwdma_mask, ap->udma_mask);
3095
3096 /* Apply cable rule here. Don't apply it early because when
3097 * we handle hot plug the cable type can itself change.
3098 */
3099 if (ap->cbl == ATA_CBL_PATA40)
3100 xfer_mask &= ~(0xF8 << ATA_SHIFT_UDMA);
1da177e4 3101
37deecb5
TH		 3102 xfer_mask &= ata_pack_xfermask(dev->pio_mask,
3103 dev->mwdma_mask, dev->udma_mask);
3104 xfer_mask &= ata_id_xfermask(dev->id);
565083e1 3105
b352e57d
AC		 3106 /*
3107 * CFA Advanced TrueIDE timings are not allowed on a shared
3108 * cable
3109 */
3110 if (ata_dev_pair(dev)) {
3111 /* No PIO5 or PIO6 */
3112 xfer_mask &= ~(0x03 << (ATA_SHIFT_PIO + 5));
3113 /* No MWDMA3 or MWDMA 4 */
3114 xfer_mask &= ~(0x03 << (ATA_SHIFT_MWDMA + 3));
3115 }
3116
37deecb5
TH		 3117 if (ata_dma_blacklisted(dev)) {
3118 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
f15a1daf
TH		 3119 ata_dev_printk(dev, KERN_WARNING,
3120 "device is on DMA blacklist, disabling DMA\n");
37deecb5 3121 }
a6d5a51c 3122
cca3974e 3123 if ((host->flags & ATA_HOST_SIMPLEX) && host->simplex_claimed) {
37deecb5
TH		 3124 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
3125 ata_dev_printk(dev, KERN_WARNING, "simplex DMA is claimed by "
3126 "other device, disabling DMA\n");
5444a6f4 3127 }
565083e1 3128
5444a6f4
AC		 3129 if (ap->ops->mode_filter)
3130 xfer_mask = ap->ops->mode_filter(ap, dev, xfer_mask);
3131
565083e1
TH		 3132 ata_unpack_xfermask(xfer_mask, &dev->pio_mask,
3133 &dev->mwdma_mask, &dev->udma_mask);
1da177e4
LT		 3134}
3135
1da177e4
LT		 3136/**
3137 * ata_dev_set_xfermode - Issue SET FEATURES - XFER MODE command
1da177e4
LT		 3138 * @dev: Device to which command will be sent
3139 *
780a87f7
JG		 3140 * Issue SET FEATURES - XFER MODE command to device @dev
3141 * on port @ap.
3142 *
1da177e4 3143 * LOCKING:
0cba632b 3144 * PCI/etc. bus probe sem.
83206a29
TH		 3145 *
3146 * RETURNS:
3147 * 0 on success, AC_ERR_* mask otherwise.
1da177e4
LT		 3148 */
3149
3373efd8 3150static unsigned int ata_dev_set_xfermode(struct ata_device *dev)
1da177e4 3151{
a0123703 3152 struct ata_taskfile tf;
83206a29 3153 unsigned int err_mask;
1da177e4
LT		 3154
3155 /* set up set-features taskfile */
3156 DPRINTK("set features - xfer mode\n");
3157
3373efd8 3158 ata_tf_init(dev, &tf);
a0123703
TH		 3159 tf.command = ATA_CMD_SET_FEATURES;
3160 tf.feature = SETFEATURES_XFER;
3161 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
3162 tf.protocol = ATA_PROT_NODATA;
3163 tf.nsect = dev->xfer_mode;
1da177e4 3164
3373efd8 3165 err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0);
1da177e4 3166
83206a29
TH		 3167 DPRINTK("EXIT, err_mask=%x\n", err_mask);
3168 return err_mask;
1da177e4
LT		 3169}
3170
8bf62ece
AL		 3171/**
3172 * ata_dev_init_params - Issue INIT DEV PARAMS command
8bf62ece 3173 * @dev: Device to which command will be sent
e2a7f77a
RD		 3174 * @heads: Number of heads (taskfile parameter)
3175 * @sectors: Number of sectors (taskfile parameter)
8bf62ece
AL		 3176 *
3177 * LOCKING:
6aff8f1f
TH		 3178 * Kernel thread context (may sleep)
3179 *
3180 * RETURNS:
3181 * 0 on success, AC_ERR_* mask otherwise.
8bf62ece 3182 */
3373efd8
TH		 3183static unsigned int ata_dev_init_params(struct ata_device *dev,
3184 u16 heads, u16 sectors)
8bf62ece 3185{
a0123703 3186 struct ata_taskfile tf;
6aff8f1f 3187 unsigned int err_mask;
8bf62ece
AL		 3188
3189 /* Number of sectors per track 1-255. Number of heads 1-16 */
3190 if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
00b6f5e9 3191 return AC_ERR_INVALID;
8bf62ece
AL		 3192
3193 /* set up init dev params taskfile */
3194 DPRINTK("init dev params \n");
3195
3373efd8 3196 ata_tf_init(dev, &tf);
a0123703
TH		 3197 tf.command = ATA_CMD_INIT_DEV_PARAMS;
3198 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
3199 tf.protocol = ATA_PROT_NODATA;
3200 tf.nsect = sectors;
3201 tf.device |= (heads - 1) & 0x0f; /* max head = num. of heads - 1 */
8bf62ece 3202
3373efd8 3203 err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0);
8bf62ece 3204
6aff8f1f
TH		 3205 DPRINTK("EXIT, err_mask=%x\n", err_mask);
3206 return err_mask;
8bf62ece
AL		 3207}
3208
1da177e4 3209/**
0cba632b
JG		 3210 * ata_sg_clean - Unmap DMA memory associated with command
3211 * @qc: Command containing DMA memory to be released
3212 *
3213 * Unmap all mapped DMA memory associated with this command.
1da177e4
LT		 3214 *
3215 * LOCKING:
cca3974e 3216 * spin_lock_irqsave(host lock)
1da177e4
LT		 3217 */
3218
3219static void ata_sg_clean(struct ata_queued_cmd *qc)
3220{
3221 struct ata_port *ap = qc->ap;
cedc9a47 3222 struct scatterlist *sg = qc->__sg;
1da177e4 3223 int dir = qc->dma_dir;
cedc9a47 3224 void *pad_buf = NULL;
1da177e4 3225
a4631474
TH		 3226 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
3227 WARN_ON(sg == NULL);
1da177e4
LT		 3228
3229 if (qc->flags & ATA_QCFLAG_SINGLE)
f131883e 3230 WARN_ON(qc->n_elem > 1);
1da177e4 3231
2c13b7ce 3232 VPRINTK("unmapping %u sg elements\n", qc->n_elem);
1da177e4 3233
cedc9a47
JG		 3234 /* if we padded the buffer out to 32-bit bound, and data
3235 * xfer direction is from-device, we must copy from the
3236 * pad buffer back into the supplied buffer
3237 */
3238 if (qc->pad_len && !(qc->tf.flags & ATA_TFLAG_WRITE))
3239 pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
3240
3241 if (qc->flags & ATA_QCFLAG_SG) {
e1410f2d 3242 if (qc->n_elem)
2f1f610b 3243 dma_unmap_sg(ap->dev, sg, qc->n_elem, dir);
cedc9a47
JG		 3244 /* restore last sg */
3245 sg[qc->orig_n_elem - 1].length += qc->pad_len;
3246 if (pad_buf) {
3247 struct scatterlist *psg = &qc->pad_sgent;
3248 void *addr = kmap_atomic(psg->page, KM_IRQ0);
3249 memcpy(addr + psg->offset, pad_buf, qc->pad_len);
dfa15988 3250 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 3251 }
3252 } else {
2e242fa9 3253 if (qc->n_elem)
2f1f610b 3254 dma_unmap_single(ap->dev,
e1410f2d
JG		 3255 sg_dma_address(&sg[0]), sg_dma_len(&sg[0]),
3256 dir);
cedc9a47
JG		 3257 /* restore sg */
3258 sg->length += qc->pad_len;
3259 if (pad_buf)
3260 memcpy(qc->buf_virt + sg->length - qc->pad_len,
3261 pad_buf, qc->pad_len);
3262 }
1da177e4
LT		 3263
3264 qc->flags &= ~ATA_QCFLAG_DMAMAP;
cedc9a47 3265 qc->__sg = NULL;
1da177e4
LT		 3266}
3267
3268/**
3269 * ata_fill_sg - Fill PCI IDE PRD table
3270 * @qc: Metadata associated with taskfile to be transferred
3271 *
780a87f7
JG		 3272 * Fill PCI IDE PRD (scatter-gather) table with segments
3273 * associated with the current disk command.
3274 *
1da177e4 3275 * LOCKING:
cca3974e 3276 * spin_lock_irqsave(host lock)
1da177e4
LT		 3277 *
3278 */
3279static void ata_fill_sg(struct ata_queued_cmd *qc)
3280{
1da177e4 3281 struct ata_port *ap = qc->ap;
cedc9a47
JG		 3282 struct scatterlist *sg;
3283 unsigned int idx;
1da177e4 3284
a4631474 3285 WARN_ON(qc->__sg == NULL);
f131883e 3286 WARN_ON(qc->n_elem == 0 && qc->pad_len == 0);
1da177e4
LT		 3287
3288 idx = 0;
cedc9a47 3289 ata_for_each_sg(sg, qc) {
1da177e4
LT		 3290 u32 addr, offset;
3291 u32 sg_len, len;
3292
3293 /* determine if physical DMA addr spans 64K boundary.
3294 * Note h/w doesn't support 64-bit, so we unconditionally
3295 * truncate dma_addr_t to u32.
3296 */
3297 addr = (u32) sg_dma_address(sg);
3298 sg_len = sg_dma_len(sg);
3299
3300 while (sg_len) {
3301 offset = addr & 0xffff;
3302 len = sg_len;
3303 if ((offset + sg_len) > 0x10000)
3304 len = 0x10000 - offset;
3305
3306 ap->prd[idx].addr = cpu_to_le32(addr);
3307 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
3308 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
3309
3310 idx++;
3311 sg_len -= len;
3312 addr += len;
3313 }
3314 }
3315
3316 if (idx)
3317 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
3318}
3319/**
3320 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported
3321 * @qc: Metadata associated with taskfile to check
3322 *
780a87f7
JG		 3323 * Allow low-level driver to filter ATA PACKET commands, returning
3324 * a status indicating whether or not it is OK to use DMA for the
3325 * supplied PACKET command.
3326 *
1da177e4 3327 * LOCKING:
cca3974e 3328 * spin_lock_irqsave(host lock)
0cba632b 3329 *
1da177e4
LT		 3330 * RETURNS: 0 when ATAPI DMA can be used
3331 * nonzero otherwise
3332 */
3333int ata_check_atapi_dma(struct ata_queued_cmd *qc)
3334{
3335 struct ata_port *ap = qc->ap;
3336 int rc = 0; /* Assume ATAPI DMA is OK by default */
3337
3338 if (ap->ops->check_atapi_dma)
3339 rc = ap->ops->check_atapi_dma(qc);
3340
3341 return rc;
3342}
3343/**
3344 * ata_qc_prep - Prepare taskfile for submission
3345 * @qc: Metadata associated with taskfile to be prepared
3346 *
780a87f7
JG		 3347 * Prepare ATA taskfile for submission.
3348 *
1da177e4 3349 * LOCKING:
cca3974e 3350 * spin_lock_irqsave(host lock)
1da177e4
LT		 3351 */
3352void ata_qc_prep(struct ata_queued_cmd *qc)
3353{
3354 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
3355 return;
3356
3357 ata_fill_sg(qc);
3358}
3359
e46834cd
BK		 3360void ata_noop_qc_prep(struct ata_queued_cmd *qc) { }
3361
0cba632b
JG		 3362/**
3363 * ata_sg_init_one - Associate command with memory buffer
3364 * @qc: Command to be associated
3365 * @buf: Memory buffer
3366 * @buflen: Length of memory buffer, in bytes.
3367 *
3368 * Initialize the data-related elements of queued_cmd @qc
3369 * to point to a single memory buffer, @buf of byte length @buflen.
3370 *
3371 * LOCKING:
cca3974e 3372 * spin_lock_irqsave(host lock)
0cba632b
JG		 3373 */
3374
1da177e4
LT		 3375void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf, unsigned int buflen)
3376{
3377 struct scatterlist *sg;
3378
3379 qc->flags |= ATA_QCFLAG_SINGLE;
3380
3381 memset(&qc->sgent, 0, sizeof(qc->sgent));
cedc9a47 3382 qc->__sg = &qc->sgent;
1da177e4 3383 qc->n_elem = 1;
cedc9a47 3384 qc->orig_n_elem = 1;
1da177e4 3385 qc->buf_virt = buf;
233277ca 3386 qc->nbytes = buflen;
1da177e4 3387
cedc9a47 3388 sg = qc->__sg;
f0612bbc 3389 sg_init_one(sg, buf, buflen);
1da177e4
LT		 3390}
3391
0cba632b
JG		 3392/**
3393 * ata_sg_init - Associate command with scatter-gather table.
3394 * @qc: Command to be associated
3395 * @sg: Scatter-gather table.
3396 * @n_elem: Number of elements in s/g table.
3397 *
3398 * Initialize the data-related elements of queued_cmd @qc
3399 * to point to a scatter-gather table @sg, containing @n_elem
3400 * elements.
3401 *
3402 * LOCKING:
cca3974e 3403 * spin_lock_irqsave(host lock)
0cba632b
JG		 3404 */
3405
1da177e4
LT		 3406void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
3407 unsigned int n_elem)
3408{
3409 qc->flags |= ATA_QCFLAG_SG;
cedc9a47 3410 qc->__sg = sg;
1da177e4 3411 qc->n_elem = n_elem;
cedc9a47 3412 qc->orig_n_elem = n_elem;
1da177e4
LT		 3413}
3414
3415/**
0cba632b
JG		 3416 * ata_sg_setup_one - DMA-map the memory buffer associated with a command.
3417 * @qc: Command with memory buffer to be mapped.
3418 *
3419 * DMA-map the memory buffer associated with queued_cmd @qc.
1da177e4
LT		 3420 *
3421 * LOCKING:
cca3974e 3422 * spin_lock_irqsave(host lock)
1da177e4
LT		 3423 *
3424 * RETURNS:
0cba632b 3425 * Zero on success, negative on error.
1da177e4
LT		 3426 */
3427
3428static int ata_sg_setup_one(struct ata_queued_cmd *qc)
3429{
3430 struct ata_port *ap = qc->ap;
3431 int dir = qc->dma_dir;
cedc9a47 3432 struct scatterlist *sg = qc->__sg;
1da177e4 3433 dma_addr_t dma_address;
2e242fa9 3434 int trim_sg = 0;
1da177e4 3435
cedc9a47
JG		 3436 /* we must lengthen transfers to end on a 32-bit boundary */
3437 qc->pad_len = sg->length & 3;
3438 if (qc->pad_len) {
3439 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
3440 struct scatterlist *psg = &qc->pad_sgent;
3441
a4631474 3442 WARN_ON(qc->dev->class != ATA_DEV_ATAPI);
cedc9a47
JG		 3443
3444 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
3445
3446 if (qc->tf.flags & ATA_TFLAG_WRITE)
3447 memcpy(pad_buf, qc->buf_virt + sg->length - qc->pad_len,
3448 qc->pad_len);
3449
3450 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
3451 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
3452 /* trim sg */
3453 sg->length -= qc->pad_len;
2e242fa9
TH		 3454 if (sg->length == 0)
3455 trim_sg = 1;
cedc9a47
JG		 3456
3457 DPRINTK("padding done, sg->length=%u pad_len=%u\n",
3458 sg->length, qc->pad_len);
3459 }
3460
2e242fa9
TH		 3461 if (trim_sg) {
3462 qc->n_elem--;
e1410f2d
JG		 3463 goto skip_map;
3464 }
3465
2f1f610b 3466 dma_address = dma_map_single(ap->dev, qc->buf_virt,
32529e01 3467 sg->length, dir);
537a95d9
TH		 3468 if (dma_mapping_error(dma_address)) {
3469 /* restore sg */
3470 sg->length += qc->pad_len;
1da177e4 3471 return -1;
537a95d9 3472 }
1da177e4
LT		 3473
3474 sg_dma_address(sg) = dma_address;
32529e01 3475 sg_dma_len(sg) = sg->length;
1da177e4 3476
2e242fa9 3477skip_map:
1da177e4
LT		 3478 DPRINTK("mapped buffer of %d bytes for %s\n", sg_dma_len(sg),
3479 qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3480
3481 return 0;
3482}
3483
3484/**
0cba632b
JG		 3485 * ata_sg_setup - DMA-map the scatter-gather table associated with a command.
3486 * @qc: Command with scatter-gather table to be mapped.
3487 *
3488 * DMA-map the scatter-gather table associated with queued_cmd @qc.
1da177e4
LT		 3489 *
3490 * LOCKING:
cca3974e 3491 * spin_lock_irqsave(host lock)
1da177e4
LT		 3492 *
3493 * RETURNS:
0cba632b 3494 * Zero on success, negative on error.
1da177e4
LT		 3495 *
3496 */
3497
3498static int ata_sg_setup(struct ata_queued_cmd *qc)
3499{
3500 struct ata_port *ap = qc->ap;
cedc9a47
JG		 3501 struct scatterlist *sg = qc->__sg;
3502 struct scatterlist *lsg = &sg[qc->n_elem - 1];
e1410f2d 3503 int n_elem, pre_n_elem, dir, trim_sg = 0;
1da177e4
LT		 3504
3505 VPRINTK("ENTER, ata%u\n", ap->id);
a4631474 3506 WARN_ON(!(qc->flags & ATA_QCFLAG_SG));
1da177e4 3507
cedc9a47
JG		 3508 /* we must lengthen transfers to end on a 32-bit boundary */
3509 qc->pad_len = lsg->length & 3;
3510 if (qc->pad_len) {
3511 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
3512 struct scatterlist *psg = &qc->pad_sgent;
3513 unsigned int offset;
3514
a4631474 3515 WARN_ON(qc->dev->class != ATA_DEV_ATAPI);
cedc9a47
JG		 3516
3517 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
3518
3519 /*
3520 * psg->page/offset are used to copy to-be-written
3521 * data in this function or read data in ata_sg_clean.
3522 */
3523 offset = lsg->offset + lsg->length - qc->pad_len;
3524 psg->page = nth_page(lsg->page, offset >> PAGE_SHIFT);
3525 psg->offset = offset_in_page(offset);
3526
3527 if (qc->tf.flags & ATA_TFLAG_WRITE) {
3528 void *addr = kmap_atomic(psg->page, KM_IRQ0);
3529 memcpy(pad_buf, addr + psg->offset, qc->pad_len);
dfa15988 3530 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 3531 }
3532
3533 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
3534 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
3535 /* trim last sg */
3536 lsg->length -= qc->pad_len;
e1410f2d
JG		 3537 if (lsg->length == 0)
3538 trim_sg = 1;
cedc9a47
JG		 3539
3540 DPRINTK("padding done, sg[%d].length=%u pad_len=%u\n",
3541 qc->n_elem - 1, lsg->length, qc->pad_len);
3542 }
3543
e1410f2d
JG		 3544 pre_n_elem = qc->n_elem;
3545 if (trim_sg && pre_n_elem)
3546 pre_n_elem--;
3547
3548 if (!pre_n_elem) {
3549 n_elem = 0;
3550 goto skip_map;
3551 }
3552
1da177e4 3553 dir = qc->dma_dir;
2f1f610b 3554 n_elem = dma_map_sg(ap->dev, sg, pre_n_elem, dir);
537a95d9
TH		 3555 if (n_elem < 1) {
3556 /* restore last sg */
3557 lsg->length += qc->pad_len;
1da177e4 3558 return -1;
537a95d9 3559 }
1da177e4
LT		 3560
3561 DPRINTK("%d sg elements mapped\n", n_elem);
3562
e1410f2d 3563skip_map:
1da177e4
LT		 3564 qc->n_elem = n_elem;
3565
3566 return 0;
3567}
3568
0baab86b 3569/**
c893a3ae 3570 * swap_buf_le16 - swap halves of 16-bit words in place
0baab86b
EF		 3571 * @buf: Buffer to swap
3572 * @buf_words: Number of 16-bit words in buffer.
3573 *
3574 * Swap halves of 16-bit words if needed to convert from
3575 * little-endian byte order to native cpu byte order, or
3576 * vice-versa.
3577 *
3578 * LOCKING:
6f0ef4fa 3579 * Inherited from caller.
0baab86b 3580 */
1da177e4
LT		 3581void swap_buf_le16(u16 *buf, unsigned int buf_words)
3582{
3583#ifdef __BIG_ENDIAN
3584 unsigned int i;
3585
3586 for (i = 0; i < buf_words; i++)
3587 buf[i] = le16_to_cpu(buf[i]);
3588#endif /* __BIG_ENDIAN */
3589}
3590
6ae4cfb5
AL		 3591/**
3592 * ata_mmio_data_xfer - Transfer data by MMIO
bf717b11 3593 * @adev: device for this I/O
6ae4cfb5
AL		 3594 * @buf: data buffer
3595 * @buflen: buffer length
344babaa 3596 * @write_data: read/write
6ae4cfb5
AL		 3597 *
3598 * Transfer data from/to the device data register by MMIO.
3599 *
3600 * LOCKING:
3601 * Inherited from caller.
6ae4cfb5
AL		 3602 */
3603
88574551 3604void ata_mmio_data_xfer(struct ata_device *adev, unsigned char *buf,
a6b2c5d4 3605 unsigned int buflen, int write_data)
1da177e4 3606{
a6b2c5d4 3607 struct ata_port *ap = adev->ap;
1da177e4
LT		 3608 unsigned int i;
3609 unsigned int words = buflen >> 1;
3610 u16 *buf16 = (u16 *) buf;
3611 void __iomem *mmio = (void __iomem *)ap->ioaddr.data_addr;
3612
6ae4cfb5 3613 /* Transfer multiple of 2 bytes */
1da177e4
LT		 3614 if (write_data) {
3615 for (i = 0; i < words; i++)
3616 writew(le16_to_cpu(buf16[i]), mmio);
3617 } else {
3618 for (i = 0; i < words; i++)
3619 buf16[i] = cpu_to_le16(readw(mmio));
3620 }
6ae4cfb5
AL		 3621
3622 /* Transfer trailing 1 byte, if any. */
3623 if (unlikely(buflen & 0x01)) {
3624 u16 align_buf[1] = { 0 };
3625 unsigned char *trailing_buf = buf + buflen - 1;
3626
3627 if (write_data) {
3628 memcpy(align_buf, trailing_buf, 1);
3629 writew(le16_to_cpu(align_buf[0]), mmio);
3630 } else {
3631 align_buf[0] = cpu_to_le16(readw(mmio));
3632 memcpy(trailing_buf, align_buf, 1);
3633 }
3634 }
1da177e4
LT		 3635}
3636
6ae4cfb5
AL		 3637/**
3638 * ata_pio_data_xfer - Transfer data by PIO
a6b2c5d4 3639 * @adev: device to target
6ae4cfb5
AL		 3640 * @buf: data buffer
3641 * @buflen: buffer length
344babaa 3642 * @write_data: read/write
6ae4cfb5
AL		 3643 *
3644 * Transfer data from/to the device data register by PIO.
3645 *
3646 * LOCKING:
3647 * Inherited from caller.
6ae4cfb5
AL		 3648 */
3649
88574551 3650void ata_pio_data_xfer(struct ata_device *adev, unsigned char *buf,
a6b2c5d4 3651 unsigned int buflen, int write_data)
1da177e4 3652{
a6b2c5d4 3653 struct ata_port *ap = adev->ap;
6ae4cfb5 3654 unsigned int words = buflen >> 1;
1da177e4 3655
6ae4cfb5 3656 /* Transfer multiple of 2 bytes */
1da177e4 3657 if (write_data)
6ae4cfb5 3658 outsw(ap->ioaddr.data_addr, buf, words);
1da177e4 3659 else
6ae4cfb5
AL		 3660 insw(ap->ioaddr.data_addr, buf, words);
3661
3662 /* Transfer trailing 1 byte, if any. */
3663 if (unlikely(buflen & 0x01)) {
3664 u16 align_buf[1] = { 0 };
3665 unsigned char *trailing_buf = buf + buflen - 1;
3666
3667 if (write_data) {
3668 memcpy(align_buf, trailing_buf, 1);
3669 outw(le16_to_cpu(align_buf[0]), ap->ioaddr.data_addr);
3670 } else {
3671 align_buf[0] = cpu_to_le16(inw(ap->ioaddr.data_addr));
3672 memcpy(trailing_buf, align_buf, 1);
3673 }
3674 }
1da177e4
LT		 3675}
3676
75e99585
AC		 3677/**
3678 * ata_pio_data_xfer_noirq - Transfer data by PIO
3679 * @adev: device to target
3680 * @buf: data buffer
3681 * @buflen: buffer length
3682 * @write_data: read/write
3683 *
88574551 3684 * Transfer data from/to the device data register by PIO. Do the
75e99585
AC		 3685 * transfer with interrupts disabled.
3686 *
3687 * LOCKING:
3688 * Inherited from caller.
3689 */
3690
3691void ata_pio_data_xfer_noirq(struct ata_device *adev, unsigned char *buf,
3692 unsigned int buflen, int write_data)
3693{
3694 unsigned long flags;
3695 local_irq_save(flags);
3696 ata_pio_data_xfer(adev, buf, buflen, write_data);
3697 local_irq_restore(flags);
3698}
3699
3700
6ae4cfb5
AL		 3701/**
3702 * ata_pio_sector - Transfer ATA_SECT_SIZE (512 bytes) of data.
3703 * @qc: Command on going
3704 *
3705 * Transfer ATA_SECT_SIZE of data from/to the ATA device.
3706 *
3707 * LOCKING:
3708 * Inherited from caller.
3709 */
3710
1da177e4
LT		 3711static void ata_pio_sector(struct ata_queued_cmd *qc)
3712{
3713 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3714 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3715 struct ata_port *ap = qc->ap;
3716 struct page *page;
3717 unsigned int offset;
3718 unsigned char *buf;
3719
3720 if (qc->cursect == (qc->nsect - 1))
14be71f4 3721 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3722
3723 page = sg[qc->cursg].page;
3724 offset = sg[qc->cursg].offset + qc->cursg_ofs * ATA_SECT_SIZE;
3725
3726 /* get the current page and offset */
3727 page = nth_page(page, (offset >> PAGE_SHIFT));
3728 offset %= PAGE_SIZE;
3729
1da177e4
LT		 3730 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3731
91b8b313
AL		 3732 if (PageHighMem(page)) {
3733 unsigned long flags;
3734
a6b2c5d4 3735 /* FIXME: use a bounce buffer */
91b8b313
AL		 3736 local_irq_save(flags);
3737 buf = kmap_atomic(page, KM_IRQ0);
083958d3 3738
91b8b313 3739 /* do the actual data transfer */
a6b2c5d4 3740 ap->ops->data_xfer(qc->dev, buf + offset, ATA_SECT_SIZE, do_write);
1da177e4 3741
91b8b313
AL		 3742 kunmap_atomic(buf, KM_IRQ0);
3743 local_irq_restore(flags);
3744 } else {
3745 buf = page_address(page);
a6b2c5d4 3746 ap->ops->data_xfer(qc->dev, buf + offset, ATA_SECT_SIZE, do_write);
91b8b313 3747 }
1da177e4
LT		 3748
3749 qc->cursect++;
3750 qc->cursg_ofs++;
3751
32529e01 3752 if ((qc->cursg_ofs * ATA_SECT_SIZE) == (&sg[qc->cursg])->length) {
1da177e4
LT		 3753 qc->cursg++;
3754 qc->cursg_ofs = 0;
3755 }
1da177e4 3756}
1da177e4 3757
07f6f7d0
AL		 3758/**
3759 * ata_pio_sectors - Transfer one or many 512-byte sectors.
3760 * @qc: Command on going
3761 *
c81e29b4 3762 * Transfer one or many ATA_SECT_SIZE of data from/to the
07f6f7d0
AL		 3763 * ATA device for the DRQ request.
3764 *
3765 * LOCKING:
3766 * Inherited from caller.
3767 */
1da177e4 3768
07f6f7d0
AL		 3769static void ata_pio_sectors(struct ata_queued_cmd *qc)
3770{
3771 if (is_multi_taskfile(&qc->tf)) {
3772 /* READ/WRITE MULTIPLE */
3773 unsigned int nsect;
3774
587005de 3775 WARN_ON(qc->dev->multi_count == 0);
1da177e4 3776
07f6f7d0
AL		 3777 nsect = min(qc->nsect - qc->cursect, qc->dev->multi_count);
3778 while (nsect--)
3779 ata_pio_sector(qc);
3780 } else
3781 ata_pio_sector(qc);
3782}
3783
c71c1857
AL		 3784/**
3785 * atapi_send_cdb - Write CDB bytes to hardware
3786 * @ap: Port to which ATAPI device is attached.
3787 * @qc: Taskfile currently active
3788 *
3789 * When device has indicated its readiness to accept
3790 * a CDB, this function is called. Send the CDB.
3791 *
3792 * LOCKING:
3793 * caller.
3794 */
3795
3796static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
3797{
3798 /* send SCSI cdb */
3799 DPRINTK("send cdb\n");
db024d53 3800 WARN_ON(qc->dev->cdb_len < 12);
c71c1857 3801
a6b2c5d4 3802 ap->ops->data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
c71c1857
AL		 3803 ata_altstatus(ap); /* flush */
3804
3805 switch (qc->tf.protocol) {
3806 case ATA_PROT_ATAPI:
3807 ap->hsm_task_state = HSM_ST;
3808 break;
3809 case ATA_PROT_ATAPI_NODATA:
3810 ap->hsm_task_state = HSM_ST_LAST;
3811 break;
3812 case ATA_PROT_ATAPI_DMA:
3813 ap->hsm_task_state = HSM_ST_LAST;
3814 /* initiate bmdma */
3815 ap->ops->bmdma_start(qc);
3816 break;
3817 }
1da177e4
LT		 3818}
3819
6ae4cfb5
AL		 3820/**
3821 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
3822 * @qc: Command on going
3823 * @bytes: number of bytes
3824 *
3825 * Transfer Transfer data from/to the ATAPI device.
3826 *
3827 * LOCKING:
3828 * Inherited from caller.
3829 *
3830 */
3831
1da177e4
LT		 3832static void __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
3833{
3834 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3835 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3836 struct ata_port *ap = qc->ap;
3837 struct page *page;
3838 unsigned char *buf;
3839 unsigned int offset, count;
3840
563a6e1f 3841 if (qc->curbytes + bytes >= qc->nbytes)
14be71f4 3842 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3843
3844next_sg:
563a6e1f 3845 if (unlikely(qc->cursg >= qc->n_elem)) {
7fb6ec28 3846 /*
563a6e1f
AL		 3847 * The end of qc->sg is reached and the device expects
3848 * more data to transfer. In order not to overrun qc->sg
3849 * and fulfill length specified in the byte count register,
3850 * - for read case, discard trailing data from the device
3851 * - for write case, padding zero data to the device
3852 */
3853 u16 pad_buf[1] = { 0 };
3854 unsigned int words = bytes >> 1;
3855 unsigned int i;
3856
3857 if (words) /* warning if bytes > 1 */
f15a1daf
TH		 3858 ata_dev_printk(qc->dev, KERN_WARNING,
3859 "%u bytes trailing data\n", bytes);
563a6e1f
AL		 3860
3861 for (i = 0; i < words; i++)
a6b2c5d4 3862 ap->ops->data_xfer(qc->dev, (unsigned char*)pad_buf, 2, do_write);
563a6e1f 3863
14be71f4 3864 ap->hsm_task_state = HSM_ST_LAST;
563a6e1f
AL		 3865 return;
3866 }
3867
cedc9a47 3868 sg = &qc->__sg[qc->cursg];
1da177e4 3869
1da177e4
LT		 3870 page = sg->page;
3871 offset = sg->offset + qc->cursg_ofs;
3872
3873 /* get the current page and offset */
3874 page = nth_page(page, (offset >> PAGE_SHIFT));
3875 offset %= PAGE_SIZE;
3876
6952df03 3877 /* don't overrun current sg */
32529e01 3878 count = min(sg->length - qc->cursg_ofs, bytes);
1da177e4
LT		 3879
3880 /* don't cross page boundaries */
3881 count = min(count, (unsigned int)PAGE_SIZE - offset);
3882
7282aa4b
AL		 3883 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3884
91b8b313
AL		 3885 if (PageHighMem(page)) {
3886 unsigned long flags;
3887
a6b2c5d4 3888 /* FIXME: use bounce buffer */
91b8b313
AL		 3889 local_irq_save(flags);
3890 buf = kmap_atomic(page, KM_IRQ0);
083958d3 3891
91b8b313 3892 /* do the actual data transfer */
a6b2c5d4 3893 ap->ops->data_xfer(qc->dev, buf + offset, count, do_write);
7282aa4b 3894
91b8b313
AL		 3895 kunmap_atomic(buf, KM_IRQ0);
3896 local_irq_restore(flags);
3897 } else {
3898 buf = page_address(page);
a6b2c5d4 3899 ap->ops->data_xfer(qc->dev, buf + offset, count, do_write);
91b8b313 3900 }
1da177e4
LT		 3901
3902 bytes -= count;
3903 qc->curbytes += count;
3904 qc->cursg_ofs += count;
3905
32529e01 3906 if (qc->cursg_ofs == sg->length) {
1da177e4
LT		 3907 qc->cursg++;
3908 qc->cursg_ofs = 0;
3909 }
3910
563a6e1f 3911 if (bytes)
1da177e4 3912 goto next_sg;
1da177e4
LT		 3913}
3914
6ae4cfb5
AL		 3915/**
3916 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
3917 * @qc: Command on going
3918 *
3919 * Transfer Transfer data from/to the ATAPI device.
3920 *
3921 * LOCKING:
3922 * Inherited from caller.
6ae4cfb5
AL		 3923 */
3924
1da177e4
LT		 3925static void atapi_pio_bytes(struct ata_queued_cmd *qc)
3926{
3927 struct ata_port *ap = qc->ap;
3928 struct ata_device *dev = qc->dev;
3929 unsigned int ireason, bc_lo, bc_hi, bytes;
3930 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
3931
eec4c3f3
AL		 3932 /* Abuse qc->result_tf for temp storage of intermediate TF
3933 * here to save some kernel stack usage.
3934 * For normal completion, qc->result_tf is not relevant. For
3935 * error, qc->result_tf is later overwritten by ata_qc_complete().
3936 * So, the correctness of qc->result_tf is not affected.
3937 */
3938 ap->ops->tf_read(ap, &qc->result_tf);
3939 ireason = qc->result_tf.nsect;
3940 bc_lo = qc->result_tf.lbam;
3941 bc_hi = qc->result_tf.lbah;
1da177e4
LT		 3942 bytes = (bc_hi << 8) | bc_lo;
3943
3944 /* shall be cleared to zero, indicating xfer of data */
3945 if (ireason & (1 << 0))
3946 goto err_out;
3947
3948 /* make sure transfer direction matches expected */
3949 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
3950 if (do_write != i_write)
3951 goto err_out;
3952
312f7da2
AL		 3953 VPRINTK("ata%u: xfering %d bytes\n", ap->id, bytes);
3954
1da177e4
LT		 3955 __atapi_pio_bytes(qc, bytes);
3956
3957 return;
3958
3959err_out:
f15a1daf 3960 ata_dev_printk(dev, KERN_INFO, "ATAPI check failed\n");
11a56d24 3961 qc->err_mask |= AC_ERR_HSM;
14be71f4 3962 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3963}
3964
3965/**
c234fb00
AL		 3966 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
3967 * @ap: the target ata_port
3968 * @qc: qc on going
1da177e4 3969 *
c234fb00
AL		 3970 * RETURNS:
3971 * 1 if ok in workqueue, 0 otherwise.
1da177e4 3972 */
c234fb00
AL		 3973
3974static inline int ata_hsm_ok_in_wq(struct ata_port *ap, struct ata_queued_cmd *qc)
1da177e4 3975{
c234fb00
AL		 3976 if (qc->tf.flags & ATA_TFLAG_POLLING)
3977 return 1;
1da177e4 3978
c234fb00
AL		 3979 if (ap->hsm_task_state == HSM_ST_FIRST) {
3980 if (qc->tf.protocol == ATA_PROT_PIO &&
3981 (qc->tf.flags & ATA_TFLAG_WRITE))
3982 return 1;
1da177e4 3983
c234fb00
AL		 3984 if (is_atapi_taskfile(&qc->tf) &&
3985 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
3986 return 1;
fe79e683
AL		 3987 }
3988
c234fb00
AL		 3989 return 0;
3990}
1da177e4 3991
c17ea20d
TH		 3992/**
3993 * ata_hsm_qc_complete - finish a qc running on standard HSM
3994 * @qc: Command to complete
3995 * @in_wq: 1 if called from workqueue, 0 otherwise
3996 *
3997 * Finish @qc which is running on standard HSM.
3998 *
3999 * LOCKING:
cca3974e 4000 * If @in_wq is zero, spin_lock_irqsave(host lock).
c17ea20d
TH		 4001 * Otherwise, none on entry and grabs host lock.
4002 */
4003static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
4004{
4005 struct ata_port *ap = qc->ap;
4006 unsigned long flags;
4007
4008 if (ap->ops->error_handler) {
4009 if (in_wq) {
ba6a1308 4010 spin_lock_irqsave(ap->lock, flags);
c17ea20d 4011
cca3974e
JG		 4012 /* EH might have kicked in while host lock is
4013 * released.
c17ea20d
TH		 4014 */
4015 qc = ata_qc_from_tag(ap, qc->tag);
4016 if (qc) {
4017 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
4018 ata_irq_on(ap);
4019 ata_qc_complete(qc);
4020 } else
4021 ata_port_freeze(ap);
4022 }
4023
ba6a1308 4024 spin_unlock_irqrestore(ap->lock, flags);
c17ea20d
TH		 4025 } else {
4026 if (likely(!(qc->err_mask & AC_ERR_HSM)))
4027 ata_qc_complete(qc);
4028 else
4029 ata_port_freeze(ap);
4030 }
4031 } else {
4032 if (in_wq) {
ba6a1308 4033 spin_lock_irqsave(ap->lock, flags);
c17ea20d
TH		 4034 ata_irq_on(ap);
4035 ata_qc_complete(qc);
ba6a1308 4036 spin_unlock_irqrestore(ap->lock, flags);
c17ea20d
TH		 4037 } else
4038 ata_qc_complete(qc);
4039 }
1da177e4 4040
c81e29b4 4041 ata_altstatus(ap); /* flush */
c17ea20d
TH		 4042}
4043
bb5cb290
AL		 4044/**
4045 * ata_hsm_move - move the HSM to the next state.
4046 * @ap: the target ata_port
4047 * @qc: qc on going
4048 * @status: current device status
4049 * @in_wq: 1 if called from workqueue, 0 otherwise
4050 *
4051 * RETURNS:
4052 * 1 when poll next status needed, 0 otherwise.
4053 */
9a1004d0
TH		 4054int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
4055 u8 status, int in_wq)
e2cec771 4056{
bb5cb290
AL		 4057 unsigned long flags = 0;
4058 int poll_next;
4059
6912ccd5
AL		 4060 WARN_ON((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
4061
bb5cb290
AL		 4062 /* Make sure ata_qc_issue_prot() does not throw things
4063 * like DMA polling into the workqueue. Notice that
4064 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
4065 */
c234fb00 4066 WARN_ON(in_wq != ata_hsm_ok_in_wq(ap, qc));
bb5cb290 4067
e2cec771 4068fsm_start:
999bb6f4
AL		 4069 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
4070 ap->id, qc->tf.protocol, ap->hsm_task_state, status);
4071
e2cec771
AL		 4072 switch (ap->hsm_task_state) {
4073 case HSM_ST_FIRST:
bb5cb290
AL		 4074 /* Send first data block or PACKET CDB */
4075
4076 /* If polling, we will stay in the work queue after
4077 * sending the data. Otherwise, interrupt handler
4078 * takes over after sending the data.
4079 */
4080 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
4081
e2cec771 4082 /* check device status */
3655d1d3
AL		 4083 if (unlikely((status & ATA_DRQ) == 0)) {
4084 /* handle BSY=0, DRQ=0 as error */
4085 if (likely(status & (ATA_ERR | ATA_DF)))
4086 /* device stops HSM for abort/error */
4087 qc->err_mask |= AC_ERR_DEV;
4088 else
4089 /* HSM violation. Let EH handle this */
4090 qc->err_mask |= AC_ERR_HSM;
4091
14be71f4 4092 ap->hsm_task_state = HSM_ST_ERR;
e2cec771 4093 goto fsm_start;
1da177e4
LT		 4094 }
4095
71601958
AL		 4096 /* Device should not ask for data transfer (DRQ=1)
4097 * when it finds something wrong.
eee6c32f
AL		 4098 * We ignore DRQ here and stop the HSM by
4099 * changing hsm_task_state to HSM_ST_ERR and
4100 * let the EH abort the command or reset the device.
71601958
AL		 4101 */
4102 if (unlikely(status & (ATA_ERR | ATA_DF))) {
4103 printk(KERN_WARNING "ata%d: DRQ=1 with device error, dev_stat 0x%X\n",
4104 ap->id, status);
3655d1d3 4105 qc->err_mask |= AC_ERR_HSM;
eee6c32f
AL		 4106 ap->hsm_task_state = HSM_ST_ERR;
4107 goto fsm_start;
71601958 4108 }
1da177e4 4109
bb5cb290
AL		 4110 /* Send the CDB (atapi) or the first data block (ata pio out).
4111 * During the state transition, interrupt handler shouldn't
4112 * be invoked before the data transfer is complete and
4113 * hsm_task_state is changed. Hence, the following locking.
4114 */
4115 if (in_wq)
ba6a1308 4116 spin_lock_irqsave(ap->lock, flags);
1da177e4 4117
bb5cb290
AL		 4118 if (qc->tf.protocol == ATA_PROT_PIO) {
4119 /* PIO data out protocol.
4120 * send first data block.
4121 */
0565c26d 4122
bb5cb290
AL		 4123 /* ata_pio_sectors() might change the state
4124 * to HSM_ST_LAST. so, the state is changed here
4125 * before ata_pio_sectors().
4126 */
4127 ap->hsm_task_state = HSM_ST;
4128 ata_pio_sectors(qc);
4129 ata_altstatus(ap); /* flush */
4130 } else
4131 /* send CDB */
4132 atapi_send_cdb(ap, qc);
4133
4134 if (in_wq)
ba6a1308 4135 spin_unlock_irqrestore(ap->lock, flags);
bb5cb290
AL		 4136
4137 /* if polling, ata_pio_task() handles the rest.
4138 * otherwise, interrupt handler takes over from here.
4139 */
e2cec771 4140 break;
1c848984 4141
e2cec771
AL		 4142 case HSM_ST:
4143 /* complete command or read/write the data register */
4144 if (qc->tf.protocol == ATA_PROT_ATAPI) {
4145 /* ATAPI PIO protocol */
4146 if ((status & ATA_DRQ) == 0) {
3655d1d3
AL		 4147 /* No more data to transfer or device error.
4148 * Device error will be tagged in HSM_ST_LAST.
4149 */
e2cec771
AL		 4150 ap->hsm_task_state = HSM_ST_LAST;
4151 goto fsm_start;
4152 }
1da177e4 4153
71601958
AL		 4154 /* Device should not ask for data transfer (DRQ=1)
4155 * when it finds something wrong.
eee6c32f
AL		 4156 * We ignore DRQ here and stop the HSM by
4157 * changing hsm_task_state to HSM_ST_ERR and
4158 * let the EH abort the command or reset the device.
71601958
AL		 4159 */
4160 if (unlikely(status & (ATA_ERR | ATA_DF))) {
4161 printk(KERN_WARNING "ata%d: DRQ=1 with device error, dev_stat 0x%X\n",
4162 ap->id, status);
3655d1d3 4163 qc->err_mask |= AC_ERR_HSM;
eee6c32f
AL		 4164 ap->hsm_task_state = HSM_ST_ERR;
4165 goto fsm_start;
71601958 4166 }
1da177e4 4167
e2cec771 4168 atapi_pio_bytes(qc);
7fb6ec28 4169
e2cec771
AL		 4170 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
4171 /* bad ireason reported by device */
4172 goto fsm_start;
1da177e4 4173
e2cec771
AL		 4174 } else {
4175 /* ATA PIO protocol */
4176 if (unlikely((status & ATA_DRQ) == 0)) {
4177 /* handle BSY=0, DRQ=0 as error */
3655d1d3
AL		 4178 if (likely(status & (ATA_ERR | ATA_DF)))
4179 /* device stops HSM for abort/error */
4180 qc->err_mask |= AC_ERR_DEV;
4181 else
4182 /* HSM violation. Let EH handle this */
4183 qc->err_mask |= AC_ERR_HSM;
4184
e2cec771
AL		 4185 ap->hsm_task_state = HSM_ST_ERR;
4186 goto fsm_start;
4187 }
1da177e4 4188
eee6c32f
AL		 4189 /* For PIO reads, some devices may ask for
4190 * data transfer (DRQ=1) alone with ERR=1.
4191 * We respect DRQ here and transfer one
4192 * block of junk data before changing the
4193 * hsm_task_state to HSM_ST_ERR.
4194 *
4195 * For PIO writes, ERR=1 DRQ=1 doesn't make
4196 * sense since the data block has been
4197 * transferred to the device.
71601958
AL		 4198 */
4199 if (unlikely(status & (ATA_ERR | ATA_DF))) {
71601958
AL		 4200 /* data might be corrputed */
4201 qc->err_mask |= AC_ERR_DEV;
eee6c32f
AL		 4202
4203 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
4204 ata_pio_sectors(qc);
4205 ata_altstatus(ap);
4206 status = ata_wait_idle(ap);
4207 }
4208
3655d1d3
AL		 4209 if (status & (ATA_BUSY | ATA_DRQ))
4210 qc->err_mask |= AC_ERR_HSM;
4211
eee6c32f
AL		 4212 /* ata_pio_sectors() might change the
4213 * state to HSM_ST_LAST. so, the state
4214 * is changed after ata_pio_sectors().
4215 */
4216 ap->hsm_task_state = HSM_ST_ERR;
4217 goto fsm_start;
71601958
AL		 4218 }
4219
e2cec771
AL		 4220 ata_pio_sectors(qc);
4221
4222 if (ap->hsm_task_state == HSM_ST_LAST &&
4223 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
4224 /* all data read */
4225 ata_altstatus(ap);
52a32205 4226 status = ata_wait_idle(ap);
e2cec771
AL		 4227 goto fsm_start;
4228 }
4229 }
4230
4231 ata_altstatus(ap); /* flush */
bb5cb290 4232 poll_next = 1;
1da177e4
LT		 4233 break;
4234
14be71f4 4235 case HSM_ST_LAST:
6912ccd5
AL		 4236 if (unlikely(!ata_ok(status))) {
4237 qc->err_mask |= __ac_err_mask(status);
e2cec771
AL		 4238 ap->hsm_task_state = HSM_ST_ERR;
4239 goto fsm_start;
4240 }
4241
4242 /* no more data to transfer */
4332a771
AL		 4243 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
4244 ap->id, qc->dev->devno, status);
e2cec771 4245
6912ccd5
AL		 4246 WARN_ON(qc->err_mask);
4247
e2cec771 4248 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 4249
e2cec771 4250 /* complete taskfile transaction */
c17ea20d 4251 ata_hsm_qc_complete(qc, in_wq);
bb5cb290
AL		 4252
4253 poll_next = 0;
1da177e4
LT		 4254 break;
4255
14be71f4 4256 case HSM_ST_ERR:
e2cec771
AL		 4257 /* make sure qc->err_mask is available to
4258 * know what's wrong and recover
4259 */
4260 WARN_ON(qc->err_mask == 0);
4261
4262 ap->hsm_task_state = HSM_ST_IDLE;
bb5cb290 4263
999bb6f4 4264 /* complete taskfile transaction */
c17ea20d 4265 ata_hsm_qc_complete(qc, in_wq);
bb5cb290
AL		 4266
4267 poll_next = 0;
e2cec771
AL		 4268 break;
4269 default:
bb5cb290 4270 poll_next = 0;
6912ccd5 4271 BUG();
1da177e4
LT		 4272 }
4273
bb5cb290 4274 return poll_next;
1da177e4
LT		 4275}
4276
1da177e4 4277static void ata_pio_task(void *_data)
8061f5f0 4278{
c91af2c8
TH		 4279 struct ata_queued_cmd *qc = _data;
4280 struct ata_port *ap = qc->ap;
8061f5f0 4281 u8 status;
a1af3734 4282 int poll_next;
8061f5f0 4283
7fb6ec28 4284fsm_start:
a1af3734 4285 WARN_ON(ap->hsm_task_state == HSM_ST_IDLE);
8061f5f0 4286
a1af3734
AL		 4287 /*
4288 * This is purely heuristic. This is a fast path.
4289 * Sometimes when we enter, BSY will be cleared in
4290 * a chk-status or two. If not, the drive is probably seeking
4291 * or something. Snooze for a couple msecs, then
4292 * chk-status again. If still busy, queue delayed work.
4293 */
4294 status = ata_busy_wait(ap, ATA_BUSY, 5);
4295 if (status & ATA_BUSY) {
4296 msleep(2);
4297 status = ata_busy_wait(ap, ATA_BUSY, 10);
4298 if (status & ATA_BUSY) {
31ce6dae 4299 ata_port_queue_task(ap, ata_pio_task, qc, ATA_SHORT_PAUSE);
a1af3734
AL		 4300 return;
4301 }
8061f5f0
TH		 4302 }
4303
a1af3734
AL		 4304 /* move the HSM */
4305 poll_next = ata_hsm_move(ap, qc, status, 1);
8061f5f0 4306
a1af3734
AL		 4307 /* another command or interrupt handler
4308 * may be running at this point.
4309 */
4310 if (poll_next)
7fb6ec28 4311 goto fsm_start;
8061f5f0
TH		 4312}
4313
1da177e4
LT		 4314/**
4315 * ata_qc_new - Request an available ATA command, for queueing
4316 * @ap: Port associated with device @dev
4317 * @dev: Device from whom we request an available command structure
4318 *
4319 * LOCKING:
0cba632b 4320 * None.
1da177e4
LT		 4321 */
4322
4323static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap)
4324{
4325 struct ata_queued_cmd *qc = NULL;
4326 unsigned int i;
4327
e3180499 4328 /* no command while frozen */
b51e9e5d 4329 if (unlikely(ap->pflags & ATA_PFLAG_FROZEN))
e3180499
TH		 4330 return NULL;
4331
2ab7db1f
TH		 4332 /* the last tag is reserved for internal command. */
4333 for (i = 0; i < ATA_MAX_QUEUE - 1; i++)
6cec4a39 4334 if (!test_and_set_bit(i, &ap->qc_allocated)) {
f69499f4 4335 qc = __ata_qc_from_tag(ap, i);
1da177e4
LT		 4336 break;
4337 }
4338
4339 if (qc)
4340 qc->tag = i;
4341
4342 return qc;
4343}
4344
4345/**
4346 * ata_qc_new_init - Request an available ATA command, and initialize it
1da177e4
LT		 4347 * @dev: Device from whom we request an available command structure
4348 *
4349 * LOCKING:
0cba632b 4350 * None.
1da177e4
LT		 4351 */
4352
3373efd8 4353struct ata_queued_cmd *ata_qc_new_init(struct ata_device *dev)
1da177e4 4354{
3373efd8 4355 struct ata_port *ap = dev->ap;
1da177e4
LT		 4356 struct ata_queued_cmd *qc;
4357
4358 qc = ata_qc_new(ap);
4359 if (qc) {
1da177e4
LT		 4360 qc->scsicmd = NULL;
4361 qc->ap = ap;
4362 qc->dev = dev;
1da177e4 4363
2c13b7ce 4364 ata_qc_reinit(qc);
1da177e4
LT		 4365 }
4366
4367 return qc;
4368}
4369
1da177e4
LT		 4370/**
4371 * ata_qc_free - free unused ata_queued_cmd
4372 * @qc: Command to complete
4373 *
4374 * Designed to free unused ata_queued_cmd object
4375 * in case something prevents using it.
4376 *
4377 * LOCKING:
cca3974e 4378 * spin_lock_irqsave(host lock)
1da177e4
LT		 4379 */
4380void ata_qc_free(struct ata_queued_cmd *qc)
4381{
4ba946e9
TH		 4382 struct ata_port *ap = qc->ap;
4383 unsigned int tag;
4384
a4631474 4385 WARN_ON(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
1da177e4 4386
4ba946e9
TH		 4387 qc->flags = 0;
4388 tag = qc->tag;
4389 if (likely(ata_tag_valid(tag))) {
4ba946e9 4390 qc->tag = ATA_TAG_POISON;
6cec4a39 4391 clear_bit(tag, &ap->qc_allocated);
4ba946e9 4392 }
1da177e4
LT		 4393}
4394
76014427 4395void __ata_qc_complete(struct ata_queued_cmd *qc)
1da177e4 4396{
dedaf2b0
TH		 4397 struct ata_port *ap = qc->ap;
4398
a4631474
TH		 4399 WARN_ON(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
4400 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
1da177e4
LT		 4401
4402 if (likely(qc->flags & ATA_QCFLAG_DMAMAP))
4403 ata_sg_clean(qc);
4404
7401abf2 4405 /* command should be marked inactive atomically with qc completion */
dedaf2b0
TH		 4406 if (qc->tf.protocol == ATA_PROT_NCQ)
4407 ap->sactive &= ~(1 << qc->tag);
4408 else
4409 ap->active_tag = ATA_TAG_POISON;
7401abf2 4410
3f3791d3
AL		 4411 /* atapi: mark qc as inactive to prevent the interrupt handler
4412 * from completing the command twice later, before the error handler
4413 * is called. (when rc != 0 and atapi request sense is needed)
4414 */
4415 qc->flags &= ~ATA_QCFLAG_ACTIVE;
dedaf2b0 4416 ap->qc_active &= ~(1 << qc->tag);
3f3791d3 4417
1da177e4 4418 /* call completion callback */
77853bf2 4419 qc->complete_fn(qc);
1da177e4
LT		 4420}
4421
f686bcb8
TH		 4422/**
4423 * ata_qc_complete - Complete an active ATA command
4424 * @qc: Command to complete
4425 * @err_mask: ATA Status register contents
4426 *
4427 * Indicate to the mid and upper layers that an ATA
4428 * command has completed, with either an ok or not-ok status.
4429 *
4430 * LOCKING:
cca3974e 4431 * spin_lock_irqsave(host lock)
f686bcb8
TH		 4432 */
4433void ata_qc_complete(struct ata_queued_cmd *qc)
4434{
4435 struct ata_port *ap = qc->ap;
4436
4437 /* XXX: New EH and old EH use different mechanisms to
4438 * synchronize EH with regular execution path.
4439 *
4440 * In new EH, a failed qc is marked with ATA_QCFLAG_FAILED.
4441 * Normal execution path is responsible for not accessing a
4442 * failed qc. libata core enforces the rule by returning NULL
4443 * from ata_qc_from_tag() for failed qcs.
4444 *
4445 * Old EH depends on ata_qc_complete() nullifying completion
4446 * requests if ATA_QCFLAG_EH_SCHEDULED is set. Old EH does
4447 * not synchronize with interrupt handler. Only PIO task is
4448 * taken care of.
4449 */
4450 if (ap->ops->error_handler) {
b51e9e5d 4451 WARN_ON(ap->pflags & ATA_PFLAG_FROZEN);
f686bcb8
TH		 4452
4453 if (unlikely(qc->err_mask))
4454 qc->flags |= ATA_QCFLAG_FAILED;
4455
4456 if (unlikely(qc->flags & ATA_QCFLAG_FAILED)) {
4457 if (!ata_tag_internal(qc->tag)) {
4458 /* always fill result TF for failed qc */
4459 ap->ops->tf_read(ap, &qc->result_tf);
4460 ata_qc_schedule_eh(qc);
4461 return;
4462 }
4463 }
4464
4465 /* read result TF if requested */
4466 if (qc->flags & ATA_QCFLAG_RESULT_TF)
4467 ap->ops->tf_read(ap, &qc->result_tf);
4468
4469 __ata_qc_complete(qc);
4470 } else {
4471 if (qc->flags & ATA_QCFLAG_EH_SCHEDULED)
4472 return;
4473
4474 /* read result TF if failed or requested */
4475 if (qc->err_mask || qc->flags & ATA_QCFLAG_RESULT_TF)
4476 ap->ops->tf_read(ap, &qc->result_tf);
4477
4478 __ata_qc_complete(qc);
4479 }
4480}
4481
dedaf2b0
TH		 4482/**
4483 * ata_qc_complete_multiple - Complete multiple qcs successfully
4484 * @ap: port in question
4485 * @qc_active: new qc_active mask
4486 * @finish_qc: LLDD callback invoked before completing a qc
4487 *
4488 * Complete in-flight commands. This functions is meant to be
4489 * called from low-level driver's interrupt routine to complete
4490 * requests normally. ap->qc_active and @qc_active is compared
4491 * and commands are completed accordingly.
4492 *
4493 * LOCKING:
cca3974e 4494 * spin_lock_irqsave(host lock)
dedaf2b0
TH		 4495 *
4496 * RETURNS:
4497 * Number of completed commands on success, -errno otherwise.
4498 */
4499int ata_qc_complete_multiple(struct ata_port *ap, u32 qc_active,
4500 void (*finish_qc)(struct ata_queued_cmd *))
4501{
4502 int nr_done = 0;
4503 u32 done_mask;
4504 int i;
4505
4506 done_mask = ap->qc_active ^ qc_active;
4507
4508 if (unlikely(done_mask & qc_active)) {
4509 ata_port_printk(ap, KERN_ERR, "illegal qc_active transition "
4510 "(%08x->%08x)\n", ap->qc_active, qc_active);
4511 return -EINVAL;
4512 }
4513
4514 for (i = 0; i < ATA_MAX_QUEUE; i++) {
4515 struct ata_queued_cmd *qc;
4516
4517 if (!(done_mask & (1 << i)))
4518 continue;
4519
4520 if ((qc = ata_qc_from_tag(ap, i))) {
4521 if (finish_qc)
4522 finish_qc(qc);
4523 ata_qc_complete(qc);
4524 nr_done++;
4525 }
4526 }
4527
4528 return nr_done;
4529}
4530
1da177e4
LT		 4531static inline int ata_should_dma_map(struct ata_queued_cmd *qc)
4532{
4533 struct ata_port *ap = qc->ap;
4534
4535 switch (qc->tf.protocol) {
3dc1d881 4536 case ATA_PROT_NCQ:
1da177e4
LT		 4537 case ATA_PROT_DMA:
4538 case ATA_PROT_ATAPI_DMA:
4539 return 1;
4540
4541 case ATA_PROT_ATAPI:
4542 case ATA_PROT_PIO:
1da177e4
LT		 4543 if (ap->flags & ATA_FLAG_PIO_DMA)
4544 return 1;
4545
4546 /* fall through */
4547
4548 default:
4549 return 0;
4550 }
4551
4552 /* never reached */
4553}
4554
4555/**
4556 * ata_qc_issue - issue taskfile to device
4557 * @qc: command to issue to device
4558 *
4559 * Prepare an ATA command to submission to device.
4560 * This includes mapping the data into a DMA-able
4561 * area, filling in the S/G table, and finally
4562 * writing the taskfile to hardware, starting the command.
4563 *
4564 * LOCKING:
cca3974e 4565 * spin_lock_irqsave(host lock)
1da177e4 4566 */
8e0e694a 4567void ata_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 4568{
4569 struct ata_port *ap = qc->ap;
4570
dedaf2b0
TH		 4571 /* Make sure only one non-NCQ command is outstanding. The
4572 * check is skipped for old EH because it reuses active qc to
4573 * request ATAPI sense.
4574 */
4575 WARN_ON(ap->ops->error_handler && ata_tag_valid(ap->active_tag));
4576
4577 if (qc->tf.protocol == ATA_PROT_NCQ) {
4578 WARN_ON(ap->sactive & (1 << qc->tag));
4579 ap->sactive |= 1 << qc->tag;
4580 } else {
4581 WARN_ON(ap->sactive);
4582 ap->active_tag = qc->tag;
4583 }
4584
e4a70e76 4585 qc->flags |= ATA_QCFLAG_ACTIVE;
dedaf2b0 4586 ap->qc_active |= 1 << qc->tag;
e4a70e76 4587
1da177e4
LT		 4588 if (ata_should_dma_map(qc)) {
4589 if (qc->flags & ATA_QCFLAG_SG) {
4590 if (ata_sg_setup(qc))
8e436af9 4591 goto sg_err;
1da177e4
LT		 4592 } else if (qc->flags & ATA_QCFLAG_SINGLE) {
4593 if (ata_sg_setup_one(qc))
8e436af9 4594 goto sg_err;
1da177e4
LT		 4595 }
4596 } else {
4597 qc->flags &= ~ATA_QCFLAG_DMAMAP;
4598 }
4599
4600 ap->ops->qc_prep(qc);
4601
8e0e694a
TH		 4602 qc->err_mask |= ap->ops->qc_issue(qc);
4603 if (unlikely(qc->err_mask))
4604 goto err;
4605 return;
1da177e4 4606
8e436af9
TH		 4607sg_err:
4608 qc->flags &= ~ATA_QCFLAG_DMAMAP;
8e0e694a
TH		 4609 qc->err_mask |= AC_ERR_SYSTEM;
4610err:
4611 ata_qc_complete(qc);
1da177e4
LT		 4612}
4613
4614/**
4615 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
4616 * @qc: command to issue to device
4617 *
4618 * Using various libata functions and hooks, this function
4619 * starts an ATA command. ATA commands are grouped into
4620 * classes called "protocols", and issuing each type of protocol
4621 * is slightly different.
4622 *
0baab86b
EF		 4623 * May be used as the qc_issue() entry in ata_port_operations.
4624 *
1da177e4 4625 * LOCKING:
cca3974e 4626 * spin_lock_irqsave(host lock)
1da177e4
LT		 4627 *
4628 * RETURNS:
9a3d9eb0 4629 * Zero on success, AC_ERR_* mask on failure
1da177e4
LT		 4630 */
4631
9a3d9eb0 4632unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
1da177e4
LT		 4633{
4634 struct ata_port *ap = qc->ap;
4635
e50362ec
AL		 4636 /* Use polling pio if the LLD doesn't handle
4637 * interrupt driven pio and atapi CDB interrupt.
4638 */
4639 if (ap->flags & ATA_FLAG_PIO_POLLING) {
4640 switch (qc->tf.protocol) {
4641 case ATA_PROT_PIO:
4642 case ATA_PROT_ATAPI:
4643 case ATA_PROT_ATAPI_NODATA:
4644 qc->tf.flags |= ATA_TFLAG_POLLING;
4645 break;
4646 case ATA_PROT_ATAPI_DMA:
4647 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
3a778275 4648 /* see ata_dma_blacklisted() */
e50362ec
AL		 4649 BUG();
4650 break;
4651 default:
4652 break;
4653 }
4654 }
4655
312f7da2 4656 /* select the device */
1da177e4
LT		 4657 ata_dev_select(ap, qc->dev->devno, 1, 0);
4658
312f7da2 4659 /* start the command */
1da177e4
LT		 4660 switch (qc->tf.protocol) {
4661 case ATA_PROT_NODATA:
312f7da2
AL		 4662 if (qc->tf.flags & ATA_TFLAG_POLLING)
4663 ata_qc_set_polling(qc);
4664
e5338254 4665 ata_tf_to_host(ap, &qc->tf);
312f7da2
AL		 4666 ap->hsm_task_state = HSM_ST_LAST;
4667
4668 if (qc->tf.flags & ATA_TFLAG_POLLING)
31ce6dae 4669 ata_port_queue_task(ap, ata_pio_task, qc, 0);
312f7da2 4670
1da177e4
LT		 4671 break;
4672
4673 case ATA_PROT_DMA:
587005de 4674 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
312f7da2 4675
1da177e4
LT		 4676 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
4677 ap->ops->bmdma_setup(qc); /* set up bmdma */
4678 ap->ops->bmdma_start(qc); /* initiate bmdma */
312f7da2 4679 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 4680 break;
4681
312f7da2
AL		 4682 case ATA_PROT_PIO:
4683 if (qc->tf.flags & ATA_TFLAG_POLLING)
4684 ata_qc_set_polling(qc);
1da177e4 4685
e5338254 4686 ata_tf_to_host(ap, &qc->tf);
312f7da2 4687
54f00389
AL		 4688 if (qc->tf.flags & ATA_TFLAG_WRITE) {
4689 /* PIO data out protocol */
4690 ap->hsm_task_state = HSM_ST_FIRST;
31ce6dae 4691 ata_port_queue_task(ap, ata_pio_task, qc, 0);
54f00389
AL		 4692
4693 /* always send first data block using
e27486db 4694 * the ata_pio_task() codepath.
54f00389 4695 */
312f7da2 4696 } else {
54f00389
AL		 4697 /* PIO data in protocol */
4698 ap->hsm_task_state = HSM_ST;
4699
4700 if (qc->tf.flags & ATA_TFLAG_POLLING)
31ce6dae 4701 ata_port_queue_task(ap, ata_pio_task, qc, 0);
54f00389
AL		 4702
4703 /* if polling, ata_pio_task() handles the rest.
4704 * otherwise, interrupt handler takes over from here.
4705 */
312f7da2
AL		 4706 }
4707
1da177e4
LT		 4708 break;
4709
1da177e4 4710 case ATA_PROT_ATAPI:
1da177e4 4711 case ATA_PROT_ATAPI_NODATA:
312f7da2
AL		 4712 if (qc->tf.flags & ATA_TFLAG_POLLING)
4713 ata_qc_set_polling(qc);
4714
e5338254 4715 ata_tf_to_host(ap, &qc->tf);
f6ef65e6 4716
312f7da2
AL		 4717 ap->hsm_task_state = HSM_ST_FIRST;
4718
4719 /* send cdb by polling if no cdb interrupt */
4720 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
4721 (qc->tf.flags & ATA_TFLAG_POLLING))
31ce6dae 4722 ata_port_queue_task(ap, ata_pio_task, qc, 0);
1da177e4
LT		 4723 break;
4724
4725 case ATA_PROT_ATAPI_DMA:
587005de 4726 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
312f7da2 4727
1da177e4
LT		 4728 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
4729 ap->ops->bmdma_setup(qc); /* set up bmdma */
312f7da2
AL		 4730 ap->hsm_task_state = HSM_ST_FIRST;
4731
4732 /* send cdb by polling if no cdb interrupt */
4733 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
31ce6dae 4734 ata_port_queue_task(ap, ata_pio_task, qc, 0);
1da177e4
LT		 4735 break;
4736
4737 default:
4738 WARN_ON(1);
9a3d9eb0 4739 return AC_ERR_SYSTEM;
1da177e4
LT		 4740 }
4741
4742 return 0;
4743}
4744
1da177e4
LT		 4745/**
4746 * ata_host_intr - Handle host interrupt for given (port, task)
4747 * @ap: Port on which interrupt arrived (possibly...)
4748 * @qc: Taskfile currently active in engine
4749 *
4750 * Handle host interrupt for given queued command. Currently,
4751 * only DMA interrupts are handled. All other commands are
4752 * handled via polling with interrupts disabled (nIEN bit).
4753 *
4754 * LOCKING:
cca3974e 4755 * spin_lock_irqsave(host lock)
1da177e4
LT		 4756 *
4757 * RETURNS:
4758 * One if interrupt was handled, zero if not (shared irq).
4759 */
4760
4761inline unsigned int ata_host_intr (struct ata_port *ap,
4762 struct ata_queued_cmd *qc)
4763{
312f7da2 4764 u8 status, host_stat = 0;
1da177e4 4765
312f7da2
AL		 4766 VPRINTK("ata%u: protocol %d task_state %d\n",
4767 ap->id, qc->tf.protocol, ap->hsm_task_state);
1da177e4 4768
312f7da2
AL		 4769 /* Check whether we are expecting interrupt in this state */
4770 switch (ap->hsm_task_state) {
4771 case HSM_ST_FIRST:
6912ccd5
AL		 4772 /* Some pre-ATAPI-4 devices assert INTRQ
4773 * at this state when ready to receive CDB.
4774 */
1da177e4 4775
312f7da2
AL		 4776 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
4777 * The flag was turned on only for atapi devices.
4778 * No need to check is_atapi_taskfile(&qc->tf) again.
4779 */
4780 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1da177e4 4781 goto idle_irq;
1da177e4 4782 break;
312f7da2
AL		 4783 case HSM_ST_LAST:
4784 if (qc->tf.protocol == ATA_PROT_DMA ||
4785 qc->tf.protocol == ATA_PROT_ATAPI_DMA) {
4786 /* check status of DMA engine */
4787 host_stat = ap->ops->bmdma_status(ap);
4788 VPRINTK("ata%u: host_stat 0x%X\n", ap->id, host_stat);
4789
4790 /* if it's not our irq... */
4791 if (!(host_stat & ATA_DMA_INTR))
4792 goto idle_irq;
4793
4794 /* before we do anything else, clear DMA-Start bit */
4795 ap->ops->bmdma_stop(qc);
a4f16610
AL		 4796
4797 if (unlikely(host_stat & ATA_DMA_ERR)) {
4798 /* error when transfering data to/from memory */
4799 qc->err_mask |= AC_ERR_HOST_BUS;
4800 ap->hsm_task_state = HSM_ST_ERR;
4801 }
312f7da2
AL		 4802 }
4803 break;
4804 case HSM_ST:
4805 break;
1da177e4
LT		 4806 default:
4807 goto idle_irq;
4808 }
4809
312f7da2
AL		 4810 /* check altstatus */
4811 status = ata_altstatus(ap);
4812 if (status & ATA_BUSY)
4813 goto idle_irq;
1da177e4 4814
312f7da2
AL		 4815 /* check main status, clearing INTRQ */
4816 status = ata_chk_status(ap);
4817 if (unlikely(status & ATA_BUSY))
4818 goto idle_irq;
1da177e4 4819
312f7da2
AL		 4820 /* ack bmdma irq events */
4821 ap->ops->irq_clear(ap);
1da177e4 4822
bb5cb290 4823 ata_hsm_move(ap, qc, status, 0);
1da177e4
LT		 4824 return 1; /* irq handled */
4825
4826idle_irq:
4827 ap->stats.idle_irq++;
4828
4829#ifdef ATA_IRQ_TRAP
4830 if ((ap->stats.idle_irq % 1000) == 0) {
1da177e4 4831 ata_irq_ack(ap, 0); /* debug trap */
f15a1daf 4832 ata_port_printk(ap, KERN_WARNING, "irq trap\n");
23cfce89 4833 return 1;
1da177e4
LT		 4834 }
4835#endif
4836 return 0; /* irq not handled */
4837}
4838
4839/**
4840 * ata_interrupt - Default ATA host interrupt handler
0cba632b 4841 * @irq: irq line (unused)
cca3974e 4842 * @dev_instance: pointer to our ata_host information structure
1da177e4
LT		 4843 * @regs: unused
4844 *
0cba632b
JG		 4845 * Default interrupt handler for PCI IDE devices. Calls
4846 * ata_host_intr() for each port that is not disabled.
4847 *
1da177e4 4848 * LOCKING:
cca3974e 4849 * Obtains host lock during operation.
1da177e4
LT		 4850 *
4851 * RETURNS:
0cba632b 4852 * IRQ_NONE or IRQ_HANDLED.
1da177e4
LT		 4853 */
4854
4855irqreturn_t ata_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
4856{
cca3974e 4857 struct ata_host *host = dev_instance;
1da177e4
LT		 4858 unsigned int i;
4859 unsigned int handled = 0;
4860 unsigned long flags;
4861
4862 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
cca3974e 4863 spin_lock_irqsave(&host->lock, flags);
1da177e4 4864
cca3974e 4865 for (i = 0; i < host->n_ports; i++) {
1da177e4
LT		 4866 struct ata_port *ap;
4867
cca3974e 4868 ap = host->ports[i];
c1389503 4869 if (ap &&
029f5468 4870 !(ap->flags & ATA_FLAG_DISABLED)) {
1da177e4
LT		 4871 struct ata_queued_cmd *qc;
4872
4873 qc = ata_qc_from_tag(ap, ap->active_tag);
312f7da2 4874 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
21b1ed74 4875 (qc->flags & ATA_QCFLAG_ACTIVE))
1da177e4
LT		 4876 handled |= ata_host_intr(ap, qc);
4877 }
4878 }
4879
cca3974e 4880 spin_unlock_irqrestore(&host->lock, flags);
1da177e4
LT		 4881
4882 return IRQ_RETVAL(handled);
4883}
4884
34bf2170
TH		 4885/**
4886 * sata_scr_valid - test whether SCRs are accessible
4887 * @ap: ATA port to test SCR accessibility for
4888 *
4889 * Test whether SCRs are accessible for @ap.
4890 *
4891 * LOCKING:
4892 * None.
4893 *
4894 * RETURNS:
4895 * 1 if SCRs are accessible, 0 otherwise.
4896 */
4897int sata_scr_valid(struct ata_port *ap)
4898{
4899 return ap->cbl == ATA_CBL_SATA && ap->ops->scr_read;
4900}
4901
4902/**
4903 * sata_scr_read - read SCR register of the specified port
4904 * @ap: ATA port to read SCR for
4905 * @reg: SCR to read
4906 * @val: Place to store read value
4907 *
4908 * Read SCR register @reg of @ap into *@val. This function is
4909 * guaranteed to succeed if the cable type of the port is SATA
4910 * and the port implements ->scr_read.
4911 *
4912 * LOCKING:
4913 * None.
4914 *
4915 * RETURNS:
4916 * 0 on success, negative errno on failure.
4917 */
4918int sata_scr_read(struct ata_port *ap, int reg, u32 *val)
4919{
4920 if (sata_scr_valid(ap)) {
4921 *val = ap->ops->scr_read(ap, reg);
4922 return 0;
4923 }
4924 return -EOPNOTSUPP;
4925}
4926
4927/**
4928 * sata_scr_write - write SCR register of the specified port
4929 * @ap: ATA port to write SCR for
4930 * @reg: SCR to write
4931 * @val: value to write
4932 *
4933 * Write @val to SCR register @reg of @ap. This function is
4934 * guaranteed to succeed if the cable type of the port is SATA
4935 * and the port implements ->scr_read.
4936 *
4937 * LOCKING:
4938 * None.
4939 *
4940 * RETURNS:
4941 * 0 on success, negative errno on failure.
4942 */
4943int sata_scr_write(struct ata_port *ap, int reg, u32 val)
4944{
4945 if (sata_scr_valid(ap)) {
4946 ap->ops->scr_write(ap, reg, val);
4947 return 0;
4948 }
4949 return -EOPNOTSUPP;
4950}
4951
4952/**
4953 * sata_scr_write_flush - write SCR register of the specified port and flush
4954 * @ap: ATA port to write SCR for
4955 * @reg: SCR to write
4956 * @val: value to write
4957 *
4958 * This function is identical to sata_scr_write() except that this
4959 * function performs flush after writing to the register.
4960 *
4961 * LOCKING:
4962 * None.
4963 *
4964 * RETURNS:
4965 * 0 on success, negative errno on failure.
4966 */
4967int sata_scr_write_flush(struct ata_port *ap, int reg, u32 val)
4968{
4969 if (sata_scr_valid(ap)) {
4970 ap->ops->scr_write(ap, reg, val);
4971 ap->ops->scr_read(ap, reg);
4972 return 0;
4973 }
4974 return -EOPNOTSUPP;
4975}
4976
4977/**
4978 * ata_port_online - test whether the given port is online
4979 * @ap: ATA port to test
4980 *
4981 * Test whether @ap is online. Note that this function returns 0
4982 * if online status of @ap cannot be obtained, so
4983 * ata_port_online(ap) != !ata_port_offline(ap).
4984 *
4985 * LOCKING:
4986 * None.
4987 *
4988 * RETURNS:
4989 * 1 if the port online status is available and online.
4990 */
4991int ata_port_online(struct ata_port *ap)
4992{
4993 u32 sstatus;
4994
4995 if (!sata_scr_read(ap, SCR_STATUS, &sstatus) && (sstatus & 0xf) == 0x3)
4996 return 1;
4997 return 0;
4998}
4999
5000/**
5001 * ata_port_offline - test whether the given port is offline
5002 * @ap: ATA port to test
5003 *
5004 * Test whether @ap is offline. Note that this function returns
5005 * 0 if offline status of @ap cannot be obtained, so
5006 * ata_port_online(ap) != !ata_port_offline(ap).
5007 *
5008 * LOCKING:
5009 * None.
5010 *
5011 * RETURNS:
5012 * 1 if the port offline status is available and offline.
5013 */
5014int ata_port_offline(struct ata_port *ap)
5015{
5016 u32 sstatus;
5017
5018 if (!sata_scr_read(ap, SCR_STATUS, &sstatus) && (sstatus & 0xf) != 0x3)
5019 return 1;
5020 return 0;
5021}
0baab86b 5022
77b08fb5 5023int ata_flush_cache(struct ata_device *dev)
9b847548 5024{
977e6b9f 5025 unsigned int err_mask;
9b847548
JA		 5026 u8 cmd;
5027
5028 if (!ata_try_flush_cache(dev))
5029 return 0;
5030
5031 if (ata_id_has_flush_ext(dev->id))
5032 cmd = ATA_CMD_FLUSH_EXT;
5033 else
5034 cmd = ATA_CMD_FLUSH;
5035
977e6b9f
TH		 5036 err_mask = ata_do_simple_cmd(dev, cmd);
5037 if (err_mask) {
5038 ata_dev_printk(dev, KERN_ERR, "failed to flush cache\n");
5039 return -EIO;
5040 }
5041
5042 return 0;
9b847548
JA		 5043}
5044
cca3974e
JG		 5045static int ata_host_request_pm(struct ata_host *host, pm_message_t mesg,
5046 unsigned int action, unsigned int ehi_flags,
5047 int wait)
500530f6
TH		 5048{
5049 unsigned long flags;
5050 int i, rc;
5051
cca3974e
JG		 5052 for (i = 0; i < host->n_ports; i++) {
5053 struct ata_port *ap = host->ports[i];
500530f6
TH		 5054
5055 /* Previous resume operation might still be in
5056 * progress. Wait for PM_PENDING to clear.
5057 */
5058 if (ap->pflags & ATA_PFLAG_PM_PENDING) {
5059 ata_port_wait_eh(ap);
5060 WARN_ON(ap->pflags & ATA_PFLAG_PM_PENDING);
5061 }
5062
5063 /* request PM ops to EH */
5064 spin_lock_irqsave(ap->lock, flags);
5065
5066 ap->pm_mesg = mesg;
5067 if (wait) {
5068 rc = 0;
5069 ap->pm_result = &rc;
5070 }
5071
5072 ap->pflags |= ATA_PFLAG_PM_PENDING;
5073 ap->eh_info.action |= action;
5074 ap->eh_info.flags |= ehi_flags;
5075
5076 ata_port_schedule_eh(ap);
5077
5078 spin_unlock_irqrestore(ap->lock, flags);
5079
5080 /* wait and check result */
5081 if (wait) {
5082 ata_port_wait_eh(ap);
5083 WARN_ON(ap->pflags & ATA_PFLAG_PM_PENDING);
5084 if (rc)
5085 return rc;
5086 }
5087 }
5088
5089 return 0;
5090}
5091
5092/**
cca3974e
JG		 5093 * ata_host_suspend - suspend host
5094 * @host: host to suspend
500530f6
TH		 5095 * @mesg: PM message
5096 *
cca3974e 5097 * Suspend @host. Actual operation is performed by EH. This
500530f6
TH		 5098 * function requests EH to perform PM operations and waits for EH
5099 * to finish.
5100 *
5101 * LOCKING:
5102 * Kernel thread context (may sleep).
5103 *
5104 * RETURNS:
5105 * 0 on success, -errno on failure.
5106 */
cca3974e 5107int ata_host_suspend(struct ata_host *host, pm_message_t mesg)
500530f6
TH		 5108{
5109 int i, j, rc;
5110
cca3974e 5111 rc = ata_host_request_pm(host, mesg, 0, ATA_EHI_QUIET, 1);
500530f6
TH		 5112 if (rc)
5113 goto fail;
5114
5115 /* EH is quiescent now. Fail if we have any ready device.
5116 * This happens if hotplug occurs between completion of device
5117 * suspension and here.
5118 */
cca3974e
JG		 5119 for (i = 0; i < host->n_ports; i++) {
5120 struct ata_port *ap = host->ports[i];
500530f6
TH		 5121
5122 for (j = 0; j < ATA_MAX_DEVICES; j++) {
5123 struct ata_device *dev = &ap->device[j];
5124
5125 if (ata_dev_ready(dev)) {
5126 ata_port_printk(ap, KERN_WARNING,
5127 "suspend failed, device %d "
5128 "still active\n", dev->devno);
5129 rc = -EBUSY;
5130 goto fail;
5131 }
5132 }
5133 }
5134
cca3974e 5135 host->dev->power.power_state = mesg;
500530f6
TH		 5136 return 0;
5137
5138 fail:
cca3974e 5139 ata_host_resume(host);
500530f6
TH		 5140 return rc;
5141}
5142
5143/**
cca3974e
JG		 5144 * ata_host_resume - resume host
5145 * @host: host to resume
500530f6 5146 *
cca3974e 5147 * Resume @host. Actual operation is performed by EH. This
500530f6
TH		 5148 * function requests EH to perform PM operations and returns.
5149 * Note that all resume operations are performed parallely.
5150 *
5151 * LOCKING:
5152 * Kernel thread context (may sleep).
5153 */
cca3974e 5154void ata_host_resume(struct ata_host *host)
500530f6 5155{
cca3974e
JG		 5156 ata_host_request_pm(host, PMSG_ON, ATA_EH_SOFTRESET,
5157 ATA_EHI_NO_AUTOPSY | ATA_EHI_QUIET, 0);
5158 host->dev->power.power_state = PMSG_ON;
500530f6
TH		 5159}
5160
c893a3ae
RD		 5161/**
5162 * ata_port_start - Set port up for dma.
5163 * @ap: Port to initialize
5164 *
5165 * Called just after data structures for each port are
5166 * initialized. Allocates space for PRD table.
5167 *
5168 * May be used as the port_start() entry in ata_port_operations.
5169 *
5170 * LOCKING:
5171 * Inherited from caller.
5172 */
5173
1da177e4
LT		 5174int ata_port_start (struct ata_port *ap)
5175{
2f1f610b 5176 struct device *dev = ap->dev;
6037d6bb 5177 int rc;
1da177e4
LT		 5178
5179 ap->prd = dma_alloc_coherent(dev, ATA_PRD_TBL_SZ, &ap->prd_dma, GFP_KERNEL);
5180 if (!ap->prd)
5181 return -ENOMEM;
5182
6037d6bb
JG		 5183 rc = ata_pad_alloc(ap, dev);
5184 if (rc) {
cedc9a47 5185 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 5186 return rc;
cedc9a47
JG		 5187 }
5188
1da177e4
LT		 5189 DPRINTK("prd alloc, virt %p, dma %llx\n", ap->prd, (unsigned long long) ap->prd_dma);
5190
5191 return 0;
5192}
5193
0baab86b
EF		 5194
5195/**
5196 * ata_port_stop - Undo ata_port_start()
5197 * @ap: Port to shut down
5198 *
5199 * Frees the PRD table.
5200 *
5201 * May be used as the port_stop() entry in ata_port_operations.
5202 *
5203 * LOCKING:
6f0ef4fa 5204 * Inherited from caller.
0baab86b
EF		 5205 */
5206
1da177e4
LT		 5207void ata_port_stop (struct ata_port *ap)
5208{
2f1f610b 5209 struct device *dev = ap->dev;
1da177e4
LT		 5210
5211 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 5212 ata_pad_free(ap, dev);
1da177e4
LT		 5213}
5214
cca3974e 5215void ata_host_stop (struct ata_host *host)
aa8f0dc6 5216{
cca3974e
JG		 5217 if (host->mmio_base)
5218 iounmap(host->mmio_base);
aa8f0dc6
JG		 5219}
5220
3ef3b43d
TH		 5221/**
5222 * ata_dev_init - Initialize an ata_device structure
5223 * @dev: Device structure to initialize
5224 *
5225 * Initialize @dev in preparation for probing.
5226 *
5227 * LOCKING:
5228 * Inherited from caller.
5229 */
5230void ata_dev_init(struct ata_device *dev)
5231{
5232 struct ata_port *ap = dev->ap;
72fa4b74
TH		 5233 unsigned long flags;
5234
5a04bf4b
TH		 5235 /* SATA spd limit is bound to the first device */
5236 ap->sata_spd_limit = ap->hw_sata_spd_limit;
5237
72fa4b74
TH		 5238 /* High bits of dev->flags are used to record warm plug
5239 * requests which occur asynchronously. Synchronize using
cca3974e 5240 * host lock.
72fa4b74 5241 */
ba6a1308 5242 spin_lock_irqsave(ap->lock, flags);
72fa4b74 5243 dev->flags &= ~ATA_DFLAG_INIT_MASK;
ba6a1308 5244 spin_unlock_irqrestore(ap->lock, flags);
3ef3b43d 5245
72fa4b74
TH		 5246 memset((void *)dev + ATA_DEVICE_CLEAR_OFFSET, 0,
5247 sizeof(*dev) - ATA_DEVICE_CLEAR_OFFSET);
3ef3b43d
TH		 5248 dev->pio_mask = UINT_MAX;
5249 dev->mwdma_mask = UINT_MAX;
5250 dev->udma_mask = UINT_MAX;
5251}
5252
1da177e4 5253/**
155a8a9c 5254 * ata_port_init - Initialize an ata_port structure
1da177e4 5255 * @ap: Structure to initialize
cca3974e 5256 * @host: Collection of hosts to which @ap belongs
1da177e4
LT		 5257 * @ent: Probe information provided by low-level driver
5258 * @port_no: Port number associated with this ata_port
5259 *
155a8a9c 5260 * Initialize a new ata_port structure.
0cba632b 5261 *
1da177e4 5262 * LOCKING:
0cba632b 5263 * Inherited from caller.
1da177e4 5264 */
cca3974e 5265void ata_port_init(struct ata_port *ap, struct ata_host *host,
155a8a9c 5266 const struct ata_probe_ent *ent, unsigned int port_no)
1da177e4
LT		 5267{
5268 unsigned int i;
5269
cca3974e 5270 ap->lock = &host->lock;
198e0fed 5271 ap->flags = ATA_FLAG_DISABLED;
155a8a9c 5272 ap->id = ata_unique_id++;
1da177e4 5273 ap->ctl = ATA_DEVCTL_OBS;
cca3974e 5274 ap->host = host;
2f1f610b 5275 ap->dev = ent->dev;
1da177e4 5276 ap->port_no = port_no;
fea63e38
TH		 5277 if (port_no == 1 && ent->pinfo2) {
5278 ap->pio_mask = ent->pinfo2->pio_mask;
5279 ap->mwdma_mask = ent->pinfo2->mwdma_mask;
5280 ap->udma_mask = ent->pinfo2->udma_mask;
5281 ap->flags |= ent->pinfo2->flags;
5282 ap->ops = ent->pinfo2->port_ops;
5283 } else {
5284 ap->pio_mask = ent->pio_mask;
5285 ap->mwdma_mask = ent->mwdma_mask;
5286 ap->udma_mask = ent->udma_mask;
5287 ap->flags |= ent->port_flags;
5288 ap->ops = ent->port_ops;
5289 }
5a04bf4b 5290 ap->hw_sata_spd_limit = UINT_MAX;
1da177e4
LT		 5291 ap->active_tag = ATA_TAG_POISON;
5292 ap->last_ctl = 0xFF;
bd5d825c
BP		 5293
5294#if defined(ATA_VERBOSE_DEBUG)
5295 /* turn on all debugging levels */
5296 ap->msg_enable = 0x00FF;
5297#elif defined(ATA_DEBUG)
5298 ap->msg_enable = ATA_MSG_DRV | ATA_MSG_INFO | ATA_MSG_CTL | ATA_MSG_WARN | ATA_MSG_ERR;
88574551 5299#else
0dd4b21f 5300 ap->msg_enable = ATA_MSG_DRV | ATA_MSG_ERR | ATA_MSG_WARN;
bd5d825c 5301#endif
1da177e4 5302
86e45b6b 5303 INIT_WORK(&ap->port_task, NULL, NULL);
580b2102 5304 INIT_WORK(&ap->hotplug_task, ata_scsi_hotplug, ap);
3057ac3c 5305 INIT_WORK(&ap->scsi_rescan_task, ata_scsi_dev_rescan, ap);
a72ec4ce 5306 INIT_LIST_HEAD(&ap->eh_done_q);
c6cf9e99 5307 init_waitqueue_head(&ap->eh_wait_q);
1da177e4 5308
838df628
TH		 5309 /* set cable type */
5310 ap->cbl = ATA_CBL_NONE;
5311 if (ap->flags & ATA_FLAG_SATA)
5312 ap->cbl = ATA_CBL_SATA;
5313
acf356b1
TH		 5314 for (i = 0; i < ATA_MAX_DEVICES; i++) {
5315 struct ata_device *dev = &ap->device[i];
38d87234 5316 dev->ap = ap;
72fa4b74 5317 dev->devno = i;
3ef3b43d 5318 ata_dev_init(dev);
acf356b1 5319 }
1da177e4
LT		 5320
5321#ifdef ATA_IRQ_TRAP
5322 ap->stats.unhandled_irq = 1;
5323 ap->stats.idle_irq = 1;
5324#endif
5325
5326 memcpy(&ap->ioaddr, &ent->port[port_no], sizeof(struct ata_ioports));
5327}
5328
155a8a9c 5329/**
4608c160
TH		 5330 * ata_port_init_shost - Initialize SCSI host associated with ATA port
5331 * @ap: ATA port to initialize SCSI host for
5332 * @shost: SCSI host associated with @ap
155a8a9c 5333 *
4608c160 5334 * Initialize SCSI host @shost associated with ATA port @ap.
155a8a9c
BK		 5335 *
5336 * LOCKING:
5337 * Inherited from caller.
5338 */
4608c160 5339static void ata_port_init_shost(struct ata_port *ap, struct Scsi_Host *shost)
155a8a9c 5340{
cca3974e 5341 ap->scsi_host = shost;
155a8a9c 5342
4608c160
TH		 5343 shost->unique_id = ap->id;
5344 shost->max_id = 16;
5345 shost->max_lun = 1;
5346 shost->max_channel = 1;
5347 shost->max_cmd_len = 12;
155a8a9c
BK		 5348}
5349
1da177e4 5350/**
996139f1 5351 * ata_port_add - Attach low-level ATA driver to system
1da177e4 5352 * @ent: Information provided by low-level driver
cca3974e 5353 * @host: Collections of ports to which we add
1da177e4
LT		 5354 * @port_no: Port number associated with this host
5355 *
0cba632b
JG		 5356 * Attach low-level ATA driver to system.
5357 *
1da177e4 5358 * LOCKING:
0cba632b 5359 * PCI/etc. bus probe sem.
1da177e4
LT		 5360 *
5361 * RETURNS:
0cba632b 5362 * New ata_port on success, for NULL on error.
1da177e4 5363 */
996139f1 5364static struct ata_port * ata_port_add(const struct ata_probe_ent *ent,
cca3974e 5365 struct ata_host *host,
1da177e4
LT		 5366 unsigned int port_no)
5367{
996139f1 5368 struct Scsi_Host *shost;
1da177e4 5369 struct ata_port *ap;
1da177e4
LT		 5370
5371 DPRINTK("ENTER\n");
aec5c3c1 5372
52783c5d 5373 if (!ent->port_ops->error_handler &&
cca3974e 5374 !(ent->port_flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST))) {
aec5c3c1
TH		 5375 printk(KERN_ERR "ata%u: no reset mechanism available\n",
5376 port_no);
5377 return NULL;
5378 }
5379
996139f1
JG		 5380 shost = scsi_host_alloc(ent->sht, sizeof(struct ata_port));
5381 if (!shost)
1da177e4
LT		 5382 return NULL;
5383
996139f1 5384 shost->transportt = &ata_scsi_transport_template;
30afc84c 5385
996139f1 5386 ap = ata_shost_to_port(shost);
1da177e4 5387
cca3974e 5388 ata_port_init(ap, host, ent, port_no);
996139f1 5389 ata_port_init_shost(ap, shost);
1da177e4 5390
1da177e4 5391 return ap;
1da177e4
LT		 5392}
5393
b03732f0 5394/**
cca3974e
JG		 5395 * ata_sas_host_init - Initialize a host struct
5396 * @host: host to initialize
5397 * @dev: device host is attached to
5398 * @flags: host flags
5399 * @ops: port_ops
b03732f0
BK		 5400 *
5401 * LOCKING:
5402 * PCI/etc. bus probe sem.
5403 *
5404 */
5405
cca3974e
JG		 5406void ata_host_init(struct ata_host *host, struct device *dev,
5407 unsigned long flags, const struct ata_port_operations *ops)
b03732f0 5408{
cca3974e
JG		 5409 spin_lock_init(&host->lock);
5410 host->dev = dev;
5411 host->flags = flags;
5412 host->ops = ops;
b03732f0
BK		 5413}
5414
1da177e4 5415/**
0cba632b
JG		 5416 * ata_device_add - Register hardware device with ATA and SCSI layers
5417 * @ent: Probe information describing hardware device to be registered
5418 *
5419 * This function processes the information provided in the probe
5420 * information struct @ent, allocates the necessary ATA and SCSI
5421 * host information structures, initializes them, and registers
5422 * everything with requisite kernel subsystems.
5423 *
5424 * This function requests irqs, probes the ATA bus, and probes
5425 * the SCSI bus.
1da177e4
LT		 5426 *
5427 * LOCKING:
0cba632b 5428 * PCI/etc. bus probe sem.
1da177e4
LT		 5429 *
5430 * RETURNS:
0cba632b 5431 * Number of ports registered. Zero on error (no ports registered).
1da177e4 5432 */
057ace5e 5433int ata_device_add(const struct ata_probe_ent *ent)
1da177e4 5434{
6d0500df 5435 unsigned int i;
1da177e4 5436 struct device *dev = ent->dev;
cca3974e 5437 struct ata_host *host;
39b07ce6 5438 int rc;
1da177e4
LT		 5439
5440 DPRINTK("ENTER\n");
5441 /* alloc a container for our list of ATA ports (buses) */
cca3974e
JG		 5442 host = kzalloc(sizeof(struct ata_host) +
5443 (ent->n_ports * sizeof(void *)), GFP_KERNEL);
5444 if (!host)
1da177e4 5445 return 0;
1da177e4 5446
cca3974e
JG		 5447 ata_host_init(host, dev, ent->_host_flags, ent->port_ops);
5448 host->n_ports = ent->n_ports;
5449 host->irq = ent->irq;
5450 host->irq2 = ent->irq2;
5451 host->mmio_base = ent->mmio_base;
5452 host->private_data = ent->private_data;
1da177e4
LT		 5453
5454 /* register each port bound to this device */
cca3974e 5455 for (i = 0; i < host->n_ports; i++) {
1da177e4
LT		 5456 struct ata_port *ap;
5457 unsigned long xfer_mode_mask;
2ec7df04 5458 int irq_line = ent->irq;
1da177e4 5459
cca3974e 5460 ap = ata_port_add(ent, host, i);
1da177e4
LT		 5461 if (!ap)
5462 goto err_out;
5463
cca3974e 5464 host->ports[i] = ap;
dd5b06c4
TH		 5465
5466 /* dummy? */
5467 if (ent->dummy_port_mask & (1 << i)) {
5468 ata_port_printk(ap, KERN_INFO, "DUMMY\n");
5469 ap->ops = &ata_dummy_port_ops;
5470 continue;
5471 }
5472
5473 /* start port */
5474 rc = ap->ops->port_start(ap);
5475 if (rc) {
cca3974e
JG		 5476 host->ports[i] = NULL;
5477 scsi_host_put(ap->scsi_host);
dd5b06c4
TH		 5478 goto err_out;
5479 }
5480
2ec7df04
AC		 5481 /* Report the secondary IRQ for second channel legacy */
5482 if (i == 1 && ent->irq2)
5483 irq_line = ent->irq2;
5484
1da177e4
LT		 5485 xfer_mode_mask =(ap->udma_mask << ATA_SHIFT_UDMA) |
5486 (ap->mwdma_mask << ATA_SHIFT_MWDMA) |
5487 (ap->pio_mask << ATA_SHIFT_PIO);
5488
5489 /* print per-port info to dmesg */
f15a1daf 5490 ata_port_printk(ap, KERN_INFO, "%cATA max %s cmd 0x%lX "
2ec7df04 5491 "ctl 0x%lX bmdma 0x%lX irq %d\n",
f15a1daf
TH		 5492 ap->flags & ATA_FLAG_SATA ? 'S' : 'P',
5493 ata_mode_string(xfer_mode_mask),
5494 ap->ioaddr.cmd_addr,
5495 ap->ioaddr.ctl_addr,
5496 ap->ioaddr.bmdma_addr,
2ec7df04 5497 irq_line);
1da177e4
LT		 5498
5499 ata_chk_status(ap);
cca3974e 5500 host->ops->irq_clear(ap);
e3180499 5501 ata_eh_freeze_port(ap); /* freeze port before requesting IRQ */
1da177e4
LT		 5502 }
5503
2ec7df04 5504 /* obtain irq, that may be shared between channels */
39b07ce6 5505 rc = request_irq(ent->irq, ent->port_ops->irq_handler, ent->irq_flags,
cca3974e 5506 DRV_NAME, host);
39b07ce6
JG		 5507 if (rc) {
5508 dev_printk(KERN_ERR, dev, "irq %lu request failed: %d\n",
5509 ent->irq, rc);
1da177e4 5510 goto err_out;
39b07ce6 5511 }
1da177e4 5512
2ec7df04
AC		 5513 /* do we have a second IRQ for the other channel, eg legacy mode */
5514 if (ent->irq2) {
5515 /* We will get weird core code crashes later if this is true
5516 so trap it now */
5517 BUG_ON(ent->irq == ent->irq2);
5518
5519 rc = request_irq(ent->irq2, ent->port_ops->irq_handler, ent->irq_flags,
cca3974e 5520 DRV_NAME, host);
2ec7df04
AC		 5521 if (rc) {
5522 dev_printk(KERN_ERR, dev, "irq %lu request failed: %d\n",
5523 ent->irq2, rc);
5524 goto err_out_free_irq;
5525 }
5526 }
5527
1da177e4
LT		 5528 /* perform each probe synchronously */
5529 DPRINTK("probe begin\n");
cca3974e
JG		 5530 for (i = 0; i < host->n_ports; i++) {
5531 struct ata_port *ap = host->ports[i];
5a04bf4b 5532 u32 scontrol;
1da177e4
LT		 5533 int rc;
5534
5a04bf4b
TH		 5535 /* init sata_spd_limit to the current value */
5536 if (sata_scr_read(ap, SCR_CONTROL, &scontrol) == 0) {
5537 int spd = (scontrol >> 4) & 0xf;
5538 ap->hw_sata_spd_limit &= (1 << spd) - 1;
5539 }
5540 ap->sata_spd_limit = ap->hw_sata_spd_limit;
5541
cca3974e 5542 rc = scsi_add_host(ap->scsi_host, dev);
1da177e4 5543 if (rc) {
f15a1daf 5544 ata_port_printk(ap, KERN_ERR, "scsi_add_host failed\n");
1da177e4
LT		 5545 /* FIXME: do something useful here */
5546 /* FIXME: handle unconditional calls to
5547 * scsi_scan_host and ata_host_remove, below,
5548 * at the very least
5549 */
5550 }
3e706399 5551
52783c5d 5552 if (ap->ops->error_handler) {
1cdaf534 5553 struct ata_eh_info *ehi = &ap->eh_info;
3e706399
TH		 5554 unsigned long flags;
5555
5556 ata_port_probe(ap);
5557
5558 /* kick EH for boot probing */
ba6a1308 5559 spin_lock_irqsave(ap->lock, flags);
3e706399 5560
1cdaf534
TH		 5561 ehi->probe_mask = (1 << ATA_MAX_DEVICES) - 1;
5562 ehi->action |= ATA_EH_SOFTRESET;
5563 ehi->flags |= ATA_EHI_NO_AUTOPSY | ATA_EHI_QUIET;
3e706399 5564
b51e9e5d 5565 ap->pflags |= ATA_PFLAG_LOADING;
3e706399
TH		 5566 ata_port_schedule_eh(ap);
5567
ba6a1308 5568 spin_unlock_irqrestore(ap->lock, flags);
3e706399
TH		 5569
5570 /* wait for EH to finish */
5571 ata_port_wait_eh(ap);
5572 } else {
5573 DPRINTK("ata%u: bus probe begin\n", ap->id);
5574 rc = ata_bus_probe(ap);
5575 DPRINTK("ata%u: bus probe end\n", ap->id);
5576
5577 if (rc) {
5578 /* FIXME: do something useful here?
5579 * Current libata behavior will
5580 * tear down everything when
5581 * the module is removed
5582 * or the h/w is unplugged.
5583 */
5584 }
5585 }
1da177e4
LT		 5586 }
5587
5588 /* probes are done, now scan each port's disk(s) */
c893a3ae 5589 DPRINTK("host probe begin\n");
cca3974e
JG		 5590 for (i = 0; i < host->n_ports; i++) {
5591 struct ata_port *ap = host->ports[i];
1da177e4 5592
644dd0cc 5593 ata_scsi_scan_host(ap);
1da177e4
LT		 5594 }
5595
cca3974e 5596 dev_set_drvdata(dev, host);
1da177e4
LT		 5597
5598 VPRINTK("EXIT, returning %u\n", ent->n_ports);
5599 return ent->n_ports; /* success */
5600
2ec7df04 5601err_out_free_irq:
cca3974e 5602 free_irq(ent->irq, host);
1da177e4 5603err_out:
cca3974e
JG		 5604 for (i = 0; i < host->n_ports; i++) {
5605 struct ata_port *ap = host->ports[i];
77f3f879
TH		 5606 if (ap) {
5607 ap->ops->port_stop(ap);
cca3974e 5608 scsi_host_put(ap->scsi_host);
77f3f879 5609 }
1da177e4 5610 }
6d0500df 5611
cca3974e 5612 kfree(host);
1da177e4
LT		 5613 VPRINTK("EXIT, returning 0\n");
5614 return 0;
5615}
5616
720ba126
TH		 5617/**
5618 * ata_port_detach - Detach ATA port in prepration of device removal
5619 * @ap: ATA port to be detached
5620 *
5621 * Detach all ATA devices and the associated SCSI devices of @ap;
5622 * then, remove the associated SCSI host. @ap is guaranteed to
5623 * be quiescent on return from this function.
5624 *
5625 * LOCKING:
5626 * Kernel thread context (may sleep).
5627 */
5628void ata_port_detach(struct ata_port *ap)
5629{
5630 unsigned long flags;
5631 int i;
5632
5633 if (!ap->ops->error_handler)
c3cf30a9 5634 goto skip_eh;
720ba126
TH		 5635
5636 /* tell EH we're leaving & flush EH */
ba6a1308 5637 spin_lock_irqsave(ap->lock, flags);
b51e9e5d 5638 ap->pflags |= ATA_PFLAG_UNLOADING;
ba6a1308 5639 spin_unlock_irqrestore(ap->lock, flags);
720ba126
TH		 5640
5641 ata_port_wait_eh(ap);
5642
5643 /* EH is now guaranteed to see UNLOADING, so no new device
5644 * will be attached. Disable all existing devices.
5645 */
ba6a1308 5646 spin_lock_irqsave(ap->lock, flags);
720ba126
TH		 5647
5648 for (i = 0; i < ATA_MAX_DEVICES; i++)
5649 ata_dev_disable(&ap->device[i]);
5650
ba6a1308 5651 spin_unlock_irqrestore(ap->lock, flags);
720ba126
TH		 5652
5653 /* Final freeze & EH. All in-flight commands are aborted. EH
5654 * will be skipped and retrials will be terminated with bad
5655 * target.
5656 */
ba6a1308 5657 spin_lock_irqsave(ap->lock, flags);
720ba126 5658 ata_port_freeze(ap); /* won't be thawed */
ba6a1308 5659 spin_unlock_irqrestore(ap->lock, flags);
720ba126
TH		 5660
5661 ata_port_wait_eh(ap);
5662
5663 /* Flush hotplug task. The sequence is similar to
5664 * ata_port_flush_task().
5665 */
5666 flush_workqueue(ata_aux_wq);
5667 cancel_delayed_work(&ap->hotplug_task);
5668 flush_workqueue(ata_aux_wq);
5669
c3cf30a9 5670 skip_eh:
720ba126 5671 /* remove the associated SCSI host */
cca3974e 5672 scsi_remove_host(ap->scsi_host);
720ba126
TH		 5673}
5674
17b14451 5675/**
cca3974e
JG		 5676 * ata_host_remove - PCI layer callback for device removal
5677 * @host: ATA host set that was removed
17b14451 5678 *
2e9edbf8 5679 * Unregister all objects associated with this host set. Free those
17b14451
AC		 5680 * objects.
5681 *
5682 * LOCKING:
5683 * Inherited from calling layer (may sleep).
5684 */
5685
cca3974e 5686void ata_host_remove(struct ata_host *host)
17b14451 5687{
17b14451
AC		 5688 unsigned int i;
5689
cca3974e
JG		 5690 for (i = 0; i < host->n_ports; i++)
5691 ata_port_detach(host->ports[i]);
17b14451 5692
cca3974e
JG		 5693 free_irq(host->irq, host);
5694 if (host->irq2)
5695 free_irq(host->irq2, host);
17b14451 5696
cca3974e
JG		 5697 for (i = 0; i < host->n_ports; i++) {
5698 struct ata_port *ap = host->ports[i];
17b14451 5699
cca3974e 5700 ata_scsi_release(ap->scsi_host);
17b14451
AC		 5701
5702 if ((ap->flags & ATA_FLAG_NO_LEGACY) == 0) {
5703 struct ata_ioports *ioaddr = &ap->ioaddr;
5704
2ec7df04
AC		 5705 /* FIXME: Add -ac IDE pci mods to remove these special cases */
5706 if (ioaddr->cmd_addr == ATA_PRIMARY_CMD)
5707 release_region(ATA_PRIMARY_CMD, 8);
5708 else if (ioaddr->cmd_addr == ATA_SECONDARY_CMD)
5709 release_region(ATA_SECONDARY_CMD, 8);
17b14451
AC		 5710 }
5711
cca3974e 5712 scsi_host_put(ap->scsi_host);
17b14451
AC		 5713 }
5714
cca3974e
JG		 5715 if (host->ops->host_stop)
5716 host->ops->host_stop(host);
17b14451 5717
cca3974e 5718 kfree(host);
17b14451
AC		 5719}
5720
1da177e4
LT		 5721/**
5722 * ata_scsi_release - SCSI layer callback hook for host unload
5723 * @host: libata host to be unloaded
5724 *
5725 * Performs all duties necessary to shut down a libata port...
5726 * Kill port kthread, disable port, and release resources.
5727 *
5728 * LOCKING:
5729 * Inherited from SCSI layer.
5730 *
5731 * RETURNS:
5732 * One.
5733 */
5734
cca3974e 5735int ata_scsi_release(struct Scsi_Host *shost)
1da177e4 5736{
cca3974e 5737 struct ata_port *ap = ata_shost_to_port(shost);
1da177e4
LT		 5738
5739 DPRINTK("ENTER\n");
5740
5741 ap->ops->port_disable(ap);
6543bc07 5742 ap->ops->port_stop(ap);
1da177e4
LT		 5743
5744 DPRINTK("EXIT\n");
5745 return 1;
5746}
5747
f6d950e2
BK		 5748struct ata_probe_ent *
5749ata_probe_ent_alloc(struct device *dev, const struct ata_port_info *port)
5750{
5751 struct ata_probe_ent *probe_ent;
5752
5753 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
5754 if (!probe_ent) {
5755 printk(KERN_ERR DRV_NAME "(%s): out of memory\n",
5756 kobject_name(&(dev->kobj)));
5757 return NULL;
5758 }
5759
5760 INIT_LIST_HEAD(&probe_ent->node);
5761 probe_ent->dev = dev;
5762
5763 probe_ent->sht = port->sht;
cca3974e 5764 probe_ent->port_flags = port->flags;
f6d950e2
BK		 5765 probe_ent->pio_mask = port->pio_mask;
5766 probe_ent->mwdma_mask = port->mwdma_mask;
5767 probe_ent->udma_mask = port->udma_mask;
5768 probe_ent->port_ops = port->port_ops;
5769
5770 return probe_ent;
5771}
5772
1da177e4
LT		 5773/**
5774 * ata_std_ports - initialize ioaddr with standard port offsets.
5775 * @ioaddr: IO address structure to be initialized
0baab86b
EF		 5776 *
5777 * Utility function which initializes data_addr, error_addr,
5778 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
5779 * device_addr, status_addr, and command_addr to standard offsets
5780 * relative to cmd_addr.
5781 *
5782 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
1da177e4 5783 */
0baab86b 5784
1da177e4
LT		 5785void ata_std_ports(struct ata_ioports *ioaddr)
5786{
5787 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
5788 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
5789 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
5790 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
5791 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
5792 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
5793 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
5794 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
5795 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
5796 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
5797}
5798
0baab86b 5799
374b1873
JG		 5800#ifdef CONFIG_PCI
5801
cca3974e 5802void ata_pci_host_stop (struct ata_host *host)
374b1873 5803{
cca3974e 5804 struct pci_dev *pdev = to_pci_dev(host->dev);
374b1873 5805
cca3974e 5806 pci_iounmap(pdev, host->mmio_base);
374b1873
JG		 5807}
5808
1da177e4
LT		 5809/**
5810 * ata_pci_remove_one - PCI layer callback for device removal
5811 * @pdev: PCI device that was removed
5812 *
5813 * PCI layer indicates to libata via this hook that
6f0ef4fa 5814 * hot-unplug or module unload event has occurred.
1da177e4
LT		 5815 * Handle this by unregistering all objects associated
5816 * with this PCI device. Free those objects. Then finally
5817 * release PCI resources and disable device.
5818 *
5819 * LOCKING:
5820 * Inherited from PCI layer (may sleep).
5821 */
5822
5823void ata_pci_remove_one (struct pci_dev *pdev)
5824{
5825 struct device *dev = pci_dev_to_dev(pdev);
cca3974e 5826 struct ata_host *host = dev_get_drvdata(dev);
1da177e4 5827
cca3974e 5828 ata_host_remove(host);
f0eb62b8 5829
1da177e4
LT		 5830 pci_release_regions(pdev);
5831 pci_disable_device(pdev);
5832 dev_set_drvdata(dev, NULL);
5833}
5834
5835/* move to PCI subsystem */
057ace5e 5836int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits)
1da177e4
LT		 5837{
5838 unsigned long tmp = 0;
5839
5840 switch (bits->width) {
5841 case 1: {
5842 u8 tmp8 = 0;
5843 pci_read_config_byte(pdev, bits->reg, &tmp8);
5844 tmp = tmp8;
5845 break;
5846 }
5847 case 2: {
5848 u16 tmp16 = 0;
5849 pci_read_config_word(pdev, bits->reg, &tmp16);
5850 tmp = tmp16;
5851 break;
5852 }
5853 case 4: {
5854 u32 tmp32 = 0;
5855 pci_read_config_dword(pdev, bits->reg, &tmp32);
5856 tmp = tmp32;
5857 break;
5858 }
5859
5860 default:
5861 return -EINVAL;
5862 }
5863
5864 tmp &= bits->mask;
5865
5866 return (tmp == bits->val) ? 1 : 0;
5867}
9b847548 5868
3c5100c1 5869void ata_pci_device_do_suspend(struct pci_dev *pdev, pm_message_t mesg)
9b847548
JA		 5870{
5871 pci_save_state(pdev);
500530f6 5872
3c5100c1 5873 if (mesg.event == PM_EVENT_SUSPEND) {
500530f6
TH		 5874 pci_disable_device(pdev);
5875 pci_set_power_state(pdev, PCI_D3hot);
5876 }
9b847548
JA		 5877}
5878
500530f6 5879void ata_pci_device_do_resume(struct pci_dev *pdev)
9b847548
JA		 5880{
5881 pci_set_power_state(pdev, PCI_D0);
5882 pci_restore_state(pdev);
5883 pci_enable_device(pdev);
5884 pci_set_master(pdev);
500530f6
TH		 5885}
5886
3c5100c1 5887int ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
500530f6 5888{
cca3974e 5889 struct ata_host *host = dev_get_drvdata(&pdev->dev);
500530f6
TH		 5890 int rc = 0;
5891
cca3974e 5892 rc = ata_host_suspend(host, mesg);
500530f6
TH		 5893 if (rc)
5894 return rc;
5895
3c5100c1 5896 ata_pci_device_do_suspend(pdev, mesg);
500530f6
TH		 5897
5898 return 0;
5899}
5900
5901int ata_pci_device_resume(struct pci_dev *pdev)
5902{
cca3974e 5903 struct ata_host *host = dev_get_drvdata(&pdev->dev);
500530f6
TH		 5904
5905 ata_pci_device_do_resume(pdev);
cca3974e 5906 ata_host_resume(host);
9b847548
JA		 5907 return 0;
5908}
1da177e4
LT		 5909#endif /* CONFIG_PCI */
5910
5911
1da177e4
LT		 5912static int __init ata_init(void)
5913{
a8601e5f 5914 ata_probe_timeout *= HZ;
1da177e4
LT		 5915 ata_wq = create_workqueue("ata");
5916 if (!ata_wq)
5917 return -ENOMEM;
5918
453b07ac
TH		 5919 ata_aux_wq = create_singlethread_workqueue("ata_aux");
5920 if (!ata_aux_wq) {
5921 destroy_workqueue(ata_wq);
5922 return -ENOMEM;
5923 }
5924
1da177e4
LT		 5925 printk(KERN_DEBUG "libata version " DRV_VERSION " loaded.\n");
5926 return 0;
5927}
5928
5929static void __exit ata_exit(void)
5930{
5931 destroy_workqueue(ata_wq);
453b07ac 5932 destroy_workqueue(ata_aux_wq);
1da177e4
LT		 5933}
5934
5935module_init(ata_init);
5936module_exit(ata_exit);
5937
67846b30 5938static unsigned long ratelimit_time;
34af946a 5939static DEFINE_SPINLOCK(ata_ratelimit_lock);
67846b30
JG		 5940
5941int ata_ratelimit(void)
5942{
5943 int rc;
5944 unsigned long flags;
5945
5946 spin_lock_irqsave(&ata_ratelimit_lock, flags);
5947
5948 if (time_after(jiffies, ratelimit_time)) {
5949 rc = 1;
5950 ratelimit_time = jiffies + (HZ/5);
5951 } else
5952 rc = 0;
5953
5954 spin_unlock_irqrestore(&ata_ratelimit_lock, flags);
5955
5956 return rc;
5957}
5958
c22daff4
TH		 5959/**
5960 * ata_wait_register - wait until register value changes
5961 * @reg: IO-mapped register
5962 * @mask: Mask to apply to read register value
5963 * @val: Wait condition
5964 * @interval_msec: polling interval in milliseconds
5965 * @timeout_msec: timeout in milliseconds
5966 *
5967 * Waiting for some bits of register to change is a common
5968 * operation for ATA controllers. This function reads 32bit LE
5969 * IO-mapped register @reg and tests for the following condition.
5970 *
5971 * (*@reg & mask) != val
5972 *
5973 * If the condition is met, it returns; otherwise, the process is
5974 * repeated after @interval_msec until timeout.
5975 *
5976 * LOCKING:
5977 * Kernel thread context (may sleep)
5978 *
5979 * RETURNS:
5980 * The final register value.
5981 */
5982u32 ata_wait_register(void __iomem *reg, u32 mask, u32 val,
5983 unsigned long interval_msec,
5984 unsigned long timeout_msec)
5985{
5986 unsigned long timeout;
5987 u32 tmp;
5988
5989 tmp = ioread32(reg);
5990
5991 /* Calculate timeout _after_ the first read to make sure
5992 * preceding writes reach the controller before starting to
5993 * eat away the timeout.
5994 */
5995 timeout = jiffies + (timeout_msec * HZ) / 1000;
5996
5997 while ((tmp & mask) == val && time_before(jiffies, timeout)) {
5998 msleep(interval_msec);
5999 tmp = ioread32(reg);
6000 }
6001
6002 return tmp;
6003}
6004
dd5b06c4
TH		 6005/*
6006 * Dummy port_ops
6007 */
6008static void ata_dummy_noret(struct ata_port *ap) { }
6009static int ata_dummy_ret0(struct ata_port *ap) { return 0; }
6010static void ata_dummy_qc_noret(struct ata_queued_cmd *qc) { }
6011
6012static u8 ata_dummy_check_status(struct ata_port *ap)
6013{
6014 return ATA_DRDY;
6015}
6016
6017static unsigned int ata_dummy_qc_issue(struct ata_queued_cmd *qc)
6018{
6019 return AC_ERR_SYSTEM;
6020}
6021
6022const struct ata_port_operations ata_dummy_port_ops = {
6023 .port_disable = ata_port_disable,
6024 .check_status = ata_dummy_check_status,
6025 .check_altstatus = ata_dummy_check_status,
6026 .dev_select = ata_noop_dev_select,
6027 .qc_prep = ata_noop_qc_prep,
6028 .qc_issue = ata_dummy_qc_issue,
6029 .freeze = ata_dummy_noret,
6030 .thaw = ata_dummy_noret,
6031 .error_handler = ata_dummy_noret,
6032 .post_internal_cmd = ata_dummy_qc_noret,
6033 .irq_clear = ata_dummy_noret,
6034 .port_start = ata_dummy_ret0,
6035 .port_stop = ata_dummy_noret,
6036};
6037
1da177e4
LT		 6038/*
6039 * libata is essentially a library of internal helper functions for
6040 * low-level ATA host controller drivers. As such, the API/ABI is
6041 * likely to change as new drivers are added and updated.
6042 * Do not depend on ABI/API stability.
6043 */
6044
e9c83914
TH		 6045EXPORT_SYMBOL_GPL(sata_deb_timing_normal);
6046EXPORT_SYMBOL_GPL(sata_deb_timing_hotplug);
6047EXPORT_SYMBOL_GPL(sata_deb_timing_long);
dd5b06c4 6048EXPORT_SYMBOL_GPL(ata_dummy_port_ops);
1da177e4
LT		 6049EXPORT_SYMBOL_GPL(ata_std_bios_param);
6050EXPORT_SYMBOL_GPL(ata_std_ports);
cca3974e 6051EXPORT_SYMBOL_GPL(ata_host_init);
1da177e4 6052EXPORT_SYMBOL_GPL(ata_device_add);
720ba126 6053EXPORT_SYMBOL_GPL(ata_port_detach);
cca3974e 6054EXPORT_SYMBOL_GPL(ata_host_remove);
1da177e4
LT		 6055EXPORT_SYMBOL_GPL(ata_sg_init);
6056EXPORT_SYMBOL_GPL(ata_sg_init_one);
9a1004d0 6057EXPORT_SYMBOL_GPL(ata_hsm_move);
f686bcb8 6058EXPORT_SYMBOL_GPL(ata_qc_complete);
dedaf2b0 6059EXPORT_SYMBOL_GPL(ata_qc_complete_multiple);
1da177e4 6060EXPORT_SYMBOL_GPL(ata_qc_issue_prot);
1da177e4
LT		 6061EXPORT_SYMBOL_GPL(ata_tf_load);
6062EXPORT_SYMBOL_GPL(ata_tf_read);
6063EXPORT_SYMBOL_GPL(ata_noop_dev_select);
6064EXPORT_SYMBOL_GPL(ata_std_dev_select);
6065EXPORT_SYMBOL_GPL(ata_tf_to_fis);
6066EXPORT_SYMBOL_GPL(ata_tf_from_fis);
6067EXPORT_SYMBOL_GPL(ata_check_status);
6068EXPORT_SYMBOL_GPL(ata_altstatus);
1da177e4
LT		 6069EXPORT_SYMBOL_GPL(ata_exec_command);
6070EXPORT_SYMBOL_GPL(ata_port_start);
6071EXPORT_SYMBOL_GPL(ata_port_stop);
aa8f0dc6 6072EXPORT_SYMBOL_GPL(ata_host_stop);
1da177e4 6073EXPORT_SYMBOL_GPL(ata_interrupt);
a6b2c5d4
AC		 6074EXPORT_SYMBOL_GPL(ata_mmio_data_xfer);
6075EXPORT_SYMBOL_GPL(ata_pio_data_xfer);
75e99585 6076EXPORT_SYMBOL_GPL(ata_pio_data_xfer_noirq);
1da177e4 6077EXPORT_SYMBOL_GPL(ata_qc_prep);
e46834cd 6078EXPORT_SYMBOL_GPL(ata_noop_qc_prep);
1da177e4
LT		 6079EXPORT_SYMBOL_GPL(ata_bmdma_setup);
6080EXPORT_SYMBOL_GPL(ata_bmdma_start);
6081EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
6082EXPORT_SYMBOL_GPL(ata_bmdma_status);
6083EXPORT_SYMBOL_GPL(ata_bmdma_stop);
6d97dbd7
TH		 6084EXPORT_SYMBOL_GPL(ata_bmdma_freeze);
6085EXPORT_SYMBOL_GPL(ata_bmdma_thaw);
6086EXPORT_SYMBOL_GPL(ata_bmdma_drive_eh);
6087EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
6088EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
1da177e4 6089EXPORT_SYMBOL_GPL(ata_port_probe);
3c567b7d 6090EXPORT_SYMBOL_GPL(sata_set_spd);
d7bb4cc7
TH		 6091EXPORT_SYMBOL_GPL(sata_phy_debounce);
6092EXPORT_SYMBOL_GPL(sata_phy_resume);
1da177e4
LT		 6093EXPORT_SYMBOL_GPL(sata_phy_reset);
6094EXPORT_SYMBOL_GPL(__sata_phy_reset);
6095EXPORT_SYMBOL_GPL(ata_bus_reset);
f5914a46 6096EXPORT_SYMBOL_GPL(ata_std_prereset);
c2bd5804
TH		 6097EXPORT_SYMBOL_GPL(ata_std_softreset);
6098EXPORT_SYMBOL_GPL(sata_std_hardreset);
6099EXPORT_SYMBOL_GPL(ata_std_postreset);
623a3128 6100EXPORT_SYMBOL_GPL(ata_dev_revalidate);
2e9edbf8
JG		 6101EXPORT_SYMBOL_GPL(ata_dev_classify);
6102EXPORT_SYMBOL_GPL(ata_dev_pair);
1da177e4 6103EXPORT_SYMBOL_GPL(ata_port_disable);
67846b30 6104EXPORT_SYMBOL_GPL(ata_ratelimit);
c22daff4 6105EXPORT_SYMBOL_GPL(ata_wait_register);
6f8b9958 6106EXPORT_SYMBOL_GPL(ata_busy_sleep);
86e45b6b 6107EXPORT_SYMBOL_GPL(ata_port_queue_task);
1da177e4
LT		 6108EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
6109EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
1da177e4 6110EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
83c47bcb 6111EXPORT_SYMBOL_GPL(ata_scsi_slave_destroy);
a6e6ce8e 6112EXPORT_SYMBOL_GPL(ata_scsi_change_queue_depth);
1da177e4
LT		 6113EXPORT_SYMBOL_GPL(ata_scsi_release);
6114EXPORT_SYMBOL_GPL(ata_host_intr);
34bf2170
TH		 6115EXPORT_SYMBOL_GPL(sata_scr_valid);
6116EXPORT_SYMBOL_GPL(sata_scr_read);
6117EXPORT_SYMBOL_GPL(sata_scr_write);
6118EXPORT_SYMBOL_GPL(sata_scr_write_flush);
6119EXPORT_SYMBOL_GPL(ata_port_online);
6120EXPORT_SYMBOL_GPL(ata_port_offline);
cca3974e
JG		 6121EXPORT_SYMBOL_GPL(ata_host_suspend);
6122EXPORT_SYMBOL_GPL(ata_host_resume);
6a62a04d
TH		 6123EXPORT_SYMBOL_GPL(ata_id_string);
6124EXPORT_SYMBOL_GPL(ata_id_c_string);
1da177e4
LT		 6125EXPORT_SYMBOL_GPL(ata_scsi_simulate);
6126
1bc4ccff 6127EXPORT_SYMBOL_GPL(ata_pio_need_iordy);
452503f9
AC		 6128EXPORT_SYMBOL_GPL(ata_timing_compute);
6129EXPORT_SYMBOL_GPL(ata_timing_merge);
6130
1da177e4
LT		 6131#ifdef CONFIG_PCI
6132EXPORT_SYMBOL_GPL(pci_test_config_bits);
374b1873 6133EXPORT_SYMBOL_GPL(ata_pci_host_stop);
1da177e4
LT		 6134EXPORT_SYMBOL_GPL(ata_pci_init_native_mode);
6135EXPORT_SYMBOL_GPL(ata_pci_init_one);
6136EXPORT_SYMBOL_GPL(ata_pci_remove_one);
500530f6
TH		 6137EXPORT_SYMBOL_GPL(ata_pci_device_do_suspend);
6138EXPORT_SYMBOL_GPL(ata_pci_device_do_resume);
9b847548
JA		 6139EXPORT_SYMBOL_GPL(ata_pci_device_suspend);
6140EXPORT_SYMBOL_GPL(ata_pci_device_resume);
67951ade
AC		 6141EXPORT_SYMBOL_GPL(ata_pci_default_filter);
6142EXPORT_SYMBOL_GPL(ata_pci_clear_simplex);
1da177e4 6143#endif /* CONFIG_PCI */
9b847548 6144
9b847548
JA		 6145EXPORT_SYMBOL_GPL(ata_scsi_device_suspend);
6146EXPORT_SYMBOL_GPL(ata_scsi_device_resume);
ece1d636 6147
ece1d636 6148EXPORT_SYMBOL_GPL(ata_eng_timeout);
7b70fc03
TH		 6149EXPORT_SYMBOL_GPL(ata_port_schedule_eh);
6150EXPORT_SYMBOL_GPL(ata_port_abort);
e3180499
TH		 6151EXPORT_SYMBOL_GPL(ata_port_freeze);
6152EXPORT_SYMBOL_GPL(ata_eh_freeze_port);
6153EXPORT_SYMBOL_GPL(ata_eh_thaw_port);
ece1d636
TH		 6154EXPORT_SYMBOL_GPL(ata_eh_qc_complete);
6155EXPORT_SYMBOL_GPL(ata_eh_qc_retry);
022bdb07 6156EXPORT_SYMBOL_GPL(ata_do_eh);
Linux kernel - Deliverables
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