[deliverable/linux.git] / drivers / ata / pata_hpt366.c

/*
 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
 *
 * This driver is heavily based upon:
 *
 * linux/drivers/ide/pci/hpt366.c		Version 0.36	April 25, 2003
 *
 * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>
 * Portions Copyright (C) 2001	        Sun Microsystems, Inc.
 * Portions Copyright (C) 2003		Red Hat Inc
 *
 *
 * TODO
 *	Look into engine reset on timeout errors. Should not be required.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"pata_hpt366"
#define DRV_VERSION	"0.6.11"

struct hpt_clock {
	u8	xfer_mode;
	u32	timing;
};

/* key for bus clock timings
 * bit
 * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 *        cycles = value + 1
 * 4:7    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 *        cycles = value + 1
 * 8:11   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 *        register access.
 * 12:15  cmd_low_time. Active time of DIOW_/DIOR_ during task file
 *        register access.
 * 16:18  udma_cycle_time. Clock cycles for UDMA xfer?
 * 19:21  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
 * 22:24  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
 *        register access.
 * 28     UDMA enable.
 * 29     DMA  enable.
 * 30     PIO_MST enable. If set, the chip is in bus master mode during
 *        PIO xfer.
 * 31     FIFO enable.
 */

static const struct hpt_clock hpt366_40[] = {
	{	XFER_UDMA_4,	0x900fd943	},
	{	XFER_UDMA_3,	0x900ad943	},
	{	XFER_UDMA_2,	0x900bd943	},
	{	XFER_UDMA_1,	0x9008d943	},
	{	XFER_UDMA_0,	0x9008d943	},

	{	XFER_MW_DMA_2,	0xa008d943	},
	{	XFER_MW_DMA_1,	0xa010d955	},
	{	XFER_MW_DMA_0,	0xa010d9fc	},

	{	XFER_PIO_4,	0xc008d963	},
	{	XFER_PIO_3,	0xc010d974	},
	{	XFER_PIO_2,	0xc010d997	},
	{	XFER_PIO_1,	0xc010d9c7	},
	{	XFER_PIO_0,	0xc018d9d9	},
	{	0,		0x0120d9d9	}
};

static const struct hpt_clock hpt366_33[] = {
	{	XFER_UDMA_4,	0x90c9a731	},
	{	XFER_UDMA_3,	0x90cfa731	},
	{	XFER_UDMA_2,	0x90caa731	},
	{	XFER_UDMA_1,	0x90cba731	},
	{	XFER_UDMA_0,	0x90c8a731	},

	{	XFER_MW_DMA_2,	0xa0c8a731	},
	{	XFER_MW_DMA_1,	0xa0c8a732	},	/* 0xa0c8a733 */
	{	XFER_MW_DMA_0,	0xa0c8a797	},

	{	XFER_PIO_4,	0xc0c8a731	},
	{	XFER_PIO_3,	0xc0c8a742	},
	{	XFER_PIO_2,	0xc0d0a753	},
	{	XFER_PIO_1,	0xc0d0a7a3	},	/* 0xc0d0a793 */
	{	XFER_PIO_0,	0xc0d0a7aa	},	/* 0xc0d0a7a7 */
	{	0,		0x0120a7a7	}
};

static const struct hpt_clock hpt366_25[] = {
	{	XFER_UDMA_4,	0x90c98521	},
	{	XFER_UDMA_3,	0x90cf8521	},
	{	XFER_UDMA_2,	0x90cf8521	},
	{	XFER_UDMA_1,	0x90cb8521	},
	{	XFER_UDMA_0,	0x90cb8521	},

	{	XFER_MW_DMA_2,	0xa0ca8521	},
	{	XFER_MW_DMA_1,	0xa0ca8532	},
	{	XFER_MW_DMA_0,	0xa0ca8575	},

	{	XFER_PIO_4,	0xc0ca8521	},
	{	XFER_PIO_3,	0xc0ca8532	},
	{	XFER_PIO_2,	0xc0ca8542	},
	{	XFER_PIO_1,	0xc0d08572	},
	{	XFER_PIO_0,	0xc0d08585	},
	{	0,		0x01208585	}
};

static const char * const bad_ata33[] = {
	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
	"Maxtor 90845U3", "Maxtor 90650U2",
	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
	"Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
	"Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
	"Maxtor 90510D4",
	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
	"Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
	"Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
	NULL
};

static const char * const bad_ata66_4[] = {
	"IBM-DTLA-307075",
	"IBM-DTLA-307060",
	"IBM-DTLA-307045",
	"IBM-DTLA-307030",
	"IBM-DTLA-307020",
	"IBM-DTLA-307015",
	"IBM-DTLA-305040",
	"IBM-DTLA-305030",
	"IBM-DTLA-305020",
	"IC35L010AVER07-0",
	"IC35L020AVER07-0",
	"IC35L030AVER07-0",
	"IC35L040AVER07-0",
	"IC35L060AVER07-0",
	"WDC AC310200R",
	NULL
};

static const char * const bad_ata66_3[] = {
	"WDC AC310200R",
	NULL
};

static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
			       const char * const list[])
{
	unsigned char model_num[ATA_ID_PROD_LEN + 1];
	int i = 0;

	ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));

	while (list[i] != NULL) {
		if (!strcmp(list[i], model_num)) {
			pr_warn("%s is not supported for %s\n",
				modestr, list[i]);
			return 1;
		}
		i++;
	}
	return 0;
}

/**
 *	hpt366_filter	-	mode selection filter
 *	@adev: ATA device
 *
 *	Block UDMA on devices that cause trouble with this controller.
 */

static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
{
	if (adev->class == ATA_DEV_ATA) {
		if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
			mask &= ~ATA_MASK_UDMA;
		if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
			mask &= ~(0xF8 << ATA_SHIFT_UDMA);
		if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
			mask &= ~(0xF0 << ATA_SHIFT_UDMA);
	} else if (adev->class == ATA_DEV_ATAPI)
		mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);

	return mask;
}

static int hpt36x_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 ata66;

	/*
	 * Each channel of pata_hpt366 occupies separate PCI function
	 * as the primary channel and bit1 indicates the cable type.
	 */
	pci_read_config_byte(pdev, 0x5A, &ata66);
	if (ata66 & 2)
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,
			    u8 mode)
{
	struct hpt_clock *clocks = ap->host->private_data;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 addr = 0x40 + 4 * adev->devno;
	u32 mask, reg;

	/* determine timing mask and find matching clock entry */
	if (mode < XFER_MW_DMA_0)
		mask = 0xc1f8ffff;
	else if (mode < XFER_UDMA_0)
		mask = 0x303800ff;
	else
		mask = 0x30070000;

	while (clocks->xfer_mode) {
		if (clocks->xfer_mode == mode)
			break;
		clocks++;
	}
	if (!clocks->xfer_mode)
		BUG();

	/*
	 * Combine new mode bits with old config bits and disable
	 * on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
	 * problems handling I/O errors later.
	 */
	pci_read_config_dword(pdev, addr, &reg);
	reg = ((reg & ~mask) | (clocks->timing & mask)) & ~0xc0000000;
	pci_write_config_dword(pdev, addr, reg);
}

/**
 *	hpt366_set_piomode		-	PIO setup
 *	@ap: ATA interface
 *	@adev: device on the interface
 *
 *	Perform PIO mode setup.
 */

static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	hpt366_set_mode(ap, adev, adev->pio_mode);
}

/**
 *	hpt366_set_dmamode		-	DMA timing setup
 *	@ap: ATA interface
 *	@adev: Device being configured
 *
 *	Set up the channel for MWDMA or UDMA modes. Much the same as with
 *	PIO, load the mode number and then set MWDMA or UDMA flag.
 */

static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	hpt366_set_mode(ap, adev, adev->dma_mode);
}

static struct scsi_host_template hpt36x_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

/*
 *	Configuration for HPT366/68
 */

static struct ata_port_operations hpt366_port_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.cable_detect	= hpt36x_cable_detect,
	.mode_filter	= hpt366_filter,
	.set_piomode	= hpt366_set_piomode,
	.set_dmamode	= hpt366_set_dmamode,
};

/**
 *	hpt36x_init_chipset	-	common chip setup
 *	@dev: PCI device
 *
 *	Perform the chip setup work that must be done at both init and
 *	resume time
 */

static void hpt36x_init_chipset(struct pci_dev *dev)
{
	u8 drive_fast;

	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);

	pci_read_config_byte(dev, 0x51, &drive_fast);
	if (drive_fast & 0x80)
		pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
}

/**
 *	hpt36x_init_one		-	Initialise an HPT366/368
 *	@dev: PCI device
 *	@id: Entry in match table
 *
 *	Initialise an HPT36x device. There are some interesting complications
 *	here. Firstly the chip may report 366 and be one of several variants.
 *	Secondly all the timings depend on the clock for the chip which we must
 *	detect and look up
 *
 *	This is the known chip mappings. It may be missing a couple of later
 *	releases.
 *
 *	Chip version		PCI		Rev	Notes
 *	HPT366			4 (HPT366)	0	UDMA66
 *	HPT366			4 (HPT366)	1	UDMA66
 *	HPT368			4 (HPT366)	2	UDMA66
 *	HPT37x/30x		4 (HPT366)	3+	Other driver
 *
 */

static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static const struct ata_port_info info_hpt366 = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
		.mwdma_mask = ATA_MWDMA2,
		.udma_mask = ATA_UDMA4,
		.port_ops = &hpt366_port_ops
	};
	const struct ata_port_info *ppi[] = { &info_hpt366, NULL };

	void *hpriv = NULL;
	u32 reg1;
	int rc;

	rc = pcim_enable_device(dev);
	if (rc)
		return rc;

	/* May be a later chip in disguise. Check */
	/* Newer chips are not in the HPT36x driver. Ignore them */
	if (dev->revision > 2)
		return -ENODEV;

	hpt36x_init_chipset(dev);

	pci_read_config_dword(dev, 0x40,  &reg1);

	/* PCI clocking determines the ATA timing values to use */
	/* info_hpt366 is safe against re-entry so we can scribble on it */
	switch ((reg1 & 0x700) >> 8) {
	case 9:
		hpriv = &hpt366_40;
		break;
	case 5:
		hpriv = &hpt366_25;
		break;
	default:
		hpriv = &hpt366_33;
		break;
	}
	/* Now kick off ATA set up */
	return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, hpriv, 0);
}

#ifdef CONFIG_PM
static int hpt36x_reinit_one(struct pci_dev *dev)
{
	struct ata_host *host = dev_get_drvdata(&dev->dev);
	int rc;

	rc = ata_pci_device_do_resume(dev);
	if (rc)
		return rc;
	hpt36x_init_chipset(dev);
	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id hpt36x[] = {
	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
	{ },
};

static struct pci_driver hpt36x_pci_driver = {
	.name		= DRV_NAME,
	.id_table	= hpt36x,
	.probe		= hpt36x_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= hpt36x_reinit_one,
#endif
};

static int __init hpt36x_init(void)
{
	return pci_register_driver(&hpt36x_pci_driver);
}

static void __exit hpt36x_exit(void)
{
	pci_unregister_driver(&hpt36x_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, hpt36x);
MODULE_VERSION(DRV_VERSION);

module_init(hpt36x_init);
module_exit(hpt36x_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
	3	*
	4	* This driver is heavily based upon:
	5	*
	6	* linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
	7	*
	8	* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
	9	* Portions Copyright (C) 2001 Sun Microsystems, Inc.
	10	* Portions Copyright (C) 2003 Red Hat Inc
	11	*
	12	*
	13	* TODO
d817898c	14	* Look into engine reset on timeout errors. Should not be required.
669a5db4 JG	15	*/
669a5db4 JG	16
8d7b1c70	17	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
669a5db4 JG	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/pci.h>
	22	#include <linux/init.h>
	23	#include <linux/blkdev.h>
	24	#include <linux/delay.h>
	25	#include <scsi/scsi_host.h>
	26	#include <linux/libata.h>
	27
	28	#define DRV_NAME "pata_hpt366"
8d7b1c70	29	#define DRV_VERSION "0.6.11"
669a5db4 JG	30
669a5db4 JG	31	struct hpt_clock {
6ecb6f25	32	u8 xfer_mode;
669a5db4 JG	33	u32 timing;
	34	};
	35
	36	/* key for bus clock timings
	37	* bit
82beb5d8 SS	38	* 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
	39	* cycles = value + 1
	40	* 4:7 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
	41	* cycles = value + 1
	42	* 8:11 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
669a5db4	43	* register access.
82beb5d8	44	* 12:15 cmd_low_time. Active time of DIOW_/DIOR_ during task file
669a5db4	45	* register access.
82beb5d8 SS	46	* 16:18 udma_cycle_time. Clock cycles for UDMA xfer?
	47	* 19:21 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
	48	* 22:24 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
669a5db4	49	* register access.
82beb5d8 SS	50	* 28 UDMA enable.
	51	* 29 DMA enable.
	52	* 30 PIO_MST enable. If set, the chip is in bus master mode during
	53	* PIO xfer.
669a5db4 JG	54	* 31 FIFO enable.
	55	*/
	56
	57	static const struct hpt_clock hpt366_40[] = {
	58	{ XFER_UDMA_4, 0x900fd943 },
	59	{ XFER_UDMA_3, 0x900ad943 },
	60	{ XFER_UDMA_2, 0x900bd943 },
	61	{ XFER_UDMA_1, 0x9008d943 },
	62	{ XFER_UDMA_0, 0x9008d943 },
	63
	64	{ XFER_MW_DMA_2, 0xa008d943 },
	65	{ XFER_MW_DMA_1, 0xa010d955 },
	66	{ XFER_MW_DMA_0, 0xa010d9fc },
	67
	68	{ XFER_PIO_4, 0xc008d963 },
	69	{ XFER_PIO_3, 0xc010d974 },
	70	{ XFER_PIO_2, 0xc010d997 },
	71	{ XFER_PIO_1, 0xc010d9c7 },
	72	{ XFER_PIO_0, 0xc018d9d9 },
	73	{ 0, 0x0120d9d9 }
	74	};
	75
	76	static const struct hpt_clock hpt366_33[] = {
	77	{ XFER_UDMA_4, 0x90c9a731 },
	78	{ XFER_UDMA_3, 0x90cfa731 },
	79	{ XFER_UDMA_2, 0x90caa731 },
	80	{ XFER_UDMA_1, 0x90cba731 },
	81	{ XFER_UDMA_0, 0x90c8a731 },
	82
	83	{ XFER_MW_DMA_2, 0xa0c8a731 },
	84	{ XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
	85	{ XFER_MW_DMA_0, 0xa0c8a797 },
	86
	87	{ XFER_PIO_4, 0xc0c8a731 },
	88	{ XFER_PIO_3, 0xc0c8a742 },
	89	{ XFER_PIO_2, 0xc0d0a753 },
	90	{ XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
	91	{ XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
	92	{ 0, 0x0120a7a7 }
	93	};
	94
	95	static const struct hpt_clock hpt366_25[] = {
	96	{ XFER_UDMA_4, 0x90c98521 },
	97	{ XFER_UDMA_3, 0x90cf8521 },
	98	{ XFER_UDMA_2, 0x90cf8521 },
	99	{ XFER_UDMA_1, 0x90cb8521 },
	100	{ XFER_UDMA_0, 0x90cb8521 },
	101
	102	{ XFER_MW_DMA_2, 0xa0ca8521 },
	103	{ XFER_MW_DMA_1, 0xa0ca8532 },
	104	{ XFER_MW_DMA_0, 0xa0ca8575 },
	105
	106	{ XFER_PIO_4, 0xc0ca8521 },
	107	{ XFER_PIO_3, 0xc0ca8532 },
	108	{ XFER_PIO_2, 0xc0ca8542 },
	109	{ XFER_PIO_1, 0xc0d08572 },
	110	{ XFER_PIO_0, 0xc0d08585 },
	111	{ 0, 0x01208585 }
	112	};
	113
28cd4b6b SS	114	static const char * const bad_ata33[] = {
	115	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
	116	"Maxtor 90845U3", "Maxtor 90650U2",
	117	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
	118	"Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
	119	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
	120	"Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
669a5db4 JG	121	"Maxtor 90510D4",
669a5db4 JG	122	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
28cd4b6b SS	123	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
	124	"Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
	125	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
	126	"Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
669a5db4 JG	127	NULL
	128	};
	129
28cd4b6b	130	static const char * const bad_ata66_4[] = {
669a5db4 JG	131	"IBM-DTLA-307075",
	132	"IBM-DTLA-307060",
	133	"IBM-DTLA-307045",
	134	"IBM-DTLA-307030",
	135	"IBM-DTLA-307020",
	136	"IBM-DTLA-307015",
	137	"IBM-DTLA-305040",
	138	"IBM-DTLA-305030",
	139	"IBM-DTLA-305020",
	140	"IC35L010AVER07-0",
	141	"IC35L020AVER07-0",
	142	"IC35L030AVER07-0",
	143	"IC35L040AVER07-0",
	144	"IC35L060AVER07-0",
	145	"WDC AC310200R",
	146	NULL
	147	};
	148
28cd4b6b	149	static const char * const bad_ata66_3[] = {
669a5db4 JG	150	"WDC AC310200R",
	151	NULL
	152	};
	153
28cd4b6b SS	154	static int hpt_dma_blacklisted(const struct ata_device dev, char modestr,
28cd4b6b SS	155	const char * const list[])
669a5db4	156	{
8bfa79fc	157	unsigned char model_num[ATA_ID_PROD_LEN + 1];
669a5db4 JG	158	int i = 0;
669a5db4 JG	159
8bfa79fc	160	ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
669a5db4	161
8bfa79fc TH	162	while (list[i] != NULL) {
8bfa79fc TH	163	if (!strcmp(list[i], model_num)) {
8d7b1c70 JP	164	pr_warn("%s is not supported for %s\n",
8d7b1c70 JP	165	modestr, list[i]);
669a5db4 JG	166	return 1;
	167	}
	168	i++;
	169	}
	170	return 0;
	171	}
	172
	173	/**
	174	* hpt366_filter - mode selection filter
669a5db4 JG	175	* @adev: ATA device
	176	*
	177	* Block UDMA on devices that cause trouble with this controller.
	178	*/
85cd7251	179
a76b62ca	180	static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
669a5db4 JG	181	{
	182	if (adev->class == ATA_DEV_ATA) {
	183	if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
	184	mask &= ~ATA_MASK_UDMA;
	185	if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
6ddd6861	186	mask &= ~(0xF8 << ATA_SHIFT_UDMA);
669a5db4	187	if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
6ddd6861	188	mask &= ~(0xF0 << ATA_SHIFT_UDMA);
3ee89f17 TH	189	} else if (adev->class == ATA_DEV_ATAPI)
	190	mask &= ~(ATA_MASK_MWDMA \| ATA_MASK_UDMA);
	191
c7087652	192	return mask;
669a5db4 JG	193	}
669a5db4 JG	194
fecfda5d AC	195	static int hpt36x_cable_detect(struct ata_port *ap)
fecfda5d AC	196	{
fecfda5d	197	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
bab5b32a	198	u8 ata66;
fecfda5d	199
bab5b32a TH	200	/*
	201	* Each channel of pata_hpt366 occupies separate PCI function
	202	* as the primary channel and bit1 indicates the cable type.
	203	*/
fecfda5d	204	pci_read_config_byte(pdev, 0x5A, &ata66);
bab5b32a	205	if (ata66 & 2)
fecfda5d AC	206	return ATA_CBL_PATA40;
	207	return ATA_CBL_PATA80;
	208	}
	209
6ecb6f25 TH	210	static void hpt366_set_mode(struct ata_port ap, struct ata_device adev,
6ecb6f25 TH	211	u8 mode)
669a5db4	212	{
6ecb6f25	213	struct hpt_clock *clocks = ap->host->private_data;
669a5db4	214	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
859faa87	215	u32 addr = 0x40 + 4 * adev->devno;
6ecb6f25	216	u32 mask, reg;
85cd7251	217
6ecb6f25 TH	218	/* determine timing mask and find matching clock entry */
	219	if (mode < XFER_MW_DMA_0)
	220	mask = 0xc1f8ffff;
	221	else if (mode < XFER_UDMA_0)
	222	mask = 0x303800ff;
	223	else
	224	mask = 0x30070000;
	225
	226	while (clocks->xfer_mode) {
	227	if (clocks->xfer_mode == mode)
	228	break;
	229	clocks++;
	230	}
	231	if (!clocks->xfer_mode)
	232	BUG();
	233
	234	/*
	235	* Combine new mode bits with old config bits and disable
	236	* on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
	237	* problems handling I/O errors later.
	238	*/
859faa87	239	pci_read_config_dword(pdev, addr, &reg);
6ecb6f25	240	reg = ((reg & ~mask) \| (clocks->timing & mask)) & ~0xc0000000;
859faa87	241	pci_write_config_dword(pdev, addr, reg);
6ecb6f25 TH	242	}
	243
	244	/**
	245	* hpt366_set_piomode - PIO setup
	246	* @ap: ATA interface
	247	* @adev: device on the interface
	248	*
	249	* Perform PIO mode setup.
	250	*/
	251
	252	static void hpt366_set_piomode(struct ata_port ap, struct ata_device adev)
	253	{
	254	hpt366_set_mode(ap, adev, adev->pio_mode);
669a5db4 JG	255	}
	256
	257	/**
	258	* hpt366_set_dmamode - DMA timing setup
	259	* @ap: ATA interface
	260	* @adev: Device being configured
	261	*
	262	* Set up the channel for MWDMA or UDMA modes. Much the same as with
	263	* PIO, load the mode number and then set MWDMA or UDMA flag.
	264	*/
85cd7251	265
669a5db4 JG	266	static void hpt366_set_dmamode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	267	{
6ecb6f25	268	hpt366_set_mode(ap, adev, adev->dma_mode);
669a5db4 JG	269	}
	270
	271	static struct scsi_host_template hpt36x_sht = {
68d1d07b	272	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	273	};
	274
	275	/*
	276	* Configuration for HPT366/68
	277	*/
85cd7251	278
669a5db4	279	static struct ata_port_operations hpt366_port_ops = {
029cfd6b TH	280	.inherits = &ata_bmdma_port_ops,
	281	.cable_detect = hpt36x_cable_detect,
	282	.mode_filter = hpt366_filter,
669a5db4 JG	283	.set_piomode = hpt366_set_piomode,
669a5db4 JG	284	.set_dmamode = hpt366_set_dmamode,
85cd7251	285	};
669a5db4	286
aa54ab1e A	287	/**
	288	* hpt36x_init_chipset - common chip setup
	289	* @dev: PCI device
	290	*
	291	* Perform the chip setup work that must be done at both init and
	292	* resume time
	293	*/
	294
	295	static void hpt36x_init_chipset(struct pci_dev *dev)
	296	{
	297	u8 drive_fast;
28cd4b6b	298
aa54ab1e A	299	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
	300	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
	301	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
	302	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
	303
	304	pci_read_config_byte(dev, 0x51, &drive_fast);
	305	if (drive_fast & 0x80)
	306	pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
	307	}
	308
669a5db4 JG	309	/**
	310	* hpt36x_init_one - Initialise an HPT366/368
	311	* @dev: PCI device
	312	* @id: Entry in match table
	313	*
	314	* Initialise an HPT36x device. There are some interesting complications
	315	* here. Firstly the chip may report 366 and be one of several variants.
	316	* Secondly all the timings depend on the clock for the chip which we must
	317	* detect and look up
	318	*
	319	* This is the known chip mappings. It may be missing a couple of later
	320	* releases.
	321	*
	322	* Chip version PCI Rev Notes
	323	* HPT366 4 (HPT366) 0 UDMA66
	324	* HPT366 4 (HPT366) 1 UDMA66
	325	* HPT368 4 (HPT366) 2 UDMA66
	326	* HPT37x/30x 4 (HPT366) 3+ Other driver
	327	*
	328	*/
85cd7251	329
669a5db4 JG	330	static int hpt36x_init_one(struct pci_dev dev, const struct pci_device_id id)
669a5db4 JG	331	{
1626aeb8	332	static const struct ata_port_info info_hpt366 = {
1d2808fd	333	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	334	.pio_mask = ATA_PIO4,
14bdef98 EIB	335	.mwdma_mask = ATA_MWDMA2,
bf6263a8	336	.udma_mask = ATA_UDMA4,
669a5db4 JG	337	.port_ops = &hpt366_port_ops
669a5db4 JG	338	};
887125e3	339	const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
669a5db4	340
887125e3	341	void *hpriv = NULL;
669a5db4	342	u32 reg1;
f08048e9 TH	343	int rc;
	344
	345	rc = pcim_enable_device(dev);
	346	if (rc)
	347	return rc;
669a5db4	348
669a5db4 JG	349	/* May be a later chip in disguise. Check */
669a5db4 JG	350	/* Newer chips are not in the HPT36x driver. Ignore them */
89d3b360 SS	351	if (dev->revision > 2)
89d3b360 SS	352	return -ENODEV;
669a5db4	353
aa54ab1e	354	hpt36x_init_chipset(dev);
669a5db4 JG	355
669a5db4 JG	356	pci_read_config_dword(dev, 0x40, &reg1);
85cd7251	357
669a5db4 JG	358	/* PCI clocking determines the ATA timing values to use */
669a5db4 JG	359	/* info_hpt366 is safe against re-entry so we can scribble on it */
28cd4b6b SS	360	switch ((reg1 & 0x700) >> 8) {
	361	case 9:
	362	hpriv = &hpt366_40;
	363	break;
	364	case 5:
	365	hpriv = &hpt366_25;
	366	break;
	367	default:
	368	hpriv = &hpt366_33;
	369	break;
669a5db4 JG	370	}
669a5db4 JG	371	/* Now kick off ATA set up */
1c5afdf7	372	return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, hpriv, 0);
669a5db4 JG	373	}
669a5db4 JG	374
438ac6d5	375	#ifdef CONFIG_PM
aa54ab1e A	376	static int hpt36x_reinit_one(struct pci_dev *dev)
aa54ab1e A	377	{
f08048e9 TH	378	struct ata_host *host = dev_get_drvdata(&dev->dev);
	379	int rc;
	380
	381	rc = ata_pci_device_do_resume(dev);
	382	if (rc)
	383	return rc;
aa54ab1e	384	hpt36x_init_chipset(dev);
f08048e9 TH	385	ata_host_resume(host);
f08048e9 TH	386	return 0;
aa54ab1e	387	}
438ac6d5	388	#endif
aa54ab1e	389
2d2744fc JG	390	static const struct pci_device_id hpt36x[] = {
2d2744fc JG	391	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
2d2744fc	392	{ },
669a5db4 JG	393	};
	394
	395	static struct pci_driver hpt36x_pci_driver = {
28cd4b6b	396	.name = DRV_NAME,
669a5db4	397	.id_table = hpt36x,
28cd4b6b	398	.probe = hpt36x_init_one,
aa54ab1e	399	.remove = ata_pci_remove_one,
438ac6d5	400	#ifdef CONFIG_PM
aa54ab1e A	401	.suspend = ata_pci_device_suspend,
aa54ab1e A	402	.resume = hpt36x_reinit_one,
438ac6d5	403	#endif
669a5db4 JG	404	};
	405
	406	static int __init hpt36x_init(void)
	407	{
	408	return pci_register_driver(&hpt36x_pci_driver);
	409	}
	410
669a5db4 JG	411	static void __exit hpt36x_exit(void)
	412	{
	413	pci_unregister_driver(&hpt36x_pci_driver);
	414	}
	415
669a5db4 JG	416	MODULE_AUTHOR("Alan Cox");
	417	MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
	418	MODULE_LICENSE("GPL");
	419	MODULE_DEVICE_TABLE(pci, hpt36x);
	420	MODULE_VERSION(DRV_VERSION);
	421
	422	module_init(hpt36x_init);
	423	module_exit(hpt36x_exit);