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8f8f484b | 1 | /* |
dba4072a | 2 | * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. |
8f8f484b PG |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | #include <linux/slab.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/clk-provider.h> | |
22 | #include <linux/clk.h> | |
23 | ||
24 | #include "clk.h" | |
25 | ||
26 | #define PLL_BASE_BYPASS BIT(31) | |
27 | #define PLL_BASE_ENABLE BIT(30) | |
28 | #define PLL_BASE_REF_ENABLE BIT(29) | |
29 | #define PLL_BASE_OVERRIDE BIT(28) | |
30 | ||
31 | #define PLL_BASE_DIVP_SHIFT 20 | |
32 | #define PLL_BASE_DIVP_WIDTH 3 | |
33 | #define PLL_BASE_DIVN_SHIFT 8 | |
34 | #define PLL_BASE_DIVN_WIDTH 10 | |
35 | #define PLL_BASE_DIVM_SHIFT 0 | |
36 | #define PLL_BASE_DIVM_WIDTH 5 | |
37 | #define PLLU_POST_DIVP_MASK 0x1 | |
38 | ||
39 | #define PLL_MISC_DCCON_SHIFT 20 | |
40 | #define PLL_MISC_CPCON_SHIFT 8 | |
41 | #define PLL_MISC_CPCON_WIDTH 4 | |
42 | #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1) | |
43 | #define PLL_MISC_LFCON_SHIFT 4 | |
44 | #define PLL_MISC_LFCON_WIDTH 4 | |
45 | #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1) | |
46 | #define PLL_MISC_VCOCON_SHIFT 0 | |
47 | #define PLL_MISC_VCOCON_WIDTH 4 | |
48 | #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1) | |
49 | ||
50 | #define OUT_OF_TABLE_CPCON 8 | |
51 | ||
52 | #define PMC_PLLP_WB0_OVERRIDE 0xf8 | |
53 | #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12) | |
54 | #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11) | |
55 | ||
56 | #define PLL_POST_LOCK_DELAY 50 | |
57 | ||
58 | #define PLLDU_LFCON_SET_DIVN 600 | |
59 | ||
60 | #define PLLE_BASE_DIVCML_SHIFT 24 | |
61 | #define PLLE_BASE_DIVCML_WIDTH 4 | |
62 | #define PLLE_BASE_DIVP_SHIFT 16 | |
63 | #define PLLE_BASE_DIVP_WIDTH 7 | |
64 | #define PLLE_BASE_DIVN_SHIFT 8 | |
65 | #define PLLE_BASE_DIVN_WIDTH 8 | |
66 | #define PLLE_BASE_DIVM_SHIFT 0 | |
67 | #define PLLE_BASE_DIVM_WIDTH 8 | |
68 | ||
69 | #define PLLE_MISC_SETUP_BASE_SHIFT 16 | |
70 | #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT) | |
71 | #define PLLE_MISC_LOCK_ENABLE BIT(9) | |
72 | #define PLLE_MISC_READY BIT(15) | |
73 | #define PLLE_MISC_SETUP_EX_SHIFT 2 | |
74 | #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT) | |
75 | #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \ | |
76 | PLLE_MISC_SETUP_EX_MASK) | |
77 | #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT) | |
78 | ||
79 | #define PLLE_SS_CTRL 0x68 | |
642fb0cf PDS |
80 | #define PLLE_SS_CNTL_BYPASS_SS BIT(10) |
81 | #define PLLE_SS_CNTL_INTERP_RESET BIT(11) | |
82 | #define PLLE_SS_CNTL_SSC_BYP BIT(12) | |
83 | #define PLLE_SS_CNTL_CENTER BIT(14) | |
84 | #define PLLE_SS_CNTL_INVERT BIT(15) | |
85 | #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\ | |
86 | PLLE_SS_CNTL_SSC_BYP) | |
87 | #define PLLE_SS_MAX_MASK 0x1ff | |
88 | #define PLLE_SS_MAX_VAL 0x25 | |
89 | #define PLLE_SS_INC_MASK (0xff << 16) | |
90 | #define PLLE_SS_INC_VAL (0x1 << 16) | |
91 | #define PLLE_SS_INCINTRV_MASK (0x3f << 24) | |
92 | #define PLLE_SS_INCINTRV_VAL (0x20 << 24) | |
93 | #define PLLE_SS_COEFFICIENTS_MASK \ | |
94 | (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK) | |
95 | #define PLLE_SS_COEFFICIENTS_VAL \ | |
96 | (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL) | |
8f8f484b | 97 | |
c1d1939c PDS |
98 | #define PLLE_AUX_PLLP_SEL BIT(2) |
99 | #define PLLE_AUX_ENABLE_SWCTL BIT(4) | |
100 | #define PLLE_AUX_SEQ_ENABLE BIT(24) | |
101 | #define PLLE_AUX_PLLRE_SEL BIT(28) | |
102 | ||
103 | #define PLLE_MISC_PLLE_PTS BIT(8) | |
104 | #define PLLE_MISC_IDDQ_SW_VALUE BIT(13) | |
105 | #define PLLE_MISC_IDDQ_SW_CTRL BIT(14) | |
106 | #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4 | |
107 | #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT) | |
108 | #define PLLE_MISC_VREG_CTRL_SHIFT 2 | |
109 | #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT) | |
110 | ||
111 | #define PLLCX_MISC_STROBE BIT(31) | |
112 | #define PLLCX_MISC_RESET BIT(30) | |
113 | #define PLLCX_MISC_SDM_DIV_SHIFT 28 | |
114 | #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT) | |
115 | #define PLLCX_MISC_FILT_DIV_SHIFT 26 | |
116 | #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT) | |
117 | #define PLLCX_MISC_ALPHA_SHIFT 18 | |
118 | #define PLLCX_MISC_DIV_LOW_RANGE \ | |
119 | ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \ | |
120 | (0x1 << PLLCX_MISC_FILT_DIV_SHIFT)) | |
121 | #define PLLCX_MISC_DIV_HIGH_RANGE \ | |
122 | ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \ | |
123 | (0x2 << PLLCX_MISC_FILT_DIV_SHIFT)) | |
124 | #define PLLCX_MISC_COEF_LOW_RANGE \ | |
125 | ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT)) | |
126 | #define PLLCX_MISC_KA_SHIFT 2 | |
127 | #define PLLCX_MISC_KB_SHIFT 9 | |
128 | #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \ | |
129 | (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \ | |
130 | PLLCX_MISC_DIV_LOW_RANGE | \ | |
131 | PLLCX_MISC_RESET) | |
132 | #define PLLCX_MISC1_DEFAULT 0x000d2308 | |
133 | #define PLLCX_MISC2_DEFAULT 0x30211200 | |
134 | #define PLLCX_MISC3_DEFAULT 0x200 | |
135 | ||
8f8f484b PG |
136 | #define PMC_SATA_PWRGT 0x1ac |
137 | #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5) | |
138 | #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4) | |
139 | ||
140 | #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset) | |
141 | #define pll_readl_base(p) pll_readl(p->params->base_reg, p) | |
142 | #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p) | |
408a24f8 | 143 | #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset) |
8f8f484b PG |
144 | |
145 | #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset) | |
146 | #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p) | |
147 | #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p) | |
408a24f8 | 148 | #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset) |
8f8f484b PG |
149 | |
150 | #define mask(w) ((1 << (w)) - 1) | |
aa6fefde PDS |
151 | #define divm_mask(p) mask(p->params->div_nmp->divm_width) |
152 | #define divn_mask(p) mask(p->params->div_nmp->divn_width) | |
8f8f484b | 153 | #define divp_mask(p) (p->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK : \ |
aa6fefde | 154 | mask(p->params->div_nmp->divp_width)) |
8f8f484b PG |
155 | |
156 | #define divm_max(p) (divm_mask(p)) | |
157 | #define divn_max(p) (divn_mask(p)) | |
158 | #define divp_max(p) (1 << (divp_mask(p))) | |
159 | ||
aa6fefde PDS |
160 | static struct div_nmp default_nmp = { |
161 | .divn_shift = PLL_BASE_DIVN_SHIFT, | |
162 | .divn_width = PLL_BASE_DIVN_WIDTH, | |
163 | .divm_shift = PLL_BASE_DIVM_SHIFT, | |
164 | .divm_width = PLL_BASE_DIVM_WIDTH, | |
165 | .divp_shift = PLL_BASE_DIVP_SHIFT, | |
166 | .divp_width = PLL_BASE_DIVP_WIDTH, | |
167 | }; | |
168 | ||
8f8f484b PG |
169 | static void clk_pll_enable_lock(struct tegra_clk_pll *pll) |
170 | { | |
171 | u32 val; | |
172 | ||
173 | if (!(pll->flags & TEGRA_PLL_USE_LOCK)) | |
174 | return; | |
175 | ||
7ba28813 PDS |
176 | if (!(pll->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) |
177 | return; | |
178 | ||
8f8f484b PG |
179 | val = pll_readl_misc(pll); |
180 | val |= BIT(pll->params->lock_enable_bit_idx); | |
181 | pll_writel_misc(val, pll); | |
182 | } | |
183 | ||
dba4072a | 184 | static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) |
8f8f484b PG |
185 | { |
186 | int i; | |
3e72771e | 187 | u32 val, lock_mask; |
dba4072a | 188 | void __iomem *lock_addr; |
8f8f484b PG |
189 | |
190 | if (!(pll->flags & TEGRA_PLL_USE_LOCK)) { | |
191 | udelay(pll->params->lock_delay); | |
192 | return 0; | |
193 | } | |
194 | ||
dba4072a PDS |
195 | lock_addr = pll->clk_base; |
196 | if (pll->flags & TEGRA_PLL_LOCK_MISC) | |
197 | lock_addr += pll->params->misc_reg; | |
198 | else | |
199 | lock_addr += pll->params->base_reg; | |
200 | ||
3e72771e | 201 | lock_mask = pll->params->lock_mask; |
dba4072a | 202 | |
8f8f484b PG |
203 | for (i = 0; i < pll->params->lock_delay; i++) { |
204 | val = readl_relaxed(lock_addr); | |
3e72771e | 205 | if ((val & lock_mask) == lock_mask) { |
8f8f484b PG |
206 | udelay(PLL_POST_LOCK_DELAY); |
207 | return 0; | |
208 | } | |
209 | udelay(2); /* timeout = 2 * lock time */ | |
210 | } | |
211 | ||
212 | pr_err("%s: Timed out waiting for pll %s lock\n", __func__, | |
213 | __clk_get_name(pll->hw.clk)); | |
214 | ||
215 | return -1; | |
216 | } | |
217 | ||
218 | static int clk_pll_is_enabled(struct clk_hw *hw) | |
219 | { | |
220 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
221 | u32 val; | |
222 | ||
223 | if (pll->flags & TEGRA_PLLM) { | |
224 | val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); | |
225 | if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) | |
226 | return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0; | |
227 | } | |
228 | ||
229 | val = pll_readl_base(pll); | |
230 | ||
231 | return val & PLL_BASE_ENABLE ? 1 : 0; | |
232 | } | |
233 | ||
dba4072a | 234 | static void _clk_pll_enable(struct clk_hw *hw) |
8f8f484b PG |
235 | { |
236 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
237 | u32 val; | |
238 | ||
239 | clk_pll_enable_lock(pll); | |
240 | ||
241 | val = pll_readl_base(pll); | |
dd93587b PDS |
242 | if (pll->flags & TEGRA_PLL_BYPASS) |
243 | val &= ~PLL_BASE_BYPASS; | |
8f8f484b PG |
244 | val |= PLL_BASE_ENABLE; |
245 | pll_writel_base(val, pll); | |
246 | ||
247 | if (pll->flags & TEGRA_PLLM) { | |
248 | val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); | |
249 | val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; | |
250 | writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); | |
251 | } | |
8f8f484b PG |
252 | } |
253 | ||
254 | static void _clk_pll_disable(struct clk_hw *hw) | |
255 | { | |
256 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
257 | u32 val; | |
258 | ||
259 | val = pll_readl_base(pll); | |
dd93587b PDS |
260 | if (pll->flags & TEGRA_PLL_BYPASS) |
261 | val &= ~PLL_BASE_BYPASS; | |
262 | val &= ~PLL_BASE_ENABLE; | |
8f8f484b PG |
263 | pll_writel_base(val, pll); |
264 | ||
265 | if (pll->flags & TEGRA_PLLM) { | |
266 | val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); | |
267 | val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; | |
268 | writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); | |
269 | } | |
270 | } | |
271 | ||
272 | static int clk_pll_enable(struct clk_hw *hw) | |
273 | { | |
274 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
275 | unsigned long flags = 0; | |
276 | int ret; | |
277 | ||
278 | if (pll->lock) | |
279 | spin_lock_irqsave(pll->lock, flags); | |
280 | ||
dba4072a PDS |
281 | _clk_pll_enable(hw); |
282 | ||
283 | ret = clk_pll_wait_for_lock(pll); | |
8f8f484b PG |
284 | |
285 | if (pll->lock) | |
286 | spin_unlock_irqrestore(pll->lock, flags); | |
287 | ||
288 | return ret; | |
289 | } | |
290 | ||
291 | static void clk_pll_disable(struct clk_hw *hw) | |
292 | { | |
293 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
294 | unsigned long flags = 0; | |
295 | ||
296 | if (pll->lock) | |
297 | spin_lock_irqsave(pll->lock, flags); | |
298 | ||
299 | _clk_pll_disable(hw); | |
300 | ||
301 | if (pll->lock) | |
302 | spin_unlock_irqrestore(pll->lock, flags); | |
303 | } | |
304 | ||
053b525f PDS |
305 | static int _p_div_to_hw(struct clk_hw *hw, u8 p_div) |
306 | { | |
307 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
308 | struct pdiv_map *p_tohw = pll->params->pdiv_tohw; | |
309 | ||
310 | if (p_tohw) { | |
311 | while (p_tohw->pdiv) { | |
312 | if (p_div <= p_tohw->pdiv) | |
313 | return p_tohw->hw_val; | |
314 | p_tohw++; | |
315 | } | |
316 | return -EINVAL; | |
317 | } | |
318 | return -EINVAL; | |
319 | } | |
320 | ||
321 | static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw) | |
322 | { | |
323 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
324 | struct pdiv_map *p_tohw = pll->params->pdiv_tohw; | |
325 | ||
326 | if (p_tohw) { | |
327 | while (p_tohw->pdiv) { | |
328 | if (p_div_hw == p_tohw->hw_val) | |
329 | return p_tohw->pdiv; | |
330 | p_tohw++; | |
331 | } | |
332 | return -EINVAL; | |
333 | } | |
334 | ||
335 | return 1 << p_div_hw; | |
336 | } | |
337 | ||
8f8f484b PG |
338 | static int _get_table_rate(struct clk_hw *hw, |
339 | struct tegra_clk_pll_freq_table *cfg, | |
340 | unsigned long rate, unsigned long parent_rate) | |
341 | { | |
342 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
343 | struct tegra_clk_pll_freq_table *sel; | |
344 | ||
345 | for (sel = pll->freq_table; sel->input_rate != 0; sel++) | |
346 | if (sel->input_rate == parent_rate && | |
347 | sel->output_rate == rate) | |
348 | break; | |
349 | ||
350 | if (sel->input_rate == 0) | |
351 | return -EINVAL; | |
352 | ||
8f8f484b PG |
353 | cfg->input_rate = sel->input_rate; |
354 | cfg->output_rate = sel->output_rate; | |
355 | cfg->m = sel->m; | |
356 | cfg->n = sel->n; | |
357 | cfg->p = sel->p; | |
358 | cfg->cpcon = sel->cpcon; | |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
363 | static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, | |
364 | unsigned long rate, unsigned long parent_rate) | |
365 | { | |
366 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
367 | unsigned long cfreq; | |
368 | u32 p_div = 0; | |
053b525f | 369 | int ret; |
8f8f484b PG |
370 | |
371 | switch (parent_rate) { | |
372 | case 12000000: | |
373 | case 26000000: | |
374 | cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; | |
375 | break; | |
376 | case 13000000: | |
377 | cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; | |
378 | break; | |
379 | case 16800000: | |
380 | case 19200000: | |
381 | cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; | |
382 | break; | |
383 | case 9600000: | |
384 | case 28800000: | |
385 | /* | |
386 | * PLL_P_OUT1 rate is not listed in PLLA table | |
387 | */ | |
388 | cfreq = parent_rate/(parent_rate/1000000); | |
389 | break; | |
390 | default: | |
391 | pr_err("%s Unexpected reference rate %lu\n", | |
392 | __func__, parent_rate); | |
393 | BUG(); | |
394 | } | |
395 | ||
396 | /* Raise VCO to guarantee 0.5% accuracy */ | |
397 | for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq; | |
398 | cfg->output_rate <<= 1) | |
399 | p_div++; | |
400 | ||
8f8f484b PG |
401 | cfg->m = parent_rate / cfreq; |
402 | cfg->n = cfg->output_rate / cfreq; | |
403 | cfg->cpcon = OUT_OF_TABLE_CPCON; | |
404 | ||
405 | if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) || | |
dba4072a PDS |
406 | (1 << p_div) > divp_max(pll) |
407 | || cfg->output_rate > pll->params->vco_max) { | |
8f8f484b PG |
408 | pr_err("%s: Failed to set %s rate %lu\n", |
409 | __func__, __clk_get_name(hw->clk), rate); | |
053b525f | 410 | WARN_ON(1); |
8f8f484b PG |
411 | return -EINVAL; |
412 | } | |
413 | ||
00c674e4 TR |
414 | cfg->output_rate >>= p_div; |
415 | ||
053b525f PDS |
416 | if (pll->params->pdiv_tohw) { |
417 | ret = _p_div_to_hw(hw, 1 << p_div); | |
418 | if (ret < 0) | |
419 | return ret; | |
420 | else | |
421 | cfg->p = ret; | |
0b6525ac PDS |
422 | } else |
423 | cfg->p = p_div; | |
dba4072a | 424 | |
8f8f484b PG |
425 | return 0; |
426 | } | |
427 | ||
dba4072a PDS |
428 | static void _update_pll_mnp(struct tegra_clk_pll *pll, |
429 | struct tegra_clk_pll_freq_table *cfg) | |
8f8f484b | 430 | { |
dba4072a | 431 | u32 val; |
408a24f8 PDS |
432 | struct tegra_clk_pll_params *params = pll->params; |
433 | struct div_nmp *div_nmp = params->div_nmp; | |
434 | ||
435 | if ((pll->flags & TEGRA_PLLM) && | |
436 | (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & | |
437 | PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { | |
438 | val = pll_override_readl(params->pmc_divp_reg, pll); | |
439 | val &= ~(divp_mask(pll) << div_nmp->override_divp_shift); | |
440 | val |= cfg->p << div_nmp->override_divp_shift; | |
441 | pll_override_writel(val, params->pmc_divp_reg, pll); | |
442 | ||
443 | val = pll_override_readl(params->pmc_divnm_reg, pll); | |
444 | val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) | | |
445 | ~(divn_mask(pll) << div_nmp->override_divn_shift); | |
446 | val |= (cfg->m << div_nmp->override_divm_shift) | | |
447 | (cfg->n << div_nmp->override_divn_shift); | |
448 | pll_override_writel(val, params->pmc_divnm_reg, pll); | |
449 | } else { | |
450 | val = pll_readl_base(pll); | |
8f8f484b | 451 | |
408a24f8 PDS |
452 | val &= ~((divm_mask(pll) << div_nmp->divm_shift) | |
453 | (divn_mask(pll) << div_nmp->divn_shift) | | |
454 | (divp_mask(pll) << div_nmp->divp_shift)); | |
8f8f484b | 455 | |
408a24f8 PDS |
456 | val |= ((cfg->m << div_nmp->divm_shift) | |
457 | (cfg->n << div_nmp->divn_shift) | | |
458 | (cfg->p << div_nmp->divp_shift)); | |
dba4072a | 459 | |
408a24f8 PDS |
460 | pll_writel_base(val, pll); |
461 | } | |
dba4072a PDS |
462 | } |
463 | ||
464 | static void _get_pll_mnp(struct tegra_clk_pll *pll, | |
465 | struct tegra_clk_pll_freq_table *cfg) | |
466 | { | |
467 | u32 val; | |
408a24f8 PDS |
468 | struct tegra_clk_pll_params *params = pll->params; |
469 | struct div_nmp *div_nmp = params->div_nmp; | |
470 | ||
471 | if ((pll->flags & TEGRA_PLLM) && | |
472 | (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & | |
473 | PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { | |
474 | val = pll_override_readl(params->pmc_divp_reg, pll); | |
475 | cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll); | |
476 | ||
477 | val = pll_override_readl(params->pmc_divnm_reg, pll); | |
478 | cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll); | |
479 | cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll); | |
480 | } else { | |
481 | val = pll_readl_base(pll); | |
dba4072a | 482 | |
408a24f8 PDS |
483 | cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll); |
484 | cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); | |
485 | cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); | |
486 | } | |
dba4072a PDS |
487 | } |
488 | ||
489 | static void _update_pll_cpcon(struct tegra_clk_pll *pll, | |
490 | struct tegra_clk_pll_freq_table *cfg, | |
491 | unsigned long rate) | |
492 | { | |
493 | u32 val; | |
494 | ||
495 | val = pll_readl_misc(pll); | |
496 | ||
497 | val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT); | |
498 | val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT; | |
499 | ||
500 | if (pll->flags & TEGRA_PLL_SET_LFCON) { | |
501 | val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT); | |
502 | if (cfg->n >= PLLDU_LFCON_SET_DIVN) | |
503 | val |= 1 << PLL_MISC_LFCON_SHIFT; | |
504 | } else if (pll->flags & TEGRA_PLL_SET_DCCON) { | |
505 | val &= ~(1 << PLL_MISC_DCCON_SHIFT); | |
506 | if (rate >= (pll->params->vco_max >> 1)) | |
507 | val |= 1 << PLL_MISC_DCCON_SHIFT; | |
8f8f484b PG |
508 | } |
509 | ||
dba4072a PDS |
510 | pll_writel_misc(val, pll); |
511 | } | |
512 | ||
513 | static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, | |
514 | unsigned long rate) | |
515 | { | |
516 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
517 | int state, ret = 0; | |
518 | ||
8f8f484b PG |
519 | state = clk_pll_is_enabled(hw); |
520 | ||
dba4072a | 521 | if (state) |
8f8f484b | 522 | _clk_pll_disable(hw); |
8f8f484b | 523 | |
dba4072a | 524 | _update_pll_mnp(pll, cfg); |
8f8f484b | 525 | |
dba4072a PDS |
526 | if (pll->flags & TEGRA_PLL_HAS_CPCON) |
527 | _update_pll_cpcon(pll, cfg, rate); | |
8f8f484b | 528 | |
dba4072a PDS |
529 | if (state) { |
530 | _clk_pll_enable(hw); | |
531 | ret = clk_pll_wait_for_lock(pll); | |
532 | } | |
8f8f484b | 533 | |
dba4072a | 534 | return ret; |
8f8f484b PG |
535 | } |
536 | ||
537 | static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, | |
538 | unsigned long parent_rate) | |
539 | { | |
540 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
dba4072a PDS |
541 | struct tegra_clk_pll_freq_table cfg, old_cfg; |
542 | unsigned long flags = 0; | |
543 | int ret = 0; | |
8f8f484b PG |
544 | |
545 | if (pll->flags & TEGRA_PLL_FIXED) { | |
546 | if (rate != pll->fixed_rate) { | |
547 | pr_err("%s: Can not change %s fixed rate %lu to %lu\n", | |
548 | __func__, __clk_get_name(hw->clk), | |
549 | pll->fixed_rate, rate); | |
550 | return -EINVAL; | |
551 | } | |
552 | return 0; | |
553 | } | |
554 | ||
555 | if (_get_table_rate(hw, &cfg, rate, parent_rate) && | |
053b525f PDS |
556 | _calc_rate(hw, &cfg, rate, parent_rate)) { |
557 | WARN_ON(1); | |
8f8f484b | 558 | return -EINVAL; |
053b525f | 559 | } |
dba4072a PDS |
560 | if (pll->lock) |
561 | spin_lock_irqsave(pll->lock, flags); | |
562 | ||
563 | _get_pll_mnp(pll, &old_cfg); | |
564 | ||
565 | if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p) | |
566 | ret = _program_pll(hw, &cfg, rate); | |
567 | ||
568 | if (pll->lock) | |
569 | spin_unlock_irqrestore(pll->lock, flags); | |
570 | ||
571 | return ret; | |
8f8f484b PG |
572 | } |
573 | ||
574 | static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, | |
575 | unsigned long *prate) | |
576 | { | |
577 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
578 | struct tegra_clk_pll_freq_table cfg; | |
8f8f484b PG |
579 | |
580 | if (pll->flags & TEGRA_PLL_FIXED) | |
581 | return pll->fixed_rate; | |
582 | ||
583 | /* PLLM is used for memory; we do not change rate */ | |
584 | if (pll->flags & TEGRA_PLLM) | |
585 | return __clk_get_rate(hw->clk); | |
586 | ||
587 | if (_get_table_rate(hw, &cfg, rate, *prate) && | |
053b525f PDS |
588 | _calc_rate(hw, &cfg, rate, *prate)) { |
589 | WARN_ON(1); | |
8f8f484b | 590 | return -EINVAL; |
053b525f | 591 | } |
8f8f484b | 592 | |
053b525f | 593 | return cfg.output_rate; |
8f8f484b PG |
594 | } |
595 | ||
596 | static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, | |
597 | unsigned long parent_rate) | |
598 | { | |
599 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
dba4072a PDS |
600 | struct tegra_clk_pll_freq_table cfg; |
601 | u32 val; | |
8f8f484b | 602 | u64 rate = parent_rate; |
0b6525ac | 603 | int pdiv; |
8f8f484b | 604 | |
dba4072a PDS |
605 | val = pll_readl_base(pll); |
606 | ||
dd93587b | 607 | if ((pll->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) |
8f8f484b PG |
608 | return parent_rate; |
609 | ||
610 | if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) { | |
611 | struct tegra_clk_pll_freq_table sel; | |
612 | if (_get_table_rate(hw, &sel, pll->fixed_rate, parent_rate)) { | |
613 | pr_err("Clock %s has unknown fixed frequency\n", | |
614 | __clk_get_name(hw->clk)); | |
615 | BUG(); | |
616 | } | |
617 | return pll->fixed_rate; | |
618 | } | |
619 | ||
dba4072a PDS |
620 | _get_pll_mnp(pll, &cfg); |
621 | ||
053b525f PDS |
622 | pdiv = _hw_to_p_div(hw, cfg.p); |
623 | if (pdiv < 0) { | |
624 | WARN_ON(1); | |
625 | pdiv = 1; | |
626 | } | |
8f8f484b | 627 | |
0b6525ac | 628 | cfg.m *= pdiv; |
dba4072a PDS |
629 | |
630 | rate *= cfg.n; | |
631 | do_div(rate, cfg.m); | |
8f8f484b | 632 | |
8f8f484b PG |
633 | return rate; |
634 | } | |
635 | ||
636 | static int clk_plle_training(struct tegra_clk_pll *pll) | |
637 | { | |
638 | u32 val; | |
639 | unsigned long timeout; | |
640 | ||
641 | if (!pll->pmc) | |
642 | return -ENOSYS; | |
643 | ||
644 | /* | |
645 | * PLLE is already disabled, and setup cleared; | |
646 | * create falling edge on PLLE IDDQ input. | |
647 | */ | |
648 | val = readl(pll->pmc + PMC_SATA_PWRGT); | |
649 | val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; | |
650 | writel(val, pll->pmc + PMC_SATA_PWRGT); | |
651 | ||
652 | val = readl(pll->pmc + PMC_SATA_PWRGT); | |
653 | val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; | |
654 | writel(val, pll->pmc + PMC_SATA_PWRGT); | |
655 | ||
656 | val = readl(pll->pmc + PMC_SATA_PWRGT); | |
657 | val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; | |
658 | writel(val, pll->pmc + PMC_SATA_PWRGT); | |
659 | ||
660 | val = pll_readl_misc(pll); | |
661 | ||
662 | timeout = jiffies + msecs_to_jiffies(100); | |
663 | while (1) { | |
664 | val = pll_readl_misc(pll); | |
665 | if (val & PLLE_MISC_READY) | |
666 | break; | |
667 | if (time_after(jiffies, timeout)) { | |
668 | pr_err("%s: timeout waiting for PLLE\n", __func__); | |
669 | return -EBUSY; | |
670 | } | |
671 | udelay(300); | |
672 | } | |
673 | ||
674 | return 0; | |
675 | } | |
676 | ||
677 | static int clk_plle_enable(struct clk_hw *hw) | |
678 | { | |
679 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
680 | unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); | |
681 | struct tegra_clk_pll_freq_table sel; | |
682 | u32 val; | |
683 | int err; | |
684 | ||
685 | if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate)) | |
686 | return -EINVAL; | |
687 | ||
688 | clk_pll_disable(hw); | |
689 | ||
690 | val = pll_readl_misc(pll); | |
691 | val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); | |
692 | pll_writel_misc(val, pll); | |
693 | ||
694 | val = pll_readl_misc(pll); | |
695 | if (!(val & PLLE_MISC_READY)) { | |
696 | err = clk_plle_training(pll); | |
697 | if (err) | |
698 | return err; | |
699 | } | |
700 | ||
701 | if (pll->flags & TEGRA_PLLE_CONFIGURE) { | |
702 | /* configure dividers */ | |
703 | val = pll_readl_base(pll); | |
704 | val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll)); | |
705 | val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT); | |
aa6fefde PDS |
706 | val |= sel.m << pll->params->div_nmp->divm_shift; |
707 | val |= sel.n << pll->params->div_nmp->divn_shift; | |
708 | val |= sel.p << pll->params->div_nmp->divp_shift; | |
8f8f484b PG |
709 | val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; |
710 | pll_writel_base(val, pll); | |
711 | } | |
712 | ||
713 | val = pll_readl_misc(pll); | |
714 | val |= PLLE_MISC_SETUP_VALUE; | |
715 | val |= PLLE_MISC_LOCK_ENABLE; | |
716 | pll_writel_misc(val, pll); | |
717 | ||
718 | val = readl(pll->clk_base + PLLE_SS_CTRL); | |
719 | val |= PLLE_SS_DISABLE; | |
720 | writel(val, pll->clk_base + PLLE_SS_CTRL); | |
721 | ||
722 | val |= pll_readl_base(pll); | |
723 | val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE); | |
724 | pll_writel_base(val, pll); | |
725 | ||
dba4072a PDS |
726 | clk_pll_wait_for_lock(pll); |
727 | ||
8f8f484b PG |
728 | return 0; |
729 | } | |
730 | ||
731 | static unsigned long clk_plle_recalc_rate(struct clk_hw *hw, | |
732 | unsigned long parent_rate) | |
733 | { | |
734 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
735 | u32 val = pll_readl_base(pll); | |
736 | u32 divn = 0, divm = 0, divp = 0; | |
737 | u64 rate = parent_rate; | |
738 | ||
aa6fefde PDS |
739 | divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); |
740 | divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); | |
741 | divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); | |
8f8f484b PG |
742 | divm *= divp; |
743 | ||
744 | rate *= divn; | |
745 | do_div(rate, divm); | |
746 | return rate; | |
747 | } | |
748 | ||
749 | const struct clk_ops tegra_clk_pll_ops = { | |
750 | .is_enabled = clk_pll_is_enabled, | |
751 | .enable = clk_pll_enable, | |
752 | .disable = clk_pll_disable, | |
753 | .recalc_rate = clk_pll_recalc_rate, | |
754 | .round_rate = clk_pll_round_rate, | |
755 | .set_rate = clk_pll_set_rate, | |
756 | }; | |
757 | ||
758 | const struct clk_ops tegra_clk_plle_ops = { | |
759 | .recalc_rate = clk_plle_recalc_rate, | |
760 | .is_enabled = clk_pll_is_enabled, | |
761 | .disable = clk_pll_disable, | |
762 | .enable = clk_plle_enable, | |
763 | }; | |
764 | ||
c1d1939c PDS |
765 | #ifdef CONFIG_ARCH_TEGRA_114_SOC |
766 | ||
767 | static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, | |
768 | unsigned long parent_rate) | |
769 | { | |
770 | if (parent_rate > pll_params->cf_max) | |
771 | return 2; | |
772 | else | |
773 | return 1; | |
774 | } | |
775 | ||
04edb099 PDS |
776 | static unsigned long _clip_vco_min(unsigned long vco_min, |
777 | unsigned long parent_rate) | |
778 | { | |
779 | return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate; | |
780 | } | |
781 | ||
782 | static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, | |
783 | void __iomem *clk_base, | |
784 | unsigned long parent_rate) | |
785 | { | |
786 | u32 val; | |
787 | u32 step_a, step_b; | |
788 | ||
789 | switch (parent_rate) { | |
790 | case 12000000: | |
791 | case 13000000: | |
792 | case 26000000: | |
793 | step_a = 0x2B; | |
794 | step_b = 0x0B; | |
795 | break; | |
796 | case 16800000: | |
797 | step_a = 0x1A; | |
798 | step_b = 0x09; | |
799 | break; | |
800 | case 19200000: | |
801 | step_a = 0x12; | |
802 | step_b = 0x08; | |
803 | break; | |
804 | default: | |
805 | pr_err("%s: Unexpected reference rate %lu\n", | |
806 | __func__, parent_rate); | |
807 | WARN_ON(1); | |
808 | return -EINVAL; | |
809 | } | |
810 | ||
811 | val = step_a << pll_params->stepa_shift; | |
812 | val |= step_b << pll_params->stepb_shift; | |
813 | writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); | |
814 | ||
815 | return 0; | |
816 | } | |
817 | ||
c1d1939c PDS |
818 | static int clk_pll_iddq_enable(struct clk_hw *hw) |
819 | { | |
820 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
821 | unsigned long flags = 0; | |
822 | ||
823 | u32 val; | |
824 | int ret; | |
825 | ||
826 | if (pll->lock) | |
827 | spin_lock_irqsave(pll->lock, flags); | |
828 | ||
829 | val = pll_readl(pll->params->iddq_reg, pll); | |
830 | val &= ~BIT(pll->params->iddq_bit_idx); | |
831 | pll_writel(val, pll->params->iddq_reg, pll); | |
832 | udelay(2); | |
833 | ||
834 | _clk_pll_enable(hw); | |
835 | ||
836 | ret = clk_pll_wait_for_lock(pll); | |
837 | ||
838 | if (pll->lock) | |
839 | spin_unlock_irqrestore(pll->lock, flags); | |
840 | ||
841 | return 0; | |
842 | } | |
843 | ||
844 | static void clk_pll_iddq_disable(struct clk_hw *hw) | |
845 | { | |
846 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
847 | unsigned long flags = 0; | |
848 | u32 val; | |
849 | ||
850 | if (pll->lock) | |
851 | spin_lock_irqsave(pll->lock, flags); | |
852 | ||
853 | _clk_pll_disable(hw); | |
854 | ||
855 | val = pll_readl(pll->params->iddq_reg, pll); | |
856 | val |= BIT(pll->params->iddq_bit_idx); | |
857 | pll_writel(val, pll->params->iddq_reg, pll); | |
858 | udelay(2); | |
859 | ||
860 | if (pll->lock) | |
861 | spin_unlock_irqrestore(pll->lock, flags); | |
862 | } | |
863 | ||
864 | static int _calc_dynamic_ramp_rate(struct clk_hw *hw, | |
865 | struct tegra_clk_pll_freq_table *cfg, | |
866 | unsigned long rate, unsigned long parent_rate) | |
867 | { | |
868 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
869 | unsigned int p; | |
053b525f | 870 | int p_div; |
c1d1939c PDS |
871 | |
872 | if (!rate) | |
873 | return -EINVAL; | |
874 | ||
875 | p = DIV_ROUND_UP(pll->params->vco_min, rate); | |
876 | cfg->m = _pll_fixed_mdiv(pll->params, parent_rate); | |
053b525f | 877 | cfg->output_rate = rate * p; |
c1d1939c PDS |
878 | cfg->n = cfg->output_rate * cfg->m / parent_rate; |
879 | ||
053b525f PDS |
880 | p_div = _p_div_to_hw(hw, p); |
881 | if (p_div < 0) | |
882 | return p_div; | |
883 | else | |
884 | cfg->p = p_div; | |
885 | ||
c1d1939c PDS |
886 | if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max) |
887 | return -EINVAL; | |
888 | ||
889 | return 0; | |
890 | } | |
891 | ||
892 | static int _pll_ramp_calc_pll(struct clk_hw *hw, | |
893 | struct tegra_clk_pll_freq_table *cfg, | |
894 | unsigned long rate, unsigned long parent_rate) | |
895 | { | |
896 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
053b525f | 897 | int err = 0, p_div; |
c1d1939c PDS |
898 | |
899 | err = _get_table_rate(hw, cfg, rate, parent_rate); | |
900 | if (err < 0) | |
901 | err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate); | |
053b525f PDS |
902 | else { |
903 | if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) { | |
c1d1939c PDS |
904 | WARN_ON(1); |
905 | err = -EINVAL; | |
906 | goto out; | |
053b525f PDS |
907 | } |
908 | p_div = _p_div_to_hw(hw, cfg->p); | |
909 | if (p_div < 0) | |
910 | return p_div; | |
911 | else | |
912 | cfg->p = p_div; | |
c1d1939c PDS |
913 | } |
914 | ||
053b525f | 915 | if (cfg->p > pll->params->max_p) |
c1d1939c PDS |
916 | err = -EINVAL; |
917 | ||
918 | out: | |
919 | return err; | |
920 | } | |
921 | ||
922 | static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate, | |
923 | unsigned long parent_rate) | |
924 | { | |
925 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
926 | struct tegra_clk_pll_freq_table cfg, old_cfg; | |
927 | unsigned long flags = 0; | |
928 | int ret = 0; | |
c1d1939c PDS |
929 | |
930 | ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); | |
931 | if (ret < 0) | |
932 | return ret; | |
933 | ||
934 | if (pll->lock) | |
935 | spin_lock_irqsave(pll->lock, flags); | |
936 | ||
937 | _get_pll_mnp(pll, &old_cfg); | |
938 | ||
053b525f | 939 | if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p) |
c1d1939c | 940 | ret = _program_pll(hw, &cfg, rate); |
c1d1939c PDS |
941 | |
942 | if (pll->lock) | |
943 | spin_unlock_irqrestore(pll->lock, flags); | |
944 | ||
945 | return ret; | |
946 | } | |
947 | ||
948 | static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate, | |
949 | unsigned long *prate) | |
950 | { | |
951 | struct tegra_clk_pll_freq_table cfg; | |
053b525f | 952 | int ret = 0, p_div; |
c1d1939c PDS |
953 | u64 output_rate = *prate; |
954 | ||
955 | ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate); | |
956 | if (ret < 0) | |
957 | return ret; | |
958 | ||
053b525f PDS |
959 | p_div = _hw_to_p_div(hw, cfg.p); |
960 | if (p_div < 0) | |
961 | return p_div; | |
962 | ||
c1d1939c | 963 | output_rate *= cfg.n; |
053b525f | 964 | do_div(output_rate, cfg.m * p_div); |
c1d1939c PDS |
965 | |
966 | return output_rate; | |
967 | } | |
968 | ||
969 | static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate, | |
970 | unsigned long parent_rate) | |
971 | { | |
972 | struct tegra_clk_pll_freq_table cfg; | |
973 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
974 | unsigned long flags = 0; | |
975 | int state, ret = 0; | |
c1d1939c PDS |
976 | |
977 | if (pll->lock) | |
978 | spin_lock_irqsave(pll->lock, flags); | |
979 | ||
980 | state = clk_pll_is_enabled(hw); | |
981 | if (state) { | |
982 | if (rate != clk_get_rate(hw->clk)) { | |
983 | pr_err("%s: Cannot change active PLLM\n", __func__); | |
984 | ret = -EINVAL; | |
985 | goto out; | |
986 | } | |
987 | goto out; | |
988 | } | |
989 | ||
990 | ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); | |
991 | if (ret < 0) | |
992 | goto out; | |
993 | ||
408a24f8 | 994 | _update_pll_mnp(pll, &cfg); |
c1d1939c PDS |
995 | |
996 | out: | |
997 | if (pll->lock) | |
998 | spin_unlock_irqrestore(pll->lock, flags); | |
999 | ||
1000 | return ret; | |
1001 | } | |
1002 | ||
1003 | static void _pllcx_strobe(struct tegra_clk_pll *pll) | |
1004 | { | |
1005 | u32 val; | |
1006 | ||
1007 | val = pll_readl_misc(pll); | |
1008 | val |= PLLCX_MISC_STROBE; | |
1009 | pll_writel_misc(val, pll); | |
1010 | udelay(2); | |
1011 | ||
1012 | val &= ~PLLCX_MISC_STROBE; | |
1013 | pll_writel_misc(val, pll); | |
1014 | } | |
1015 | ||
1016 | static int clk_pllc_enable(struct clk_hw *hw) | |
1017 | { | |
1018 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
1019 | u32 val; | |
1020 | int ret = 0; | |
1021 | unsigned long flags = 0; | |
1022 | ||
1023 | if (pll->lock) | |
1024 | spin_lock_irqsave(pll->lock, flags); | |
1025 | ||
1026 | _clk_pll_enable(hw); | |
1027 | udelay(2); | |
1028 | ||
1029 | val = pll_readl_misc(pll); | |
1030 | val &= ~PLLCX_MISC_RESET; | |
1031 | pll_writel_misc(val, pll); | |
1032 | udelay(2); | |
1033 | ||
1034 | _pllcx_strobe(pll); | |
1035 | ||
1036 | ret = clk_pll_wait_for_lock(pll); | |
1037 | ||
1038 | if (pll->lock) | |
1039 | spin_unlock_irqrestore(pll->lock, flags); | |
1040 | ||
1041 | return ret; | |
1042 | } | |
1043 | ||
1044 | static void _clk_pllc_disable(struct clk_hw *hw) | |
1045 | { | |
1046 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
1047 | u32 val; | |
1048 | ||
1049 | _clk_pll_disable(hw); | |
1050 | ||
1051 | val = pll_readl_misc(pll); | |
1052 | val |= PLLCX_MISC_RESET; | |
1053 | pll_writel_misc(val, pll); | |
1054 | udelay(2); | |
1055 | } | |
1056 | ||
1057 | static void clk_pllc_disable(struct clk_hw *hw) | |
1058 | { | |
1059 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
1060 | unsigned long flags = 0; | |
1061 | ||
1062 | if (pll->lock) | |
1063 | spin_lock_irqsave(pll->lock, flags); | |
1064 | ||
1065 | _clk_pllc_disable(hw); | |
1066 | ||
1067 | if (pll->lock) | |
1068 | spin_unlock_irqrestore(pll->lock, flags); | |
1069 | } | |
1070 | ||
1071 | static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll, | |
1072 | unsigned long input_rate, u32 n) | |
1073 | { | |
1074 | u32 val, n_threshold; | |
1075 | ||
1076 | switch (input_rate) { | |
1077 | case 12000000: | |
1078 | n_threshold = 70; | |
1079 | break; | |
1080 | case 13000000: | |
1081 | case 26000000: | |
1082 | n_threshold = 71; | |
1083 | break; | |
1084 | case 16800000: | |
1085 | n_threshold = 55; | |
1086 | break; | |
1087 | case 19200000: | |
1088 | n_threshold = 48; | |
1089 | break; | |
1090 | default: | |
1091 | pr_err("%s: Unexpected reference rate %lu\n", | |
1092 | __func__, input_rate); | |
1093 | return -EINVAL; | |
1094 | } | |
1095 | ||
1096 | val = pll_readl_misc(pll); | |
1097 | val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK); | |
1098 | val |= n <= n_threshold ? | |
1099 | PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE; | |
1100 | pll_writel_misc(val, pll); | |
1101 | ||
1102 | return 0; | |
1103 | } | |
1104 | ||
1105 | static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate, | |
1106 | unsigned long parent_rate) | |
1107 | { | |
053b525f | 1108 | struct tegra_clk_pll_freq_table cfg, old_cfg; |
c1d1939c PDS |
1109 | struct tegra_clk_pll *pll = to_clk_pll(hw); |
1110 | unsigned long flags = 0; | |
1111 | int state, ret = 0; | |
c1d1939c PDS |
1112 | |
1113 | if (pll->lock) | |
1114 | spin_lock_irqsave(pll->lock, flags); | |
1115 | ||
1116 | ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); | |
1117 | if (ret < 0) | |
1118 | goto out; | |
1119 | ||
053b525f | 1120 | _get_pll_mnp(pll, &old_cfg); |
c1d1939c | 1121 | |
053b525f | 1122 | if (cfg.m != old_cfg.m) { |
c1d1939c PDS |
1123 | WARN_ON(1); |
1124 | goto out; | |
1125 | } | |
1126 | ||
053b525f | 1127 | if (old_cfg.n == cfg.n && old_cfg.p == cfg.p) |
c1d1939c PDS |
1128 | goto out; |
1129 | ||
c1d1939c PDS |
1130 | state = clk_pll_is_enabled(hw); |
1131 | if (state) | |
1132 | _clk_pllc_disable(hw); | |
1133 | ||
1134 | ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); | |
1135 | if (ret < 0) | |
1136 | goto out; | |
1137 | ||
1138 | _update_pll_mnp(pll, &cfg); | |
1139 | ||
1140 | if (state) | |
1141 | ret = clk_pllc_enable(hw); | |
1142 | ||
1143 | out: | |
1144 | if (pll->lock) | |
1145 | spin_unlock_irqrestore(pll->lock, flags); | |
1146 | ||
1147 | return ret; | |
1148 | } | |
1149 | ||
1150 | static long _pllre_calc_rate(struct tegra_clk_pll *pll, | |
1151 | struct tegra_clk_pll_freq_table *cfg, | |
1152 | unsigned long rate, unsigned long parent_rate) | |
1153 | { | |
1154 | u16 m, n; | |
1155 | u64 output_rate = parent_rate; | |
1156 | ||
1157 | m = _pll_fixed_mdiv(pll->params, parent_rate); | |
1158 | n = rate * m / parent_rate; | |
1159 | ||
1160 | output_rate *= n; | |
1161 | do_div(output_rate, m); | |
1162 | ||
1163 | if (cfg) { | |
1164 | cfg->m = m; | |
1165 | cfg->n = n; | |
1166 | } | |
1167 | ||
1168 | return output_rate; | |
1169 | } | |
1170 | static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate, | |
1171 | unsigned long parent_rate) | |
1172 | { | |
1173 | struct tegra_clk_pll_freq_table cfg, old_cfg; | |
1174 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
1175 | unsigned long flags = 0; | |
1176 | int state, ret = 0; | |
1177 | ||
1178 | if (pll->lock) | |
1179 | spin_lock_irqsave(pll->lock, flags); | |
1180 | ||
1181 | _pllre_calc_rate(pll, &cfg, rate, parent_rate); | |
1182 | _get_pll_mnp(pll, &old_cfg); | |
1183 | cfg.p = old_cfg.p; | |
1184 | ||
1185 | if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) { | |
1186 | state = clk_pll_is_enabled(hw); | |
1187 | if (state) | |
1188 | _clk_pll_disable(hw); | |
1189 | ||
1190 | _update_pll_mnp(pll, &cfg); | |
1191 | ||
1192 | if (state) { | |
1193 | _clk_pll_enable(hw); | |
1194 | ret = clk_pll_wait_for_lock(pll); | |
1195 | } | |
1196 | } | |
1197 | ||
1198 | if (pll->lock) | |
1199 | spin_unlock_irqrestore(pll->lock, flags); | |
1200 | ||
1201 | return ret; | |
1202 | } | |
1203 | ||
1204 | static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw, | |
1205 | unsigned long parent_rate) | |
1206 | { | |
1207 | struct tegra_clk_pll_freq_table cfg; | |
1208 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
1209 | u64 rate = parent_rate; | |
1210 | ||
1211 | _get_pll_mnp(pll, &cfg); | |
1212 | ||
1213 | rate *= cfg.n; | |
1214 | do_div(rate, cfg.m); | |
1215 | ||
1216 | return rate; | |
1217 | } | |
1218 | ||
1219 | static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate, | |
1220 | unsigned long *prate) | |
1221 | { | |
1222 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
1223 | ||
1224 | return _pllre_calc_rate(pll, NULL, rate, *prate); | |
1225 | } | |
1226 | ||
1227 | static int clk_plle_tegra114_enable(struct clk_hw *hw) | |
1228 | { | |
1229 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
1230 | struct tegra_clk_pll_freq_table sel; | |
1231 | u32 val; | |
1232 | int ret; | |
1233 | unsigned long flags = 0; | |
1234 | unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); | |
1235 | ||
1236 | if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate)) | |
1237 | return -EINVAL; | |
1238 | ||
1239 | if (pll->lock) | |
1240 | spin_lock_irqsave(pll->lock, flags); | |
1241 | ||
1242 | val = pll_readl_base(pll); | |
1243 | val &= ~BIT(29); /* Disable lock override */ | |
1244 | pll_writel_base(val, pll); | |
1245 | ||
1246 | val = pll_readl(pll->params->aux_reg, pll); | |
1247 | val |= PLLE_AUX_ENABLE_SWCTL; | |
1248 | val &= ~PLLE_AUX_SEQ_ENABLE; | |
1249 | pll_writel(val, pll->params->aux_reg, pll); | |
1250 | udelay(1); | |
1251 | ||
1252 | val = pll_readl_misc(pll); | |
1253 | val |= PLLE_MISC_LOCK_ENABLE; | |
1254 | val |= PLLE_MISC_IDDQ_SW_CTRL; | |
1255 | val &= ~PLLE_MISC_IDDQ_SW_VALUE; | |
1256 | val |= PLLE_MISC_PLLE_PTS; | |
1257 | val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; | |
1258 | pll_writel_misc(val, pll); | |
1259 | udelay(5); | |
1260 | ||
1261 | val = pll_readl(PLLE_SS_CTRL, pll); | |
1262 | val |= PLLE_SS_DISABLE; | |
1263 | pll_writel(val, PLLE_SS_CTRL, pll); | |
1264 | ||
1265 | val = pll_readl_base(pll); | |
1266 | val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll)); | |
1267 | val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT); | |
aa6fefde PDS |
1268 | val |= sel.m << pll->params->div_nmp->divm_shift; |
1269 | val |= sel.n << pll->params->div_nmp->divn_shift; | |
c1d1939c PDS |
1270 | val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; |
1271 | pll_writel_base(val, pll); | |
1272 | udelay(1); | |
1273 | ||
1274 | _clk_pll_enable(hw); | |
1275 | ret = clk_pll_wait_for_lock(pll); | |
1276 | ||
1277 | if (ret < 0) | |
1278 | goto out; | |
1279 | ||
642fb0cf PDS |
1280 | val = pll_readl(PLLE_SS_CTRL, pll); |
1281 | val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); | |
1282 | val &= ~PLLE_SS_COEFFICIENTS_MASK; | |
1283 | val |= PLLE_SS_COEFFICIENTS_VAL; | |
1284 | pll_writel(val, PLLE_SS_CTRL, pll); | |
1285 | val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); | |
1286 | pll_writel(val, PLLE_SS_CTRL, pll); | |
1287 | udelay(1); | |
1288 | val &= ~PLLE_SS_CNTL_INTERP_RESET; | |
1289 | pll_writel(val, PLLE_SS_CTRL, pll); | |
1290 | udelay(1); | |
1291 | ||
c1d1939c PDS |
1292 | /* TODO: enable hw control of xusb brick pll */ |
1293 | ||
1294 | out: | |
1295 | if (pll->lock) | |
1296 | spin_unlock_irqrestore(pll->lock, flags); | |
1297 | ||
1298 | return ret; | |
1299 | } | |
1300 | ||
1301 | static void clk_plle_tegra114_disable(struct clk_hw *hw) | |
1302 | { | |
1303 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
1304 | unsigned long flags = 0; | |
1305 | u32 val; | |
1306 | ||
1307 | if (pll->lock) | |
1308 | spin_lock_irqsave(pll->lock, flags); | |
1309 | ||
1310 | _clk_pll_disable(hw); | |
1311 | ||
1312 | val = pll_readl_misc(pll); | |
1313 | val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; | |
1314 | pll_writel_misc(val, pll); | |
1315 | udelay(1); | |
1316 | ||
1317 | if (pll->lock) | |
1318 | spin_unlock_irqrestore(pll->lock, flags); | |
1319 | } | |
1320 | #endif | |
1321 | ||
dba4072a PDS |
1322 | static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, |
1323 | void __iomem *pmc, unsigned long fixed_rate, | |
1324 | struct tegra_clk_pll_params *pll_params, u32 pll_flags, | |
1325 | struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock) | |
8f8f484b PG |
1326 | { |
1327 | struct tegra_clk_pll *pll; | |
8f8f484b PG |
1328 | |
1329 | pll = kzalloc(sizeof(*pll), GFP_KERNEL); | |
1330 | if (!pll) | |
1331 | return ERR_PTR(-ENOMEM); | |
1332 | ||
8f8f484b PG |
1333 | pll->clk_base = clk_base; |
1334 | pll->pmc = pmc; | |
1335 | ||
1336 | pll->freq_table = freq_table; | |
1337 | pll->params = pll_params; | |
1338 | pll->fixed_rate = fixed_rate; | |
1339 | pll->flags = pll_flags; | |
1340 | pll->lock = lock; | |
1341 | ||
aa6fefde PDS |
1342 | if (!pll_params->div_nmp) |
1343 | pll_params->div_nmp = &default_nmp; | |
8f8f484b | 1344 | |
dba4072a PDS |
1345 | return pll; |
1346 | } | |
1347 | ||
1348 | static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, | |
1349 | const char *name, const char *parent_name, unsigned long flags, | |
1350 | const struct clk_ops *ops) | |
1351 | { | |
1352 | struct clk_init_data init; | |
1353 | ||
1354 | init.name = name; | |
1355 | init.ops = ops; | |
1356 | init.flags = flags; | |
1357 | init.parent_names = (parent_name ? &parent_name : NULL); | |
1358 | init.num_parents = (parent_name ? 1 : 0); | |
1359 | ||
8f8f484b PG |
1360 | /* Data in .init is copied by clk_register(), so stack variable OK */ |
1361 | pll->hw.init = &init; | |
1362 | ||
dba4072a | 1363 | return clk_register(NULL, &pll->hw); |
8f8f484b PG |
1364 | } |
1365 | ||
1366 | struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, | |
1367 | void __iomem *clk_base, void __iomem *pmc, | |
1368 | unsigned long flags, unsigned long fixed_rate, | |
dba4072a | 1369 | struct tegra_clk_pll_params *pll_params, u32 pll_flags, |
8f8f484b PG |
1370 | struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock) |
1371 | { | |
dba4072a PDS |
1372 | struct tegra_clk_pll *pll; |
1373 | struct clk *clk; | |
1374 | ||
dd93587b | 1375 | pll_flags |= TEGRA_PLL_BYPASS; |
7ba28813 | 1376 | pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE; |
dba4072a PDS |
1377 | pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, |
1378 | freq_table, lock); | |
1379 | if (IS_ERR(pll)) | |
1380 | return ERR_CAST(pll); | |
1381 | ||
1382 | clk = _tegra_clk_register_pll(pll, name, parent_name, flags, | |
1383 | &tegra_clk_pll_ops); | |
1384 | if (IS_ERR(clk)) | |
1385 | kfree(pll); | |
1386 | ||
1387 | return clk; | |
8f8f484b PG |
1388 | } |
1389 | ||
1390 | struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, | |
1391 | void __iomem *clk_base, void __iomem *pmc, | |
1392 | unsigned long flags, unsigned long fixed_rate, | |
dba4072a | 1393 | struct tegra_clk_pll_params *pll_params, u32 pll_flags, |
8f8f484b PG |
1394 | struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock) |
1395 | { | |
dba4072a PDS |
1396 | struct tegra_clk_pll *pll; |
1397 | struct clk *clk; | |
dba4072a | 1398 | |
dd93587b | 1399 | pll_flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS; |
7ba28813 | 1400 | pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE; |
dba4072a PDS |
1401 | pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, |
1402 | freq_table, lock); | |
1403 | if (IS_ERR(pll)) | |
1404 | return ERR_CAST(pll); | |
1405 | ||
1406 | clk = _tegra_clk_register_pll(pll, name, parent_name, flags, | |
1407 | &tegra_clk_plle_ops); | |
1408 | if (IS_ERR(clk)) | |
1409 | kfree(pll); | |
1410 | ||
1411 | return clk; | |
8f8f484b | 1412 | } |
c1d1939c PDS |
1413 | |
1414 | #ifdef CONFIG_ARCH_TEGRA_114_SOC | |
1415 | const struct clk_ops tegra_clk_pllxc_ops = { | |
1416 | .is_enabled = clk_pll_is_enabled, | |
1417 | .enable = clk_pll_iddq_enable, | |
1418 | .disable = clk_pll_iddq_disable, | |
1419 | .recalc_rate = clk_pll_recalc_rate, | |
1420 | .round_rate = clk_pll_ramp_round_rate, | |
1421 | .set_rate = clk_pllxc_set_rate, | |
1422 | }; | |
1423 | ||
1424 | const struct clk_ops tegra_clk_pllm_ops = { | |
1425 | .is_enabled = clk_pll_is_enabled, | |
1426 | .enable = clk_pll_iddq_enable, | |
1427 | .disable = clk_pll_iddq_disable, | |
1428 | .recalc_rate = clk_pll_recalc_rate, | |
1429 | .round_rate = clk_pll_ramp_round_rate, | |
1430 | .set_rate = clk_pllm_set_rate, | |
1431 | }; | |
1432 | ||
1433 | const struct clk_ops tegra_clk_pllc_ops = { | |
1434 | .is_enabled = clk_pll_is_enabled, | |
1435 | .enable = clk_pllc_enable, | |
1436 | .disable = clk_pllc_disable, | |
1437 | .recalc_rate = clk_pll_recalc_rate, | |
1438 | .round_rate = clk_pll_ramp_round_rate, | |
1439 | .set_rate = clk_pllc_set_rate, | |
1440 | }; | |
1441 | ||
1442 | const struct clk_ops tegra_clk_pllre_ops = { | |
1443 | .is_enabled = clk_pll_is_enabled, | |
1444 | .enable = clk_pll_iddq_enable, | |
1445 | .disable = clk_pll_iddq_disable, | |
1446 | .recalc_rate = clk_pllre_recalc_rate, | |
1447 | .round_rate = clk_pllre_round_rate, | |
1448 | .set_rate = clk_pllre_set_rate, | |
1449 | }; | |
1450 | ||
1451 | const struct clk_ops tegra_clk_plle_tegra114_ops = { | |
1452 | .is_enabled = clk_pll_is_enabled, | |
1453 | .enable = clk_plle_tegra114_enable, | |
1454 | .disable = clk_plle_tegra114_disable, | |
1455 | .recalc_rate = clk_pll_recalc_rate, | |
1456 | }; | |
1457 | ||
1458 | ||
1459 | struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, | |
1460 | void __iomem *clk_base, void __iomem *pmc, | |
1461 | unsigned long flags, unsigned long fixed_rate, | |
1462 | struct tegra_clk_pll_params *pll_params, | |
1463 | u32 pll_flags, | |
1464 | struct tegra_clk_pll_freq_table *freq_table, | |
1465 | spinlock_t *lock) | |
1466 | { | |
1467 | struct tegra_clk_pll *pll; | |
04edb099 PDS |
1468 | struct clk *clk, *parent; |
1469 | unsigned long parent_rate; | |
1470 | int err; | |
1471 | u32 val, val_iddq; | |
1472 | ||
1473 | parent = __clk_lookup(parent_name); | |
1474 | if (IS_ERR(parent)) { | |
1475 | WARN(1, "parent clk %s of %s must be registered first\n", | |
1476 | name, parent_name); | |
1477 | return ERR_PTR(-EINVAL); | |
1478 | } | |
c1d1939c PDS |
1479 | |
1480 | if (!pll_params->pdiv_tohw) | |
1481 | return ERR_PTR(-EINVAL); | |
1482 | ||
04edb099 PDS |
1483 | parent_rate = __clk_get_rate(parent); |
1484 | ||
1485 | pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); | |
1486 | ||
1487 | err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate); | |
1488 | if (err) | |
1489 | return ERR_PTR(err); | |
1490 | ||
1491 | val = readl_relaxed(clk_base + pll_params->base_reg); | |
1492 | val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); | |
1493 | ||
1494 | if (val & PLL_BASE_ENABLE) | |
1495 | WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); | |
1496 | else { | |
1497 | val_iddq |= BIT(pll_params->iddq_bit_idx); | |
1498 | writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); | |
1499 | } | |
1500 | ||
c1d1939c PDS |
1501 | pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE; |
1502 | pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, | |
1503 | freq_table, lock); | |
1504 | if (IS_ERR(pll)) | |
1505 | return ERR_CAST(pll); | |
1506 | ||
1507 | clk = _tegra_clk_register_pll(pll, name, parent_name, flags, | |
1508 | &tegra_clk_pllxc_ops); | |
1509 | if (IS_ERR(clk)) | |
1510 | kfree(pll); | |
1511 | ||
1512 | return clk; | |
1513 | } | |
1514 | ||
1515 | struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, | |
1516 | void __iomem *clk_base, void __iomem *pmc, | |
1517 | unsigned long flags, unsigned long fixed_rate, | |
1518 | struct tegra_clk_pll_params *pll_params, | |
1519 | u32 pll_flags, | |
1520 | struct tegra_clk_pll_freq_table *freq_table, | |
1521 | spinlock_t *lock, unsigned long parent_rate) | |
1522 | { | |
1523 | u32 val; | |
1524 | struct tegra_clk_pll *pll; | |
1525 | struct clk *clk; | |
1526 | ||
35d287a9 | 1527 | pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC; |
04edb099 PDS |
1528 | |
1529 | pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); | |
1530 | ||
c1d1939c PDS |
1531 | pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, |
1532 | freq_table, lock); | |
1533 | if (IS_ERR(pll)) | |
1534 | return ERR_CAST(pll); | |
1535 | ||
1536 | /* program minimum rate by default */ | |
1537 | ||
1538 | val = pll_readl_base(pll); | |
1539 | if (val & PLL_BASE_ENABLE) | |
1540 | WARN_ON(val & pll_params->iddq_bit_idx); | |
1541 | else { | |
1542 | int m; | |
1543 | ||
1544 | m = _pll_fixed_mdiv(pll_params, parent_rate); | |
1545 | val = m << PLL_BASE_DIVM_SHIFT; | |
1546 | val |= (pll_params->vco_min / parent_rate) | |
1547 | << PLL_BASE_DIVN_SHIFT; | |
1548 | pll_writel_base(val, pll); | |
1549 | } | |
1550 | ||
1551 | /* disable lock override */ | |
1552 | ||
1553 | val = pll_readl_misc(pll); | |
1554 | val &= ~BIT(29); | |
1555 | pll_writel_misc(val, pll); | |
1556 | ||
c1d1939c PDS |
1557 | clk = _tegra_clk_register_pll(pll, name, parent_name, flags, |
1558 | &tegra_clk_pllre_ops); | |
1559 | if (IS_ERR(clk)) | |
1560 | kfree(pll); | |
1561 | ||
1562 | return clk; | |
1563 | } | |
1564 | ||
1565 | struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, | |
1566 | void __iomem *clk_base, void __iomem *pmc, | |
1567 | unsigned long flags, unsigned long fixed_rate, | |
1568 | struct tegra_clk_pll_params *pll_params, | |
1569 | u32 pll_flags, | |
1570 | struct tegra_clk_pll_freq_table *freq_table, | |
1571 | spinlock_t *lock) | |
1572 | { | |
1573 | struct tegra_clk_pll *pll; | |
04edb099 PDS |
1574 | struct clk *clk, *parent; |
1575 | unsigned long parent_rate; | |
c1d1939c PDS |
1576 | |
1577 | if (!pll_params->pdiv_tohw) | |
1578 | return ERR_PTR(-EINVAL); | |
1579 | ||
04edb099 PDS |
1580 | parent = __clk_lookup(parent_name); |
1581 | if (IS_ERR(parent)) { | |
1582 | WARN(1, "parent clk %s of %s must be registered first\n", | |
1583 | name, parent_name); | |
1584 | return ERR_PTR(-EINVAL); | |
1585 | } | |
1586 | ||
1587 | parent_rate = __clk_get_rate(parent); | |
1588 | ||
1589 | pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); | |
1590 | ||
c1d1939c PDS |
1591 | pll_flags |= TEGRA_PLL_BYPASS; |
1592 | pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE; | |
408a24f8 | 1593 | pll_flags |= TEGRA_PLLM; |
c1d1939c PDS |
1594 | pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, |
1595 | freq_table, lock); | |
1596 | if (IS_ERR(pll)) | |
1597 | return ERR_CAST(pll); | |
1598 | ||
1599 | clk = _tegra_clk_register_pll(pll, name, parent_name, flags, | |
1600 | &tegra_clk_pllm_ops); | |
1601 | if (IS_ERR(clk)) | |
1602 | kfree(pll); | |
1603 | ||
1604 | return clk; | |
1605 | } | |
1606 | ||
1607 | struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, | |
1608 | void __iomem *clk_base, void __iomem *pmc, | |
1609 | unsigned long flags, unsigned long fixed_rate, | |
1610 | struct tegra_clk_pll_params *pll_params, | |
1611 | u32 pll_flags, | |
1612 | struct tegra_clk_pll_freq_table *freq_table, | |
1613 | spinlock_t *lock) | |
1614 | { | |
1615 | struct clk *parent, *clk; | |
1616 | struct pdiv_map *p_tohw = pll_params->pdiv_tohw; | |
1617 | struct tegra_clk_pll *pll; | |
1618 | struct tegra_clk_pll_freq_table cfg; | |
1619 | unsigned long parent_rate; | |
1620 | ||
1621 | if (!p_tohw) | |
1622 | return ERR_PTR(-EINVAL); | |
1623 | ||
1624 | parent = __clk_lookup(parent_name); | |
1625 | if (IS_ERR(parent)) { | |
1626 | WARN(1, "parent clk %s of %s must be registered first\n", | |
1627 | name, parent_name); | |
1628 | return ERR_PTR(-EINVAL); | |
1629 | } | |
1630 | ||
04edb099 PDS |
1631 | parent_rate = __clk_get_rate(parent); |
1632 | ||
1633 | pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); | |
1634 | ||
c1d1939c PDS |
1635 | pll_flags |= TEGRA_PLL_BYPASS; |
1636 | pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, | |
1637 | freq_table, lock); | |
1638 | if (IS_ERR(pll)) | |
1639 | return ERR_CAST(pll); | |
1640 | ||
c1d1939c PDS |
1641 | /* |
1642 | * Most of PLLC register fields are shadowed, and can not be read | |
1643 | * directly from PLL h/w. Hence, actual PLLC boot state is unknown. | |
1644 | * Initialize PLL to default state: disabled, reset; shadow registers | |
1645 | * loaded with default parameters; dividers are preset for half of | |
1646 | * minimum VCO rate (the latter assured that shadowed divider settings | |
1647 | * are within supported range). | |
1648 | */ | |
1649 | ||
1650 | cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); | |
1651 | cfg.n = cfg.m * pll_params->vco_min / parent_rate; | |
1652 | ||
1653 | while (p_tohw->pdiv) { | |
1654 | if (p_tohw->pdiv == 2) { | |
1655 | cfg.p = p_tohw->hw_val; | |
1656 | break; | |
1657 | } | |
1658 | p_tohw++; | |
1659 | } | |
1660 | ||
1661 | if (!p_tohw->pdiv) { | |
1662 | WARN_ON(1); | |
1663 | return ERR_PTR(-EINVAL); | |
1664 | } | |
1665 | ||
1666 | pll_writel_base(0, pll); | |
1667 | _update_pll_mnp(pll, &cfg); | |
1668 | ||
1669 | pll_writel_misc(PLLCX_MISC_DEFAULT, pll); | |
1670 | pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); | |
1671 | pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); | |
1672 | pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); | |
1673 | ||
1674 | _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); | |
1675 | ||
1676 | clk = _tegra_clk_register_pll(pll, name, parent_name, flags, | |
1677 | &tegra_clk_pllc_ops); | |
1678 | if (IS_ERR(clk)) | |
1679 | kfree(pll); | |
1680 | ||
1681 | return clk; | |
1682 | } | |
1683 | ||
1684 | struct clk *tegra_clk_register_plle_tegra114(const char *name, | |
1685 | const char *parent_name, | |
1686 | void __iomem *clk_base, unsigned long flags, | |
1687 | unsigned long fixed_rate, | |
1688 | struct tegra_clk_pll_params *pll_params, | |
1689 | struct tegra_clk_pll_freq_table *freq_table, | |
1690 | spinlock_t *lock) | |
1691 | { | |
1692 | struct tegra_clk_pll *pll; | |
1693 | struct clk *clk; | |
1694 | u32 val, val_aux; | |
1695 | ||
1696 | pll = _tegra_init_pll(clk_base, NULL, fixed_rate, pll_params, | |
1697 | TEGRA_PLL_HAS_LOCK_ENABLE, freq_table, lock); | |
1698 | if (IS_ERR(pll)) | |
1699 | return ERR_CAST(pll); | |
1700 | ||
1701 | /* ensure parent is set to pll_re_vco */ | |
1702 | ||
1703 | val = pll_readl_base(pll); | |
1704 | val_aux = pll_readl(pll_params->aux_reg, pll); | |
1705 | ||
1706 | if (val & PLL_BASE_ENABLE) { | |
8e9cc80a PDS |
1707 | if ((val_aux & PLLE_AUX_PLLRE_SEL) || |
1708 | (val_aux & PLLE_AUX_PLLP_SEL)) | |
c1d1939c | 1709 | WARN(1, "pll_e enabled with unsupported parent %s\n", |
8e9cc80a PDS |
1710 | (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : |
1711 | "pll_re_vco"); | |
c1d1939c | 1712 | } else { |
8e9cc80a | 1713 | val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); |
c1d1939c PDS |
1714 | pll_writel(val, pll_params->aux_reg, pll); |
1715 | } | |
1716 | ||
1717 | clk = _tegra_clk_register_pll(pll, name, parent_name, flags, | |
1718 | &tegra_clk_plle_tegra114_ops); | |
1719 | if (IS_ERR(clk)) | |
1720 | kfree(pll); | |
1721 | ||
1722 | return clk; | |
1723 | } | |
1724 | #endif |