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0ee52b15 SB |
1 | /* |
2 | * Zynq clock controller | |
3 | * | |
4 | * Copyright (C) 2012 - 2013 Xilinx | |
5 | * | |
6 | * Sören Brinkmann <soren.brinkmann@xilinx.com> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License v2 as published by | |
10 | * the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <linux/clk/zynq.h> | |
22 | #include <linux/clk-provider.h> | |
23 | #include <linux/of.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/string.h> | |
26 | #include <linux/io.h> | |
27 | ||
28 | static void __iomem *zynq_slcr_base_priv; | |
29 | ||
30 | #define SLCR_ARMPLL_CTRL (zynq_slcr_base_priv + 0x100) | |
31 | #define SLCR_DDRPLL_CTRL (zynq_slcr_base_priv + 0x104) | |
32 | #define SLCR_IOPLL_CTRL (zynq_slcr_base_priv + 0x108) | |
33 | #define SLCR_PLL_STATUS (zynq_slcr_base_priv + 0x10c) | |
34 | #define SLCR_ARM_CLK_CTRL (zynq_slcr_base_priv + 0x120) | |
35 | #define SLCR_DDR_CLK_CTRL (zynq_slcr_base_priv + 0x124) | |
36 | #define SLCR_DCI_CLK_CTRL (zynq_slcr_base_priv + 0x128) | |
37 | #define SLCR_APER_CLK_CTRL (zynq_slcr_base_priv + 0x12c) | |
38 | #define SLCR_GEM0_CLK_CTRL (zynq_slcr_base_priv + 0x140) | |
39 | #define SLCR_GEM1_CLK_CTRL (zynq_slcr_base_priv + 0x144) | |
40 | #define SLCR_SMC_CLK_CTRL (zynq_slcr_base_priv + 0x148) | |
41 | #define SLCR_LQSPI_CLK_CTRL (zynq_slcr_base_priv + 0x14c) | |
42 | #define SLCR_SDIO_CLK_CTRL (zynq_slcr_base_priv + 0x150) | |
43 | #define SLCR_UART_CLK_CTRL (zynq_slcr_base_priv + 0x154) | |
44 | #define SLCR_SPI_CLK_CTRL (zynq_slcr_base_priv + 0x158) | |
45 | #define SLCR_CAN_CLK_CTRL (zynq_slcr_base_priv + 0x15c) | |
46 | #define SLCR_CAN_MIOCLK_CTRL (zynq_slcr_base_priv + 0x160) | |
47 | #define SLCR_DBG_CLK_CTRL (zynq_slcr_base_priv + 0x164) | |
48 | #define SLCR_PCAP_CLK_CTRL (zynq_slcr_base_priv + 0x168) | |
49 | #define SLCR_FPGA0_CLK_CTRL (zynq_slcr_base_priv + 0x170) | |
50 | #define SLCR_621_TRUE (zynq_slcr_base_priv + 0x1c4) | |
51 | #define SLCR_SWDT_CLK_SEL (zynq_slcr_base_priv + 0x304) | |
52 | ||
53 | #define NUM_MIO_PINS 54 | |
54 | ||
55 | enum zynq_clk { | |
56 | armpll, ddrpll, iopll, | |
57 | cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x, | |
58 | ddr2x, ddr3x, dci, | |
59 | lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1, | |
60 | sdio0, sdio1, uart0, uart1, spi0, spi1, dma, | |
61 | usb0_aper, usb1_aper, gem0_aper, gem1_aper, | |
62 | sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper, | |
63 | i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper, | |
64 | smc_aper, swdt, dbg_trc, dbg_apb, clk_max}; | |
65 | ||
66 | static struct clk *ps_clk; | |
67 | static struct clk *clks[clk_max]; | |
68 | static struct clk_onecell_data clk_data; | |
69 | ||
70 | static DEFINE_SPINLOCK(armpll_lock); | |
71 | static DEFINE_SPINLOCK(ddrpll_lock); | |
72 | static DEFINE_SPINLOCK(iopll_lock); | |
73 | static DEFINE_SPINLOCK(armclk_lock); | |
252957cc | 74 | static DEFINE_SPINLOCK(swdtclk_lock); |
0ee52b15 SB |
75 | static DEFINE_SPINLOCK(ddrclk_lock); |
76 | static DEFINE_SPINLOCK(dciclk_lock); | |
77 | static DEFINE_SPINLOCK(gem0clk_lock); | |
78 | static DEFINE_SPINLOCK(gem1clk_lock); | |
79 | static DEFINE_SPINLOCK(canclk_lock); | |
80 | static DEFINE_SPINLOCK(canmioclk_lock); | |
81 | static DEFINE_SPINLOCK(dbgclk_lock); | |
82 | static DEFINE_SPINLOCK(aperclk_lock); | |
83 | ||
84 | static const char dummy_nm[] __initconst = "dummy_name"; | |
85 | ||
86 | static const char *armpll_parents[] __initdata = {"armpll_int", "ps_clk"}; | |
87 | static const char *ddrpll_parents[] __initdata = {"ddrpll_int", "ps_clk"}; | |
88 | static const char *iopll_parents[] __initdata = {"iopll_int", "ps_clk"}; | |
89 | static const char *gem0_mux_parents[] __initdata = {"gem0_div1", dummy_nm}; | |
90 | static const char *gem1_mux_parents[] __initdata = {"gem1_div1", dummy_nm}; | |
91 | static const char *can0_mio_mux2_parents[] __initdata = {"can0_gate", | |
92 | "can0_mio_mux"}; | |
93 | static const char *can1_mio_mux2_parents[] __initdata = {"can1_gate", | |
94 | "can1_mio_mux"}; | |
95 | static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div", | |
96 | dummy_nm}; | |
97 | ||
98 | static const char *dbgtrc_emio_input_names[] __initdata = {"trace_emio_clk"}; | |
99 | static const char *gem0_emio_input_names[] __initdata = {"gem0_emio_clk"}; | |
100 | static const char *gem1_emio_input_names[] __initdata = {"gem1_emio_clk"}; | |
101 | static const char *swdt_ext_clk_input_names[] __initdata = {"swdt_ext_clk"}; | |
102 | ||
103 | static void __init zynq_clk_register_fclk(enum zynq_clk fclk, | |
104 | const char *clk_name, void __iomem *fclk_ctrl_reg, | |
105 | const char **parents) | |
106 | { | |
107 | struct clk *clk; | |
108 | char *mux_name; | |
109 | char *div0_name; | |
110 | char *div1_name; | |
111 | spinlock_t *fclk_lock; | |
112 | spinlock_t *fclk_gate_lock; | |
113 | void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8; | |
114 | ||
115 | fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL); | |
116 | if (!fclk_lock) | |
117 | goto err; | |
118 | fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL); | |
119 | if (!fclk_gate_lock) | |
f8fe36f6 | 120 | goto err_fclk_gate_lock; |
0ee52b15 SB |
121 | spin_lock_init(fclk_lock); |
122 | spin_lock_init(fclk_gate_lock); | |
123 | ||
124 | mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name); | |
f8fe36f6 FP |
125 | if (!mux_name) |
126 | goto err_mux_name; | |
0ee52b15 | 127 | div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name); |
f8fe36f6 FP |
128 | if (!div0_name) |
129 | goto err_div0_name; | |
0ee52b15 | 130 | div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name); |
f8fe36f6 FP |
131 | if (!div1_name) |
132 | goto err_div1_name; | |
0ee52b15 | 133 | |
819c1de3 JH |
134 | clk = clk_register_mux(NULL, mux_name, parents, 4, |
135 | CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0, | |
136 | fclk_lock); | |
0ee52b15 SB |
137 | |
138 | clk = clk_register_divider(NULL, div0_name, mux_name, | |
139 | 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | | |
140 | CLK_DIVIDER_ALLOW_ZERO, fclk_lock); | |
141 | ||
142 | clk = clk_register_divider(NULL, div1_name, div0_name, | |
143 | CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6, | |
144 | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, | |
145 | fclk_lock); | |
146 | ||
147 | clks[fclk] = clk_register_gate(NULL, clk_name, | |
148 | div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, | |
149 | 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); | |
150 | kfree(mux_name); | |
151 | kfree(div0_name); | |
152 | kfree(div1_name); | |
153 | ||
154 | return; | |
155 | ||
f8fe36f6 FP |
156 | err_div1_name: |
157 | kfree(div0_name); | |
158 | err_div0_name: | |
159 | kfree(mux_name); | |
160 | err_mux_name: | |
161 | kfree(fclk_gate_lock); | |
162 | err_fclk_gate_lock: | |
163 | kfree(fclk_lock); | |
0ee52b15 SB |
164 | err: |
165 | clks[fclk] = ERR_PTR(-ENOMEM); | |
166 | } | |
167 | ||
168 | static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0, | |
169 | enum zynq_clk clk1, const char *clk_name0, | |
170 | const char *clk_name1, void __iomem *clk_ctrl, | |
171 | const char **parents, unsigned int two_gates) | |
172 | { | |
173 | struct clk *clk; | |
174 | char *mux_name; | |
175 | char *div_name; | |
176 | spinlock_t *lock; | |
177 | ||
178 | lock = kmalloc(sizeof(*lock), GFP_KERNEL); | |
179 | if (!lock) | |
180 | goto err; | |
181 | spin_lock_init(lock); | |
182 | ||
183 | mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0); | |
184 | div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0); | |
185 | ||
819c1de3 JH |
186 | clk = clk_register_mux(NULL, mux_name, parents, 4, |
187 | CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock); | |
0ee52b15 SB |
188 | |
189 | clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6, | |
190 | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); | |
191 | ||
192 | clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, | |
193 | CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock); | |
194 | if (two_gates) | |
195 | clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, | |
196 | CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock); | |
197 | ||
198 | kfree(mux_name); | |
199 | kfree(div_name); | |
200 | ||
201 | return; | |
202 | ||
203 | err: | |
204 | clks[clk0] = ERR_PTR(-ENOMEM); | |
205 | if (two_gates) | |
206 | clks[clk1] = ERR_PTR(-ENOMEM); | |
207 | } | |
208 | ||
209 | static void __init zynq_clk_setup(struct device_node *np) | |
210 | { | |
211 | int i; | |
212 | u32 tmp; | |
213 | int ret; | |
214 | struct clk *clk; | |
215 | char *clk_name; | |
216 | const char *clk_output_name[clk_max]; | |
217 | const char *cpu_parents[4]; | |
218 | const char *periph_parents[4]; | |
219 | const char *swdt_ext_clk_mux_parents[2]; | |
220 | const char *can_mio_mux_parents[NUM_MIO_PINS]; | |
221 | ||
222 | pr_info("Zynq clock init\n"); | |
223 | ||
224 | /* get clock output names from DT */ | |
225 | for (i = 0; i < clk_max; i++) { | |
226 | if (of_property_read_string_index(np, "clock-output-names", | |
227 | i, &clk_output_name[i])) { | |
228 | pr_err("%s: clock output name not in DT\n", __func__); | |
229 | BUG(); | |
230 | } | |
231 | } | |
232 | cpu_parents[0] = clk_output_name[armpll]; | |
233 | cpu_parents[1] = clk_output_name[armpll]; | |
234 | cpu_parents[2] = clk_output_name[ddrpll]; | |
235 | cpu_parents[3] = clk_output_name[iopll]; | |
236 | periph_parents[0] = clk_output_name[iopll]; | |
237 | periph_parents[1] = clk_output_name[iopll]; | |
238 | periph_parents[2] = clk_output_name[armpll]; | |
239 | periph_parents[3] = clk_output_name[ddrpll]; | |
240 | ||
241 | /* ps_clk */ | |
242 | ret = of_property_read_u32(np, "ps-clk-frequency", &tmp); | |
243 | if (ret) { | |
244 | pr_warn("ps_clk frequency not specified, using 33 MHz.\n"); | |
245 | tmp = 33333333; | |
246 | } | |
247 | ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT, | |
248 | tmp); | |
249 | ||
250 | /* PLLs */ | |
251 | clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL, | |
252 | SLCR_PLL_STATUS, 0, &armpll_lock); | |
253 | clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], | |
819c1de3 JH |
254 | armpll_parents, 2, CLK_SET_RATE_NO_REPARENT, |
255 | SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock); | |
0ee52b15 SB |
256 | |
257 | clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL, | |
258 | SLCR_PLL_STATUS, 1, &ddrpll_lock); | |
259 | clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], | |
819c1de3 JH |
260 | ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT, |
261 | SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock); | |
0ee52b15 SB |
262 | |
263 | clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL, | |
264 | SLCR_PLL_STATUS, 2, &iopll_lock); | |
265 | clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll], | |
819c1de3 JH |
266 | iopll_parents, 2, CLK_SET_RATE_NO_REPARENT, |
267 | SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock); | |
0ee52b15 SB |
268 | |
269 | /* CPU clocks */ | |
270 | tmp = readl(SLCR_621_TRUE) & 1; | |
819c1de3 JH |
271 | clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, |
272 | CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0, | |
273 | &armclk_lock); | |
0ee52b15 SB |
274 | clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0, |
275 | SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | | |
276 | CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); | |
277 | ||
278 | clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x], | |
279 | "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
280 | SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock); | |
281 | ||
282 | clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0, | |
283 | 1, 2); | |
284 | clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x], | |
285 | "cpu_3or2x_div", CLK_IGNORE_UNUSED, | |
286 | SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock); | |
287 | ||
288 | clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1, | |
289 | 2 + tmp); | |
290 | clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x], | |
291 | "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, | |
292 | 26, 0, &armclk_lock); | |
293 | ||
294 | clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1, | |
295 | 4 + 2 * tmp); | |
296 | clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x], | |
297 | "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27, | |
298 | 0, &armclk_lock); | |
299 | ||
300 | /* Timers */ | |
301 | swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x]; | |
302 | for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) { | |
303 | int idx = of_property_match_string(np, "clock-names", | |
304 | swdt_ext_clk_input_names[i]); | |
305 | if (idx >= 0) | |
306 | swdt_ext_clk_mux_parents[i + 1] = | |
307 | of_clk_get_parent_name(np, idx); | |
308 | else | |
309 | swdt_ext_clk_mux_parents[i + 1] = dummy_nm; | |
310 | } | |
311 | clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt], | |
819c1de3 JH |
312 | swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT | |
313 | CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0, | |
bef4a0ab | 314 | &swdtclk_lock); |
0ee52b15 SB |
315 | |
316 | /* DDR clocks */ | |
317 | clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, | |
318 | SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED | | |
319 | CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); | |
320 | clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x], | |
321 | "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock); | |
322 | clk_prepare_enable(clks[ddr2x]); | |
323 | clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, | |
324 | SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | | |
325 | CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); | |
326 | clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x], | |
327 | "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock); | |
328 | clk_prepare_enable(clks[ddr3x]); | |
329 | ||
330 | clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0, | |
331 | SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | | |
332 | CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock); | |
333 | clk = clk_register_divider(NULL, "dci_div1", "dci_div0", | |
334 | CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6, | |
335 | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, | |
336 | &dciclk_lock); | |
337 | clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1", | |
338 | CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0, | |
339 | &dciclk_lock); | |
340 | clk_prepare_enable(clks[dci]); | |
341 | ||
342 | /* Peripheral clocks */ | |
343 | for (i = fclk0; i <= fclk3; i++) | |
344 | zynq_clk_register_fclk(i, clk_output_name[i], | |
345 | SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0), | |
346 | periph_parents); | |
347 | ||
348 | zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL, | |
349 | SLCR_LQSPI_CLK_CTRL, periph_parents, 0); | |
350 | ||
351 | zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL, | |
352 | SLCR_SMC_CLK_CTRL, periph_parents, 0); | |
353 | ||
354 | zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL, | |
355 | SLCR_PCAP_CLK_CTRL, periph_parents, 0); | |
356 | ||
357 | zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0], | |
358 | clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL, | |
359 | periph_parents, 1); | |
360 | ||
361 | zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0], | |
362 | clk_output_name[uart1], SLCR_UART_CLK_CTRL, | |
363 | periph_parents, 1); | |
364 | ||
365 | zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0], | |
366 | clk_output_name[spi1], SLCR_SPI_CLK_CTRL, | |
367 | periph_parents, 1); | |
368 | ||
369 | for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) { | |
370 | int idx = of_property_match_string(np, "clock-names", | |
371 | gem0_emio_input_names[i]); | |
372 | if (idx >= 0) | |
373 | gem0_mux_parents[i + 1] = of_clk_get_parent_name(np, | |
374 | idx); | |
375 | } | |
819c1de3 JH |
376 | clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4, |
377 | CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0, | |
378 | &gem0clk_lock); | |
0ee52b15 SB |
379 | clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0, |
380 | SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | | |
381 | CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); | |
382 | clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0", | |
383 | CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6, | |
384 | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, | |
385 | &gem0clk_lock); | |
765b7d4c | 386 | clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, |
bef4a0ab LT |
387 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
388 | SLCR_GEM0_CLK_CTRL, 6, 1, 0, | |
765b7d4c | 389 | &gem0clk_lock); |
0ee52b15 SB |
390 | clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0], |
391 | "gem0_emio_mux", CLK_SET_RATE_PARENT, | |
392 | SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock); | |
393 | ||
394 | for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) { | |
395 | int idx = of_property_match_string(np, "clock-names", | |
396 | gem1_emio_input_names[i]); | |
397 | if (idx >= 0) | |
398 | gem1_mux_parents[i + 1] = of_clk_get_parent_name(np, | |
399 | idx); | |
400 | } | |
819c1de3 JH |
401 | clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4, |
402 | CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0, | |
403 | &gem1clk_lock); | |
0ee52b15 SB |
404 | clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0, |
405 | SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | | |
406 | CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); | |
407 | clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0", | |
408 | CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6, | |
409 | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, | |
410 | &gem1clk_lock); | |
765b7d4c | 411 | clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, |
bef4a0ab LT |
412 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
413 | SLCR_GEM1_CLK_CTRL, 6, 1, 0, | |
765b7d4c | 414 | &gem1clk_lock); |
0ee52b15 SB |
415 | clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1], |
416 | "gem1_emio_mux", CLK_SET_RATE_PARENT, | |
417 | SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock); | |
418 | ||
419 | tmp = strlen("mio_clk_00x"); | |
420 | clk_name = kmalloc(tmp, GFP_KERNEL); | |
421 | for (i = 0; i < NUM_MIO_PINS; i++) { | |
422 | int idx; | |
423 | ||
424 | snprintf(clk_name, tmp, "mio_clk_%2.2d", i); | |
425 | idx = of_property_match_string(np, "clock-names", clk_name); | |
426 | if (idx >= 0) | |
427 | can_mio_mux_parents[i] = of_clk_get_parent_name(np, | |
428 | idx); | |
429 | else | |
430 | can_mio_mux_parents[i] = dummy_nm; | |
431 | } | |
432 | kfree(clk_name); | |
819c1de3 JH |
433 | clk = clk_register_mux(NULL, "can_mux", periph_parents, 4, |
434 | CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0, | |
435 | &canclk_lock); | |
0ee52b15 SB |
436 | clk = clk_register_divider(NULL, "can_div0", "can_mux", 0, |
437 | SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | | |
438 | CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); | |
439 | clk = clk_register_divider(NULL, "can_div1", "can_div0", | |
440 | CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6, | |
441 | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, | |
442 | &canclk_lock); | |
443 | clk = clk_register_gate(NULL, "can0_gate", "can_div1", | |
444 | CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0, | |
445 | &canclk_lock); | |
446 | clk = clk_register_gate(NULL, "can1_gate", "can_div1", | |
447 | CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0, | |
448 | &canclk_lock); | |
449 | clk = clk_register_mux(NULL, "can0_mio_mux", | |
819c1de3 JH |
450 | can_mio_mux_parents, 54, CLK_SET_RATE_PARENT | |
451 | CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, | |
452 | &canmioclk_lock); | |
0ee52b15 | 453 | clk = clk_register_mux(NULL, "can1_mio_mux", |
819c1de3 JH |
454 | can_mio_mux_parents, 54, CLK_SET_RATE_PARENT | |
455 | CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6, | |
456 | 0, &canmioclk_lock); | |
0ee52b15 | 457 | clks[can0] = clk_register_mux(NULL, clk_output_name[can0], |
819c1de3 JH |
458 | can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT | |
459 | CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, | |
460 | &canmioclk_lock); | |
0ee52b15 | 461 | clks[can1] = clk_register_mux(NULL, clk_output_name[can1], |
819c1de3 JH |
462 | can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT | |
463 | CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1, | |
464 | 0, &canmioclk_lock); | |
0ee52b15 SB |
465 | |
466 | for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) { | |
467 | int idx = of_property_match_string(np, "clock-names", | |
468 | dbgtrc_emio_input_names[i]); | |
469 | if (idx >= 0) | |
470 | dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np, | |
471 | idx); | |
472 | } | |
819c1de3 JH |
473 | clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4, |
474 | CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0, | |
475 | &dbgclk_lock); | |
0ee52b15 SB |
476 | clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0, |
477 | SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | | |
478 | CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); | |
819c1de3 JH |
479 | clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, |
480 | CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0, | |
481 | &dbgclk_lock); | |
0ee52b15 SB |
482 | clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc], |
483 | "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL, | |
484 | 0, 0, &dbgclk_lock); | |
485 | clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb], | |
486 | clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0, | |
487 | &dbgclk_lock); | |
488 | ||
489 | /* One gated clock for all APER clocks. */ | |
490 | clks[dma] = clk_register_gate(NULL, clk_output_name[dma], | |
491 | clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0, | |
492 | &aperclk_lock); | |
493 | clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper], | |
494 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0, | |
495 | &aperclk_lock); | |
496 | clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper], | |
497 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0, | |
498 | &aperclk_lock); | |
499 | clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper], | |
500 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0, | |
501 | &aperclk_lock); | |
502 | clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper], | |
503 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0, | |
504 | &aperclk_lock); | |
505 | clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper], | |
506 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0, | |
507 | &aperclk_lock); | |
508 | clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper], | |
509 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0, | |
510 | &aperclk_lock); | |
511 | clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper], | |
512 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0, | |
513 | &aperclk_lock); | |
514 | clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper], | |
515 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0, | |
516 | &aperclk_lock); | |
517 | clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper], | |
518 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0, | |
519 | &aperclk_lock); | |
520 | clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper], | |
521 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0, | |
522 | &aperclk_lock); | |
523 | clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper], | |
524 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0, | |
525 | &aperclk_lock); | |
526 | clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper], | |
527 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0, | |
528 | &aperclk_lock); | |
529 | clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper], | |
530 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0, | |
531 | &aperclk_lock); | |
532 | clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper], | |
533 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0, | |
534 | &aperclk_lock); | |
535 | clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper], | |
536 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0, | |
537 | &aperclk_lock); | |
538 | clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper], | |
539 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0, | |
540 | &aperclk_lock); | |
541 | clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper], | |
542 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0, | |
543 | &aperclk_lock); | |
544 | ||
545 | for (i = 0; i < ARRAY_SIZE(clks); i++) { | |
546 | if (IS_ERR(clks[i])) { | |
547 | pr_err("Zynq clk %d: register failed with %ld\n", | |
548 | i, PTR_ERR(clks[i])); | |
549 | BUG(); | |
550 | } | |
551 | } | |
552 | ||
553 | clk_data.clks = clks; | |
554 | clk_data.clk_num = ARRAY_SIZE(clks); | |
555 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
556 | } | |
557 | ||
558 | CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup); | |
559 | ||
560 | void __init zynq_clock_init(void __iomem *slcr_base) | |
561 | { | |
562 | zynq_slcr_base_priv = slcr_base; | |
563 | of_clk_init(NULL); | |
564 | } |