Merge branch 'fixes-for-3.9-latest' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / dma / Kconfig
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1#
2# DMA engine configuration
3#
4
2ed6dc34 5menuconfig DMADEVICES
6d4f5879 6 bool "DMA Engine support"
04ce9ab3 7 depends on HAS_DMA
2ed6dc34 8 help
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9 DMA engines can do asynchronous data transfers without
10 involving the host CPU. Currently, this framework can be
11 used to offload memory copies in the network stack and
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12 RAID operations in the MD driver. This menu only presents
13 DMA Device drivers supported by the configured arch, it may
14 be empty in some cases.
2ed6dc34 15
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16config DMADEVICES_DEBUG
17 bool "DMA Engine debugging"
18 depends on DMADEVICES != n
19 help
20 This is an option for use by developers; most people should
21 say N here. This enables DMA engine core and driver debugging.
22
23config DMADEVICES_VDEBUG
24 bool "DMA Engine verbose debugging"
25 depends on DMADEVICES_DEBUG != n
26 help
27 This is an option for use by developers; most people should
28 say N here. This enables deeper (more verbose) debugging of
29 the DMA engine core and drivers.
30
31
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32if DMADEVICES
33
34comment "DMA Devices"
35
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36config INTEL_MID_DMAC
37 tristate "Intel MID DMA support for Peripheral DMA controllers"
38 depends on PCI && X86
39 select DMA_ENGINE
40 default n
41 help
42 Enable support for the Intel(R) MID DMA engine present
43 in Intel MID chipsets.
44
45 Say Y here if you have such a chipset.
46
47 If unsure, say N.
48
5fc6d897 49config ASYNC_TX_ENABLE_CHANNEL_SWITCH
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50 bool
51
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52config AMBA_PL08X
53 bool "ARM PrimeCell PL080 or PL081 support"
c6a0aec9 54 depends on ARM_AMBA
e8689e63 55 select DMA_ENGINE
083be28a 56 select DMA_VIRTUAL_CHANNELS
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57 help
58 Platform has a PL08x DMAC device
59 which can provide DMA engine support
60
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61config INTEL_IOATDMA
62 tristate "Intel I/OAT DMA support"
63 depends on PCI && X86
64 select DMA_ENGINE
65 select DCA
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66 select ASYNC_TX_DISABLE_PQ_VAL_DMA
67 select ASYNC_TX_DISABLE_XOR_VAL_DMA
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68 help
69 Enable support for the Intel(R) I/OAT DMA engine present
70 in recent Intel Xeon chipsets.
71
72 Say Y here if you have such a chipset.
73
74 If unsure, say N.
75
76config INTEL_IOP_ADMA
77 tristate "Intel IOP ADMA support"
78 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
2ed6dc34 79 select DMA_ENGINE
5fc6d897 80 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
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81 help
82 Enable support for the Intel(R) IOP Series RAID engines.
c13c8260 83
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84config DW_DMAC
85 tristate "Synopsys DesignWare AHB DMA support"
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86 select DMA_ENGINE
87 default y if CPU_AT32AP7000
88 help
89 Support the Synopsys DesignWare AHB DMA controller. This
90 can be integrated in chips such as the Atmel AT32ap7000.
91
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92config DW_DMAC_BIG_ENDIAN_IO
93 bool "Use big endian I/O register access"
94 default y if AVR32
95 depends on DW_DMAC
96 help
97 Say yes here to use big endian I/O access when reading and writing
98 to the DMA controller registers. This is needed on some platforms,
99 like the Atmel AVR32 architecture.
100
101 If unsure, use the default setting.
102
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103config AT_HDMAC
104 tristate "Atmel AHB DMA support"
f898fed0 105 depends on ARCH_AT91
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106 select DMA_ENGINE
107 help
f898fed0 108 Support the Atmel AHB DMA controller.
dc78baa2 109
173acc7c 110config FSL_DMA
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111 tristate "Freescale Elo and Elo Plus DMA support"
112 depends on FSL_SOC
173acc7c 113 select DMA_ENGINE
5fc6d897 114 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
173acc7c 115 ---help---
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116 Enable support for the Freescale Elo and Elo Plus DMA controllers.
117 The Elo is the DMA controller on some 82xx and 83xx parts, and the
118 Elo Plus is the DMA controller on 85xx and 86xx parts.
173acc7c 119
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120config MPC512X_DMA
121 tristate "Freescale MPC512x built-in DMA engine support"
ba2eea25 122 depends on PPC_MPC512x || PPC_MPC831x
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123 select DMA_ENGINE
124 ---help---
125 Enable support for the Freescale MPC512x built-in DMA engine.
126
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127source "drivers/dma/bestcomm/Kconfig"
128
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129config MV_XOR
130 bool "Marvell XOR engine support"
131 depends on PLAT_ORION
ff7b0479 132 select DMA_ENGINE
5fc6d897 133 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
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134 ---help---
135 Enable support for the Marvell XOR engine.
136
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137config MX3_IPU
138 bool "MX3x Image Processing Unit support"
8e2d41f8 139 depends on ARCH_MXC
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140 select DMA_ENGINE
141 default y
142 help
143 If you plan to use the Image Processing unit in the i.MX3x, say
144 Y here. If unsure, select Y.
145
146config MX3_IPU_IRQS
147 int "Number of dynamically mapped interrupts for IPU"
148 depends on MX3_IPU
149 range 2 137
150 default 4
151 help
152 Out of 137 interrupt sources on i.MX31 IPU only very few are used.
153 To avoid bloating the irq_desc[] array we allocate a sufficient
154 number of IRQ slots and map them dynamically to specific sources.
155
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156config TXX9_DMAC
157 tristate "Toshiba TXx9 SoC DMA support"
158 depends on MACH_TX49XX || MACH_TX39XX
159 select DMA_ENGINE
160 help
161 Support the TXx9 SoC internal DMA controller. This can be
162 integrated in chips such as the Toshiba TX4927/38/39.
163
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164config TEGRA20_APB_DMA
165 bool "NVIDIA Tegra20 APB DMA support"
166 depends on ARCH_TEGRA
167 select DMA_ENGINE
168 help
169 Support for the NVIDIA Tegra20 APB DMA controller driver. The
170 DMA controller is having multiple DMA channel which can be
171 configured for different peripherals like audio, UART, SPI,
172 I2C etc which is in APB bus.
173 This DMA controller transfers data from memory to peripheral fifo
174 or vice versa. It does not support memory to memory data transfer.
175
176
177
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178config SH_DMAE
179 tristate "Renesas SuperH DMAC support"
927a7c9c 180 depends on (SUPERH && SH_DMA) || (ARM && ARCH_SHMOBILE)
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181 depends on !SH_DMA_API
182 select DMA_ENGINE
183 help
184 Enable support for the Renesas SuperH DMA controllers.
185
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186config COH901318
187 bool "ST-Ericsson COH901318 DMA support"
188 select DMA_ENGINE
189 depends on ARCH_U300
190 help
191 Enable support for ST-Ericsson COH 901 318 DMA.
192
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193config STE_DMA40
194 bool "ST-Ericsson DMA40 support"
195 depends on ARCH_U8500
196 select DMA_ENGINE
197 help
198 Support for ST-Ericsson DMA40 controller
199
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200config AMCC_PPC440SPE_ADMA
201 tristate "AMCC PPC440SPe ADMA support"
202 depends on 440SPe || 440SP
203 select DMA_ENGINE
204 select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
5fc6d897 205 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
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206 help
207 Enable support for the AMCC PPC440SPe RAID engines.
208
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209config TIMB_DMA
210 tristate "Timberdale FPGA DMA support"
211 depends on MFD_TIMBERDALE || HAS_IOMEM
212 select DMA_ENGINE
213 help
214 Enable support for the Timberdale FPGA DMA engine.
215
ca21a146 216config SIRF_DMA
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217 tristate "CSR SiRFprimaII/SiRFmarco DMA support"
218 depends on ARCH_SIRF
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219 select DMA_ENGINE
220 help
221 Enable support for the CSR SiRFprimaII DMA engine.
222
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223config TI_EDMA
224 tristate "TI EDMA support"
225 depends on ARCH_DAVINCI
226 select DMA_ENGINE
227 select DMA_VIRTUAL_CHANNELS
228 default n
229 help
230 Enable support for the TI EDMA controller. This DMA
231 engine is found on TI DaVinci and AM33xx parts.
232
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233config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
234 bool
235
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236config PL330_DMA
237 tristate "DMA API Driver for PL330"
238 select DMA_ENGINE
1b9bb715 239 depends on ARM_AMBA
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240 help
241 Select if your platform has one or more PL330 DMACs.
242 You need to provide platform specific settings via
243 platform_data for a dma-pl330 device.
244
0c42bd0e 245config PCH_DMA
ca7fe2db 246 tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA"
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247 depends on PCI && X86
248 select DMA_ENGINE
249 help
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250 Enable support for Intel EG20T PCH DMA engine.
251
e79e72be 252 This driver also can be used for LAPIS Semiconductor IOH(Input/
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253 Output Hub), ML7213, ML7223 and ML7831.
254 ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is
255 for MP(Media Phone) use and ML7831 IOH is for general purpose use.
256 ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
257 ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
0c42bd0e 258
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259config IMX_SDMA
260 tristate "i.MX SDMA support"
8e2d41f8 261 depends on ARCH_MXC
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262 select DMA_ENGINE
263 help
264 Support the i.MX SDMA engine. This engine is integrated into
8e2d41f8 265 Freescale i.MX25/31/35/51/53 chips.
1ec1e82f 266
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267config IMX_DMA
268 tristate "i.MX DMA support"
5b2e02e4 269 depends on ARCH_MXC
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270 select DMA_ENGINE
271 help
272 Support the i.MX DMA engine. This engine is integrated into
273 Freescale i.MX1/21/27 chips.
274
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275config MXS_DMA
276 bool "MXS DMA support"
f5c55847 277 depends on SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q
f5b7efcc 278 select STMP_DEVICE
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279 select DMA_ENGINE
280 help
281 Support the MXS DMA engine. This engine including APBH-DMA
282 and APBX-DMA is integrated into Freescale i.MX23/28 chips.
283
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284config EP93XX_DMA
285 bool "Cirrus Logic EP93xx DMA support"
286 depends on ARCH_EP93XX
287 select DMA_ENGINE
288 help
289 Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
290
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291config DMA_SA11X0
292 tristate "SA-11x0 DMA support"
293 depends on ARCH_SA1100
294 select DMA_ENGINE
50437bff 295 select DMA_VIRTUAL_CHANNELS
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296 help
297 Support the DMA engine found on Intel StrongARM SA-1100 and
298 SA-1110 SoCs. This DMA engine can only be used with on-chip
299 devices.
300
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301config MMP_TDMA
302 bool "MMP Two-Channel DMA support"
49d57b5e 303 depends on ARCH_MMP
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304 select DMA_ENGINE
305 help
306 Support the MMP Two-Channel DMA engine.
307 This engine used for MMP Audio DMA and pxa910 SQU.
308
309 Say Y here if you enabled MMP ADMA, otherwise say N.
310
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311config DMA_OMAP
312 tristate "OMAP DMA support"
313 depends on ARCH_OMAP
314 select DMA_ENGINE
315 select DMA_VIRTUAL_CHANNELS
316
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317config MMP_PDMA
318 bool "MMP PDMA support"
319 depends on (ARCH_MMP || ARCH_PXA)
320 select DMA_ENGINE
321 help
322 Support the MMP PDMA engine for PXA and MMP platfrom.
323
c13c8260 324config DMA_ENGINE
2ed6dc34 325 bool
c13c8260 326
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327config DMA_VIRTUAL_CHANNELS
328 tristate
329
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330config DMA_OF
331 def_bool y
332 depends on OF
333
db217334 334comment "DMA Clients"
2ed6dc34 335 depends on DMA_ENGINE
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336
337config NET_DMA
338 bool "Network: TCP receive copy offload"
339 depends on DMA_ENGINE && NET
9c402f4e 340 default (INTEL_IOATDMA || FSL_DMA)
2ed6dc34 341 help
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342 This enables the use of DMA engines in the network stack to
343 offload receive copy-to-user operations, freeing CPU cycles.
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344
345 Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
346 say N.
db217334 347
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348config ASYNC_TX_DMA
349 bool "Async_tx: Offload support for the async_tx api"
9a8de639 350 depends on DMA_ENGINE
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351 help
352 This allows the async_tx api to take advantage of offload engines for
353 memcpy, memset, xor, and raid6 p+q operations. If your platform has
354 a dma engine that can perform raid operations and you have enabled
355 MD_RAID456 say Y.
356
357 If unsure, say N.
358
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359config DMATEST
360 tristate "DMA Test client"
361 depends on DMA_ENGINE
362 help
363 Simple DMA test client. Say N unless you're debugging a
364 DMA Device driver.
365
2ed6dc34 366endif
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