Commit | Line | Data |
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dc78baa2 NF |
1 | /* |
2 | * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems) | |
3 | * | |
4 | * Copyright (C) 2008 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * | |
12 | * This supports the Atmel AHB DMA Controller, | |
13 | * | |
14 | * The driver has currently been tested with the Atmel AT91SAM9RL | |
15 | * and AT91SAM9G45 series. | |
16 | */ | |
17 | ||
18 | #include <linux/clk.h> | |
19 | #include <linux/dmaengine.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | #include <linux/dmapool.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
c5115953 NF |
26 | #include <linux/of.h> |
27 | #include <linux/of_device.h> | |
dc78baa2 NF |
28 | |
29 | #include "at_hdmac_regs.h" | |
d2ebfb33 | 30 | #include "dmaengine.h" |
dc78baa2 NF |
31 | |
32 | /* | |
33 | * Glossary | |
34 | * -------- | |
35 | * | |
36 | * at_hdmac : Name of the ATmel AHB DMA Controller | |
37 | * at_dma_ / atdma : ATmel DMA controller entity related | |
38 | * atc_ / atchan : ATmel DMA Channel entity related | |
39 | */ | |
40 | ||
41 | #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO) | |
42 | #define ATC_DEFAULT_CTRLA (0) | |
ae14d4b5 NF |
43 | #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \ |
44 | |ATC_DIF(AT_DMA_MEM_IF)) | |
dc78baa2 NF |
45 | |
46 | /* | |
47 | * Initial number of descriptors to allocate for each channel. This could | |
48 | * be increased during dma usage. | |
49 | */ | |
50 | static unsigned int init_nr_desc_per_channel = 64; | |
51 | module_param(init_nr_desc_per_channel, uint, 0644); | |
52 | MODULE_PARM_DESC(init_nr_desc_per_channel, | |
53 | "initial descriptors per channel (default: 64)"); | |
54 | ||
55 | ||
56 | /* prototypes */ | |
57 | static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx); | |
58 | ||
59 | ||
60 | /*----------------------------------------------------------------------*/ | |
61 | ||
62 | static struct at_desc *atc_first_active(struct at_dma_chan *atchan) | |
63 | { | |
64 | return list_first_entry(&atchan->active_list, | |
65 | struct at_desc, desc_node); | |
66 | } | |
67 | ||
68 | static struct at_desc *atc_first_queued(struct at_dma_chan *atchan) | |
69 | { | |
70 | return list_first_entry(&atchan->queue, | |
71 | struct at_desc, desc_node); | |
72 | } | |
73 | ||
74 | /** | |
421f91d2 | 75 | * atc_alloc_descriptor - allocate and return an initialized descriptor |
dc78baa2 NF |
76 | * @chan: the channel to allocate descriptors for |
77 | * @gfp_flags: GFP allocation flags | |
78 | * | |
79 | * Note: The ack-bit is positioned in the descriptor flag at creation time | |
80 | * to make initial allocation more convenient. This bit will be cleared | |
81 | * and control will be given to client at usage time (during | |
82 | * preparation functions). | |
83 | */ | |
84 | static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan, | |
85 | gfp_t gfp_flags) | |
86 | { | |
87 | struct at_desc *desc = NULL; | |
88 | struct at_dma *atdma = to_at_dma(chan->device); | |
89 | dma_addr_t phys; | |
90 | ||
91 | desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys); | |
92 | if (desc) { | |
93 | memset(desc, 0, sizeof(struct at_desc)); | |
285a3c71 | 94 | INIT_LIST_HEAD(&desc->tx_list); |
dc78baa2 NF |
95 | dma_async_tx_descriptor_init(&desc->txd, chan); |
96 | /* txd.flags will be overwritten in prep functions */ | |
97 | desc->txd.flags = DMA_CTRL_ACK; | |
98 | desc->txd.tx_submit = atc_tx_submit; | |
99 | desc->txd.phys = phys; | |
100 | } | |
101 | ||
102 | return desc; | |
103 | } | |
104 | ||
105 | /** | |
af901ca1 | 106 | * atc_desc_get - get an unused descriptor from free_list |
dc78baa2 NF |
107 | * @atchan: channel we want a new descriptor for |
108 | */ | |
109 | static struct at_desc *atc_desc_get(struct at_dma_chan *atchan) | |
110 | { | |
111 | struct at_desc *desc, *_desc; | |
112 | struct at_desc *ret = NULL; | |
d8cb04b0 | 113 | unsigned long flags; |
dc78baa2 NF |
114 | unsigned int i = 0; |
115 | LIST_HEAD(tmp_list); | |
116 | ||
d8cb04b0 | 117 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 NF |
118 | list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { |
119 | i++; | |
120 | if (async_tx_test_ack(&desc->txd)) { | |
121 | list_del(&desc->desc_node); | |
122 | ret = desc; | |
123 | break; | |
124 | } | |
125 | dev_dbg(chan2dev(&atchan->chan_common), | |
126 | "desc %p not ACKed\n", desc); | |
127 | } | |
d8cb04b0 | 128 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
129 | dev_vdbg(chan2dev(&atchan->chan_common), |
130 | "scanned %u descriptors on freelist\n", i); | |
131 | ||
132 | /* no more descriptor available in initial pool: create one more */ | |
133 | if (!ret) { | |
134 | ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC); | |
135 | if (ret) { | |
d8cb04b0 | 136 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 | 137 | atchan->descs_allocated++; |
d8cb04b0 | 138 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
139 | } else { |
140 | dev_err(chan2dev(&atchan->chan_common), | |
141 | "not enough descriptors available\n"); | |
142 | } | |
143 | } | |
144 | ||
145 | return ret; | |
146 | } | |
147 | ||
148 | /** | |
149 | * atc_desc_put - move a descriptor, including any children, to the free list | |
150 | * @atchan: channel we work on | |
151 | * @desc: descriptor, at the head of a chain, to move to free list | |
152 | */ | |
153 | static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc) | |
154 | { | |
155 | if (desc) { | |
156 | struct at_desc *child; | |
d8cb04b0 | 157 | unsigned long flags; |
dc78baa2 | 158 | |
d8cb04b0 | 159 | spin_lock_irqsave(&atchan->lock, flags); |
285a3c71 | 160 | list_for_each_entry(child, &desc->tx_list, desc_node) |
dc78baa2 NF |
161 | dev_vdbg(chan2dev(&atchan->chan_common), |
162 | "moving child desc %p to freelist\n", | |
163 | child); | |
285a3c71 | 164 | list_splice_init(&desc->tx_list, &atchan->free_list); |
dc78baa2 NF |
165 | dev_vdbg(chan2dev(&atchan->chan_common), |
166 | "moving desc %p to freelist\n", desc); | |
167 | list_add(&desc->desc_node, &atchan->free_list); | |
d8cb04b0 | 168 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
169 | } |
170 | } | |
171 | ||
53830cc7 NF |
172 | /** |
173 | * atc_desc_chain - build chain adding a descripor | |
174 | * @first: address of first descripor of the chain | |
175 | * @prev: address of previous descripor of the chain | |
176 | * @desc: descriptor to queue | |
177 | * | |
178 | * Called from prep_* functions | |
179 | */ | |
180 | static void atc_desc_chain(struct at_desc **first, struct at_desc **prev, | |
181 | struct at_desc *desc) | |
182 | { | |
183 | if (!(*first)) { | |
184 | *first = desc; | |
185 | } else { | |
186 | /* inform the HW lli about chaining */ | |
187 | (*prev)->lli.dscr = desc->txd.phys; | |
188 | /* insert the link descriptor to the LD ring */ | |
189 | list_add_tail(&desc->desc_node, | |
190 | &(*first)->tx_list); | |
191 | } | |
192 | *prev = desc; | |
193 | } | |
194 | ||
dc78baa2 NF |
195 | /** |
196 | * atc_dostart - starts the DMA engine for real | |
197 | * @atchan: the channel we want to start | |
198 | * @first: first descriptor in the list we want to begin with | |
199 | * | |
200 | * Called with atchan->lock held and bh disabled | |
201 | */ | |
202 | static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first) | |
203 | { | |
204 | struct at_dma *atdma = to_at_dma(atchan->chan_common.device); | |
205 | ||
206 | /* ASSERT: channel is idle */ | |
207 | if (atc_chan_is_enabled(atchan)) { | |
208 | dev_err(chan2dev(&atchan->chan_common), | |
209 | "BUG: Attempted to start non-idle channel\n"); | |
210 | dev_err(chan2dev(&atchan->chan_common), | |
211 | " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n", | |
212 | channel_readl(atchan, SADDR), | |
213 | channel_readl(atchan, DADDR), | |
214 | channel_readl(atchan, CTRLA), | |
215 | channel_readl(atchan, CTRLB), | |
216 | channel_readl(atchan, DSCR)); | |
217 | ||
218 | /* The tasklet will hopefully advance the queue... */ | |
219 | return; | |
220 | } | |
221 | ||
222 | vdbg_dump_regs(atchan); | |
223 | ||
224 | /* clear any pending interrupt */ | |
225 | while (dma_readl(atdma, EBCISR)) | |
226 | cpu_relax(); | |
227 | ||
228 | channel_writel(atchan, SADDR, 0); | |
229 | channel_writel(atchan, DADDR, 0); | |
230 | channel_writel(atchan, CTRLA, 0); | |
231 | channel_writel(atchan, CTRLB, 0); | |
232 | channel_writel(atchan, DSCR, first->txd.phys); | |
233 | dma_writel(atdma, CHER, atchan->mask); | |
234 | ||
235 | vdbg_dump_regs(atchan); | |
236 | } | |
237 | ||
238 | /** | |
239 | * atc_chain_complete - finish work for one transaction chain | |
240 | * @atchan: channel we work on | |
241 | * @desc: descriptor at the head of the chain we want do complete | |
242 | * | |
243 | * Called with atchan->lock held and bh disabled */ | |
244 | static void | |
245 | atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) | |
246 | { | |
dc78baa2 NF |
247 | struct dma_async_tx_descriptor *txd = &desc->txd; |
248 | ||
249 | dev_vdbg(chan2dev(&atchan->chan_common), | |
250 | "descriptor %u complete\n", txd->cookie); | |
251 | ||
f7fbce07 | 252 | dma_cookie_complete(txd); |
dc78baa2 NF |
253 | |
254 | /* move children to free_list */ | |
285a3c71 | 255 | list_splice_init(&desc->tx_list, &atchan->free_list); |
dc78baa2 NF |
256 | /* move myself to free_list */ |
257 | list_move(&desc->desc_node, &atchan->free_list); | |
258 | ||
ebcf9b80 | 259 | /* unmap dma addresses (not on slave channels) */ |
657a77fa AN |
260 | if (!atchan->chan_common.private) { |
261 | struct device *parent = chan2parent(&atchan->chan_common); | |
262 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
263 | if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
264 | dma_unmap_single(parent, | |
265 | desc->lli.daddr, | |
266 | desc->len, DMA_FROM_DEVICE); | |
267 | else | |
268 | dma_unmap_page(parent, | |
269 | desc->lli.daddr, | |
270 | desc->len, DMA_FROM_DEVICE); | |
271 | } | |
272 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
273 | if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
274 | dma_unmap_single(parent, | |
275 | desc->lli.saddr, | |
276 | desc->len, DMA_TO_DEVICE); | |
277 | else | |
278 | dma_unmap_page(parent, | |
279 | desc->lli.saddr, | |
280 | desc->len, DMA_TO_DEVICE); | |
281 | } | |
dc78baa2 NF |
282 | } |
283 | ||
53830cc7 NF |
284 | /* for cyclic transfers, |
285 | * no need to replay callback function while stopping */ | |
3c477482 | 286 | if (!atc_chan_is_cyclic(atchan)) { |
53830cc7 NF |
287 | dma_async_tx_callback callback = txd->callback; |
288 | void *param = txd->callback_param; | |
289 | ||
290 | /* | |
291 | * The API requires that no submissions are done from a | |
292 | * callback, so we don't need to drop the lock here | |
293 | */ | |
294 | if (callback) | |
295 | callback(param); | |
296 | } | |
dc78baa2 NF |
297 | |
298 | dma_run_dependencies(txd); | |
299 | } | |
300 | ||
301 | /** | |
302 | * atc_complete_all - finish work for all transactions | |
303 | * @atchan: channel to complete transactions for | |
304 | * | |
305 | * Eventually submit queued descriptors if any | |
306 | * | |
307 | * Assume channel is idle while calling this function | |
308 | * Called with atchan->lock held and bh disabled | |
309 | */ | |
310 | static void atc_complete_all(struct at_dma_chan *atchan) | |
311 | { | |
312 | struct at_desc *desc, *_desc; | |
313 | LIST_HEAD(list); | |
314 | ||
315 | dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n"); | |
316 | ||
317 | BUG_ON(atc_chan_is_enabled(atchan)); | |
318 | ||
319 | /* | |
320 | * Submit queued descriptors ASAP, i.e. before we go through | |
321 | * the completed ones. | |
322 | */ | |
323 | if (!list_empty(&atchan->queue)) | |
324 | atc_dostart(atchan, atc_first_queued(atchan)); | |
325 | /* empty active_list now it is completed */ | |
326 | list_splice_init(&atchan->active_list, &list); | |
327 | /* empty queue list by moving descriptors (if any) to active_list */ | |
328 | list_splice_init(&atchan->queue, &atchan->active_list); | |
329 | ||
330 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
331 | atc_chain_complete(atchan, desc); | |
332 | } | |
333 | ||
334 | /** | |
335 | * atc_cleanup_descriptors - cleanup up finished descriptors in active_list | |
336 | * @atchan: channel to be cleaned up | |
337 | * | |
338 | * Called with atchan->lock held and bh disabled | |
339 | */ | |
340 | static void atc_cleanup_descriptors(struct at_dma_chan *atchan) | |
341 | { | |
342 | struct at_desc *desc, *_desc; | |
343 | struct at_desc *child; | |
344 | ||
345 | dev_vdbg(chan2dev(&atchan->chan_common), "cleanup descriptors\n"); | |
346 | ||
347 | list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) { | |
348 | if (!(desc->lli.ctrla & ATC_DONE)) | |
349 | /* This one is currently in progress */ | |
350 | return; | |
351 | ||
285a3c71 | 352 | list_for_each_entry(child, &desc->tx_list, desc_node) |
dc78baa2 NF |
353 | if (!(child->lli.ctrla & ATC_DONE)) |
354 | /* Currently in progress */ | |
355 | return; | |
356 | ||
357 | /* | |
358 | * No descriptors so far seem to be in progress, i.e. | |
359 | * this chain must be done. | |
360 | */ | |
361 | atc_chain_complete(atchan, desc); | |
362 | } | |
363 | } | |
364 | ||
365 | /** | |
366 | * atc_advance_work - at the end of a transaction, move forward | |
367 | * @atchan: channel where the transaction ended | |
368 | * | |
369 | * Called with atchan->lock held and bh disabled | |
370 | */ | |
371 | static void atc_advance_work(struct at_dma_chan *atchan) | |
372 | { | |
373 | dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n"); | |
374 | ||
375 | if (list_empty(&atchan->active_list) || | |
376 | list_is_singular(&atchan->active_list)) { | |
377 | atc_complete_all(atchan); | |
378 | } else { | |
379 | atc_chain_complete(atchan, atc_first_active(atchan)); | |
380 | /* advance work */ | |
381 | atc_dostart(atchan, atc_first_active(atchan)); | |
382 | } | |
383 | } | |
384 | ||
385 | ||
386 | /** | |
387 | * atc_handle_error - handle errors reported by DMA controller | |
388 | * @atchan: channel where error occurs | |
389 | * | |
390 | * Called with atchan->lock held and bh disabled | |
391 | */ | |
392 | static void atc_handle_error(struct at_dma_chan *atchan) | |
393 | { | |
394 | struct at_desc *bad_desc; | |
395 | struct at_desc *child; | |
396 | ||
397 | /* | |
398 | * The descriptor currently at the head of the active list is | |
399 | * broked. Since we don't have any way to report errors, we'll | |
400 | * just have to scream loudly and try to carry on. | |
401 | */ | |
402 | bad_desc = atc_first_active(atchan); | |
403 | list_del_init(&bad_desc->desc_node); | |
404 | ||
405 | /* As we are stopped, take advantage to push queued descriptors | |
406 | * in active_list */ | |
407 | list_splice_init(&atchan->queue, atchan->active_list.prev); | |
408 | ||
409 | /* Try to restart the controller */ | |
410 | if (!list_empty(&atchan->active_list)) | |
411 | atc_dostart(atchan, atc_first_active(atchan)); | |
412 | ||
413 | /* | |
414 | * KERN_CRITICAL may seem harsh, but since this only happens | |
415 | * when someone submits a bad physical address in a | |
416 | * descriptor, we should consider ourselves lucky that the | |
417 | * controller flagged an error instead of scribbling over | |
418 | * random memory locations. | |
419 | */ | |
420 | dev_crit(chan2dev(&atchan->chan_common), | |
421 | "Bad descriptor submitted for DMA!\n"); | |
422 | dev_crit(chan2dev(&atchan->chan_common), | |
423 | " cookie: %d\n", bad_desc->txd.cookie); | |
424 | atc_dump_lli(atchan, &bad_desc->lli); | |
285a3c71 | 425 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
dc78baa2 NF |
426 | atc_dump_lli(atchan, &child->lli); |
427 | ||
428 | /* Pretend the descriptor completed successfully */ | |
429 | atc_chain_complete(atchan, bad_desc); | |
430 | } | |
431 | ||
53830cc7 NF |
432 | /** |
433 | * atc_handle_cyclic - at the end of a period, run callback function | |
434 | * @atchan: channel used for cyclic operations | |
435 | * | |
436 | * Called with atchan->lock held and bh disabled | |
437 | */ | |
438 | static void atc_handle_cyclic(struct at_dma_chan *atchan) | |
439 | { | |
440 | struct at_desc *first = atc_first_active(atchan); | |
441 | struct dma_async_tx_descriptor *txd = &first->txd; | |
442 | dma_async_tx_callback callback = txd->callback; | |
443 | void *param = txd->callback_param; | |
444 | ||
445 | dev_vdbg(chan2dev(&atchan->chan_common), | |
446 | "new cyclic period llp 0x%08x\n", | |
447 | channel_readl(atchan, DSCR)); | |
448 | ||
449 | if (callback) | |
450 | callback(param); | |
451 | } | |
dc78baa2 NF |
452 | |
453 | /*-- IRQ & Tasklet ---------------------------------------------------*/ | |
454 | ||
455 | static void atc_tasklet(unsigned long data) | |
456 | { | |
457 | struct at_dma_chan *atchan = (struct at_dma_chan *)data; | |
d8cb04b0 | 458 | unsigned long flags; |
dc78baa2 | 459 | |
d8cb04b0 | 460 | spin_lock_irqsave(&atchan->lock, flags); |
53830cc7 | 461 | if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status)) |
dc78baa2 | 462 | atc_handle_error(atchan); |
3c477482 | 463 | else if (atc_chan_is_cyclic(atchan)) |
53830cc7 | 464 | atc_handle_cyclic(atchan); |
dc78baa2 NF |
465 | else |
466 | atc_advance_work(atchan); | |
467 | ||
d8cb04b0 | 468 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
469 | } |
470 | ||
471 | static irqreturn_t at_dma_interrupt(int irq, void *dev_id) | |
472 | { | |
473 | struct at_dma *atdma = (struct at_dma *)dev_id; | |
474 | struct at_dma_chan *atchan; | |
475 | int i; | |
476 | u32 status, pending, imr; | |
477 | int ret = IRQ_NONE; | |
478 | ||
479 | do { | |
480 | imr = dma_readl(atdma, EBCIMR); | |
481 | status = dma_readl(atdma, EBCISR); | |
482 | pending = status & imr; | |
483 | ||
484 | if (!pending) | |
485 | break; | |
486 | ||
487 | dev_vdbg(atdma->dma_common.dev, | |
488 | "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n", | |
489 | status, imr, pending); | |
490 | ||
491 | for (i = 0; i < atdma->dma_common.chancnt; i++) { | |
492 | atchan = &atdma->chan[i]; | |
9b3aa589 | 493 | if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) { |
dc78baa2 NF |
494 | if (pending & AT_DMA_ERR(i)) { |
495 | /* Disable channel on AHB error */ | |
23b5e3ad NF |
496 | dma_writel(atdma, CHDR, |
497 | AT_DMA_RES(i) | atchan->mask); | |
dc78baa2 | 498 | /* Give information to tasklet */ |
53830cc7 | 499 | set_bit(ATC_IS_ERROR, &atchan->status); |
dc78baa2 NF |
500 | } |
501 | tasklet_schedule(&atchan->tasklet); | |
502 | ret = IRQ_HANDLED; | |
503 | } | |
504 | } | |
505 | ||
506 | } while (pending); | |
507 | ||
508 | return ret; | |
509 | } | |
510 | ||
511 | ||
512 | /*-- DMA Engine API --------------------------------------------------*/ | |
513 | ||
514 | /** | |
515 | * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine | |
516 | * @desc: descriptor at the head of the transaction chain | |
517 | * | |
518 | * Queue chain if DMA engine is working already | |
519 | * | |
520 | * Cookie increment and adding to active_list or queue must be atomic | |
521 | */ | |
522 | static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx) | |
523 | { | |
524 | struct at_desc *desc = txd_to_at_desc(tx); | |
525 | struct at_dma_chan *atchan = to_at_dma_chan(tx->chan); | |
526 | dma_cookie_t cookie; | |
d8cb04b0 | 527 | unsigned long flags; |
dc78baa2 | 528 | |
d8cb04b0 | 529 | spin_lock_irqsave(&atchan->lock, flags); |
884485e1 | 530 | cookie = dma_cookie_assign(tx); |
dc78baa2 NF |
531 | |
532 | if (list_empty(&atchan->active_list)) { | |
533 | dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", | |
534 | desc->txd.cookie); | |
535 | atc_dostart(atchan, desc); | |
536 | list_add_tail(&desc->desc_node, &atchan->active_list); | |
537 | } else { | |
538 | dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", | |
539 | desc->txd.cookie); | |
540 | list_add_tail(&desc->desc_node, &atchan->queue); | |
541 | } | |
542 | ||
d8cb04b0 | 543 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
544 | |
545 | return cookie; | |
546 | } | |
547 | ||
548 | /** | |
549 | * atc_prep_dma_memcpy - prepare a memcpy operation | |
550 | * @chan: the channel to prepare operation on | |
551 | * @dest: operation virtual destination address | |
552 | * @src: operation virtual source address | |
553 | * @len: operation length | |
554 | * @flags: tx descriptor status flags | |
555 | */ | |
556 | static struct dma_async_tx_descriptor * | |
557 | atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
558 | size_t len, unsigned long flags) | |
559 | { | |
560 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
561 | struct at_desc *desc = NULL; | |
562 | struct at_desc *first = NULL; | |
563 | struct at_desc *prev = NULL; | |
564 | size_t xfer_count; | |
565 | size_t offset; | |
566 | unsigned int src_width; | |
567 | unsigned int dst_width; | |
568 | u32 ctrla; | |
569 | u32 ctrlb; | |
570 | ||
571 | dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n", | |
572 | dest, src, len, flags); | |
573 | ||
574 | if (unlikely(!len)) { | |
575 | dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); | |
576 | return NULL; | |
577 | } | |
578 | ||
579 | ctrla = ATC_DEFAULT_CTRLA; | |
9b3aa589 | 580 | ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN |
dc78baa2 NF |
581 | | ATC_SRC_ADDR_MODE_INCR |
582 | | ATC_DST_ADDR_MODE_INCR | |
583 | | ATC_FC_MEM2MEM; | |
584 | ||
585 | /* | |
586 | * We can be a lot more clever here, but this should take care | |
587 | * of the most common optimization. | |
588 | */ | |
589 | if (!((src | dest | len) & 3)) { | |
590 | ctrla |= ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD; | |
591 | src_width = dst_width = 2; | |
592 | } else if (!((src | dest | len) & 1)) { | |
593 | ctrla |= ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD; | |
594 | src_width = dst_width = 1; | |
595 | } else { | |
596 | ctrla |= ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE; | |
597 | src_width = dst_width = 0; | |
598 | } | |
599 | ||
600 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
601 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
602 | ATC_BTSIZE_MAX); | |
603 | ||
604 | desc = atc_desc_get(atchan); | |
605 | if (!desc) | |
606 | goto err_desc_get; | |
607 | ||
608 | desc->lli.saddr = src + offset; | |
609 | desc->lli.daddr = dest + offset; | |
610 | desc->lli.ctrla = ctrla | xfer_count; | |
611 | desc->lli.ctrlb = ctrlb; | |
612 | ||
613 | desc->txd.cookie = 0; | |
dc78baa2 | 614 | |
e257e156 | 615 | atc_desc_chain(&first, &prev, desc); |
dc78baa2 NF |
616 | } |
617 | ||
618 | /* First descriptor of the chain embedds additional information */ | |
619 | first->txd.cookie = -EBUSY; | |
620 | first->len = len; | |
621 | ||
622 | /* set end-of-link to the last link descriptor of list*/ | |
623 | set_desc_eol(desc); | |
624 | ||
568f7f0c | 625 | first->txd.flags = flags; /* client is in control of this ack */ |
dc78baa2 NF |
626 | |
627 | return &first->txd; | |
628 | ||
629 | err_desc_get: | |
630 | atc_desc_put(atchan, first); | |
631 | return NULL; | |
632 | } | |
633 | ||
808347f6 NF |
634 | |
635 | /** | |
636 | * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
637 | * @chan: DMA channel | |
638 | * @sgl: scatterlist to transfer to/from | |
639 | * @sg_len: number of entries in @scatterlist | |
640 | * @direction: DMA direction | |
641 | * @flags: tx descriptor status flags | |
185ecb5f | 642 | * @context: transaction context (ignored) |
808347f6 NF |
643 | */ |
644 | static struct dma_async_tx_descriptor * | |
645 | atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 646 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 647 | unsigned long flags, void *context) |
808347f6 NF |
648 | { |
649 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
650 | struct at_dma_slave *atslave = chan->private; | |
651 | struct at_desc *first = NULL; | |
652 | struct at_desc *prev = NULL; | |
653 | u32 ctrla; | |
654 | u32 ctrlb; | |
655 | dma_addr_t reg; | |
656 | unsigned int reg_width; | |
657 | unsigned int mem_width; | |
658 | unsigned int i; | |
659 | struct scatterlist *sg; | |
660 | size_t total_len = 0; | |
661 | ||
cc52a10a NF |
662 | dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n", |
663 | sg_len, | |
db8196df | 664 | direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", |
808347f6 NF |
665 | flags); |
666 | ||
667 | if (unlikely(!atslave || !sg_len)) { | |
668 | dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); | |
669 | return NULL; | |
670 | } | |
671 | ||
672 | reg_width = atslave->reg_width; | |
673 | ||
808347f6 | 674 | ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla; |
ae14d4b5 | 675 | ctrlb = ATC_IEN; |
808347f6 NF |
676 | |
677 | switch (direction) { | |
db8196df | 678 | case DMA_MEM_TO_DEV: |
808347f6 NF |
679 | ctrla |= ATC_DST_WIDTH(reg_width); |
680 | ctrlb |= ATC_DST_ADDR_MODE_FIXED | |
681 | | ATC_SRC_ADDR_MODE_INCR | |
ae14d4b5 NF |
682 | | ATC_FC_MEM2PER |
683 | | ATC_SIF(AT_DMA_MEM_IF) | ATC_DIF(AT_DMA_PER_IF); | |
808347f6 NF |
684 | reg = atslave->tx_reg; |
685 | for_each_sg(sgl, sg, sg_len, i) { | |
686 | struct at_desc *desc; | |
687 | u32 len; | |
688 | u32 mem; | |
689 | ||
690 | desc = atc_desc_get(atchan); | |
691 | if (!desc) | |
692 | goto err_desc_get; | |
693 | ||
0f70e8ce | 694 | mem = sg_dma_address(sg); |
808347f6 NF |
695 | len = sg_dma_len(sg); |
696 | mem_width = 2; | |
697 | if (unlikely(mem & 3 || len & 3)) | |
698 | mem_width = 0; | |
699 | ||
700 | desc->lli.saddr = mem; | |
701 | desc->lli.daddr = reg; | |
702 | desc->lli.ctrla = ctrla | |
703 | | ATC_SRC_WIDTH(mem_width) | |
704 | | len >> mem_width; | |
705 | desc->lli.ctrlb = ctrlb; | |
706 | ||
e257e156 | 707 | atc_desc_chain(&first, &prev, desc); |
808347f6 NF |
708 | total_len += len; |
709 | } | |
710 | break; | |
db8196df | 711 | case DMA_DEV_TO_MEM: |
808347f6 NF |
712 | ctrla |= ATC_SRC_WIDTH(reg_width); |
713 | ctrlb |= ATC_DST_ADDR_MODE_INCR | |
714 | | ATC_SRC_ADDR_MODE_FIXED | |
ae14d4b5 NF |
715 | | ATC_FC_PER2MEM |
716 | | ATC_SIF(AT_DMA_PER_IF) | ATC_DIF(AT_DMA_MEM_IF); | |
808347f6 NF |
717 | |
718 | reg = atslave->rx_reg; | |
719 | for_each_sg(sgl, sg, sg_len, i) { | |
720 | struct at_desc *desc; | |
721 | u32 len; | |
722 | u32 mem; | |
723 | ||
724 | desc = atc_desc_get(atchan); | |
725 | if (!desc) | |
726 | goto err_desc_get; | |
727 | ||
0f70e8ce | 728 | mem = sg_dma_address(sg); |
808347f6 NF |
729 | len = sg_dma_len(sg); |
730 | mem_width = 2; | |
731 | if (unlikely(mem & 3 || len & 3)) | |
732 | mem_width = 0; | |
733 | ||
734 | desc->lli.saddr = reg; | |
735 | desc->lli.daddr = mem; | |
736 | desc->lli.ctrla = ctrla | |
737 | | ATC_DST_WIDTH(mem_width) | |
59a609d9 | 738 | | len >> reg_width; |
808347f6 NF |
739 | desc->lli.ctrlb = ctrlb; |
740 | ||
e257e156 | 741 | atc_desc_chain(&first, &prev, desc); |
808347f6 NF |
742 | total_len += len; |
743 | } | |
744 | break; | |
745 | default: | |
746 | return NULL; | |
747 | } | |
748 | ||
749 | /* set end-of-link to the last link descriptor of list*/ | |
750 | set_desc_eol(prev); | |
751 | ||
752 | /* First descriptor of the chain embedds additional information */ | |
753 | first->txd.cookie = -EBUSY; | |
754 | first->len = total_len; | |
755 | ||
568f7f0c NF |
756 | /* first link descriptor of list is responsible of flags */ |
757 | first->txd.flags = flags; /* client is in control of this ack */ | |
808347f6 NF |
758 | |
759 | return &first->txd; | |
760 | ||
761 | err_desc_get: | |
762 | dev_err(chan2dev(chan), "not enough descriptors available\n"); | |
763 | atc_desc_put(atchan, first); | |
764 | return NULL; | |
765 | } | |
766 | ||
53830cc7 NF |
767 | /** |
768 | * atc_dma_cyclic_check_values | |
769 | * Check for too big/unaligned periods and unaligned DMA buffer | |
770 | */ | |
771 | static int | |
772 | atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr, | |
db8196df | 773 | size_t period_len, enum dma_transfer_direction direction) |
53830cc7 NF |
774 | { |
775 | if (period_len > (ATC_BTSIZE_MAX << reg_width)) | |
776 | goto err_out; | |
777 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
778 | goto err_out; | |
779 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
780 | goto err_out; | |
db8196df | 781 | if (unlikely(!(direction & (DMA_DEV_TO_MEM | DMA_MEM_TO_DEV)))) |
53830cc7 NF |
782 | goto err_out; |
783 | ||
784 | return 0; | |
785 | ||
786 | err_out: | |
787 | return -EINVAL; | |
788 | } | |
789 | ||
790 | /** | |
791 | * atc_dma_cyclic_fill_desc - Fill one period decriptor | |
792 | */ | |
793 | static int | |
794 | atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc, | |
795 | unsigned int period_index, dma_addr_t buf_addr, | |
db8196df | 796 | size_t period_len, enum dma_transfer_direction direction) |
53830cc7 NF |
797 | { |
798 | u32 ctrla; | |
799 | unsigned int reg_width = atslave->reg_width; | |
800 | ||
801 | /* prepare common CRTLA value */ | |
802 | ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla | |
803 | | ATC_DST_WIDTH(reg_width) | |
804 | | ATC_SRC_WIDTH(reg_width) | |
805 | | period_len >> reg_width; | |
806 | ||
807 | switch (direction) { | |
db8196df | 808 | case DMA_MEM_TO_DEV: |
53830cc7 NF |
809 | desc->lli.saddr = buf_addr + (period_len * period_index); |
810 | desc->lli.daddr = atslave->tx_reg; | |
811 | desc->lli.ctrla = ctrla; | |
ae14d4b5 | 812 | desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED |
53830cc7 | 813 | | ATC_SRC_ADDR_MODE_INCR |
ae14d4b5 NF |
814 | | ATC_FC_MEM2PER |
815 | | ATC_SIF(AT_DMA_MEM_IF) | |
816 | | ATC_DIF(AT_DMA_PER_IF); | |
53830cc7 NF |
817 | break; |
818 | ||
db8196df | 819 | case DMA_DEV_TO_MEM: |
53830cc7 NF |
820 | desc->lli.saddr = atslave->rx_reg; |
821 | desc->lli.daddr = buf_addr + (period_len * period_index); | |
822 | desc->lli.ctrla = ctrla; | |
ae14d4b5 | 823 | desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR |
53830cc7 | 824 | | ATC_SRC_ADDR_MODE_FIXED |
ae14d4b5 NF |
825 | | ATC_FC_PER2MEM |
826 | | ATC_SIF(AT_DMA_PER_IF) | |
827 | | ATC_DIF(AT_DMA_MEM_IF); | |
53830cc7 NF |
828 | break; |
829 | ||
830 | default: | |
831 | return -EINVAL; | |
832 | } | |
833 | ||
834 | return 0; | |
835 | } | |
836 | ||
837 | /** | |
838 | * atc_prep_dma_cyclic - prepare the cyclic DMA transfer | |
839 | * @chan: the DMA channel to prepare | |
840 | * @buf_addr: physical DMA address where the buffer starts | |
841 | * @buf_len: total number of bytes for the entire buffer | |
842 | * @period_len: number of bytes for each period | |
843 | * @direction: transfer direction, to or from device | |
185ecb5f | 844 | * @context: transfer context (ignored) |
53830cc7 NF |
845 | */ |
846 | static struct dma_async_tx_descriptor * | |
847 | atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
185ecb5f AB |
848 | size_t period_len, enum dma_transfer_direction direction, |
849 | void *context) | |
53830cc7 NF |
850 | { |
851 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
852 | struct at_dma_slave *atslave = chan->private; | |
853 | struct at_desc *first = NULL; | |
854 | struct at_desc *prev = NULL; | |
855 | unsigned long was_cyclic; | |
856 | unsigned int periods = buf_len / period_len; | |
857 | unsigned int i; | |
858 | ||
859 | dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n", | |
db8196df | 860 | direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", |
53830cc7 NF |
861 | buf_addr, |
862 | periods, buf_len, period_len); | |
863 | ||
864 | if (unlikely(!atslave || !buf_len || !period_len)) { | |
865 | dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n"); | |
866 | return NULL; | |
867 | } | |
868 | ||
869 | was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status); | |
870 | if (was_cyclic) { | |
871 | dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n"); | |
872 | return NULL; | |
873 | } | |
874 | ||
875 | /* Check for too big/unaligned periods and unaligned DMA buffer */ | |
876 | if (atc_dma_cyclic_check_values(atslave->reg_width, buf_addr, | |
877 | period_len, direction)) | |
878 | goto err_out; | |
879 | ||
880 | /* build cyclic linked list */ | |
881 | for (i = 0; i < periods; i++) { | |
882 | struct at_desc *desc; | |
883 | ||
884 | desc = atc_desc_get(atchan); | |
885 | if (!desc) | |
886 | goto err_desc_get; | |
887 | ||
888 | if (atc_dma_cyclic_fill_desc(atslave, desc, i, buf_addr, | |
889 | period_len, direction)) | |
890 | goto err_desc_get; | |
891 | ||
892 | atc_desc_chain(&first, &prev, desc); | |
893 | } | |
894 | ||
895 | /* lets make a cyclic list */ | |
896 | prev->lli.dscr = first->txd.phys; | |
897 | ||
898 | /* First descriptor of the chain embedds additional information */ | |
899 | first->txd.cookie = -EBUSY; | |
900 | first->len = buf_len; | |
901 | ||
902 | return &first->txd; | |
903 | ||
904 | err_desc_get: | |
905 | dev_err(chan2dev(chan), "not enough descriptors available\n"); | |
906 | atc_desc_put(atchan, first); | |
907 | err_out: | |
908 | clear_bit(ATC_IS_CYCLIC, &atchan->status); | |
909 | return NULL; | |
910 | } | |
911 | ||
912 | ||
05827630 LW |
913 | static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
914 | unsigned long arg) | |
808347f6 NF |
915 | { |
916 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
917 | struct at_dma *atdma = to_at_dma(chan->device); | |
23b5e3ad | 918 | int chan_id = atchan->chan_common.chan_id; |
d8cb04b0 | 919 | unsigned long flags; |
23b5e3ad | 920 | |
808347f6 NF |
921 | LIST_HEAD(list); |
922 | ||
23b5e3ad | 923 | dev_vdbg(chan2dev(chan), "atc_control (%d)\n", cmd); |
c3635c78 | 924 | |
23b5e3ad | 925 | if (cmd == DMA_PAUSE) { |
d8cb04b0 | 926 | spin_lock_irqsave(&atchan->lock, flags); |
808347f6 | 927 | |
23b5e3ad | 928 | dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id)); |
23b5e3ad | 929 | set_bit(ATC_IS_PAUSED, &atchan->status); |
808347f6 | 930 | |
d8cb04b0 | 931 | spin_unlock_irqrestore(&atchan->lock, flags); |
23b5e3ad | 932 | } else if (cmd == DMA_RESUME) { |
3c477482 | 933 | if (!atc_chan_is_paused(atchan)) |
23b5e3ad | 934 | return 0; |
808347f6 | 935 | |
d8cb04b0 | 936 | spin_lock_irqsave(&atchan->lock, flags); |
808347f6 | 937 | |
23b5e3ad NF |
938 | dma_writel(atdma, CHDR, AT_DMA_RES(chan_id)); |
939 | clear_bit(ATC_IS_PAUSED, &atchan->status); | |
c3635c78 | 940 | |
d8cb04b0 | 941 | spin_unlock_irqrestore(&atchan->lock, flags); |
23b5e3ad NF |
942 | } else if (cmd == DMA_TERMINATE_ALL) { |
943 | struct at_desc *desc, *_desc; | |
944 | /* | |
945 | * This is only called when something went wrong elsewhere, so | |
946 | * we don't really care about the data. Just disable the | |
947 | * channel. We still have to poll the channel enable bit due | |
948 | * to AHB/HSB limitations. | |
949 | */ | |
d8cb04b0 | 950 | spin_lock_irqsave(&atchan->lock, flags); |
23b5e3ad NF |
951 | |
952 | /* disabling channel: must also remove suspend state */ | |
953 | dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask); | |
954 | ||
955 | /* confirm that this channel is disabled */ | |
956 | while (dma_readl(atdma, CHSR) & atchan->mask) | |
957 | cpu_relax(); | |
958 | ||
959 | /* active_list entries will end up before queued entries */ | |
960 | list_splice_init(&atchan->queue, &list); | |
961 | list_splice_init(&atchan->active_list, &list); | |
962 | ||
963 | /* Flush all pending and queued descriptors */ | |
964 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
965 | atc_chain_complete(atchan, desc); | |
966 | ||
967 | clear_bit(ATC_IS_PAUSED, &atchan->status); | |
968 | /* if channel dedicated to cyclic operations, free it */ | |
969 | clear_bit(ATC_IS_CYCLIC, &atchan->status); | |
970 | ||
d8cb04b0 | 971 | spin_unlock_irqrestore(&atchan->lock, flags); |
23b5e3ad NF |
972 | } else { |
973 | return -ENXIO; | |
974 | } | |
b0ebeb9c | 975 | |
c3635c78 | 976 | return 0; |
808347f6 NF |
977 | } |
978 | ||
dc78baa2 | 979 | /** |
07934481 | 980 | * atc_tx_status - poll for transaction completion |
dc78baa2 NF |
981 | * @chan: DMA channel |
982 | * @cookie: transaction identifier to check status of | |
07934481 | 983 | * @txstate: if not %NULL updated with transaction state |
dc78baa2 | 984 | * |
07934481 | 985 | * If @txstate is passed in, upon return it reflect the driver |
dc78baa2 NF |
986 | * internal state and can be used with dma_async_is_complete() to check |
987 | * the status of multiple cookies without re-checking hardware state. | |
988 | */ | |
989 | static enum dma_status | |
07934481 | 990 | atc_tx_status(struct dma_chan *chan, |
dc78baa2 | 991 | dma_cookie_t cookie, |
07934481 | 992 | struct dma_tx_state *txstate) |
dc78baa2 NF |
993 | { |
994 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
995 | dma_cookie_t last_used; | |
996 | dma_cookie_t last_complete; | |
d8cb04b0 | 997 | unsigned long flags; |
dc78baa2 NF |
998 | enum dma_status ret; |
999 | ||
d8cb04b0 | 1000 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 | 1001 | |
96a2af41 | 1002 | ret = dma_cookie_status(chan, cookie, txstate); |
dc78baa2 NF |
1003 | if (ret != DMA_SUCCESS) { |
1004 | atc_cleanup_descriptors(atchan); | |
1005 | ||
96a2af41 | 1006 | ret = dma_cookie_status(chan, cookie, txstate); |
dc78baa2 NF |
1007 | } |
1008 | ||
96a2af41 RKAL |
1009 | last_complete = chan->completed_cookie; |
1010 | last_used = chan->cookie; | |
1011 | ||
d8cb04b0 | 1012 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 | 1013 | |
543aabc7 | 1014 | if (ret != DMA_SUCCESS) |
96a2af41 | 1015 | dma_set_residue(txstate, atc_first_active(atchan)->len); |
543aabc7 | 1016 | |
3c477482 | 1017 | if (atc_chan_is_paused(atchan)) |
23b5e3ad NF |
1018 | ret = DMA_PAUSED; |
1019 | ||
1020 | dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d (d%d, u%d)\n", | |
1021 | ret, cookie, last_complete ? last_complete : 0, | |
07934481 | 1022 | last_used ? last_used : 0); |
dc78baa2 NF |
1023 | |
1024 | return ret; | |
1025 | } | |
1026 | ||
1027 | /** | |
1028 | * atc_issue_pending - try to finish work | |
1029 | * @chan: target DMA channel | |
1030 | */ | |
1031 | static void atc_issue_pending(struct dma_chan *chan) | |
1032 | { | |
1033 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
d8cb04b0 | 1034 | unsigned long flags; |
dc78baa2 NF |
1035 | |
1036 | dev_vdbg(chan2dev(chan), "issue_pending\n"); | |
1037 | ||
53830cc7 | 1038 | /* Not needed for cyclic transfers */ |
3c477482 | 1039 | if (atc_chan_is_cyclic(atchan)) |
53830cc7 NF |
1040 | return; |
1041 | ||
d8cb04b0 | 1042 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 | 1043 | if (!atc_chan_is_enabled(atchan)) { |
dc78baa2 | 1044 | atc_advance_work(atchan); |
dc78baa2 | 1045 | } |
d8cb04b0 | 1046 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
1047 | } |
1048 | ||
1049 | /** | |
1050 | * atc_alloc_chan_resources - allocate resources for DMA channel | |
1051 | * @chan: allocate descriptor resources for this channel | |
1052 | * @client: current client requesting the channel be ready for requests | |
1053 | * | |
1054 | * return - the number of allocated descriptors | |
1055 | */ | |
1056 | static int atc_alloc_chan_resources(struct dma_chan *chan) | |
1057 | { | |
1058 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1059 | struct at_dma *atdma = to_at_dma(chan->device); | |
1060 | struct at_desc *desc; | |
808347f6 | 1061 | struct at_dma_slave *atslave; |
d8cb04b0 | 1062 | unsigned long flags; |
dc78baa2 | 1063 | int i; |
808347f6 | 1064 | u32 cfg; |
dc78baa2 NF |
1065 | LIST_HEAD(tmp_list); |
1066 | ||
1067 | dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); | |
1068 | ||
1069 | /* ASSERT: channel is idle */ | |
1070 | if (atc_chan_is_enabled(atchan)) { | |
1071 | dev_dbg(chan2dev(chan), "DMA channel not idle ?\n"); | |
1072 | return -EIO; | |
1073 | } | |
1074 | ||
808347f6 NF |
1075 | cfg = ATC_DEFAULT_CFG; |
1076 | ||
1077 | atslave = chan->private; | |
1078 | if (atslave) { | |
1079 | /* | |
1080 | * We need controller-specific data to set up slave | |
1081 | * transfers. | |
1082 | */ | |
1083 | BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev); | |
1084 | ||
1085 | /* if cfg configuration specified take it instad of default */ | |
1086 | if (atslave->cfg) | |
1087 | cfg = atslave->cfg; | |
1088 | } | |
1089 | ||
1090 | /* have we already been set up? | |
1091 | * reconfigure channel but no need to reallocate descriptors */ | |
dc78baa2 NF |
1092 | if (!list_empty(&atchan->free_list)) |
1093 | return atchan->descs_allocated; | |
1094 | ||
1095 | /* Allocate initial pool of descriptors */ | |
1096 | for (i = 0; i < init_nr_desc_per_channel; i++) { | |
1097 | desc = atc_alloc_descriptor(chan, GFP_KERNEL); | |
1098 | if (!desc) { | |
1099 | dev_err(atdma->dma_common.dev, | |
1100 | "Only %d initial descriptors\n", i); | |
1101 | break; | |
1102 | } | |
1103 | list_add_tail(&desc->desc_node, &tmp_list); | |
1104 | } | |
1105 | ||
d8cb04b0 | 1106 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 NF |
1107 | atchan->descs_allocated = i; |
1108 | list_splice(&tmp_list, &atchan->free_list); | |
d3ee98cd | 1109 | dma_cookie_init(chan); |
d8cb04b0 | 1110 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
1111 | |
1112 | /* channel parameters */ | |
808347f6 | 1113 | channel_writel(atchan, CFG, cfg); |
dc78baa2 NF |
1114 | |
1115 | dev_dbg(chan2dev(chan), | |
1116 | "alloc_chan_resources: allocated %d descriptors\n", | |
1117 | atchan->descs_allocated); | |
1118 | ||
1119 | return atchan->descs_allocated; | |
1120 | } | |
1121 | ||
1122 | /** | |
1123 | * atc_free_chan_resources - free all channel resources | |
1124 | * @chan: DMA channel | |
1125 | */ | |
1126 | static void atc_free_chan_resources(struct dma_chan *chan) | |
1127 | { | |
1128 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1129 | struct at_dma *atdma = to_at_dma(chan->device); | |
1130 | struct at_desc *desc, *_desc; | |
1131 | LIST_HEAD(list); | |
1132 | ||
1133 | dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n", | |
1134 | atchan->descs_allocated); | |
1135 | ||
1136 | /* ASSERT: channel is idle */ | |
1137 | BUG_ON(!list_empty(&atchan->active_list)); | |
1138 | BUG_ON(!list_empty(&atchan->queue)); | |
1139 | BUG_ON(atc_chan_is_enabled(atchan)); | |
1140 | ||
1141 | list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { | |
1142 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); | |
1143 | list_del(&desc->desc_node); | |
1144 | /* free link descriptor */ | |
1145 | dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys); | |
1146 | } | |
1147 | list_splice_init(&atchan->free_list, &list); | |
1148 | atchan->descs_allocated = 0; | |
53830cc7 | 1149 | atchan->status = 0; |
dc78baa2 NF |
1150 | |
1151 | dev_vdbg(chan2dev(chan), "free_chan_resources: done\n"); | |
1152 | } | |
1153 | ||
1154 | ||
1155 | /*-- Module Management -----------------------------------------------*/ | |
1156 | ||
02f88be9 NF |
1157 | /* cap_mask is a multi-u32 bitfield, fill it with proper C code. */ |
1158 | static struct at_dma_platform_data at91sam9rl_config = { | |
1159 | .nr_channels = 2, | |
1160 | }; | |
1161 | static struct at_dma_platform_data at91sam9g45_config = { | |
1162 | .nr_channels = 8, | |
1163 | }; | |
1164 | ||
c5115953 NF |
1165 | #if defined(CONFIG_OF) |
1166 | static const struct of_device_id atmel_dma_dt_ids[] = { | |
1167 | { | |
1168 | .compatible = "atmel,at91sam9rl-dma", | |
02f88be9 | 1169 | .data = &at91sam9rl_config, |
c5115953 NF |
1170 | }, { |
1171 | .compatible = "atmel,at91sam9g45-dma", | |
02f88be9 | 1172 | .data = &at91sam9g45_config, |
dcc81734 NF |
1173 | }, { |
1174 | /* sentinel */ | |
1175 | } | |
c5115953 NF |
1176 | }; |
1177 | ||
1178 | MODULE_DEVICE_TABLE(of, atmel_dma_dt_ids); | |
1179 | #endif | |
1180 | ||
0ab88a01 | 1181 | static const struct platform_device_id atdma_devtypes[] = { |
67348450 NF |
1182 | { |
1183 | .name = "at91sam9rl_dma", | |
02f88be9 | 1184 | .driver_data = (unsigned long) &at91sam9rl_config, |
67348450 NF |
1185 | }, { |
1186 | .name = "at91sam9g45_dma", | |
02f88be9 | 1187 | .driver_data = (unsigned long) &at91sam9g45_config, |
67348450 NF |
1188 | }, { |
1189 | /* sentinel */ | |
1190 | } | |
1191 | }; | |
1192 | ||
02f88be9 NF |
1193 | static inline struct at_dma_platform_data * __init at_dma_get_driver_data( |
1194 | struct platform_device *pdev) | |
c5115953 NF |
1195 | { |
1196 | if (pdev->dev.of_node) { | |
1197 | const struct of_device_id *match; | |
1198 | match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node); | |
1199 | if (match == NULL) | |
02f88be9 NF |
1200 | return NULL; |
1201 | return match->data; | |
c5115953 | 1202 | } |
02f88be9 NF |
1203 | return (struct at_dma_platform_data *) |
1204 | platform_get_device_id(pdev)->driver_data; | |
c5115953 NF |
1205 | } |
1206 | ||
dc78baa2 NF |
1207 | /** |
1208 | * at_dma_off - disable DMA controller | |
1209 | * @atdma: the Atmel HDAMC device | |
1210 | */ | |
1211 | static void at_dma_off(struct at_dma *atdma) | |
1212 | { | |
1213 | dma_writel(atdma, EN, 0); | |
1214 | ||
1215 | /* disable all interrupts */ | |
1216 | dma_writel(atdma, EBCIDR, -1L); | |
1217 | ||
1218 | /* confirm that all channels are disabled */ | |
1219 | while (dma_readl(atdma, CHSR) & atdma->all_chan_mask) | |
1220 | cpu_relax(); | |
1221 | } | |
1222 | ||
1223 | static int __init at_dma_probe(struct platform_device *pdev) | |
1224 | { | |
dc78baa2 NF |
1225 | struct resource *io; |
1226 | struct at_dma *atdma; | |
1227 | size_t size; | |
1228 | int irq; | |
1229 | int err; | |
1230 | int i; | |
02f88be9 | 1231 | struct at_dma_platform_data *plat_dat; |
67348450 | 1232 | |
02f88be9 NF |
1233 | /* setup platform data for each SoC */ |
1234 | dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask); | |
1235 | dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask); | |
1236 | dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask); | |
67348450 NF |
1237 | |
1238 | /* get DMA parameters from controller type */ | |
02f88be9 NF |
1239 | plat_dat = at_dma_get_driver_data(pdev); |
1240 | if (!plat_dat) | |
1241 | return -ENODEV; | |
dc78baa2 NF |
1242 | |
1243 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1244 | if (!io) | |
1245 | return -EINVAL; | |
1246 | ||
1247 | irq = platform_get_irq(pdev, 0); | |
1248 | if (irq < 0) | |
1249 | return irq; | |
1250 | ||
1251 | size = sizeof(struct at_dma); | |
02f88be9 | 1252 | size += plat_dat->nr_channels * sizeof(struct at_dma_chan); |
dc78baa2 NF |
1253 | atdma = kzalloc(size, GFP_KERNEL); |
1254 | if (!atdma) | |
1255 | return -ENOMEM; | |
1256 | ||
67348450 | 1257 | /* discover transaction capabilities */ |
02f88be9 NF |
1258 | atdma->dma_common.cap_mask = plat_dat->cap_mask; |
1259 | atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1; | |
dc78baa2 | 1260 | |
114df7d6 | 1261 | size = resource_size(io); |
dc78baa2 NF |
1262 | if (!request_mem_region(io->start, size, pdev->dev.driver->name)) { |
1263 | err = -EBUSY; | |
1264 | goto err_kfree; | |
1265 | } | |
1266 | ||
1267 | atdma->regs = ioremap(io->start, size); | |
1268 | if (!atdma->regs) { | |
1269 | err = -ENOMEM; | |
1270 | goto err_release_r; | |
1271 | } | |
1272 | ||
1273 | atdma->clk = clk_get(&pdev->dev, "dma_clk"); | |
1274 | if (IS_ERR(atdma->clk)) { | |
1275 | err = PTR_ERR(atdma->clk); | |
1276 | goto err_clk; | |
1277 | } | |
1278 | clk_enable(atdma->clk); | |
1279 | ||
1280 | /* force dma off, just in case */ | |
1281 | at_dma_off(atdma); | |
1282 | ||
1283 | err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma); | |
1284 | if (err) | |
1285 | goto err_irq; | |
1286 | ||
1287 | platform_set_drvdata(pdev, atdma); | |
1288 | ||
1289 | /* create a pool of consistent memory blocks for hardware descriptors */ | |
1290 | atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool", | |
1291 | &pdev->dev, sizeof(struct at_desc), | |
1292 | 4 /* word alignment */, 0); | |
1293 | if (!atdma->dma_desc_pool) { | |
1294 | dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); | |
1295 | err = -ENOMEM; | |
1296 | goto err_pool_create; | |
1297 | } | |
1298 | ||
1299 | /* clear any pending interrupt */ | |
1300 | while (dma_readl(atdma, EBCISR)) | |
1301 | cpu_relax(); | |
1302 | ||
1303 | /* initialize channels related values */ | |
1304 | INIT_LIST_HEAD(&atdma->dma_common.channels); | |
02f88be9 | 1305 | for (i = 0; i < plat_dat->nr_channels; i++) { |
dc78baa2 NF |
1306 | struct at_dma_chan *atchan = &atdma->chan[i]; |
1307 | ||
1308 | atchan->chan_common.device = &atdma->dma_common; | |
d3ee98cd | 1309 | dma_cookie_init(&atchan->chan_common); |
dc78baa2 NF |
1310 | list_add_tail(&atchan->chan_common.device_node, |
1311 | &atdma->dma_common.channels); | |
1312 | ||
1313 | atchan->ch_regs = atdma->regs + ch_regs(i); | |
1314 | spin_lock_init(&atchan->lock); | |
1315 | atchan->mask = 1 << i; | |
1316 | ||
1317 | INIT_LIST_HEAD(&atchan->active_list); | |
1318 | INIT_LIST_HEAD(&atchan->queue); | |
1319 | INIT_LIST_HEAD(&atchan->free_list); | |
1320 | ||
1321 | tasklet_init(&atchan->tasklet, atc_tasklet, | |
1322 | (unsigned long)atchan); | |
bda3a47c | 1323 | atc_enable_chan_irq(atdma, i); |
dc78baa2 NF |
1324 | } |
1325 | ||
1326 | /* set base routines */ | |
1327 | atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources; | |
1328 | atdma->dma_common.device_free_chan_resources = atc_free_chan_resources; | |
07934481 | 1329 | atdma->dma_common.device_tx_status = atc_tx_status; |
dc78baa2 NF |
1330 | atdma->dma_common.device_issue_pending = atc_issue_pending; |
1331 | atdma->dma_common.dev = &pdev->dev; | |
1332 | ||
1333 | /* set prep routines based on capability */ | |
1334 | if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask)) | |
1335 | atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy; | |
1336 | ||
d7db8080 | 1337 | if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) { |
808347f6 | 1338 | atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg; |
d7db8080 NF |
1339 | /* controller can do slave DMA: can trigger cyclic transfers */ |
1340 | dma_cap_set(DMA_CYCLIC, atdma->dma_common.cap_mask); | |
53830cc7 | 1341 | atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic; |
c3635c78 | 1342 | atdma->dma_common.device_control = atc_control; |
d7db8080 | 1343 | } |
808347f6 | 1344 | |
dc78baa2 NF |
1345 | dma_writel(atdma, EN, AT_DMA_ENABLE); |
1346 | ||
1347 | dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s), %d channels\n", | |
1348 | dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "", | |
1349 | dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "", | |
02f88be9 | 1350 | plat_dat->nr_channels); |
dc78baa2 NF |
1351 | |
1352 | dma_async_device_register(&atdma->dma_common); | |
1353 | ||
1354 | return 0; | |
1355 | ||
1356 | err_pool_create: | |
1357 | platform_set_drvdata(pdev, NULL); | |
1358 | free_irq(platform_get_irq(pdev, 0), atdma); | |
1359 | err_irq: | |
1360 | clk_disable(atdma->clk); | |
1361 | clk_put(atdma->clk); | |
1362 | err_clk: | |
1363 | iounmap(atdma->regs); | |
1364 | atdma->regs = NULL; | |
1365 | err_release_r: | |
1366 | release_mem_region(io->start, size); | |
1367 | err_kfree: | |
1368 | kfree(atdma); | |
1369 | return err; | |
1370 | } | |
1371 | ||
1372 | static int __exit at_dma_remove(struct platform_device *pdev) | |
1373 | { | |
1374 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
1375 | struct dma_chan *chan, *_chan; | |
1376 | struct resource *io; | |
1377 | ||
1378 | at_dma_off(atdma); | |
1379 | dma_async_device_unregister(&atdma->dma_common); | |
1380 | ||
1381 | dma_pool_destroy(atdma->dma_desc_pool); | |
1382 | platform_set_drvdata(pdev, NULL); | |
1383 | free_irq(platform_get_irq(pdev, 0), atdma); | |
1384 | ||
1385 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1386 | device_node) { | |
1387 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1388 | ||
1389 | /* Disable interrupts */ | |
bda3a47c | 1390 | atc_disable_chan_irq(atdma, chan->chan_id); |
dc78baa2 NF |
1391 | tasklet_disable(&atchan->tasklet); |
1392 | ||
1393 | tasklet_kill(&atchan->tasklet); | |
1394 | list_del(&chan->device_node); | |
1395 | } | |
1396 | ||
1397 | clk_disable(atdma->clk); | |
1398 | clk_put(atdma->clk); | |
1399 | ||
1400 | iounmap(atdma->regs); | |
1401 | atdma->regs = NULL; | |
1402 | ||
1403 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
114df7d6 | 1404 | release_mem_region(io->start, resource_size(io)); |
dc78baa2 NF |
1405 | |
1406 | kfree(atdma); | |
1407 | ||
1408 | return 0; | |
1409 | } | |
1410 | ||
1411 | static void at_dma_shutdown(struct platform_device *pdev) | |
1412 | { | |
1413 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
1414 | ||
1415 | at_dma_off(platform_get_drvdata(pdev)); | |
1416 | clk_disable(atdma->clk); | |
1417 | } | |
1418 | ||
c0ba5947 NF |
1419 | static int at_dma_prepare(struct device *dev) |
1420 | { | |
1421 | struct platform_device *pdev = to_platform_device(dev); | |
1422 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
1423 | struct dma_chan *chan, *_chan; | |
1424 | ||
1425 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1426 | device_node) { | |
1427 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1428 | /* wait for transaction completion (except in cyclic case) */ | |
3c477482 | 1429 | if (atc_chan_is_enabled(atchan) && !atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
1430 | return -EAGAIN; |
1431 | } | |
1432 | return 0; | |
1433 | } | |
1434 | ||
1435 | static void atc_suspend_cyclic(struct at_dma_chan *atchan) | |
1436 | { | |
1437 | struct dma_chan *chan = &atchan->chan_common; | |
1438 | ||
1439 | /* Channel should be paused by user | |
1440 | * do it anyway even if it is not done already */ | |
3c477482 | 1441 | if (!atc_chan_is_paused(atchan)) { |
c0ba5947 NF |
1442 | dev_warn(chan2dev(chan), |
1443 | "cyclic channel not paused, should be done by channel user\n"); | |
1444 | atc_control(chan, DMA_PAUSE, 0); | |
1445 | } | |
1446 | ||
1447 | /* now preserve additional data for cyclic operations */ | |
1448 | /* next descriptor address in the cyclic list */ | |
1449 | atchan->save_dscr = channel_readl(atchan, DSCR); | |
1450 | ||
1451 | vdbg_dump_regs(atchan); | |
1452 | } | |
1453 | ||
33f82d14 | 1454 | static int at_dma_suspend_noirq(struct device *dev) |
dc78baa2 | 1455 | { |
33f82d14 DW |
1456 | struct platform_device *pdev = to_platform_device(dev); |
1457 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
c0ba5947 | 1458 | struct dma_chan *chan, *_chan; |
dc78baa2 | 1459 | |
c0ba5947 NF |
1460 | /* preserve data */ |
1461 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1462 | device_node) { | |
1463 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1464 | ||
3c477482 | 1465 | if (atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
1466 | atc_suspend_cyclic(atchan); |
1467 | atchan->save_cfg = channel_readl(atchan, CFG); | |
1468 | } | |
1469 | atdma->save_imr = dma_readl(atdma, EBCIMR); | |
1470 | ||
1471 | /* disable DMA controller */ | |
1472 | at_dma_off(atdma); | |
dc78baa2 NF |
1473 | clk_disable(atdma->clk); |
1474 | return 0; | |
1475 | } | |
1476 | ||
c0ba5947 NF |
1477 | static void atc_resume_cyclic(struct at_dma_chan *atchan) |
1478 | { | |
1479 | struct at_dma *atdma = to_at_dma(atchan->chan_common.device); | |
1480 | ||
1481 | /* restore channel status for cyclic descriptors list: | |
1482 | * next descriptor in the cyclic list at the time of suspend */ | |
1483 | channel_writel(atchan, SADDR, 0); | |
1484 | channel_writel(atchan, DADDR, 0); | |
1485 | channel_writel(atchan, CTRLA, 0); | |
1486 | channel_writel(atchan, CTRLB, 0); | |
1487 | channel_writel(atchan, DSCR, atchan->save_dscr); | |
1488 | dma_writel(atdma, CHER, atchan->mask); | |
1489 | ||
1490 | /* channel pause status should be removed by channel user | |
1491 | * We cannot take the initiative to do it here */ | |
1492 | ||
1493 | vdbg_dump_regs(atchan); | |
1494 | } | |
1495 | ||
33f82d14 | 1496 | static int at_dma_resume_noirq(struct device *dev) |
dc78baa2 | 1497 | { |
33f82d14 DW |
1498 | struct platform_device *pdev = to_platform_device(dev); |
1499 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
c0ba5947 | 1500 | struct dma_chan *chan, *_chan; |
dc78baa2 | 1501 | |
c0ba5947 | 1502 | /* bring back DMA controller */ |
dc78baa2 NF |
1503 | clk_enable(atdma->clk); |
1504 | dma_writel(atdma, EN, AT_DMA_ENABLE); | |
c0ba5947 NF |
1505 | |
1506 | /* clear any pending interrupt */ | |
1507 | while (dma_readl(atdma, EBCISR)) | |
1508 | cpu_relax(); | |
1509 | ||
1510 | /* restore saved data */ | |
1511 | dma_writel(atdma, EBCIER, atdma->save_imr); | |
1512 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1513 | device_node) { | |
1514 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1515 | ||
1516 | channel_writel(atchan, CFG, atchan->save_cfg); | |
3c477482 | 1517 | if (atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
1518 | atc_resume_cyclic(atchan); |
1519 | } | |
dc78baa2 | 1520 | return 0; |
dc78baa2 NF |
1521 | } |
1522 | ||
47145210 | 1523 | static const struct dev_pm_ops at_dma_dev_pm_ops = { |
c0ba5947 | 1524 | .prepare = at_dma_prepare, |
33f82d14 DW |
1525 | .suspend_noirq = at_dma_suspend_noirq, |
1526 | .resume_noirq = at_dma_resume_noirq, | |
1527 | }; | |
1528 | ||
dc78baa2 NF |
1529 | static struct platform_driver at_dma_driver = { |
1530 | .remove = __exit_p(at_dma_remove), | |
1531 | .shutdown = at_dma_shutdown, | |
67348450 | 1532 | .id_table = atdma_devtypes, |
dc78baa2 NF |
1533 | .driver = { |
1534 | .name = "at_hdmac", | |
33f82d14 | 1535 | .pm = &at_dma_dev_pm_ops, |
c5115953 | 1536 | .of_match_table = of_match_ptr(atmel_dma_dt_ids), |
dc78baa2 NF |
1537 | }, |
1538 | }; | |
1539 | ||
1540 | static int __init at_dma_init(void) | |
1541 | { | |
1542 | return platform_driver_probe(&at_dma_driver, at_dma_probe); | |
1543 | } | |
93d0bec2 | 1544 | subsys_initcall(at_dma_init); |
dc78baa2 NF |
1545 | |
1546 | static void __exit at_dma_exit(void) | |
1547 | { | |
1548 | platform_driver_unregister(&at_dma_driver); | |
1549 | } | |
1550 | module_exit(at_dma_exit); | |
1551 | ||
1552 | MODULE_DESCRIPTION("Atmel AHB DMA Controller driver"); | |
1553 | MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>"); | |
1554 | MODULE_LICENSE("GPL"); | |
1555 | MODULE_ALIAS("platform:at_hdmac"); |