Commit | Line | Data |
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dc78baa2 NF |
1 | /* |
2 | * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems) | |
3 | * | |
4 | * Copyright (C) 2008 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * | |
12 | * This supports the Atmel AHB DMA Controller, | |
13 | * | |
14 | * The driver has currently been tested with the Atmel AT91SAM9RL | |
15 | * and AT91SAM9G45 series. | |
16 | */ | |
17 | ||
18 | #include <linux/clk.h> | |
19 | #include <linux/dmaengine.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | #include <linux/dmapool.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
c5115953 NF |
26 | #include <linux/of.h> |
27 | #include <linux/of_device.h> | |
dc78baa2 NF |
28 | |
29 | #include "at_hdmac_regs.h" | |
d2ebfb33 | 30 | #include "dmaengine.h" |
dc78baa2 NF |
31 | |
32 | /* | |
33 | * Glossary | |
34 | * -------- | |
35 | * | |
36 | * at_hdmac : Name of the ATmel AHB DMA Controller | |
37 | * at_dma_ / atdma : ATmel DMA controller entity related | |
38 | * atc_ / atchan : ATmel DMA Channel entity related | |
39 | */ | |
40 | ||
41 | #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO) | |
42 | #define ATC_DEFAULT_CTRLA (0) | |
ae14d4b5 NF |
43 | #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \ |
44 | |ATC_DIF(AT_DMA_MEM_IF)) | |
dc78baa2 NF |
45 | |
46 | /* | |
47 | * Initial number of descriptors to allocate for each channel. This could | |
48 | * be increased during dma usage. | |
49 | */ | |
50 | static unsigned int init_nr_desc_per_channel = 64; | |
51 | module_param(init_nr_desc_per_channel, uint, 0644); | |
52 | MODULE_PARM_DESC(init_nr_desc_per_channel, | |
53 | "initial descriptors per channel (default: 64)"); | |
54 | ||
55 | ||
56 | /* prototypes */ | |
57 | static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx); | |
58 | ||
59 | ||
60 | /*----------------------------------------------------------------------*/ | |
61 | ||
62 | static struct at_desc *atc_first_active(struct at_dma_chan *atchan) | |
63 | { | |
64 | return list_first_entry(&atchan->active_list, | |
65 | struct at_desc, desc_node); | |
66 | } | |
67 | ||
68 | static struct at_desc *atc_first_queued(struct at_dma_chan *atchan) | |
69 | { | |
70 | return list_first_entry(&atchan->queue, | |
71 | struct at_desc, desc_node); | |
72 | } | |
73 | ||
74 | /** | |
421f91d2 | 75 | * atc_alloc_descriptor - allocate and return an initialized descriptor |
dc78baa2 NF |
76 | * @chan: the channel to allocate descriptors for |
77 | * @gfp_flags: GFP allocation flags | |
78 | * | |
79 | * Note: The ack-bit is positioned in the descriptor flag at creation time | |
80 | * to make initial allocation more convenient. This bit will be cleared | |
81 | * and control will be given to client at usage time (during | |
82 | * preparation functions). | |
83 | */ | |
84 | static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan, | |
85 | gfp_t gfp_flags) | |
86 | { | |
87 | struct at_desc *desc = NULL; | |
88 | struct at_dma *atdma = to_at_dma(chan->device); | |
89 | dma_addr_t phys; | |
90 | ||
91 | desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys); | |
92 | if (desc) { | |
93 | memset(desc, 0, sizeof(struct at_desc)); | |
285a3c71 | 94 | INIT_LIST_HEAD(&desc->tx_list); |
dc78baa2 NF |
95 | dma_async_tx_descriptor_init(&desc->txd, chan); |
96 | /* txd.flags will be overwritten in prep functions */ | |
97 | desc->txd.flags = DMA_CTRL_ACK; | |
98 | desc->txd.tx_submit = atc_tx_submit; | |
99 | desc->txd.phys = phys; | |
100 | } | |
101 | ||
102 | return desc; | |
103 | } | |
104 | ||
105 | /** | |
af901ca1 | 106 | * atc_desc_get - get an unused descriptor from free_list |
dc78baa2 NF |
107 | * @atchan: channel we want a new descriptor for |
108 | */ | |
109 | static struct at_desc *atc_desc_get(struct at_dma_chan *atchan) | |
110 | { | |
111 | struct at_desc *desc, *_desc; | |
112 | struct at_desc *ret = NULL; | |
d8cb04b0 | 113 | unsigned long flags; |
dc78baa2 NF |
114 | unsigned int i = 0; |
115 | LIST_HEAD(tmp_list); | |
116 | ||
d8cb04b0 | 117 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 NF |
118 | list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { |
119 | i++; | |
120 | if (async_tx_test_ack(&desc->txd)) { | |
121 | list_del(&desc->desc_node); | |
122 | ret = desc; | |
123 | break; | |
124 | } | |
125 | dev_dbg(chan2dev(&atchan->chan_common), | |
126 | "desc %p not ACKed\n", desc); | |
127 | } | |
d8cb04b0 | 128 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
129 | dev_vdbg(chan2dev(&atchan->chan_common), |
130 | "scanned %u descriptors on freelist\n", i); | |
131 | ||
132 | /* no more descriptor available in initial pool: create one more */ | |
133 | if (!ret) { | |
134 | ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC); | |
135 | if (ret) { | |
d8cb04b0 | 136 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 | 137 | atchan->descs_allocated++; |
d8cb04b0 | 138 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
139 | } else { |
140 | dev_err(chan2dev(&atchan->chan_common), | |
141 | "not enough descriptors available\n"); | |
142 | } | |
143 | } | |
144 | ||
145 | return ret; | |
146 | } | |
147 | ||
148 | /** | |
149 | * atc_desc_put - move a descriptor, including any children, to the free list | |
150 | * @atchan: channel we work on | |
151 | * @desc: descriptor, at the head of a chain, to move to free list | |
152 | */ | |
153 | static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc) | |
154 | { | |
155 | if (desc) { | |
156 | struct at_desc *child; | |
d8cb04b0 | 157 | unsigned long flags; |
dc78baa2 | 158 | |
d8cb04b0 | 159 | spin_lock_irqsave(&atchan->lock, flags); |
285a3c71 | 160 | list_for_each_entry(child, &desc->tx_list, desc_node) |
dc78baa2 NF |
161 | dev_vdbg(chan2dev(&atchan->chan_common), |
162 | "moving child desc %p to freelist\n", | |
163 | child); | |
285a3c71 | 164 | list_splice_init(&desc->tx_list, &atchan->free_list); |
dc78baa2 NF |
165 | dev_vdbg(chan2dev(&atchan->chan_common), |
166 | "moving desc %p to freelist\n", desc); | |
167 | list_add(&desc->desc_node, &atchan->free_list); | |
d8cb04b0 | 168 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
169 | } |
170 | } | |
171 | ||
53830cc7 NF |
172 | /** |
173 | * atc_desc_chain - build chain adding a descripor | |
174 | * @first: address of first descripor of the chain | |
175 | * @prev: address of previous descripor of the chain | |
176 | * @desc: descriptor to queue | |
177 | * | |
178 | * Called from prep_* functions | |
179 | */ | |
180 | static void atc_desc_chain(struct at_desc **first, struct at_desc **prev, | |
181 | struct at_desc *desc) | |
182 | { | |
183 | if (!(*first)) { | |
184 | *first = desc; | |
185 | } else { | |
186 | /* inform the HW lli about chaining */ | |
187 | (*prev)->lli.dscr = desc->txd.phys; | |
188 | /* insert the link descriptor to the LD ring */ | |
189 | list_add_tail(&desc->desc_node, | |
190 | &(*first)->tx_list); | |
191 | } | |
192 | *prev = desc; | |
193 | } | |
194 | ||
dc78baa2 NF |
195 | /** |
196 | * atc_assign_cookie - compute and assign new cookie | |
197 | * @atchan: channel we work on | |
25985edc | 198 | * @desc: descriptor to assign cookie for |
dc78baa2 NF |
199 | * |
200 | * Called with atchan->lock held and bh disabled | |
201 | */ | |
202 | static dma_cookie_t | |
203 | atc_assign_cookie(struct at_dma_chan *atchan, struct at_desc *desc) | |
204 | { | |
205 | dma_cookie_t cookie = atchan->chan_common.cookie; | |
206 | ||
207 | if (++cookie < 0) | |
208 | cookie = 1; | |
209 | ||
210 | atchan->chan_common.cookie = cookie; | |
211 | desc->txd.cookie = cookie; | |
212 | ||
213 | return cookie; | |
214 | } | |
215 | ||
216 | /** | |
217 | * atc_dostart - starts the DMA engine for real | |
218 | * @atchan: the channel we want to start | |
219 | * @first: first descriptor in the list we want to begin with | |
220 | * | |
221 | * Called with atchan->lock held and bh disabled | |
222 | */ | |
223 | static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first) | |
224 | { | |
225 | struct at_dma *atdma = to_at_dma(atchan->chan_common.device); | |
226 | ||
227 | /* ASSERT: channel is idle */ | |
228 | if (atc_chan_is_enabled(atchan)) { | |
229 | dev_err(chan2dev(&atchan->chan_common), | |
230 | "BUG: Attempted to start non-idle channel\n"); | |
231 | dev_err(chan2dev(&atchan->chan_common), | |
232 | " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n", | |
233 | channel_readl(atchan, SADDR), | |
234 | channel_readl(atchan, DADDR), | |
235 | channel_readl(atchan, CTRLA), | |
236 | channel_readl(atchan, CTRLB), | |
237 | channel_readl(atchan, DSCR)); | |
238 | ||
239 | /* The tasklet will hopefully advance the queue... */ | |
240 | return; | |
241 | } | |
242 | ||
243 | vdbg_dump_regs(atchan); | |
244 | ||
245 | /* clear any pending interrupt */ | |
246 | while (dma_readl(atdma, EBCISR)) | |
247 | cpu_relax(); | |
248 | ||
249 | channel_writel(atchan, SADDR, 0); | |
250 | channel_writel(atchan, DADDR, 0); | |
251 | channel_writel(atchan, CTRLA, 0); | |
252 | channel_writel(atchan, CTRLB, 0); | |
253 | channel_writel(atchan, DSCR, first->txd.phys); | |
254 | dma_writel(atdma, CHER, atchan->mask); | |
255 | ||
256 | vdbg_dump_regs(atchan); | |
257 | } | |
258 | ||
259 | /** | |
260 | * atc_chain_complete - finish work for one transaction chain | |
261 | * @atchan: channel we work on | |
262 | * @desc: descriptor at the head of the chain we want do complete | |
263 | * | |
264 | * Called with atchan->lock held and bh disabled */ | |
265 | static void | |
266 | atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) | |
267 | { | |
dc78baa2 NF |
268 | struct dma_async_tx_descriptor *txd = &desc->txd; |
269 | ||
270 | dev_vdbg(chan2dev(&atchan->chan_common), | |
271 | "descriptor %u complete\n", txd->cookie); | |
272 | ||
4d4e58de | 273 | atchan->chan_common.completed_cookie = txd->cookie; |
dc78baa2 NF |
274 | |
275 | /* move children to free_list */ | |
285a3c71 | 276 | list_splice_init(&desc->tx_list, &atchan->free_list); |
dc78baa2 NF |
277 | /* move myself to free_list */ |
278 | list_move(&desc->desc_node, &atchan->free_list); | |
279 | ||
ebcf9b80 | 280 | /* unmap dma addresses (not on slave channels) */ |
657a77fa AN |
281 | if (!atchan->chan_common.private) { |
282 | struct device *parent = chan2parent(&atchan->chan_common); | |
283 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
284 | if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
285 | dma_unmap_single(parent, | |
286 | desc->lli.daddr, | |
287 | desc->len, DMA_FROM_DEVICE); | |
288 | else | |
289 | dma_unmap_page(parent, | |
290 | desc->lli.daddr, | |
291 | desc->len, DMA_FROM_DEVICE); | |
292 | } | |
293 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
294 | if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
295 | dma_unmap_single(parent, | |
296 | desc->lli.saddr, | |
297 | desc->len, DMA_TO_DEVICE); | |
298 | else | |
299 | dma_unmap_page(parent, | |
300 | desc->lli.saddr, | |
301 | desc->len, DMA_TO_DEVICE); | |
302 | } | |
dc78baa2 NF |
303 | } |
304 | ||
53830cc7 NF |
305 | /* for cyclic transfers, |
306 | * no need to replay callback function while stopping */ | |
3c477482 | 307 | if (!atc_chan_is_cyclic(atchan)) { |
53830cc7 NF |
308 | dma_async_tx_callback callback = txd->callback; |
309 | void *param = txd->callback_param; | |
310 | ||
311 | /* | |
312 | * The API requires that no submissions are done from a | |
313 | * callback, so we don't need to drop the lock here | |
314 | */ | |
315 | if (callback) | |
316 | callback(param); | |
317 | } | |
dc78baa2 NF |
318 | |
319 | dma_run_dependencies(txd); | |
320 | } | |
321 | ||
322 | /** | |
323 | * atc_complete_all - finish work for all transactions | |
324 | * @atchan: channel to complete transactions for | |
325 | * | |
326 | * Eventually submit queued descriptors if any | |
327 | * | |
328 | * Assume channel is idle while calling this function | |
329 | * Called with atchan->lock held and bh disabled | |
330 | */ | |
331 | static void atc_complete_all(struct at_dma_chan *atchan) | |
332 | { | |
333 | struct at_desc *desc, *_desc; | |
334 | LIST_HEAD(list); | |
335 | ||
336 | dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n"); | |
337 | ||
338 | BUG_ON(atc_chan_is_enabled(atchan)); | |
339 | ||
340 | /* | |
341 | * Submit queued descriptors ASAP, i.e. before we go through | |
342 | * the completed ones. | |
343 | */ | |
344 | if (!list_empty(&atchan->queue)) | |
345 | atc_dostart(atchan, atc_first_queued(atchan)); | |
346 | /* empty active_list now it is completed */ | |
347 | list_splice_init(&atchan->active_list, &list); | |
348 | /* empty queue list by moving descriptors (if any) to active_list */ | |
349 | list_splice_init(&atchan->queue, &atchan->active_list); | |
350 | ||
351 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
352 | atc_chain_complete(atchan, desc); | |
353 | } | |
354 | ||
355 | /** | |
356 | * atc_cleanup_descriptors - cleanup up finished descriptors in active_list | |
357 | * @atchan: channel to be cleaned up | |
358 | * | |
359 | * Called with atchan->lock held and bh disabled | |
360 | */ | |
361 | static void atc_cleanup_descriptors(struct at_dma_chan *atchan) | |
362 | { | |
363 | struct at_desc *desc, *_desc; | |
364 | struct at_desc *child; | |
365 | ||
366 | dev_vdbg(chan2dev(&atchan->chan_common), "cleanup descriptors\n"); | |
367 | ||
368 | list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) { | |
369 | if (!(desc->lli.ctrla & ATC_DONE)) | |
370 | /* This one is currently in progress */ | |
371 | return; | |
372 | ||
285a3c71 | 373 | list_for_each_entry(child, &desc->tx_list, desc_node) |
dc78baa2 NF |
374 | if (!(child->lli.ctrla & ATC_DONE)) |
375 | /* Currently in progress */ | |
376 | return; | |
377 | ||
378 | /* | |
379 | * No descriptors so far seem to be in progress, i.e. | |
380 | * this chain must be done. | |
381 | */ | |
382 | atc_chain_complete(atchan, desc); | |
383 | } | |
384 | } | |
385 | ||
386 | /** | |
387 | * atc_advance_work - at the end of a transaction, move forward | |
388 | * @atchan: channel where the transaction ended | |
389 | * | |
390 | * Called with atchan->lock held and bh disabled | |
391 | */ | |
392 | static void atc_advance_work(struct at_dma_chan *atchan) | |
393 | { | |
394 | dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n"); | |
395 | ||
396 | if (list_empty(&atchan->active_list) || | |
397 | list_is_singular(&atchan->active_list)) { | |
398 | atc_complete_all(atchan); | |
399 | } else { | |
400 | atc_chain_complete(atchan, atc_first_active(atchan)); | |
401 | /* advance work */ | |
402 | atc_dostart(atchan, atc_first_active(atchan)); | |
403 | } | |
404 | } | |
405 | ||
406 | ||
407 | /** | |
408 | * atc_handle_error - handle errors reported by DMA controller | |
409 | * @atchan: channel where error occurs | |
410 | * | |
411 | * Called with atchan->lock held and bh disabled | |
412 | */ | |
413 | static void atc_handle_error(struct at_dma_chan *atchan) | |
414 | { | |
415 | struct at_desc *bad_desc; | |
416 | struct at_desc *child; | |
417 | ||
418 | /* | |
419 | * The descriptor currently at the head of the active list is | |
420 | * broked. Since we don't have any way to report errors, we'll | |
421 | * just have to scream loudly and try to carry on. | |
422 | */ | |
423 | bad_desc = atc_first_active(atchan); | |
424 | list_del_init(&bad_desc->desc_node); | |
425 | ||
426 | /* As we are stopped, take advantage to push queued descriptors | |
427 | * in active_list */ | |
428 | list_splice_init(&atchan->queue, atchan->active_list.prev); | |
429 | ||
430 | /* Try to restart the controller */ | |
431 | if (!list_empty(&atchan->active_list)) | |
432 | atc_dostart(atchan, atc_first_active(atchan)); | |
433 | ||
434 | /* | |
435 | * KERN_CRITICAL may seem harsh, but since this only happens | |
436 | * when someone submits a bad physical address in a | |
437 | * descriptor, we should consider ourselves lucky that the | |
438 | * controller flagged an error instead of scribbling over | |
439 | * random memory locations. | |
440 | */ | |
441 | dev_crit(chan2dev(&atchan->chan_common), | |
442 | "Bad descriptor submitted for DMA!\n"); | |
443 | dev_crit(chan2dev(&atchan->chan_common), | |
444 | " cookie: %d\n", bad_desc->txd.cookie); | |
445 | atc_dump_lli(atchan, &bad_desc->lli); | |
285a3c71 | 446 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
dc78baa2 NF |
447 | atc_dump_lli(atchan, &child->lli); |
448 | ||
449 | /* Pretend the descriptor completed successfully */ | |
450 | atc_chain_complete(atchan, bad_desc); | |
451 | } | |
452 | ||
53830cc7 NF |
453 | /** |
454 | * atc_handle_cyclic - at the end of a period, run callback function | |
455 | * @atchan: channel used for cyclic operations | |
456 | * | |
457 | * Called with atchan->lock held and bh disabled | |
458 | */ | |
459 | static void atc_handle_cyclic(struct at_dma_chan *atchan) | |
460 | { | |
461 | struct at_desc *first = atc_first_active(atchan); | |
462 | struct dma_async_tx_descriptor *txd = &first->txd; | |
463 | dma_async_tx_callback callback = txd->callback; | |
464 | void *param = txd->callback_param; | |
465 | ||
466 | dev_vdbg(chan2dev(&atchan->chan_common), | |
467 | "new cyclic period llp 0x%08x\n", | |
468 | channel_readl(atchan, DSCR)); | |
469 | ||
470 | if (callback) | |
471 | callback(param); | |
472 | } | |
dc78baa2 NF |
473 | |
474 | /*-- IRQ & Tasklet ---------------------------------------------------*/ | |
475 | ||
476 | static void atc_tasklet(unsigned long data) | |
477 | { | |
478 | struct at_dma_chan *atchan = (struct at_dma_chan *)data; | |
d8cb04b0 | 479 | unsigned long flags; |
dc78baa2 | 480 | |
d8cb04b0 | 481 | spin_lock_irqsave(&atchan->lock, flags); |
53830cc7 | 482 | if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status)) |
dc78baa2 | 483 | atc_handle_error(atchan); |
3c477482 | 484 | else if (atc_chan_is_cyclic(atchan)) |
53830cc7 | 485 | atc_handle_cyclic(atchan); |
dc78baa2 NF |
486 | else |
487 | atc_advance_work(atchan); | |
488 | ||
d8cb04b0 | 489 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
490 | } |
491 | ||
492 | static irqreturn_t at_dma_interrupt(int irq, void *dev_id) | |
493 | { | |
494 | struct at_dma *atdma = (struct at_dma *)dev_id; | |
495 | struct at_dma_chan *atchan; | |
496 | int i; | |
497 | u32 status, pending, imr; | |
498 | int ret = IRQ_NONE; | |
499 | ||
500 | do { | |
501 | imr = dma_readl(atdma, EBCIMR); | |
502 | status = dma_readl(atdma, EBCISR); | |
503 | pending = status & imr; | |
504 | ||
505 | if (!pending) | |
506 | break; | |
507 | ||
508 | dev_vdbg(atdma->dma_common.dev, | |
509 | "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n", | |
510 | status, imr, pending); | |
511 | ||
512 | for (i = 0; i < atdma->dma_common.chancnt; i++) { | |
513 | atchan = &atdma->chan[i]; | |
9b3aa589 | 514 | if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) { |
dc78baa2 NF |
515 | if (pending & AT_DMA_ERR(i)) { |
516 | /* Disable channel on AHB error */ | |
23b5e3ad NF |
517 | dma_writel(atdma, CHDR, |
518 | AT_DMA_RES(i) | atchan->mask); | |
dc78baa2 | 519 | /* Give information to tasklet */ |
53830cc7 | 520 | set_bit(ATC_IS_ERROR, &atchan->status); |
dc78baa2 NF |
521 | } |
522 | tasklet_schedule(&atchan->tasklet); | |
523 | ret = IRQ_HANDLED; | |
524 | } | |
525 | } | |
526 | ||
527 | } while (pending); | |
528 | ||
529 | return ret; | |
530 | } | |
531 | ||
532 | ||
533 | /*-- DMA Engine API --------------------------------------------------*/ | |
534 | ||
535 | /** | |
536 | * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine | |
537 | * @desc: descriptor at the head of the transaction chain | |
538 | * | |
539 | * Queue chain if DMA engine is working already | |
540 | * | |
541 | * Cookie increment and adding to active_list or queue must be atomic | |
542 | */ | |
543 | static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx) | |
544 | { | |
545 | struct at_desc *desc = txd_to_at_desc(tx); | |
546 | struct at_dma_chan *atchan = to_at_dma_chan(tx->chan); | |
547 | dma_cookie_t cookie; | |
d8cb04b0 | 548 | unsigned long flags; |
dc78baa2 | 549 | |
d8cb04b0 | 550 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 NF |
551 | cookie = atc_assign_cookie(atchan, desc); |
552 | ||
553 | if (list_empty(&atchan->active_list)) { | |
554 | dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", | |
555 | desc->txd.cookie); | |
556 | atc_dostart(atchan, desc); | |
557 | list_add_tail(&desc->desc_node, &atchan->active_list); | |
558 | } else { | |
559 | dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", | |
560 | desc->txd.cookie); | |
561 | list_add_tail(&desc->desc_node, &atchan->queue); | |
562 | } | |
563 | ||
d8cb04b0 | 564 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
565 | |
566 | return cookie; | |
567 | } | |
568 | ||
569 | /** | |
570 | * atc_prep_dma_memcpy - prepare a memcpy operation | |
571 | * @chan: the channel to prepare operation on | |
572 | * @dest: operation virtual destination address | |
573 | * @src: operation virtual source address | |
574 | * @len: operation length | |
575 | * @flags: tx descriptor status flags | |
576 | */ | |
577 | static struct dma_async_tx_descriptor * | |
578 | atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
579 | size_t len, unsigned long flags) | |
580 | { | |
581 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
582 | struct at_desc *desc = NULL; | |
583 | struct at_desc *first = NULL; | |
584 | struct at_desc *prev = NULL; | |
585 | size_t xfer_count; | |
586 | size_t offset; | |
587 | unsigned int src_width; | |
588 | unsigned int dst_width; | |
589 | u32 ctrla; | |
590 | u32 ctrlb; | |
591 | ||
592 | dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n", | |
593 | dest, src, len, flags); | |
594 | ||
595 | if (unlikely(!len)) { | |
596 | dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); | |
597 | return NULL; | |
598 | } | |
599 | ||
600 | ctrla = ATC_DEFAULT_CTRLA; | |
9b3aa589 | 601 | ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN |
dc78baa2 NF |
602 | | ATC_SRC_ADDR_MODE_INCR |
603 | | ATC_DST_ADDR_MODE_INCR | |
604 | | ATC_FC_MEM2MEM; | |
605 | ||
606 | /* | |
607 | * We can be a lot more clever here, but this should take care | |
608 | * of the most common optimization. | |
609 | */ | |
610 | if (!((src | dest | len) & 3)) { | |
611 | ctrla |= ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD; | |
612 | src_width = dst_width = 2; | |
613 | } else if (!((src | dest | len) & 1)) { | |
614 | ctrla |= ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD; | |
615 | src_width = dst_width = 1; | |
616 | } else { | |
617 | ctrla |= ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE; | |
618 | src_width = dst_width = 0; | |
619 | } | |
620 | ||
621 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
622 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
623 | ATC_BTSIZE_MAX); | |
624 | ||
625 | desc = atc_desc_get(atchan); | |
626 | if (!desc) | |
627 | goto err_desc_get; | |
628 | ||
629 | desc->lli.saddr = src + offset; | |
630 | desc->lli.daddr = dest + offset; | |
631 | desc->lli.ctrla = ctrla | xfer_count; | |
632 | desc->lli.ctrlb = ctrlb; | |
633 | ||
634 | desc->txd.cookie = 0; | |
dc78baa2 | 635 | |
e257e156 | 636 | atc_desc_chain(&first, &prev, desc); |
dc78baa2 NF |
637 | } |
638 | ||
639 | /* First descriptor of the chain embedds additional information */ | |
640 | first->txd.cookie = -EBUSY; | |
641 | first->len = len; | |
642 | ||
643 | /* set end-of-link to the last link descriptor of list*/ | |
644 | set_desc_eol(desc); | |
645 | ||
568f7f0c | 646 | first->txd.flags = flags; /* client is in control of this ack */ |
dc78baa2 NF |
647 | |
648 | return &first->txd; | |
649 | ||
650 | err_desc_get: | |
651 | atc_desc_put(atchan, first); | |
652 | return NULL; | |
653 | } | |
654 | ||
808347f6 NF |
655 | |
656 | /** | |
657 | * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
658 | * @chan: DMA channel | |
659 | * @sgl: scatterlist to transfer to/from | |
660 | * @sg_len: number of entries in @scatterlist | |
661 | * @direction: DMA direction | |
662 | * @flags: tx descriptor status flags | |
663 | */ | |
664 | static struct dma_async_tx_descriptor * | |
665 | atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 666 | unsigned int sg_len, enum dma_transfer_direction direction, |
808347f6 NF |
667 | unsigned long flags) |
668 | { | |
669 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
670 | struct at_dma_slave *atslave = chan->private; | |
671 | struct at_desc *first = NULL; | |
672 | struct at_desc *prev = NULL; | |
673 | u32 ctrla; | |
674 | u32 ctrlb; | |
675 | dma_addr_t reg; | |
676 | unsigned int reg_width; | |
677 | unsigned int mem_width; | |
678 | unsigned int i; | |
679 | struct scatterlist *sg; | |
680 | size_t total_len = 0; | |
681 | ||
cc52a10a NF |
682 | dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n", |
683 | sg_len, | |
db8196df | 684 | direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", |
808347f6 NF |
685 | flags); |
686 | ||
687 | if (unlikely(!atslave || !sg_len)) { | |
688 | dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); | |
689 | return NULL; | |
690 | } | |
691 | ||
692 | reg_width = atslave->reg_width; | |
693 | ||
808347f6 | 694 | ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla; |
ae14d4b5 | 695 | ctrlb = ATC_IEN; |
808347f6 NF |
696 | |
697 | switch (direction) { | |
db8196df | 698 | case DMA_MEM_TO_DEV: |
808347f6 NF |
699 | ctrla |= ATC_DST_WIDTH(reg_width); |
700 | ctrlb |= ATC_DST_ADDR_MODE_FIXED | |
701 | | ATC_SRC_ADDR_MODE_INCR | |
ae14d4b5 NF |
702 | | ATC_FC_MEM2PER |
703 | | ATC_SIF(AT_DMA_MEM_IF) | ATC_DIF(AT_DMA_PER_IF); | |
808347f6 NF |
704 | reg = atslave->tx_reg; |
705 | for_each_sg(sgl, sg, sg_len, i) { | |
706 | struct at_desc *desc; | |
707 | u32 len; | |
708 | u32 mem; | |
709 | ||
710 | desc = atc_desc_get(atchan); | |
711 | if (!desc) | |
712 | goto err_desc_get; | |
713 | ||
0f70e8ce | 714 | mem = sg_dma_address(sg); |
808347f6 NF |
715 | len = sg_dma_len(sg); |
716 | mem_width = 2; | |
717 | if (unlikely(mem & 3 || len & 3)) | |
718 | mem_width = 0; | |
719 | ||
720 | desc->lli.saddr = mem; | |
721 | desc->lli.daddr = reg; | |
722 | desc->lli.ctrla = ctrla | |
723 | | ATC_SRC_WIDTH(mem_width) | |
724 | | len >> mem_width; | |
725 | desc->lli.ctrlb = ctrlb; | |
726 | ||
e257e156 | 727 | atc_desc_chain(&first, &prev, desc); |
808347f6 NF |
728 | total_len += len; |
729 | } | |
730 | break; | |
db8196df | 731 | case DMA_DEV_TO_MEM: |
808347f6 NF |
732 | ctrla |= ATC_SRC_WIDTH(reg_width); |
733 | ctrlb |= ATC_DST_ADDR_MODE_INCR | |
734 | | ATC_SRC_ADDR_MODE_FIXED | |
ae14d4b5 NF |
735 | | ATC_FC_PER2MEM |
736 | | ATC_SIF(AT_DMA_PER_IF) | ATC_DIF(AT_DMA_MEM_IF); | |
808347f6 NF |
737 | |
738 | reg = atslave->rx_reg; | |
739 | for_each_sg(sgl, sg, sg_len, i) { | |
740 | struct at_desc *desc; | |
741 | u32 len; | |
742 | u32 mem; | |
743 | ||
744 | desc = atc_desc_get(atchan); | |
745 | if (!desc) | |
746 | goto err_desc_get; | |
747 | ||
0f70e8ce | 748 | mem = sg_dma_address(sg); |
808347f6 NF |
749 | len = sg_dma_len(sg); |
750 | mem_width = 2; | |
751 | if (unlikely(mem & 3 || len & 3)) | |
752 | mem_width = 0; | |
753 | ||
754 | desc->lli.saddr = reg; | |
755 | desc->lli.daddr = mem; | |
756 | desc->lli.ctrla = ctrla | |
757 | | ATC_DST_WIDTH(mem_width) | |
59a609d9 | 758 | | len >> reg_width; |
808347f6 NF |
759 | desc->lli.ctrlb = ctrlb; |
760 | ||
e257e156 | 761 | atc_desc_chain(&first, &prev, desc); |
808347f6 NF |
762 | total_len += len; |
763 | } | |
764 | break; | |
765 | default: | |
766 | return NULL; | |
767 | } | |
768 | ||
769 | /* set end-of-link to the last link descriptor of list*/ | |
770 | set_desc_eol(prev); | |
771 | ||
772 | /* First descriptor of the chain embedds additional information */ | |
773 | first->txd.cookie = -EBUSY; | |
774 | first->len = total_len; | |
775 | ||
568f7f0c NF |
776 | /* first link descriptor of list is responsible of flags */ |
777 | first->txd.flags = flags; /* client is in control of this ack */ | |
808347f6 NF |
778 | |
779 | return &first->txd; | |
780 | ||
781 | err_desc_get: | |
782 | dev_err(chan2dev(chan), "not enough descriptors available\n"); | |
783 | atc_desc_put(atchan, first); | |
784 | return NULL; | |
785 | } | |
786 | ||
53830cc7 NF |
787 | /** |
788 | * atc_dma_cyclic_check_values | |
789 | * Check for too big/unaligned periods and unaligned DMA buffer | |
790 | */ | |
791 | static int | |
792 | atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr, | |
db8196df | 793 | size_t period_len, enum dma_transfer_direction direction) |
53830cc7 NF |
794 | { |
795 | if (period_len > (ATC_BTSIZE_MAX << reg_width)) | |
796 | goto err_out; | |
797 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
798 | goto err_out; | |
799 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
800 | goto err_out; | |
db8196df | 801 | if (unlikely(!(direction & (DMA_DEV_TO_MEM | DMA_MEM_TO_DEV)))) |
53830cc7 NF |
802 | goto err_out; |
803 | ||
804 | return 0; | |
805 | ||
806 | err_out: | |
807 | return -EINVAL; | |
808 | } | |
809 | ||
810 | /** | |
811 | * atc_dma_cyclic_fill_desc - Fill one period decriptor | |
812 | */ | |
813 | static int | |
814 | atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc, | |
815 | unsigned int period_index, dma_addr_t buf_addr, | |
db8196df | 816 | size_t period_len, enum dma_transfer_direction direction) |
53830cc7 NF |
817 | { |
818 | u32 ctrla; | |
819 | unsigned int reg_width = atslave->reg_width; | |
820 | ||
821 | /* prepare common CRTLA value */ | |
822 | ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla | |
823 | | ATC_DST_WIDTH(reg_width) | |
824 | | ATC_SRC_WIDTH(reg_width) | |
825 | | period_len >> reg_width; | |
826 | ||
827 | switch (direction) { | |
db8196df | 828 | case DMA_MEM_TO_DEV: |
53830cc7 NF |
829 | desc->lli.saddr = buf_addr + (period_len * period_index); |
830 | desc->lli.daddr = atslave->tx_reg; | |
831 | desc->lli.ctrla = ctrla; | |
ae14d4b5 | 832 | desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED |
53830cc7 | 833 | | ATC_SRC_ADDR_MODE_INCR |
ae14d4b5 NF |
834 | | ATC_FC_MEM2PER |
835 | | ATC_SIF(AT_DMA_MEM_IF) | |
836 | | ATC_DIF(AT_DMA_PER_IF); | |
53830cc7 NF |
837 | break; |
838 | ||
db8196df | 839 | case DMA_DEV_TO_MEM: |
53830cc7 NF |
840 | desc->lli.saddr = atslave->rx_reg; |
841 | desc->lli.daddr = buf_addr + (period_len * period_index); | |
842 | desc->lli.ctrla = ctrla; | |
ae14d4b5 | 843 | desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR |
53830cc7 | 844 | | ATC_SRC_ADDR_MODE_FIXED |
ae14d4b5 NF |
845 | | ATC_FC_PER2MEM |
846 | | ATC_SIF(AT_DMA_PER_IF) | |
847 | | ATC_DIF(AT_DMA_MEM_IF); | |
53830cc7 NF |
848 | break; |
849 | ||
850 | default: | |
851 | return -EINVAL; | |
852 | } | |
853 | ||
854 | return 0; | |
855 | } | |
856 | ||
857 | /** | |
858 | * atc_prep_dma_cyclic - prepare the cyclic DMA transfer | |
859 | * @chan: the DMA channel to prepare | |
860 | * @buf_addr: physical DMA address where the buffer starts | |
861 | * @buf_len: total number of bytes for the entire buffer | |
862 | * @period_len: number of bytes for each period | |
863 | * @direction: transfer direction, to or from device | |
864 | */ | |
865 | static struct dma_async_tx_descriptor * | |
866 | atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
db8196df | 867 | size_t period_len, enum dma_transfer_direction direction) |
53830cc7 NF |
868 | { |
869 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
870 | struct at_dma_slave *atslave = chan->private; | |
871 | struct at_desc *first = NULL; | |
872 | struct at_desc *prev = NULL; | |
873 | unsigned long was_cyclic; | |
874 | unsigned int periods = buf_len / period_len; | |
875 | unsigned int i; | |
876 | ||
877 | dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n", | |
db8196df | 878 | direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", |
53830cc7 NF |
879 | buf_addr, |
880 | periods, buf_len, period_len); | |
881 | ||
882 | if (unlikely(!atslave || !buf_len || !period_len)) { | |
883 | dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n"); | |
884 | return NULL; | |
885 | } | |
886 | ||
887 | was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status); | |
888 | if (was_cyclic) { | |
889 | dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n"); | |
890 | return NULL; | |
891 | } | |
892 | ||
893 | /* Check for too big/unaligned periods and unaligned DMA buffer */ | |
894 | if (atc_dma_cyclic_check_values(atslave->reg_width, buf_addr, | |
895 | period_len, direction)) | |
896 | goto err_out; | |
897 | ||
898 | /* build cyclic linked list */ | |
899 | for (i = 0; i < periods; i++) { | |
900 | struct at_desc *desc; | |
901 | ||
902 | desc = atc_desc_get(atchan); | |
903 | if (!desc) | |
904 | goto err_desc_get; | |
905 | ||
906 | if (atc_dma_cyclic_fill_desc(atslave, desc, i, buf_addr, | |
907 | period_len, direction)) | |
908 | goto err_desc_get; | |
909 | ||
910 | atc_desc_chain(&first, &prev, desc); | |
911 | } | |
912 | ||
913 | /* lets make a cyclic list */ | |
914 | prev->lli.dscr = first->txd.phys; | |
915 | ||
916 | /* First descriptor of the chain embedds additional information */ | |
917 | first->txd.cookie = -EBUSY; | |
918 | first->len = buf_len; | |
919 | ||
920 | return &first->txd; | |
921 | ||
922 | err_desc_get: | |
923 | dev_err(chan2dev(chan), "not enough descriptors available\n"); | |
924 | atc_desc_put(atchan, first); | |
925 | err_out: | |
926 | clear_bit(ATC_IS_CYCLIC, &atchan->status); | |
927 | return NULL; | |
928 | } | |
929 | ||
930 | ||
05827630 LW |
931 | static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
932 | unsigned long arg) | |
808347f6 NF |
933 | { |
934 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
935 | struct at_dma *atdma = to_at_dma(chan->device); | |
23b5e3ad | 936 | int chan_id = atchan->chan_common.chan_id; |
d8cb04b0 | 937 | unsigned long flags; |
23b5e3ad | 938 | |
808347f6 NF |
939 | LIST_HEAD(list); |
940 | ||
23b5e3ad | 941 | dev_vdbg(chan2dev(chan), "atc_control (%d)\n", cmd); |
c3635c78 | 942 | |
23b5e3ad | 943 | if (cmd == DMA_PAUSE) { |
d8cb04b0 | 944 | spin_lock_irqsave(&atchan->lock, flags); |
808347f6 | 945 | |
23b5e3ad | 946 | dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id)); |
23b5e3ad | 947 | set_bit(ATC_IS_PAUSED, &atchan->status); |
808347f6 | 948 | |
d8cb04b0 | 949 | spin_unlock_irqrestore(&atchan->lock, flags); |
23b5e3ad | 950 | } else if (cmd == DMA_RESUME) { |
3c477482 | 951 | if (!atc_chan_is_paused(atchan)) |
23b5e3ad | 952 | return 0; |
808347f6 | 953 | |
d8cb04b0 | 954 | spin_lock_irqsave(&atchan->lock, flags); |
808347f6 | 955 | |
23b5e3ad NF |
956 | dma_writel(atdma, CHDR, AT_DMA_RES(chan_id)); |
957 | clear_bit(ATC_IS_PAUSED, &atchan->status); | |
c3635c78 | 958 | |
d8cb04b0 | 959 | spin_unlock_irqrestore(&atchan->lock, flags); |
23b5e3ad NF |
960 | } else if (cmd == DMA_TERMINATE_ALL) { |
961 | struct at_desc *desc, *_desc; | |
962 | /* | |
963 | * This is only called when something went wrong elsewhere, so | |
964 | * we don't really care about the data. Just disable the | |
965 | * channel. We still have to poll the channel enable bit due | |
966 | * to AHB/HSB limitations. | |
967 | */ | |
d8cb04b0 | 968 | spin_lock_irqsave(&atchan->lock, flags); |
23b5e3ad NF |
969 | |
970 | /* disabling channel: must also remove suspend state */ | |
971 | dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask); | |
972 | ||
973 | /* confirm that this channel is disabled */ | |
974 | while (dma_readl(atdma, CHSR) & atchan->mask) | |
975 | cpu_relax(); | |
976 | ||
977 | /* active_list entries will end up before queued entries */ | |
978 | list_splice_init(&atchan->queue, &list); | |
979 | list_splice_init(&atchan->active_list, &list); | |
980 | ||
981 | /* Flush all pending and queued descriptors */ | |
982 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
983 | atc_chain_complete(atchan, desc); | |
984 | ||
985 | clear_bit(ATC_IS_PAUSED, &atchan->status); | |
986 | /* if channel dedicated to cyclic operations, free it */ | |
987 | clear_bit(ATC_IS_CYCLIC, &atchan->status); | |
988 | ||
d8cb04b0 | 989 | spin_unlock_irqrestore(&atchan->lock, flags); |
23b5e3ad NF |
990 | } else { |
991 | return -ENXIO; | |
992 | } | |
b0ebeb9c | 993 | |
c3635c78 | 994 | return 0; |
808347f6 NF |
995 | } |
996 | ||
dc78baa2 | 997 | /** |
07934481 | 998 | * atc_tx_status - poll for transaction completion |
dc78baa2 NF |
999 | * @chan: DMA channel |
1000 | * @cookie: transaction identifier to check status of | |
07934481 | 1001 | * @txstate: if not %NULL updated with transaction state |
dc78baa2 | 1002 | * |
07934481 | 1003 | * If @txstate is passed in, upon return it reflect the driver |
dc78baa2 NF |
1004 | * internal state and can be used with dma_async_is_complete() to check |
1005 | * the status of multiple cookies without re-checking hardware state. | |
1006 | */ | |
1007 | static enum dma_status | |
07934481 | 1008 | atc_tx_status(struct dma_chan *chan, |
dc78baa2 | 1009 | dma_cookie_t cookie, |
07934481 | 1010 | struct dma_tx_state *txstate) |
dc78baa2 NF |
1011 | { |
1012 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1013 | dma_cookie_t last_used; | |
1014 | dma_cookie_t last_complete; | |
d8cb04b0 | 1015 | unsigned long flags; |
dc78baa2 NF |
1016 | enum dma_status ret; |
1017 | ||
d8cb04b0 | 1018 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 | 1019 | |
4d4e58de | 1020 | last_complete = chan->completed_cookie; |
dc78baa2 NF |
1021 | last_used = chan->cookie; |
1022 | ||
1023 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
1024 | if (ret != DMA_SUCCESS) { | |
1025 | atc_cleanup_descriptors(atchan); | |
1026 | ||
4d4e58de | 1027 | last_complete = chan->completed_cookie; |
dc78baa2 NF |
1028 | last_used = chan->cookie; |
1029 | ||
1030 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
1031 | } | |
1032 | ||
d8cb04b0 | 1033 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 | 1034 | |
543aabc7 NF |
1035 | if (ret != DMA_SUCCESS) |
1036 | dma_set_tx_state(txstate, last_complete, last_used, | |
1037 | atc_first_active(atchan)->len); | |
1038 | else | |
1039 | dma_set_tx_state(txstate, last_complete, last_used, 0); | |
1040 | ||
3c477482 | 1041 | if (atc_chan_is_paused(atchan)) |
23b5e3ad NF |
1042 | ret = DMA_PAUSED; |
1043 | ||
1044 | dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d (d%d, u%d)\n", | |
1045 | ret, cookie, last_complete ? last_complete : 0, | |
07934481 | 1046 | last_used ? last_used : 0); |
dc78baa2 NF |
1047 | |
1048 | return ret; | |
1049 | } | |
1050 | ||
1051 | /** | |
1052 | * atc_issue_pending - try to finish work | |
1053 | * @chan: target DMA channel | |
1054 | */ | |
1055 | static void atc_issue_pending(struct dma_chan *chan) | |
1056 | { | |
1057 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
d8cb04b0 | 1058 | unsigned long flags; |
dc78baa2 NF |
1059 | |
1060 | dev_vdbg(chan2dev(chan), "issue_pending\n"); | |
1061 | ||
53830cc7 | 1062 | /* Not needed for cyclic transfers */ |
3c477482 | 1063 | if (atc_chan_is_cyclic(atchan)) |
53830cc7 NF |
1064 | return; |
1065 | ||
d8cb04b0 | 1066 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 | 1067 | if (!atc_chan_is_enabled(atchan)) { |
dc78baa2 | 1068 | atc_advance_work(atchan); |
dc78baa2 | 1069 | } |
d8cb04b0 | 1070 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
1071 | } |
1072 | ||
1073 | /** | |
1074 | * atc_alloc_chan_resources - allocate resources for DMA channel | |
1075 | * @chan: allocate descriptor resources for this channel | |
1076 | * @client: current client requesting the channel be ready for requests | |
1077 | * | |
1078 | * return - the number of allocated descriptors | |
1079 | */ | |
1080 | static int atc_alloc_chan_resources(struct dma_chan *chan) | |
1081 | { | |
1082 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1083 | struct at_dma *atdma = to_at_dma(chan->device); | |
1084 | struct at_desc *desc; | |
808347f6 | 1085 | struct at_dma_slave *atslave; |
d8cb04b0 | 1086 | unsigned long flags; |
dc78baa2 | 1087 | int i; |
808347f6 | 1088 | u32 cfg; |
dc78baa2 NF |
1089 | LIST_HEAD(tmp_list); |
1090 | ||
1091 | dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); | |
1092 | ||
1093 | /* ASSERT: channel is idle */ | |
1094 | if (atc_chan_is_enabled(atchan)) { | |
1095 | dev_dbg(chan2dev(chan), "DMA channel not idle ?\n"); | |
1096 | return -EIO; | |
1097 | } | |
1098 | ||
808347f6 NF |
1099 | cfg = ATC_DEFAULT_CFG; |
1100 | ||
1101 | atslave = chan->private; | |
1102 | if (atslave) { | |
1103 | /* | |
1104 | * We need controller-specific data to set up slave | |
1105 | * transfers. | |
1106 | */ | |
1107 | BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev); | |
1108 | ||
1109 | /* if cfg configuration specified take it instad of default */ | |
1110 | if (atslave->cfg) | |
1111 | cfg = atslave->cfg; | |
1112 | } | |
1113 | ||
1114 | /* have we already been set up? | |
1115 | * reconfigure channel but no need to reallocate descriptors */ | |
dc78baa2 NF |
1116 | if (!list_empty(&atchan->free_list)) |
1117 | return atchan->descs_allocated; | |
1118 | ||
1119 | /* Allocate initial pool of descriptors */ | |
1120 | for (i = 0; i < init_nr_desc_per_channel; i++) { | |
1121 | desc = atc_alloc_descriptor(chan, GFP_KERNEL); | |
1122 | if (!desc) { | |
1123 | dev_err(atdma->dma_common.dev, | |
1124 | "Only %d initial descriptors\n", i); | |
1125 | break; | |
1126 | } | |
1127 | list_add_tail(&desc->desc_node, &tmp_list); | |
1128 | } | |
1129 | ||
d8cb04b0 | 1130 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 NF |
1131 | atchan->descs_allocated = i; |
1132 | list_splice(&tmp_list, &atchan->free_list); | |
4d4e58de | 1133 | chan->completed_cookie = chan->cookie = 1; |
d8cb04b0 | 1134 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
1135 | |
1136 | /* channel parameters */ | |
808347f6 | 1137 | channel_writel(atchan, CFG, cfg); |
dc78baa2 NF |
1138 | |
1139 | dev_dbg(chan2dev(chan), | |
1140 | "alloc_chan_resources: allocated %d descriptors\n", | |
1141 | atchan->descs_allocated); | |
1142 | ||
1143 | return atchan->descs_allocated; | |
1144 | } | |
1145 | ||
1146 | /** | |
1147 | * atc_free_chan_resources - free all channel resources | |
1148 | * @chan: DMA channel | |
1149 | */ | |
1150 | static void atc_free_chan_resources(struct dma_chan *chan) | |
1151 | { | |
1152 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1153 | struct at_dma *atdma = to_at_dma(chan->device); | |
1154 | struct at_desc *desc, *_desc; | |
1155 | LIST_HEAD(list); | |
1156 | ||
1157 | dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n", | |
1158 | atchan->descs_allocated); | |
1159 | ||
1160 | /* ASSERT: channel is idle */ | |
1161 | BUG_ON(!list_empty(&atchan->active_list)); | |
1162 | BUG_ON(!list_empty(&atchan->queue)); | |
1163 | BUG_ON(atc_chan_is_enabled(atchan)); | |
1164 | ||
1165 | list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { | |
1166 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); | |
1167 | list_del(&desc->desc_node); | |
1168 | /* free link descriptor */ | |
1169 | dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys); | |
1170 | } | |
1171 | list_splice_init(&atchan->free_list, &list); | |
1172 | atchan->descs_allocated = 0; | |
53830cc7 | 1173 | atchan->status = 0; |
dc78baa2 NF |
1174 | |
1175 | dev_vdbg(chan2dev(chan), "free_chan_resources: done\n"); | |
1176 | } | |
1177 | ||
1178 | ||
1179 | /*-- Module Management -----------------------------------------------*/ | |
1180 | ||
02f88be9 NF |
1181 | /* cap_mask is a multi-u32 bitfield, fill it with proper C code. */ |
1182 | static struct at_dma_platform_data at91sam9rl_config = { | |
1183 | .nr_channels = 2, | |
1184 | }; | |
1185 | static struct at_dma_platform_data at91sam9g45_config = { | |
1186 | .nr_channels = 8, | |
1187 | }; | |
1188 | ||
c5115953 NF |
1189 | #if defined(CONFIG_OF) |
1190 | static const struct of_device_id atmel_dma_dt_ids[] = { | |
1191 | { | |
1192 | .compatible = "atmel,at91sam9rl-dma", | |
02f88be9 | 1193 | .data = &at91sam9rl_config, |
c5115953 NF |
1194 | }, { |
1195 | .compatible = "atmel,at91sam9g45-dma", | |
02f88be9 | 1196 | .data = &at91sam9g45_config, |
dcc81734 NF |
1197 | }, { |
1198 | /* sentinel */ | |
1199 | } | |
c5115953 NF |
1200 | }; |
1201 | ||
1202 | MODULE_DEVICE_TABLE(of, atmel_dma_dt_ids); | |
1203 | #endif | |
1204 | ||
0ab88a01 | 1205 | static const struct platform_device_id atdma_devtypes[] = { |
67348450 NF |
1206 | { |
1207 | .name = "at91sam9rl_dma", | |
02f88be9 | 1208 | .driver_data = (unsigned long) &at91sam9rl_config, |
67348450 NF |
1209 | }, { |
1210 | .name = "at91sam9g45_dma", | |
02f88be9 | 1211 | .driver_data = (unsigned long) &at91sam9g45_config, |
67348450 NF |
1212 | }, { |
1213 | /* sentinel */ | |
1214 | } | |
1215 | }; | |
1216 | ||
02f88be9 NF |
1217 | static inline struct at_dma_platform_data * __init at_dma_get_driver_data( |
1218 | struct platform_device *pdev) | |
c5115953 NF |
1219 | { |
1220 | if (pdev->dev.of_node) { | |
1221 | const struct of_device_id *match; | |
1222 | match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node); | |
1223 | if (match == NULL) | |
02f88be9 NF |
1224 | return NULL; |
1225 | return match->data; | |
c5115953 | 1226 | } |
02f88be9 NF |
1227 | return (struct at_dma_platform_data *) |
1228 | platform_get_device_id(pdev)->driver_data; | |
c5115953 NF |
1229 | } |
1230 | ||
dc78baa2 NF |
1231 | /** |
1232 | * at_dma_off - disable DMA controller | |
1233 | * @atdma: the Atmel HDAMC device | |
1234 | */ | |
1235 | static void at_dma_off(struct at_dma *atdma) | |
1236 | { | |
1237 | dma_writel(atdma, EN, 0); | |
1238 | ||
1239 | /* disable all interrupts */ | |
1240 | dma_writel(atdma, EBCIDR, -1L); | |
1241 | ||
1242 | /* confirm that all channels are disabled */ | |
1243 | while (dma_readl(atdma, CHSR) & atdma->all_chan_mask) | |
1244 | cpu_relax(); | |
1245 | } | |
1246 | ||
1247 | static int __init at_dma_probe(struct platform_device *pdev) | |
1248 | { | |
dc78baa2 NF |
1249 | struct resource *io; |
1250 | struct at_dma *atdma; | |
1251 | size_t size; | |
1252 | int irq; | |
1253 | int err; | |
1254 | int i; | |
02f88be9 | 1255 | struct at_dma_platform_data *plat_dat; |
67348450 | 1256 | |
02f88be9 NF |
1257 | /* setup platform data for each SoC */ |
1258 | dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask); | |
1259 | dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask); | |
1260 | dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask); | |
67348450 NF |
1261 | |
1262 | /* get DMA parameters from controller type */ | |
02f88be9 NF |
1263 | plat_dat = at_dma_get_driver_data(pdev); |
1264 | if (!plat_dat) | |
1265 | return -ENODEV; | |
dc78baa2 NF |
1266 | |
1267 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1268 | if (!io) | |
1269 | return -EINVAL; | |
1270 | ||
1271 | irq = platform_get_irq(pdev, 0); | |
1272 | if (irq < 0) | |
1273 | return irq; | |
1274 | ||
1275 | size = sizeof(struct at_dma); | |
02f88be9 | 1276 | size += plat_dat->nr_channels * sizeof(struct at_dma_chan); |
dc78baa2 NF |
1277 | atdma = kzalloc(size, GFP_KERNEL); |
1278 | if (!atdma) | |
1279 | return -ENOMEM; | |
1280 | ||
67348450 | 1281 | /* discover transaction capabilities */ |
02f88be9 NF |
1282 | atdma->dma_common.cap_mask = plat_dat->cap_mask; |
1283 | atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1; | |
dc78baa2 | 1284 | |
114df7d6 | 1285 | size = resource_size(io); |
dc78baa2 NF |
1286 | if (!request_mem_region(io->start, size, pdev->dev.driver->name)) { |
1287 | err = -EBUSY; | |
1288 | goto err_kfree; | |
1289 | } | |
1290 | ||
1291 | atdma->regs = ioremap(io->start, size); | |
1292 | if (!atdma->regs) { | |
1293 | err = -ENOMEM; | |
1294 | goto err_release_r; | |
1295 | } | |
1296 | ||
1297 | atdma->clk = clk_get(&pdev->dev, "dma_clk"); | |
1298 | if (IS_ERR(atdma->clk)) { | |
1299 | err = PTR_ERR(atdma->clk); | |
1300 | goto err_clk; | |
1301 | } | |
1302 | clk_enable(atdma->clk); | |
1303 | ||
1304 | /* force dma off, just in case */ | |
1305 | at_dma_off(atdma); | |
1306 | ||
1307 | err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma); | |
1308 | if (err) | |
1309 | goto err_irq; | |
1310 | ||
1311 | platform_set_drvdata(pdev, atdma); | |
1312 | ||
1313 | /* create a pool of consistent memory blocks for hardware descriptors */ | |
1314 | atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool", | |
1315 | &pdev->dev, sizeof(struct at_desc), | |
1316 | 4 /* word alignment */, 0); | |
1317 | if (!atdma->dma_desc_pool) { | |
1318 | dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); | |
1319 | err = -ENOMEM; | |
1320 | goto err_pool_create; | |
1321 | } | |
1322 | ||
1323 | /* clear any pending interrupt */ | |
1324 | while (dma_readl(atdma, EBCISR)) | |
1325 | cpu_relax(); | |
1326 | ||
1327 | /* initialize channels related values */ | |
1328 | INIT_LIST_HEAD(&atdma->dma_common.channels); | |
02f88be9 | 1329 | for (i = 0; i < plat_dat->nr_channels; i++) { |
dc78baa2 NF |
1330 | struct at_dma_chan *atchan = &atdma->chan[i]; |
1331 | ||
1332 | atchan->chan_common.device = &atdma->dma_common; | |
4d4e58de | 1333 | atchan->chan_common.cookie = atchan->chan_common.completed_cookie = 1; |
dc78baa2 NF |
1334 | list_add_tail(&atchan->chan_common.device_node, |
1335 | &atdma->dma_common.channels); | |
1336 | ||
1337 | atchan->ch_regs = atdma->regs + ch_regs(i); | |
1338 | spin_lock_init(&atchan->lock); | |
1339 | atchan->mask = 1 << i; | |
1340 | ||
1341 | INIT_LIST_HEAD(&atchan->active_list); | |
1342 | INIT_LIST_HEAD(&atchan->queue); | |
1343 | INIT_LIST_HEAD(&atchan->free_list); | |
1344 | ||
1345 | tasklet_init(&atchan->tasklet, atc_tasklet, | |
1346 | (unsigned long)atchan); | |
bda3a47c | 1347 | atc_enable_chan_irq(atdma, i); |
dc78baa2 NF |
1348 | } |
1349 | ||
1350 | /* set base routines */ | |
1351 | atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources; | |
1352 | atdma->dma_common.device_free_chan_resources = atc_free_chan_resources; | |
07934481 | 1353 | atdma->dma_common.device_tx_status = atc_tx_status; |
dc78baa2 NF |
1354 | atdma->dma_common.device_issue_pending = atc_issue_pending; |
1355 | atdma->dma_common.dev = &pdev->dev; | |
1356 | ||
1357 | /* set prep routines based on capability */ | |
1358 | if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask)) | |
1359 | atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy; | |
1360 | ||
d7db8080 | 1361 | if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) { |
808347f6 | 1362 | atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg; |
d7db8080 NF |
1363 | /* controller can do slave DMA: can trigger cyclic transfers */ |
1364 | dma_cap_set(DMA_CYCLIC, atdma->dma_common.cap_mask); | |
53830cc7 | 1365 | atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic; |
c3635c78 | 1366 | atdma->dma_common.device_control = atc_control; |
d7db8080 | 1367 | } |
808347f6 | 1368 | |
dc78baa2 NF |
1369 | dma_writel(atdma, EN, AT_DMA_ENABLE); |
1370 | ||
1371 | dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s), %d channels\n", | |
1372 | dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "", | |
1373 | dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "", | |
02f88be9 | 1374 | plat_dat->nr_channels); |
dc78baa2 NF |
1375 | |
1376 | dma_async_device_register(&atdma->dma_common); | |
1377 | ||
1378 | return 0; | |
1379 | ||
1380 | err_pool_create: | |
1381 | platform_set_drvdata(pdev, NULL); | |
1382 | free_irq(platform_get_irq(pdev, 0), atdma); | |
1383 | err_irq: | |
1384 | clk_disable(atdma->clk); | |
1385 | clk_put(atdma->clk); | |
1386 | err_clk: | |
1387 | iounmap(atdma->regs); | |
1388 | atdma->regs = NULL; | |
1389 | err_release_r: | |
1390 | release_mem_region(io->start, size); | |
1391 | err_kfree: | |
1392 | kfree(atdma); | |
1393 | return err; | |
1394 | } | |
1395 | ||
1396 | static int __exit at_dma_remove(struct platform_device *pdev) | |
1397 | { | |
1398 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
1399 | struct dma_chan *chan, *_chan; | |
1400 | struct resource *io; | |
1401 | ||
1402 | at_dma_off(atdma); | |
1403 | dma_async_device_unregister(&atdma->dma_common); | |
1404 | ||
1405 | dma_pool_destroy(atdma->dma_desc_pool); | |
1406 | platform_set_drvdata(pdev, NULL); | |
1407 | free_irq(platform_get_irq(pdev, 0), atdma); | |
1408 | ||
1409 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1410 | device_node) { | |
1411 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1412 | ||
1413 | /* Disable interrupts */ | |
bda3a47c | 1414 | atc_disable_chan_irq(atdma, chan->chan_id); |
dc78baa2 NF |
1415 | tasklet_disable(&atchan->tasklet); |
1416 | ||
1417 | tasklet_kill(&atchan->tasklet); | |
1418 | list_del(&chan->device_node); | |
1419 | } | |
1420 | ||
1421 | clk_disable(atdma->clk); | |
1422 | clk_put(atdma->clk); | |
1423 | ||
1424 | iounmap(atdma->regs); | |
1425 | atdma->regs = NULL; | |
1426 | ||
1427 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
114df7d6 | 1428 | release_mem_region(io->start, resource_size(io)); |
dc78baa2 NF |
1429 | |
1430 | kfree(atdma); | |
1431 | ||
1432 | return 0; | |
1433 | } | |
1434 | ||
1435 | static void at_dma_shutdown(struct platform_device *pdev) | |
1436 | { | |
1437 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
1438 | ||
1439 | at_dma_off(platform_get_drvdata(pdev)); | |
1440 | clk_disable(atdma->clk); | |
1441 | } | |
1442 | ||
c0ba5947 NF |
1443 | static int at_dma_prepare(struct device *dev) |
1444 | { | |
1445 | struct platform_device *pdev = to_platform_device(dev); | |
1446 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
1447 | struct dma_chan *chan, *_chan; | |
1448 | ||
1449 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1450 | device_node) { | |
1451 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1452 | /* wait for transaction completion (except in cyclic case) */ | |
3c477482 | 1453 | if (atc_chan_is_enabled(atchan) && !atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
1454 | return -EAGAIN; |
1455 | } | |
1456 | return 0; | |
1457 | } | |
1458 | ||
1459 | static void atc_suspend_cyclic(struct at_dma_chan *atchan) | |
1460 | { | |
1461 | struct dma_chan *chan = &atchan->chan_common; | |
1462 | ||
1463 | /* Channel should be paused by user | |
1464 | * do it anyway even if it is not done already */ | |
3c477482 | 1465 | if (!atc_chan_is_paused(atchan)) { |
c0ba5947 NF |
1466 | dev_warn(chan2dev(chan), |
1467 | "cyclic channel not paused, should be done by channel user\n"); | |
1468 | atc_control(chan, DMA_PAUSE, 0); | |
1469 | } | |
1470 | ||
1471 | /* now preserve additional data for cyclic operations */ | |
1472 | /* next descriptor address in the cyclic list */ | |
1473 | atchan->save_dscr = channel_readl(atchan, DSCR); | |
1474 | ||
1475 | vdbg_dump_regs(atchan); | |
1476 | } | |
1477 | ||
33f82d14 | 1478 | static int at_dma_suspend_noirq(struct device *dev) |
dc78baa2 | 1479 | { |
33f82d14 DW |
1480 | struct platform_device *pdev = to_platform_device(dev); |
1481 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
c0ba5947 | 1482 | struct dma_chan *chan, *_chan; |
dc78baa2 | 1483 | |
c0ba5947 NF |
1484 | /* preserve data */ |
1485 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1486 | device_node) { | |
1487 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1488 | ||
3c477482 | 1489 | if (atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
1490 | atc_suspend_cyclic(atchan); |
1491 | atchan->save_cfg = channel_readl(atchan, CFG); | |
1492 | } | |
1493 | atdma->save_imr = dma_readl(atdma, EBCIMR); | |
1494 | ||
1495 | /* disable DMA controller */ | |
1496 | at_dma_off(atdma); | |
dc78baa2 NF |
1497 | clk_disable(atdma->clk); |
1498 | return 0; | |
1499 | } | |
1500 | ||
c0ba5947 NF |
1501 | static void atc_resume_cyclic(struct at_dma_chan *atchan) |
1502 | { | |
1503 | struct at_dma *atdma = to_at_dma(atchan->chan_common.device); | |
1504 | ||
1505 | /* restore channel status for cyclic descriptors list: | |
1506 | * next descriptor in the cyclic list at the time of suspend */ | |
1507 | channel_writel(atchan, SADDR, 0); | |
1508 | channel_writel(atchan, DADDR, 0); | |
1509 | channel_writel(atchan, CTRLA, 0); | |
1510 | channel_writel(atchan, CTRLB, 0); | |
1511 | channel_writel(atchan, DSCR, atchan->save_dscr); | |
1512 | dma_writel(atdma, CHER, atchan->mask); | |
1513 | ||
1514 | /* channel pause status should be removed by channel user | |
1515 | * We cannot take the initiative to do it here */ | |
1516 | ||
1517 | vdbg_dump_regs(atchan); | |
1518 | } | |
1519 | ||
33f82d14 | 1520 | static int at_dma_resume_noirq(struct device *dev) |
dc78baa2 | 1521 | { |
33f82d14 DW |
1522 | struct platform_device *pdev = to_platform_device(dev); |
1523 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
c0ba5947 | 1524 | struct dma_chan *chan, *_chan; |
dc78baa2 | 1525 | |
c0ba5947 | 1526 | /* bring back DMA controller */ |
dc78baa2 NF |
1527 | clk_enable(atdma->clk); |
1528 | dma_writel(atdma, EN, AT_DMA_ENABLE); | |
c0ba5947 NF |
1529 | |
1530 | /* clear any pending interrupt */ | |
1531 | while (dma_readl(atdma, EBCISR)) | |
1532 | cpu_relax(); | |
1533 | ||
1534 | /* restore saved data */ | |
1535 | dma_writel(atdma, EBCIER, atdma->save_imr); | |
1536 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1537 | device_node) { | |
1538 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1539 | ||
1540 | channel_writel(atchan, CFG, atchan->save_cfg); | |
3c477482 | 1541 | if (atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
1542 | atc_resume_cyclic(atchan); |
1543 | } | |
dc78baa2 | 1544 | return 0; |
dc78baa2 NF |
1545 | } |
1546 | ||
47145210 | 1547 | static const struct dev_pm_ops at_dma_dev_pm_ops = { |
c0ba5947 | 1548 | .prepare = at_dma_prepare, |
33f82d14 DW |
1549 | .suspend_noirq = at_dma_suspend_noirq, |
1550 | .resume_noirq = at_dma_resume_noirq, | |
1551 | }; | |
1552 | ||
dc78baa2 NF |
1553 | static struct platform_driver at_dma_driver = { |
1554 | .remove = __exit_p(at_dma_remove), | |
1555 | .shutdown = at_dma_shutdown, | |
67348450 | 1556 | .id_table = atdma_devtypes, |
dc78baa2 NF |
1557 | .driver = { |
1558 | .name = "at_hdmac", | |
33f82d14 | 1559 | .pm = &at_dma_dev_pm_ops, |
c5115953 | 1560 | .of_match_table = of_match_ptr(atmel_dma_dt_ids), |
dc78baa2 NF |
1561 | }, |
1562 | }; | |
1563 | ||
1564 | static int __init at_dma_init(void) | |
1565 | { | |
1566 | return platform_driver_probe(&at_dma_driver, at_dma_probe); | |
1567 | } | |
93d0bec2 | 1568 | subsys_initcall(at_dma_init); |
dc78baa2 NF |
1569 | |
1570 | static void __exit at_dma_exit(void) | |
1571 | { | |
1572 | platform_driver_unregister(&at_dma_driver); | |
1573 | } | |
1574 | module_exit(at_dma_exit); | |
1575 | ||
1576 | MODULE_DESCRIPTION("Atmel AHB DMA Controller driver"); | |
1577 | MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>"); | |
1578 | MODULE_LICENSE("GPL"); | |
1579 | MODULE_ALIAS("platform:at_hdmac"); |