Commit | Line | Data |
---|---|---|
7c9281d7 DT |
1 | /* |
2 | * edac_mc kernel module | |
42a8e397 DT |
3 | * (C) 2005-2007 Linux Networx (http://lnxi.com) |
4 | * | |
7c9281d7 DT |
5 | * This file may be distributed under the terms of the |
6 | * GNU General Public License. | |
7 | * | |
42a8e397 | 8 | * Written Doug Thompson <norsk5@xmission.com> www.softwarebitmaker.com |
7c9281d7 | 9 | * |
37e59f87 | 10 | * (c) 2012-2013 - Mauro Carvalho Chehab |
7a623c03 MCC |
11 | * The entire API were re-written, and ported to use struct device |
12 | * | |
7c9281d7 DT |
13 | */ |
14 | ||
7c9281d7 | 15 | #include <linux/ctype.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
30e1f7a8 | 17 | #include <linux/edac.h> |
8096cfaf | 18 | #include <linux/bug.h> |
7a623c03 | 19 | #include <linux/pm_runtime.h> |
452a6bf9 | 20 | #include <linux/uaccess.h> |
7c9281d7 | 21 | |
20bcb7a8 | 22 | #include "edac_core.h" |
7c9281d7 DT |
23 | #include "edac_module.h" |
24 | ||
25 | /* MC EDAC Controls, setable by module parameter, and sysfs */ | |
4de78c68 DJ |
26 | static int edac_mc_log_ue = 1; |
27 | static int edac_mc_log_ce = 1; | |
f044091c | 28 | static int edac_mc_panic_on_ue; |
4de78c68 | 29 | static int edac_mc_poll_msec = 1000; |
7c9281d7 DT |
30 | |
31 | /* Getter functions for above */ | |
4de78c68 | 32 | int edac_mc_get_log_ue(void) |
7c9281d7 | 33 | { |
4de78c68 | 34 | return edac_mc_log_ue; |
7c9281d7 DT |
35 | } |
36 | ||
4de78c68 | 37 | int edac_mc_get_log_ce(void) |
7c9281d7 | 38 | { |
4de78c68 | 39 | return edac_mc_log_ce; |
7c9281d7 DT |
40 | } |
41 | ||
4de78c68 | 42 | int edac_mc_get_panic_on_ue(void) |
7c9281d7 | 43 | { |
4de78c68 | 44 | return edac_mc_panic_on_ue; |
7c9281d7 DT |
45 | } |
46 | ||
81d87cb1 DJ |
47 | /* this is temporary */ |
48 | int edac_mc_get_poll_msec(void) | |
49 | { | |
4de78c68 | 50 | return edac_mc_poll_msec; |
7c9281d7 DT |
51 | } |
52 | ||
096846e2 AJ |
53 | static int edac_set_poll_msec(const char *val, struct kernel_param *kp) |
54 | { | |
9da21b15 | 55 | unsigned long l; |
096846e2 AJ |
56 | int ret; |
57 | ||
58 | if (!val) | |
59 | return -EINVAL; | |
60 | ||
9da21b15 | 61 | ret = kstrtoul(val, 0, &l); |
c542b53d JH |
62 | if (ret) |
63 | return ret; | |
9da21b15 BP |
64 | |
65 | if (l < 1000) | |
096846e2 | 66 | return -EINVAL; |
9da21b15 BP |
67 | |
68 | *((unsigned long *)kp->arg) = l; | |
096846e2 AJ |
69 | |
70 | /* notify edac_mc engine to reset the poll period */ | |
71 | edac_mc_reset_delay_period(l); | |
72 | ||
73 | return 0; | |
74 | } | |
75 | ||
7c9281d7 | 76 | /* Parameter declarations for above */ |
4de78c68 DJ |
77 | module_param(edac_mc_panic_on_ue, int, 0644); |
78 | MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on"); | |
79 | module_param(edac_mc_log_ue, int, 0644); | |
80 | MODULE_PARM_DESC(edac_mc_log_ue, | |
079708b9 | 81 | "Log uncorrectable error to console: 0=off 1=on"); |
4de78c68 DJ |
82 | module_param(edac_mc_log_ce, int, 0644); |
83 | MODULE_PARM_DESC(edac_mc_log_ce, | |
079708b9 | 84 | "Log correctable error to console: 0=off 1=on"); |
096846e2 AJ |
85 | module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int, |
86 | &edac_mc_poll_msec, 0644); | |
4de78c68 | 87 | MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds"); |
7c9281d7 | 88 | |
de3910eb | 89 | static struct device *mci_pdev; |
7a623c03 | 90 | |
7c9281d7 DT |
91 | /* |
92 | * various constants for Memory Controllers | |
93 | */ | |
8b7719e0 | 94 | static const char * const mem_types[] = { |
7c9281d7 DT |
95 | [MEM_EMPTY] = "Empty", |
96 | [MEM_RESERVED] = "Reserved", | |
97 | [MEM_UNKNOWN] = "Unknown", | |
98 | [MEM_FPM] = "FPM", | |
99 | [MEM_EDO] = "EDO", | |
100 | [MEM_BEDO] = "BEDO", | |
101 | [MEM_SDR] = "Unbuffered-SDR", | |
102 | [MEM_RDR] = "Registered-SDR", | |
103 | [MEM_DDR] = "Unbuffered-DDR", | |
104 | [MEM_RDDR] = "Registered-DDR", | |
1a9b85e6 DJ |
105 | [MEM_RMBS] = "RMBS", |
106 | [MEM_DDR2] = "Unbuffered-DDR2", | |
107 | [MEM_FB_DDR2] = "FullyBuffered-DDR2", | |
1d5f726c | 108 | [MEM_RDDR2] = "Registered-DDR2", |
b1cfebc9 YS |
109 | [MEM_XDR] = "XDR", |
110 | [MEM_DDR3] = "Unbuffered-DDR3", | |
7b827835 AR |
111 | [MEM_RDDR3] = "Registered-DDR3", |
112 | [MEM_DDR4] = "Unbuffered-DDR4", | |
113 | [MEM_RDDR4] = "Registered-DDR4" | |
7c9281d7 DT |
114 | }; |
115 | ||
8b7719e0 | 116 | static const char * const dev_types[] = { |
7c9281d7 DT |
117 | [DEV_UNKNOWN] = "Unknown", |
118 | [DEV_X1] = "x1", | |
119 | [DEV_X2] = "x2", | |
120 | [DEV_X4] = "x4", | |
121 | [DEV_X8] = "x8", | |
122 | [DEV_X16] = "x16", | |
123 | [DEV_X32] = "x32", | |
124 | [DEV_X64] = "x64" | |
125 | }; | |
126 | ||
8b7719e0 | 127 | static const char * const edac_caps[] = { |
7c9281d7 DT |
128 | [EDAC_UNKNOWN] = "Unknown", |
129 | [EDAC_NONE] = "None", | |
130 | [EDAC_RESERVED] = "Reserved", | |
131 | [EDAC_PARITY] = "PARITY", | |
132 | [EDAC_EC] = "EC", | |
133 | [EDAC_SECDED] = "SECDED", | |
134 | [EDAC_S2ECD2ED] = "S2ECD2ED", | |
135 | [EDAC_S4ECD4ED] = "S4ECD4ED", | |
136 | [EDAC_S8ECD8ED] = "S8ECD8ED", | |
137 | [EDAC_S16ECD16ED] = "S16ECD16ED" | |
138 | }; | |
139 | ||
19974710 | 140 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 MCC |
141 | /* |
142 | * EDAC sysfs CSROW data structures and methods | |
143 | */ | |
144 | ||
145 | #define to_csrow(k) container_of(k, struct csrow_info, dev) | |
146 | ||
147 | /* | |
148 | * We need it to avoid namespace conflicts between the legacy API | |
149 | * and the per-dimm/per-rank one | |
7c9281d7 | 150 | */ |
7a623c03 | 151 | #define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \ |
fbe2d361 | 152 | static struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store) |
7a623c03 MCC |
153 | |
154 | struct dev_ch_attribute { | |
155 | struct device_attribute attr; | |
156 | int channel; | |
157 | }; | |
158 | ||
159 | #define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \ | |
f11135d8 | 160 | static struct dev_ch_attribute dev_attr_legacy_##_name = \ |
7a623c03 MCC |
161 | { __ATTR(_name, _mode, _show, _store), (_var) } |
162 | ||
163 | #define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel) | |
7c9281d7 DT |
164 | |
165 | /* Set of more default csrow<id> attribute show/store functions */ | |
7a623c03 MCC |
166 | static ssize_t csrow_ue_count_show(struct device *dev, |
167 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 168 | { |
7a623c03 MCC |
169 | struct csrow_info *csrow = to_csrow(dev); |
170 | ||
079708b9 | 171 | return sprintf(data, "%u\n", csrow->ue_count); |
7c9281d7 DT |
172 | } |
173 | ||
7a623c03 MCC |
174 | static ssize_t csrow_ce_count_show(struct device *dev, |
175 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 176 | { |
7a623c03 MCC |
177 | struct csrow_info *csrow = to_csrow(dev); |
178 | ||
079708b9 | 179 | return sprintf(data, "%u\n", csrow->ce_count); |
7c9281d7 DT |
180 | } |
181 | ||
7a623c03 MCC |
182 | static ssize_t csrow_size_show(struct device *dev, |
183 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 184 | { |
7a623c03 | 185 | struct csrow_info *csrow = to_csrow(dev); |
a895bf8b MCC |
186 | int i; |
187 | u32 nr_pages = 0; | |
188 | ||
189 | for (i = 0; i < csrow->nr_channels; i++) | |
de3910eb | 190 | nr_pages += csrow->channels[i]->dimm->nr_pages; |
a895bf8b | 191 | return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages)); |
7c9281d7 DT |
192 | } |
193 | ||
7a623c03 MCC |
194 | static ssize_t csrow_mem_type_show(struct device *dev, |
195 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 196 | { |
7a623c03 MCC |
197 | struct csrow_info *csrow = to_csrow(dev); |
198 | ||
de3910eb | 199 | return sprintf(data, "%s\n", mem_types[csrow->channels[0]->dimm->mtype]); |
7c9281d7 DT |
200 | } |
201 | ||
7a623c03 MCC |
202 | static ssize_t csrow_dev_type_show(struct device *dev, |
203 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 204 | { |
7a623c03 MCC |
205 | struct csrow_info *csrow = to_csrow(dev); |
206 | ||
de3910eb | 207 | return sprintf(data, "%s\n", dev_types[csrow->channels[0]->dimm->dtype]); |
7c9281d7 DT |
208 | } |
209 | ||
7a623c03 MCC |
210 | static ssize_t csrow_edac_mode_show(struct device *dev, |
211 | struct device_attribute *mattr, | |
212 | char *data) | |
7c9281d7 | 213 | { |
7a623c03 MCC |
214 | struct csrow_info *csrow = to_csrow(dev); |
215 | ||
de3910eb | 216 | return sprintf(data, "%s\n", edac_caps[csrow->channels[0]->dimm->edac_mode]); |
7c9281d7 DT |
217 | } |
218 | ||
219 | /* show/store functions for DIMM Label attributes */ | |
7a623c03 MCC |
220 | static ssize_t channel_dimm_label_show(struct device *dev, |
221 | struct device_attribute *mattr, | |
222 | char *data) | |
7c9281d7 | 223 | { |
7a623c03 MCC |
224 | struct csrow_info *csrow = to_csrow(dev); |
225 | unsigned chan = to_channel(mattr); | |
de3910eb | 226 | struct rank_info *rank = csrow->channels[chan]; |
7a623c03 | 227 | |
124682c7 | 228 | /* if field has not been initialized, there is nothing to send */ |
7a623c03 | 229 | if (!rank->dimm->label[0]) |
124682c7 AJ |
230 | return 0; |
231 | ||
1ea62c59 | 232 | return snprintf(data, sizeof(rank->dimm->label) + 1, "%s\n", |
7a623c03 | 233 | rank->dimm->label); |
7c9281d7 DT |
234 | } |
235 | ||
7a623c03 MCC |
236 | static ssize_t channel_dimm_label_store(struct device *dev, |
237 | struct device_attribute *mattr, | |
238 | const char *data, size_t count) | |
7c9281d7 | 239 | { |
7a623c03 MCC |
240 | struct csrow_info *csrow = to_csrow(dev); |
241 | unsigned chan = to_channel(mattr); | |
de3910eb | 242 | struct rank_info *rank = csrow->channels[chan]; |
438470b8 | 243 | size_t copy_count = count; |
7a623c03 | 244 | |
438470b8 TK |
245 | if (count == 0) |
246 | return -EINVAL; | |
247 | ||
248 | if (data[count - 1] == '\0' || data[count - 1] == '\n') | |
249 | copy_count -= 1; | |
250 | ||
d0c9c930 | 251 | if (copy_count == 0 || copy_count >= sizeof(rank->dimm->label)) |
438470b8 | 252 | return -EINVAL; |
7c9281d7 | 253 | |
438470b8 TK |
254 | strncpy(rank->dimm->label, data, copy_count); |
255 | rank->dimm->label[copy_count] = '\0'; | |
7c9281d7 | 256 | |
438470b8 | 257 | return count; |
7c9281d7 DT |
258 | } |
259 | ||
260 | /* show function for dynamic chX_ce_count attribute */ | |
7a623c03 MCC |
261 | static ssize_t channel_ce_count_show(struct device *dev, |
262 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 263 | { |
7a623c03 MCC |
264 | struct csrow_info *csrow = to_csrow(dev); |
265 | unsigned chan = to_channel(mattr); | |
de3910eb | 266 | struct rank_info *rank = csrow->channels[chan]; |
7a623c03 MCC |
267 | |
268 | return sprintf(data, "%u\n", rank->ce_count); | |
7c9281d7 DT |
269 | } |
270 | ||
7a623c03 MCC |
271 | /* cwrow<id>/attribute files */ |
272 | DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL); | |
273 | DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL); | |
274 | DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL); | |
275 | DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL); | |
276 | DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL); | |
277 | DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL); | |
7c9281d7 | 278 | |
7a623c03 MCC |
279 | /* default attributes of the CSROW<id> object */ |
280 | static struct attribute *csrow_attrs[] = { | |
281 | &dev_attr_legacy_dev_type.attr, | |
282 | &dev_attr_legacy_mem_type.attr, | |
283 | &dev_attr_legacy_edac_mode.attr, | |
284 | &dev_attr_legacy_size_mb.attr, | |
285 | &dev_attr_legacy_ue_count.attr, | |
286 | &dev_attr_legacy_ce_count.attr, | |
287 | NULL, | |
288 | }; | |
7c9281d7 | 289 | |
7a623c03 MCC |
290 | static struct attribute_group csrow_attr_grp = { |
291 | .attrs = csrow_attrs, | |
292 | }; | |
7c9281d7 | 293 | |
7a623c03 MCC |
294 | static const struct attribute_group *csrow_attr_groups[] = { |
295 | &csrow_attr_grp, | |
296 | NULL | |
297 | }; | |
7c9281d7 | 298 | |
de3910eb | 299 | static void csrow_attr_release(struct device *dev) |
7c9281d7 | 300 | { |
de3910eb MCC |
301 | struct csrow_info *csrow = container_of(dev, struct csrow_info, dev); |
302 | ||
956b9ba1 | 303 | edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev)); |
de3910eb | 304 | kfree(csrow); |
7c9281d7 DT |
305 | } |
306 | ||
7a623c03 MCC |
307 | static struct device_type csrow_attr_type = { |
308 | .groups = csrow_attr_groups, | |
309 | .release = csrow_attr_release, | |
7c9281d7 DT |
310 | }; |
311 | ||
7a623c03 MCC |
312 | /* |
313 | * possible dynamic channel DIMM Label attribute files | |
314 | * | |
315 | */ | |
7a623c03 | 316 | DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 317 | channel_dimm_label_show, channel_dimm_label_store, 0); |
7a623c03 | 318 | DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 319 | channel_dimm_label_show, channel_dimm_label_store, 1); |
7a623c03 | 320 | DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 321 | channel_dimm_label_show, channel_dimm_label_store, 2); |
7a623c03 | 322 | DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 323 | channel_dimm_label_show, channel_dimm_label_store, 3); |
7a623c03 | 324 | DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 325 | channel_dimm_label_show, channel_dimm_label_store, 4); |
7a623c03 | 326 | DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 327 | channel_dimm_label_show, channel_dimm_label_store, 5); |
bba14295 BP |
328 | DEVICE_CHANNEL(ch6_dimm_label, S_IRUGO | S_IWUSR, |
329 | channel_dimm_label_show, channel_dimm_label_store, 6); | |
330 | DEVICE_CHANNEL(ch7_dimm_label, S_IRUGO | S_IWUSR, | |
331 | channel_dimm_label_show, channel_dimm_label_store, 7); | |
7c9281d7 DT |
332 | |
333 | /* Total possible dynamic DIMM Label attribute file table */ | |
2c1946b6 TI |
334 | static struct attribute *dynamic_csrow_dimm_attr[] = { |
335 | &dev_attr_legacy_ch0_dimm_label.attr.attr, | |
336 | &dev_attr_legacy_ch1_dimm_label.attr.attr, | |
337 | &dev_attr_legacy_ch2_dimm_label.attr.attr, | |
338 | &dev_attr_legacy_ch3_dimm_label.attr.attr, | |
339 | &dev_attr_legacy_ch4_dimm_label.attr.attr, | |
340 | &dev_attr_legacy_ch5_dimm_label.attr.attr, | |
bba14295 BP |
341 | &dev_attr_legacy_ch6_dimm_label.attr.attr, |
342 | &dev_attr_legacy_ch7_dimm_label.attr.attr, | |
2c1946b6 | 343 | NULL |
7c9281d7 DT |
344 | }; |
345 | ||
346 | /* possible dynamic channel ce_count attribute files */ | |
c8c64d16 | 347 | DEVICE_CHANNEL(ch0_ce_count, S_IRUGO, |
7a623c03 | 348 | channel_ce_count_show, NULL, 0); |
c8c64d16 | 349 | DEVICE_CHANNEL(ch1_ce_count, S_IRUGO, |
7a623c03 | 350 | channel_ce_count_show, NULL, 1); |
c8c64d16 | 351 | DEVICE_CHANNEL(ch2_ce_count, S_IRUGO, |
7a623c03 | 352 | channel_ce_count_show, NULL, 2); |
c8c64d16 | 353 | DEVICE_CHANNEL(ch3_ce_count, S_IRUGO, |
7a623c03 | 354 | channel_ce_count_show, NULL, 3); |
c8c64d16 | 355 | DEVICE_CHANNEL(ch4_ce_count, S_IRUGO, |
7a623c03 | 356 | channel_ce_count_show, NULL, 4); |
c8c64d16 | 357 | DEVICE_CHANNEL(ch5_ce_count, S_IRUGO, |
7a623c03 | 358 | channel_ce_count_show, NULL, 5); |
bba14295 BP |
359 | DEVICE_CHANNEL(ch6_ce_count, S_IRUGO, |
360 | channel_ce_count_show, NULL, 6); | |
361 | DEVICE_CHANNEL(ch7_ce_count, S_IRUGO, | |
362 | channel_ce_count_show, NULL, 7); | |
7c9281d7 DT |
363 | |
364 | /* Total possible dynamic ce_count attribute file table */ | |
2c1946b6 TI |
365 | static struct attribute *dynamic_csrow_ce_count_attr[] = { |
366 | &dev_attr_legacy_ch0_ce_count.attr.attr, | |
367 | &dev_attr_legacy_ch1_ce_count.attr.attr, | |
368 | &dev_attr_legacy_ch2_ce_count.attr.attr, | |
369 | &dev_attr_legacy_ch3_ce_count.attr.attr, | |
370 | &dev_attr_legacy_ch4_ce_count.attr.attr, | |
371 | &dev_attr_legacy_ch5_ce_count.attr.attr, | |
bba14295 BP |
372 | &dev_attr_legacy_ch6_ce_count.attr.attr, |
373 | &dev_attr_legacy_ch7_ce_count.attr.attr, | |
2c1946b6 TI |
374 | NULL |
375 | }; | |
376 | ||
377 | static umode_t csrow_dev_is_visible(struct kobject *kobj, | |
378 | struct attribute *attr, int idx) | |
379 | { | |
380 | struct device *dev = kobj_to_dev(kobj); | |
381 | struct csrow_info *csrow = container_of(dev, struct csrow_info, dev); | |
382 | ||
383 | if (idx >= csrow->nr_channels) | |
384 | return 0; | |
bba14295 BP |
385 | |
386 | if (idx >= ARRAY_SIZE(dynamic_csrow_ce_count_attr) - 1) { | |
387 | WARN_ONCE(1, "idx: %d\n", idx); | |
388 | return 0; | |
389 | } | |
390 | ||
2c1946b6 TI |
391 | /* Only expose populated DIMMs */ |
392 | if (!csrow->channels[idx]->dimm->nr_pages) | |
393 | return 0; | |
bba14295 | 394 | |
2c1946b6 TI |
395 | return attr->mode; |
396 | } | |
397 | ||
398 | ||
399 | static const struct attribute_group csrow_dev_dimm_group = { | |
400 | .attrs = dynamic_csrow_dimm_attr, | |
401 | .is_visible = csrow_dev_is_visible, | |
402 | }; | |
403 | ||
404 | static const struct attribute_group csrow_dev_ce_count_group = { | |
405 | .attrs = dynamic_csrow_ce_count_attr, | |
406 | .is_visible = csrow_dev_is_visible, | |
407 | }; | |
408 | ||
409 | static const struct attribute_group *csrow_dev_groups[] = { | |
410 | &csrow_dev_dimm_group, | |
411 | &csrow_dev_ce_count_group, | |
412 | NULL | |
7c9281d7 DT |
413 | }; |
414 | ||
e39f4ea9 MCC |
415 | static inline int nr_pages_per_csrow(struct csrow_info *csrow) |
416 | { | |
417 | int chan, nr_pages = 0; | |
418 | ||
419 | for (chan = 0; chan < csrow->nr_channels; chan++) | |
de3910eb | 420 | nr_pages += csrow->channels[chan]->dimm->nr_pages; |
e39f4ea9 MCC |
421 | |
422 | return nr_pages; | |
423 | } | |
424 | ||
7a623c03 MCC |
425 | /* Create a CSROW object under specifed edac_mc_device */ |
426 | static int edac_create_csrow_object(struct mem_ctl_info *mci, | |
427 | struct csrow_info *csrow, int index) | |
7c9281d7 | 428 | { |
7a623c03 | 429 | csrow->dev.type = &csrow_attr_type; |
88d84ac9 | 430 | csrow->dev.bus = mci->bus; |
2c1946b6 | 431 | csrow->dev.groups = csrow_dev_groups; |
7a623c03 MCC |
432 | device_initialize(&csrow->dev); |
433 | csrow->dev.parent = &mci->dev; | |
921a6899 | 434 | csrow->mci = mci; |
7a623c03 MCC |
435 | dev_set_name(&csrow->dev, "csrow%d", index); |
436 | dev_set_drvdata(&csrow->dev, csrow); | |
7c9281d7 | 437 | |
956b9ba1 JP |
438 | edac_dbg(0, "creating (virtual) csrow node %s\n", |
439 | dev_name(&csrow->dev)); | |
7c9281d7 | 440 | |
2c1946b6 | 441 | return device_add(&csrow->dev); |
7a623c03 | 442 | } |
7c9281d7 DT |
443 | |
444 | /* Create a CSROW object under specifed edac_mc_device */ | |
7a623c03 | 445 | static int edac_create_csrow_objects(struct mem_ctl_info *mci) |
7c9281d7 | 446 | { |
2c1946b6 | 447 | int err, i; |
7a623c03 | 448 | struct csrow_info *csrow; |
7c9281d7 | 449 | |
7a623c03 | 450 | for (i = 0; i < mci->nr_csrows; i++) { |
de3910eb | 451 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
452 | if (!nr_pages_per_csrow(csrow)) |
453 | continue; | |
de3910eb | 454 | err = edac_create_csrow_object(mci, mci->csrows[i], i); |
3d958823 MCC |
455 | if (err < 0) { |
456 | edac_dbg(1, | |
457 | "failure: create csrow objects for csrow %d\n", | |
458 | i); | |
7a623c03 | 459 | goto error; |
3d958823 | 460 | } |
7a623c03 MCC |
461 | } |
462 | return 0; | |
8096cfaf | 463 | |
7a623c03 MCC |
464 | error: |
465 | for (--i; i >= 0; i--) { | |
de3910eb | 466 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
467 | if (!nr_pages_per_csrow(csrow)) |
468 | continue; | |
de3910eb | 469 | put_device(&mci->csrows[i]->dev); |
8096cfaf | 470 | } |
7c9281d7 | 471 | |
7a623c03 MCC |
472 | return err; |
473 | } | |
8096cfaf | 474 | |
7a623c03 MCC |
475 | static void edac_delete_csrow_objects(struct mem_ctl_info *mci) |
476 | { | |
2c1946b6 | 477 | int i; |
7a623c03 | 478 | struct csrow_info *csrow; |
8096cfaf | 479 | |
7a623c03 | 480 | for (i = mci->nr_csrows - 1; i >= 0; i--) { |
de3910eb | 481 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
482 | if (!nr_pages_per_csrow(csrow)) |
483 | continue; | |
44d22e24 | 484 | device_unregister(&mci->csrows[i]->dev); |
7c9281d7 | 485 | } |
7c9281d7 | 486 | } |
19974710 MCC |
487 | #endif |
488 | ||
489 | /* | |
490 | * Per-dimm (or per-rank) devices | |
491 | */ | |
492 | ||
493 | #define to_dimm(k) container_of(k, struct dimm_info, dev) | |
494 | ||
495 | /* show/store functions for DIMM Label attributes */ | |
496 | static ssize_t dimmdev_location_show(struct device *dev, | |
497 | struct device_attribute *mattr, char *data) | |
498 | { | |
499 | struct dimm_info *dimm = to_dimm(dev); | |
19974710 | 500 | |
6e84d359 | 501 | return edac_dimm_info_location(dimm, data, PAGE_SIZE); |
19974710 MCC |
502 | } |
503 | ||
504 | static ssize_t dimmdev_label_show(struct device *dev, | |
505 | struct device_attribute *mattr, char *data) | |
506 | { | |
507 | struct dimm_info *dimm = to_dimm(dev); | |
508 | ||
509 | /* if field has not been initialized, there is nothing to send */ | |
510 | if (!dimm->label[0]) | |
511 | return 0; | |
512 | ||
1ea62c59 | 513 | return snprintf(data, sizeof(dimm->label) + 1, "%s\n", dimm->label); |
19974710 MCC |
514 | } |
515 | ||
516 | static ssize_t dimmdev_label_store(struct device *dev, | |
517 | struct device_attribute *mattr, | |
518 | const char *data, | |
519 | size_t count) | |
520 | { | |
521 | struct dimm_info *dimm = to_dimm(dev); | |
438470b8 | 522 | size_t copy_count = count; |
19974710 | 523 | |
438470b8 TK |
524 | if (count == 0) |
525 | return -EINVAL; | |
526 | ||
527 | if (data[count - 1] == '\0' || data[count - 1] == '\n') | |
528 | copy_count -= 1; | |
529 | ||
d0c9c930 | 530 | if (copy_count == 0 || copy_count >= sizeof(dimm->label)) |
438470b8 | 531 | return -EINVAL; |
19974710 | 532 | |
438470b8 TK |
533 | strncpy(dimm->label, data, copy_count); |
534 | dimm->label[copy_count] = '\0'; | |
19974710 | 535 | |
438470b8 | 536 | return count; |
19974710 MCC |
537 | } |
538 | ||
539 | static ssize_t dimmdev_size_show(struct device *dev, | |
540 | struct device_attribute *mattr, char *data) | |
541 | { | |
542 | struct dimm_info *dimm = to_dimm(dev); | |
543 | ||
544 | return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages)); | |
545 | } | |
546 | ||
547 | static ssize_t dimmdev_mem_type_show(struct device *dev, | |
548 | struct device_attribute *mattr, char *data) | |
549 | { | |
550 | struct dimm_info *dimm = to_dimm(dev); | |
551 | ||
552 | return sprintf(data, "%s\n", mem_types[dimm->mtype]); | |
553 | } | |
554 | ||
555 | static ssize_t dimmdev_dev_type_show(struct device *dev, | |
556 | struct device_attribute *mattr, char *data) | |
557 | { | |
558 | struct dimm_info *dimm = to_dimm(dev); | |
559 | ||
560 | return sprintf(data, "%s\n", dev_types[dimm->dtype]); | |
561 | } | |
562 | ||
563 | static ssize_t dimmdev_edac_mode_show(struct device *dev, | |
564 | struct device_attribute *mattr, | |
565 | char *data) | |
566 | { | |
567 | struct dimm_info *dimm = to_dimm(dev); | |
568 | ||
569 | return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]); | |
570 | } | |
571 | ||
572 | /* dimm/rank attribute files */ | |
573 | static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR, | |
574 | dimmdev_label_show, dimmdev_label_store); | |
575 | static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL); | |
576 | static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL); | |
577 | static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL); | |
578 | static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL); | |
579 | static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL); | |
580 | ||
581 | /* attributes of the dimm<id>/rank<id> object */ | |
582 | static struct attribute *dimm_attrs[] = { | |
583 | &dev_attr_dimm_label.attr, | |
584 | &dev_attr_dimm_location.attr, | |
585 | &dev_attr_size.attr, | |
586 | &dev_attr_dimm_mem_type.attr, | |
587 | &dev_attr_dimm_dev_type.attr, | |
588 | &dev_attr_dimm_edac_mode.attr, | |
589 | NULL, | |
590 | }; | |
591 | ||
592 | static struct attribute_group dimm_attr_grp = { | |
593 | .attrs = dimm_attrs, | |
594 | }; | |
595 | ||
596 | static const struct attribute_group *dimm_attr_groups[] = { | |
597 | &dimm_attr_grp, | |
598 | NULL | |
599 | }; | |
600 | ||
de3910eb | 601 | static void dimm_attr_release(struct device *dev) |
19974710 | 602 | { |
de3910eb MCC |
603 | struct dimm_info *dimm = container_of(dev, struct dimm_info, dev); |
604 | ||
956b9ba1 | 605 | edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev)); |
de3910eb | 606 | kfree(dimm); |
19974710 MCC |
607 | } |
608 | ||
609 | static struct device_type dimm_attr_type = { | |
610 | .groups = dimm_attr_groups, | |
611 | .release = dimm_attr_release, | |
612 | }; | |
613 | ||
614 | /* Create a DIMM object under specifed memory controller device */ | |
615 | static int edac_create_dimm_object(struct mem_ctl_info *mci, | |
616 | struct dimm_info *dimm, | |
617 | int index) | |
618 | { | |
619 | int err; | |
620 | dimm->mci = mci; | |
621 | ||
622 | dimm->dev.type = &dimm_attr_type; | |
88d84ac9 | 623 | dimm->dev.bus = mci->bus; |
19974710 MCC |
624 | device_initialize(&dimm->dev); |
625 | ||
626 | dimm->dev.parent = &mci->dev; | |
9713faec | 627 | if (mci->csbased) |
19974710 MCC |
628 | dev_set_name(&dimm->dev, "rank%d", index); |
629 | else | |
630 | dev_set_name(&dimm->dev, "dimm%d", index); | |
631 | dev_set_drvdata(&dimm->dev, dimm); | |
632 | pm_runtime_forbid(&mci->dev); | |
633 | ||
634 | err = device_add(&dimm->dev); | |
635 | ||
956b9ba1 | 636 | edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev)); |
19974710 MCC |
637 | |
638 | return err; | |
639 | } | |
7c9281d7 | 640 | |
7a623c03 MCC |
641 | /* |
642 | * Memory controller device | |
643 | */ | |
644 | ||
645 | #define to_mci(k) container_of(k, struct mem_ctl_info, dev) | |
7c9281d7 | 646 | |
7a623c03 MCC |
647 | static ssize_t mci_reset_counters_store(struct device *dev, |
648 | struct device_attribute *mattr, | |
079708b9 | 649 | const char *data, size_t count) |
7c9281d7 | 650 | { |
7a623c03 MCC |
651 | struct mem_ctl_info *mci = to_mci(dev); |
652 | int cnt, row, chan, i; | |
5926ff50 MCC |
653 | mci->ue_mc = 0; |
654 | mci->ce_mc = 0; | |
7a623c03 MCC |
655 | mci->ue_noinfo_count = 0; |
656 | mci->ce_noinfo_count = 0; | |
7c9281d7 DT |
657 | |
658 | for (row = 0; row < mci->nr_csrows; row++) { | |
de3910eb | 659 | struct csrow_info *ri = mci->csrows[row]; |
7c9281d7 DT |
660 | |
661 | ri->ue_count = 0; | |
662 | ri->ce_count = 0; | |
663 | ||
664 | for (chan = 0; chan < ri->nr_channels; chan++) | |
de3910eb | 665 | ri->channels[chan]->ce_count = 0; |
7c9281d7 DT |
666 | } |
667 | ||
7a623c03 MCC |
668 | cnt = 1; |
669 | for (i = 0; i < mci->n_layers; i++) { | |
670 | cnt *= mci->layers[i].size; | |
671 | memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32)); | |
672 | memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32)); | |
673 | } | |
674 | ||
7c9281d7 DT |
675 | mci->start_time = jiffies; |
676 | return count; | |
677 | } | |
678 | ||
39094443 BP |
679 | /* Memory scrubbing interface: |
680 | * | |
681 | * A MC driver can limit the scrubbing bandwidth based on the CPU type. | |
682 | * Therefore, ->set_sdram_scrub_rate should be made to return the actual | |
683 | * bandwidth that is accepted or 0 when scrubbing is to be disabled. | |
684 | * | |
685 | * Negative value still means that an error has occurred while setting | |
686 | * the scrub rate. | |
687 | */ | |
7a623c03 MCC |
688 | static ssize_t mci_sdram_scrub_rate_store(struct device *dev, |
689 | struct device_attribute *mattr, | |
eba042a8 | 690 | const char *data, size_t count) |
7c9281d7 | 691 | { |
7a623c03 | 692 | struct mem_ctl_info *mci = to_mci(dev); |
eba042a8 | 693 | unsigned long bandwidth = 0; |
39094443 | 694 | int new_bw = 0; |
7c9281d7 | 695 | |
c7f62fc8 | 696 | if (kstrtoul(data, 10, &bandwidth) < 0) |
eba042a8 | 697 | return -EINVAL; |
7c9281d7 | 698 | |
39094443 | 699 | new_bw = mci->set_sdram_scrub_rate(mci, bandwidth); |
4949603a MT |
700 | if (new_bw < 0) { |
701 | edac_printk(KERN_WARNING, EDAC_MC, | |
702 | "Error setting scrub rate to: %lu\n", bandwidth); | |
703 | return -EINVAL; | |
7c9281d7 | 704 | } |
39094443 | 705 | |
4949603a | 706 | return count; |
7c9281d7 DT |
707 | } |
708 | ||
39094443 BP |
709 | /* |
710 | * ->get_sdram_scrub_rate() return value semantics same as above. | |
711 | */ | |
7a623c03 MCC |
712 | static ssize_t mci_sdram_scrub_rate_show(struct device *dev, |
713 | struct device_attribute *mattr, | |
714 | char *data) | |
7c9281d7 | 715 | { |
7a623c03 | 716 | struct mem_ctl_info *mci = to_mci(dev); |
39094443 | 717 | int bandwidth = 0; |
eba042a8 | 718 | |
39094443 BP |
719 | bandwidth = mci->get_sdram_scrub_rate(mci); |
720 | if (bandwidth < 0) { | |
eba042a8 | 721 | edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n"); |
39094443 | 722 | return bandwidth; |
7c9281d7 | 723 | } |
39094443 | 724 | |
39094443 | 725 | return sprintf(data, "%d\n", bandwidth); |
7c9281d7 DT |
726 | } |
727 | ||
728 | /* default attribute files for the MCI object */ | |
7a623c03 MCC |
729 | static ssize_t mci_ue_count_show(struct device *dev, |
730 | struct device_attribute *mattr, | |
731 | char *data) | |
7c9281d7 | 732 | { |
7a623c03 MCC |
733 | struct mem_ctl_info *mci = to_mci(dev); |
734 | ||
5926ff50 | 735 | return sprintf(data, "%d\n", mci->ue_mc); |
7c9281d7 DT |
736 | } |
737 | ||
7a623c03 MCC |
738 | static ssize_t mci_ce_count_show(struct device *dev, |
739 | struct device_attribute *mattr, | |
740 | char *data) | |
7c9281d7 | 741 | { |
7a623c03 MCC |
742 | struct mem_ctl_info *mci = to_mci(dev); |
743 | ||
5926ff50 | 744 | return sprintf(data, "%d\n", mci->ce_mc); |
7c9281d7 DT |
745 | } |
746 | ||
7a623c03 MCC |
747 | static ssize_t mci_ce_noinfo_show(struct device *dev, |
748 | struct device_attribute *mattr, | |
749 | char *data) | |
7c9281d7 | 750 | { |
7a623c03 MCC |
751 | struct mem_ctl_info *mci = to_mci(dev); |
752 | ||
079708b9 | 753 | return sprintf(data, "%d\n", mci->ce_noinfo_count); |
7c9281d7 DT |
754 | } |
755 | ||
7a623c03 MCC |
756 | static ssize_t mci_ue_noinfo_show(struct device *dev, |
757 | struct device_attribute *mattr, | |
758 | char *data) | |
7c9281d7 | 759 | { |
7a623c03 MCC |
760 | struct mem_ctl_info *mci = to_mci(dev); |
761 | ||
079708b9 | 762 | return sprintf(data, "%d\n", mci->ue_noinfo_count); |
7c9281d7 DT |
763 | } |
764 | ||
7a623c03 MCC |
765 | static ssize_t mci_seconds_show(struct device *dev, |
766 | struct device_attribute *mattr, | |
767 | char *data) | |
7c9281d7 | 768 | { |
7a623c03 MCC |
769 | struct mem_ctl_info *mci = to_mci(dev); |
770 | ||
079708b9 | 771 | return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ); |
7c9281d7 DT |
772 | } |
773 | ||
7a623c03 MCC |
774 | static ssize_t mci_ctl_name_show(struct device *dev, |
775 | struct device_attribute *mattr, | |
776 | char *data) | |
7c9281d7 | 777 | { |
7a623c03 MCC |
778 | struct mem_ctl_info *mci = to_mci(dev); |
779 | ||
079708b9 | 780 | return sprintf(data, "%s\n", mci->ctl_name); |
7c9281d7 DT |
781 | } |
782 | ||
7a623c03 MCC |
783 | static ssize_t mci_size_mb_show(struct device *dev, |
784 | struct device_attribute *mattr, | |
785 | char *data) | |
7c9281d7 | 786 | { |
7a623c03 | 787 | struct mem_ctl_info *mci = to_mci(dev); |
a895bf8b | 788 | int total_pages = 0, csrow_idx, j; |
7c9281d7 | 789 | |
a895bf8b | 790 | for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) { |
de3910eb | 791 | struct csrow_info *csrow = mci->csrows[csrow_idx]; |
7c9281d7 | 792 | |
1eef1282 MCC |
793 | for (j = 0; j < csrow->nr_channels; j++) { |
794 | struct dimm_info *dimm = csrow->channels[j]->dimm; | |
3c062276 | 795 | |
1eef1282 | 796 | total_pages += dimm->nr_pages; |
a895bf8b | 797 | } |
7c9281d7 DT |
798 | } |
799 | ||
079708b9 | 800 | return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages)); |
7c9281d7 DT |
801 | } |
802 | ||
8ad6c78a MCC |
803 | static ssize_t mci_max_location_show(struct device *dev, |
804 | struct device_attribute *mattr, | |
805 | char *data) | |
806 | { | |
807 | struct mem_ctl_info *mci = to_mci(dev); | |
808 | int i; | |
809 | char *p = data; | |
810 | ||
811 | for (i = 0; i < mci->n_layers; i++) { | |
812 | p += sprintf(p, "%s %d ", | |
813 | edac_layer_name[mci->layers[i].type], | |
814 | mci->layers[i].size - 1); | |
815 | } | |
816 | ||
817 | return p - data; | |
818 | } | |
819 | ||
7c9281d7 | 820 | /* default Control file */ |
f11135d8 | 821 | static DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store); |
7c9281d7 DT |
822 | |
823 | /* default Attribute files */ | |
f11135d8 BP |
824 | static DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL); |
825 | static DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL); | |
826 | static DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL); | |
827 | static DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL); | |
828 | static DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL); | |
829 | static DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL); | |
830 | static DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL); | |
831 | static DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL); | |
7c9281d7 DT |
832 | |
833 | /* memory scrubber attribute file */ | |
2c1946b6 TI |
834 | DEVICE_ATTR(sdram_scrub_rate, 0, mci_sdram_scrub_rate_show, |
835 | mci_sdram_scrub_rate_store); /* umode set later in is_visible */ | |
7c9281d7 | 836 | |
7a623c03 MCC |
837 | static struct attribute *mci_attrs[] = { |
838 | &dev_attr_reset_counters.attr, | |
839 | &dev_attr_mc_name.attr, | |
840 | &dev_attr_size_mb.attr, | |
841 | &dev_attr_seconds_since_reset.attr, | |
842 | &dev_attr_ue_noinfo_count.attr, | |
843 | &dev_attr_ce_noinfo_count.attr, | |
844 | &dev_attr_ue_count.attr, | |
845 | &dev_attr_ce_count.attr, | |
8ad6c78a | 846 | &dev_attr_max_location.attr, |
2c1946b6 | 847 | &dev_attr_sdram_scrub_rate.attr, |
7c9281d7 DT |
848 | NULL |
849 | }; | |
850 | ||
2c1946b6 TI |
851 | static umode_t mci_attr_is_visible(struct kobject *kobj, |
852 | struct attribute *attr, int idx) | |
853 | { | |
854 | struct device *dev = kobj_to_dev(kobj); | |
855 | struct mem_ctl_info *mci = to_mci(dev); | |
856 | umode_t mode = 0; | |
857 | ||
858 | if (attr != &dev_attr_sdram_scrub_rate.attr) | |
859 | return attr->mode; | |
860 | if (mci->get_sdram_scrub_rate) | |
861 | mode |= S_IRUGO; | |
862 | if (mci->set_sdram_scrub_rate) | |
863 | mode |= S_IWUSR; | |
864 | return mode; | |
865 | } | |
866 | ||
7a623c03 MCC |
867 | static struct attribute_group mci_attr_grp = { |
868 | .attrs = mci_attrs, | |
2c1946b6 | 869 | .is_visible = mci_attr_is_visible, |
cc301b3a MCC |
870 | }; |
871 | ||
7a623c03 MCC |
872 | static const struct attribute_group *mci_attr_groups[] = { |
873 | &mci_attr_grp, | |
874 | NULL | |
cc301b3a MCC |
875 | }; |
876 | ||
de3910eb | 877 | static void mci_attr_release(struct device *dev) |
42a8e397 | 878 | { |
de3910eb MCC |
879 | struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev); |
880 | ||
956b9ba1 | 881 | edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev)); |
de3910eb | 882 | kfree(mci); |
42a8e397 DT |
883 | } |
884 | ||
7a623c03 MCC |
885 | static struct device_type mci_attr_type = { |
886 | .groups = mci_attr_groups, | |
887 | .release = mci_attr_release, | |
888 | }; | |
8096cfaf | 889 | |
7c9281d7 DT |
890 | /* |
891 | * Create a new Memory Controller kobject instance, | |
892 | * mc<id> under the 'mc' directory | |
893 | * | |
894 | * Return: | |
895 | * 0 Success | |
896 | * !0 Failure | |
897 | */ | |
4e8d230d TI |
898 | int edac_create_sysfs_mci_device(struct mem_ctl_info *mci, |
899 | const struct attribute_group **groups) | |
7c9281d7 | 900 | { |
12e26969 | 901 | char *name; |
7a623c03 | 902 | int i, err; |
7c9281d7 | 903 | |
de3910eb MCC |
904 | /* |
905 | * The memory controller needs its own bus, in order to avoid | |
906 | * namespace conflicts at /sys/bus/edac. | |
907 | */ | |
12e26969 BP |
908 | name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx); |
909 | if (!name) | |
de3910eb | 910 | return -ENOMEM; |
88d84ac9 | 911 | |
12e26969 BP |
912 | mci->bus->name = name; |
913 | ||
88d84ac9 BP |
914 | edac_dbg(0, "creating bus %s\n", mci->bus->name); |
915 | ||
916 | err = bus_register(mci->bus); | |
12e26969 BP |
917 | if (err < 0) { |
918 | kfree(name); | |
919 | return err; | |
920 | } | |
7c9281d7 | 921 | |
7a623c03 | 922 | /* get the /sys/devices/system/edac subsys reference */ |
7a623c03 MCC |
923 | mci->dev.type = &mci_attr_type; |
924 | device_initialize(&mci->dev); | |
7c9281d7 | 925 | |
de3910eb | 926 | mci->dev.parent = mci_pdev; |
88d84ac9 | 927 | mci->dev.bus = mci->bus; |
4e8d230d | 928 | mci->dev.groups = groups; |
7a623c03 MCC |
929 | dev_set_name(&mci->dev, "mc%d", mci->mc_idx); |
930 | dev_set_drvdata(&mci->dev, mci); | |
931 | pm_runtime_forbid(&mci->dev); | |
932 | ||
956b9ba1 | 933 | edac_dbg(0, "creating device %s\n", dev_name(&mci->dev)); |
7a623c03 MCC |
934 | err = device_add(&mci->dev); |
935 | if (err < 0) { | |
3d958823 | 936 | edac_dbg(1, "failure: create device %s\n", dev_name(&mci->dev)); |
1bf1950c | 937 | goto fail_unregister_bus; |
42a8e397 DT |
938 | } |
939 | ||
7a623c03 MCC |
940 | /* |
941 | * Create the dimm/rank devices | |
7c9281d7 | 942 | */ |
7a623c03 | 943 | for (i = 0; i < mci->tot_dimms; i++) { |
de3910eb | 944 | struct dimm_info *dimm = mci->dimms[i]; |
7a623c03 | 945 | /* Only expose populated DIMMs */ |
1bf1950c | 946 | if (!dimm->nr_pages) |
7a623c03 | 947 | continue; |
1bf1950c | 948 | |
7a623c03 | 949 | #ifdef CONFIG_EDAC_DEBUG |
956b9ba1 | 950 | edac_dbg(1, "creating dimm%d, located at ", i); |
7a623c03 MCC |
951 | if (edac_debug_level >= 1) { |
952 | int lay; | |
953 | for (lay = 0; lay < mci->n_layers; lay++) | |
954 | printk(KERN_CONT "%s %d ", | |
955 | edac_layer_name[mci->layers[lay].type], | |
956 | dimm->location[lay]); | |
957 | printk(KERN_CONT "\n"); | |
7c9281d7 | 958 | } |
7a623c03 | 959 | #endif |
19974710 MCC |
960 | err = edac_create_dimm_object(mci, dimm, i); |
961 | if (err) { | |
956b9ba1 | 962 | edac_dbg(1, "failure: create dimm %d obj\n", i); |
1bf1950c | 963 | goto fail_unregister_dimm; |
19974710 | 964 | } |
7c9281d7 DT |
965 | } |
966 | ||
19974710 | 967 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 MCC |
968 | err = edac_create_csrow_objects(mci); |
969 | if (err < 0) | |
1bf1950c | 970 | goto fail_unregister_dimm; |
19974710 | 971 | #endif |
7a623c03 | 972 | |
7ac8bf9b | 973 | edac_create_debugfs_nodes(mci); |
7c9281d7 DT |
974 | return 0; |
975 | ||
1bf1950c | 976 | fail_unregister_dimm: |
079708b9 | 977 | for (i--; i >= 0; i--) { |
de3910eb | 978 | struct dimm_info *dimm = mci->dimms[i]; |
1bf1950c | 979 | if (!dimm->nr_pages) |
7a623c03 | 980 | continue; |
1bf1950c | 981 | |
44d22e24 | 982 | device_unregister(&dimm->dev); |
7c9281d7 | 983 | } |
44d22e24 | 984 | device_unregister(&mci->dev); |
1bf1950c | 985 | fail_unregister_bus: |
88d84ac9 | 986 | bus_unregister(mci->bus); |
12e26969 BP |
987 | kfree(name); |
988 | ||
7c9281d7 DT |
989 | return err; |
990 | } | |
991 | ||
992 | /* | |
993 | * remove a Memory Controller instance | |
994 | */ | |
995 | void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci) | |
996 | { | |
7a623c03 | 997 | int i; |
7c9281d7 | 998 | |
956b9ba1 | 999 | edac_dbg(0, "\n"); |
7c9281d7 | 1000 | |
452a6bf9 | 1001 | #ifdef CONFIG_EDAC_DEBUG |
30f84a89 | 1002 | edac_debugfs_remove_recursive(mci->debugfs); |
452a6bf9 | 1003 | #endif |
19974710 | 1004 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 | 1005 | edac_delete_csrow_objects(mci); |
19974710 | 1006 | #endif |
7c9281d7 | 1007 | |
7a623c03 | 1008 | for (i = 0; i < mci->tot_dimms; i++) { |
de3910eb | 1009 | struct dimm_info *dimm = mci->dimms[i]; |
7a623c03 MCC |
1010 | if (dimm->nr_pages == 0) |
1011 | continue; | |
956b9ba1 | 1012 | edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev)); |
44d22e24 | 1013 | device_unregister(&dimm->dev); |
6fe1108f | 1014 | } |
7c9281d7 | 1015 | } |
8096cfaf | 1016 | |
7a623c03 MCC |
1017 | void edac_unregister_sysfs(struct mem_ctl_info *mci) |
1018 | { | |
ab67b6c2 | 1019 | struct bus_type *bus = mci->bus; |
12e26969 BP |
1020 | const char *name = mci->bus->name; |
1021 | ||
956b9ba1 | 1022 | edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev)); |
44d22e24 | 1023 | device_unregister(&mci->dev); |
ab67b6c2 | 1024 | bus_unregister(bus); |
12e26969 | 1025 | kfree(name); |
7a623c03 | 1026 | } |
8096cfaf | 1027 | |
de3910eb | 1028 | static void mc_attr_release(struct device *dev) |
7a623c03 | 1029 | { |
de3910eb MCC |
1030 | /* |
1031 | * There's no container structure here, as this is just the mci | |
1032 | * parent device, used to create the /sys/devices/mc sysfs node. | |
1033 | * So, there are no attributes on it. | |
1034 | */ | |
956b9ba1 | 1035 | edac_dbg(1, "Releasing device %s\n", dev_name(dev)); |
de3910eb | 1036 | kfree(dev); |
7a623c03 | 1037 | } |
8096cfaf | 1038 | |
7a623c03 MCC |
1039 | static struct device_type mc_attr_type = { |
1040 | .release = mc_attr_release, | |
1041 | }; | |
8096cfaf | 1042 | /* |
7a623c03 | 1043 | * Init/exit code for the module. Basically, creates/removes /sys/class/rc |
8096cfaf | 1044 | */ |
7a623c03 | 1045 | int __init edac_mc_sysfs_init(void) |
8096cfaf | 1046 | { |
7a623c03 | 1047 | int err; |
8096cfaf | 1048 | |
de3910eb | 1049 | mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL); |
2d56b109 DK |
1050 | if (!mci_pdev) { |
1051 | err = -ENOMEM; | |
733476cf | 1052 | goto out; |
2d56b109 | 1053 | } |
de3910eb | 1054 | |
d4538000 | 1055 | mci_pdev->bus = edac_get_sysfs_subsys(); |
de3910eb MCC |
1056 | mci_pdev->type = &mc_attr_type; |
1057 | device_initialize(mci_pdev); | |
1058 | dev_set_name(mci_pdev, "mc"); | |
8096cfaf | 1059 | |
de3910eb | 1060 | err = device_add(mci_pdev); |
7a623c03 | 1061 | if (err < 0) |
2d56b109 | 1062 | goto out_dev_free; |
8096cfaf | 1063 | |
956b9ba1 | 1064 | edac_dbg(0, "device %s created\n", dev_name(mci_pdev)); |
de3910eb | 1065 | |
8096cfaf | 1066 | return 0; |
2d56b109 DK |
1067 | |
1068 | out_dev_free: | |
1069 | kfree(mci_pdev); | |
2d56b109 DK |
1070 | out: |
1071 | return err; | |
8096cfaf DT |
1072 | } |
1073 | ||
c6b97bcf | 1074 | void edac_mc_sysfs_exit(void) |
8096cfaf | 1075 | { |
44d22e24 | 1076 | device_unregister(mci_pdev); |
8096cfaf | 1077 | } |