amd64_edac: Don't pass driver name as an error parameter
[deliverable/linux.git] / drivers / edac / edac_mc_sysfs.c
CommitLineData
7c9281d7
DT
1/*
2 * edac_mc kernel module
42a8e397
DT
3 * (C) 2005-2007 Linux Networx (http://lnxi.com)
4 *
7c9281d7
DT
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
7 *
42a8e397 8 * Written Doug Thompson <norsk5@xmission.com> www.softwarebitmaker.com
7c9281d7 9 *
7a623c03
MCC
10 * (c) 2012 - Mauro Carvalho Chehab <mchehab@redhat.com>
11 * The entire API were re-written, and ported to use struct device
12 *
7c9281d7
DT
13 */
14
7c9281d7 15#include <linux/ctype.h>
5a0e3ad6 16#include <linux/slab.h>
30e1f7a8 17#include <linux/edac.h>
8096cfaf 18#include <linux/bug.h>
7a623c03 19#include <linux/pm_runtime.h>
452a6bf9 20#include <linux/uaccess.h>
7c9281d7 21
20bcb7a8 22#include "edac_core.h"
7c9281d7
DT
23#include "edac_module.h"
24
25/* MC EDAC Controls, setable by module parameter, and sysfs */
4de78c68
DJ
26static int edac_mc_log_ue = 1;
27static int edac_mc_log_ce = 1;
f044091c 28static int edac_mc_panic_on_ue;
4de78c68 29static int edac_mc_poll_msec = 1000;
7c9281d7
DT
30
31/* Getter functions for above */
4de78c68 32int edac_mc_get_log_ue(void)
7c9281d7 33{
4de78c68 34 return edac_mc_log_ue;
7c9281d7
DT
35}
36
4de78c68 37int edac_mc_get_log_ce(void)
7c9281d7 38{
4de78c68 39 return edac_mc_log_ce;
7c9281d7
DT
40}
41
4de78c68 42int edac_mc_get_panic_on_ue(void)
7c9281d7 43{
4de78c68 44 return edac_mc_panic_on_ue;
7c9281d7
DT
45}
46
81d87cb1
DJ
47/* this is temporary */
48int edac_mc_get_poll_msec(void)
49{
4de78c68 50 return edac_mc_poll_msec;
7c9281d7
DT
51}
52
096846e2
AJ
53static int edac_set_poll_msec(const char *val, struct kernel_param *kp)
54{
55 long l;
56 int ret;
57
58 if (!val)
59 return -EINVAL;
60
61 ret = strict_strtol(val, 0, &l);
62 if (ret == -EINVAL || ((int)l != l))
63 return -EINVAL;
64 *((int *)kp->arg) = l;
65
66 /* notify edac_mc engine to reset the poll period */
67 edac_mc_reset_delay_period(l);
68
69 return 0;
70}
71
7c9281d7 72/* Parameter declarations for above */
4de78c68
DJ
73module_param(edac_mc_panic_on_ue, int, 0644);
74MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on");
75module_param(edac_mc_log_ue, int, 0644);
76MODULE_PARM_DESC(edac_mc_log_ue,
079708b9 77 "Log uncorrectable error to console: 0=off 1=on");
4de78c68
DJ
78module_param(edac_mc_log_ce, int, 0644);
79MODULE_PARM_DESC(edac_mc_log_ce,
079708b9 80 "Log correctable error to console: 0=off 1=on");
096846e2
AJ
81module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int,
82 &edac_mc_poll_msec, 0644);
4de78c68 83MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds");
7c9281d7 84
de3910eb 85static struct device *mci_pdev;
7a623c03 86
7c9281d7
DT
87/*
88 * various constants for Memory Controllers
89 */
90static const char *mem_types[] = {
91 [MEM_EMPTY] = "Empty",
92 [MEM_RESERVED] = "Reserved",
93 [MEM_UNKNOWN] = "Unknown",
94 [MEM_FPM] = "FPM",
95 [MEM_EDO] = "EDO",
96 [MEM_BEDO] = "BEDO",
97 [MEM_SDR] = "Unbuffered-SDR",
98 [MEM_RDR] = "Registered-SDR",
99 [MEM_DDR] = "Unbuffered-DDR",
100 [MEM_RDDR] = "Registered-DDR",
1a9b85e6
DJ
101 [MEM_RMBS] = "RMBS",
102 [MEM_DDR2] = "Unbuffered-DDR2",
103 [MEM_FB_DDR2] = "FullyBuffered-DDR2",
1d5f726c 104 [MEM_RDDR2] = "Registered-DDR2",
b1cfebc9
YS
105 [MEM_XDR] = "XDR",
106 [MEM_DDR3] = "Unbuffered-DDR3",
107 [MEM_RDDR3] = "Registered-DDR3"
7c9281d7
DT
108};
109
110static const char *dev_types[] = {
111 [DEV_UNKNOWN] = "Unknown",
112 [DEV_X1] = "x1",
113 [DEV_X2] = "x2",
114 [DEV_X4] = "x4",
115 [DEV_X8] = "x8",
116 [DEV_X16] = "x16",
117 [DEV_X32] = "x32",
118 [DEV_X64] = "x64"
119};
120
121static const char *edac_caps[] = {
122 [EDAC_UNKNOWN] = "Unknown",
123 [EDAC_NONE] = "None",
124 [EDAC_RESERVED] = "Reserved",
125 [EDAC_PARITY] = "PARITY",
126 [EDAC_EC] = "EC",
127 [EDAC_SECDED] = "SECDED",
128 [EDAC_S2ECD2ED] = "S2ECD2ED",
129 [EDAC_S4ECD4ED] = "S4ECD4ED",
130 [EDAC_S8ECD8ED] = "S8ECD8ED",
131 [EDAC_S16ECD16ED] = "S16ECD16ED"
132};
133
19974710 134#ifdef CONFIG_EDAC_LEGACY_SYSFS
7a623c03
MCC
135/*
136 * EDAC sysfs CSROW data structures and methods
137 */
138
139#define to_csrow(k) container_of(k, struct csrow_info, dev)
140
141/*
142 * We need it to avoid namespace conflicts between the legacy API
143 * and the per-dimm/per-rank one
7c9281d7 144 */
7a623c03
MCC
145#define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \
146 struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store)
147
148struct dev_ch_attribute {
149 struct device_attribute attr;
150 int channel;
151};
152
153#define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \
154 struct dev_ch_attribute dev_attr_legacy_##_name = \
155 { __ATTR(_name, _mode, _show, _store), (_var) }
156
157#define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel)
7c9281d7
DT
158
159/* Set of more default csrow<id> attribute show/store functions */
7a623c03
MCC
160static ssize_t csrow_ue_count_show(struct device *dev,
161 struct device_attribute *mattr, char *data)
7c9281d7 162{
7a623c03
MCC
163 struct csrow_info *csrow = to_csrow(dev);
164
079708b9 165 return sprintf(data, "%u\n", csrow->ue_count);
7c9281d7
DT
166}
167
7a623c03
MCC
168static ssize_t csrow_ce_count_show(struct device *dev,
169 struct device_attribute *mattr, char *data)
7c9281d7 170{
7a623c03
MCC
171 struct csrow_info *csrow = to_csrow(dev);
172
079708b9 173 return sprintf(data, "%u\n", csrow->ce_count);
7c9281d7
DT
174}
175
7a623c03
MCC
176static ssize_t csrow_size_show(struct device *dev,
177 struct device_attribute *mattr, char *data)
7c9281d7 178{
7a623c03 179 struct csrow_info *csrow = to_csrow(dev);
a895bf8b
MCC
180 int i;
181 u32 nr_pages = 0;
182
183 for (i = 0; i < csrow->nr_channels; i++)
de3910eb 184 nr_pages += csrow->channels[i]->dimm->nr_pages;
a895bf8b 185 return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages));
7c9281d7
DT
186}
187
7a623c03
MCC
188static ssize_t csrow_mem_type_show(struct device *dev,
189 struct device_attribute *mattr, char *data)
7c9281d7 190{
7a623c03
MCC
191 struct csrow_info *csrow = to_csrow(dev);
192
de3910eb 193 return sprintf(data, "%s\n", mem_types[csrow->channels[0]->dimm->mtype]);
7c9281d7
DT
194}
195
7a623c03
MCC
196static ssize_t csrow_dev_type_show(struct device *dev,
197 struct device_attribute *mattr, char *data)
7c9281d7 198{
7a623c03
MCC
199 struct csrow_info *csrow = to_csrow(dev);
200
de3910eb 201 return sprintf(data, "%s\n", dev_types[csrow->channels[0]->dimm->dtype]);
7c9281d7
DT
202}
203
7a623c03
MCC
204static ssize_t csrow_edac_mode_show(struct device *dev,
205 struct device_attribute *mattr,
206 char *data)
7c9281d7 207{
7a623c03
MCC
208 struct csrow_info *csrow = to_csrow(dev);
209
de3910eb 210 return sprintf(data, "%s\n", edac_caps[csrow->channels[0]->dimm->edac_mode]);
7c9281d7
DT
211}
212
213/* show/store functions for DIMM Label attributes */
7a623c03
MCC
214static ssize_t channel_dimm_label_show(struct device *dev,
215 struct device_attribute *mattr,
216 char *data)
7c9281d7 217{
7a623c03
MCC
218 struct csrow_info *csrow = to_csrow(dev);
219 unsigned chan = to_channel(mattr);
de3910eb 220 struct rank_info *rank = csrow->channels[chan];
7a623c03 221
124682c7 222 /* if field has not been initialized, there is nothing to send */
7a623c03 223 if (!rank->dimm->label[0])
124682c7
AJ
224 return 0;
225
226 return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n",
7a623c03 227 rank->dimm->label);
7c9281d7
DT
228}
229
7a623c03
MCC
230static ssize_t channel_dimm_label_store(struct device *dev,
231 struct device_attribute *mattr,
232 const char *data, size_t count)
7c9281d7 233{
7a623c03
MCC
234 struct csrow_info *csrow = to_csrow(dev);
235 unsigned chan = to_channel(mattr);
de3910eb 236 struct rank_info *rank = csrow->channels[chan];
7a623c03 237
7c9281d7
DT
238 ssize_t max_size = 0;
239
079708b9 240 max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
7a623c03
MCC
241 strncpy(rank->dimm->label, data, max_size);
242 rank->dimm->label[max_size] = '\0';
7c9281d7
DT
243
244 return max_size;
245}
246
247/* show function for dynamic chX_ce_count attribute */
7a623c03
MCC
248static ssize_t channel_ce_count_show(struct device *dev,
249 struct device_attribute *mattr, char *data)
7c9281d7 250{
7a623c03
MCC
251 struct csrow_info *csrow = to_csrow(dev);
252 unsigned chan = to_channel(mattr);
de3910eb 253 struct rank_info *rank = csrow->channels[chan];
7a623c03
MCC
254
255 return sprintf(data, "%u\n", rank->ce_count);
7c9281d7
DT
256}
257
7a623c03
MCC
258/* cwrow<id>/attribute files */
259DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL);
260DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL);
261DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL);
262DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL);
263DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL);
264DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL);
7c9281d7 265
7a623c03
MCC
266/* default attributes of the CSROW<id> object */
267static struct attribute *csrow_attrs[] = {
268 &dev_attr_legacy_dev_type.attr,
269 &dev_attr_legacy_mem_type.attr,
270 &dev_attr_legacy_edac_mode.attr,
271 &dev_attr_legacy_size_mb.attr,
272 &dev_attr_legacy_ue_count.attr,
273 &dev_attr_legacy_ce_count.attr,
274 NULL,
275};
7c9281d7 276
7a623c03
MCC
277static struct attribute_group csrow_attr_grp = {
278 .attrs = csrow_attrs,
279};
7c9281d7 280
7a623c03
MCC
281static const struct attribute_group *csrow_attr_groups[] = {
282 &csrow_attr_grp,
283 NULL
284};
7c9281d7 285
de3910eb 286static void csrow_attr_release(struct device *dev)
7c9281d7 287{
de3910eb
MCC
288 struct csrow_info *csrow = container_of(dev, struct csrow_info, dev);
289
956b9ba1 290 edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
de3910eb 291 kfree(csrow);
7c9281d7
DT
292}
293
7a623c03
MCC
294static struct device_type csrow_attr_type = {
295 .groups = csrow_attr_groups,
296 .release = csrow_attr_release,
7c9281d7
DT
297};
298
7a623c03
MCC
299/*
300 * possible dynamic channel DIMM Label attribute files
301 *
302 */
7c9281d7 303
7a623c03 304#define EDAC_NR_CHANNELS 6
7c9281d7 305
7a623c03 306DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 307 channel_dimm_label_show, channel_dimm_label_store, 0);
7a623c03 308DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 309 channel_dimm_label_show, channel_dimm_label_store, 1);
7a623c03 310DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 311 channel_dimm_label_show, channel_dimm_label_store, 2);
7a623c03 312DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 313 channel_dimm_label_show, channel_dimm_label_store, 3);
7a623c03 314DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 315 channel_dimm_label_show, channel_dimm_label_store, 4);
7a623c03 316DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 317 channel_dimm_label_show, channel_dimm_label_store, 5);
7c9281d7
DT
318
319/* Total possible dynamic DIMM Label attribute file table */
7a623c03
MCC
320static struct device_attribute *dynamic_csrow_dimm_attr[] = {
321 &dev_attr_legacy_ch0_dimm_label.attr,
322 &dev_attr_legacy_ch1_dimm_label.attr,
323 &dev_attr_legacy_ch2_dimm_label.attr,
324 &dev_attr_legacy_ch3_dimm_label.attr,
325 &dev_attr_legacy_ch4_dimm_label.attr,
326 &dev_attr_legacy_ch5_dimm_label.attr
7c9281d7
DT
327};
328
329/* possible dynamic channel ce_count attribute files */
7a623c03
MCC
330DEVICE_CHANNEL(ch0_ce_count, S_IRUGO | S_IWUSR,
331 channel_ce_count_show, NULL, 0);
332DEVICE_CHANNEL(ch1_ce_count, S_IRUGO | S_IWUSR,
333 channel_ce_count_show, NULL, 1);
334DEVICE_CHANNEL(ch2_ce_count, S_IRUGO | S_IWUSR,
335 channel_ce_count_show, NULL, 2);
336DEVICE_CHANNEL(ch3_ce_count, S_IRUGO | S_IWUSR,
337 channel_ce_count_show, NULL, 3);
338DEVICE_CHANNEL(ch4_ce_count, S_IRUGO | S_IWUSR,
339 channel_ce_count_show, NULL, 4);
340DEVICE_CHANNEL(ch5_ce_count, S_IRUGO | S_IWUSR,
341 channel_ce_count_show, NULL, 5);
7c9281d7
DT
342
343/* Total possible dynamic ce_count attribute file table */
7a623c03
MCC
344static struct device_attribute *dynamic_csrow_ce_count_attr[] = {
345 &dev_attr_legacy_ch0_ce_count.attr,
346 &dev_attr_legacy_ch1_ce_count.attr,
347 &dev_attr_legacy_ch2_ce_count.attr,
348 &dev_attr_legacy_ch3_ce_count.attr,
349 &dev_attr_legacy_ch4_ce_count.attr,
350 &dev_attr_legacy_ch5_ce_count.attr
7c9281d7
DT
351};
352
e39f4ea9
MCC
353static inline int nr_pages_per_csrow(struct csrow_info *csrow)
354{
355 int chan, nr_pages = 0;
356
357 for (chan = 0; chan < csrow->nr_channels; chan++)
de3910eb 358 nr_pages += csrow->channels[chan]->dimm->nr_pages;
e39f4ea9
MCC
359
360 return nr_pages;
361}
362
7a623c03
MCC
363/* Create a CSROW object under specifed edac_mc_device */
364static int edac_create_csrow_object(struct mem_ctl_info *mci,
365 struct csrow_info *csrow, int index)
7c9281d7 366{
7a623c03 367 int err, chan;
7c9281d7 368
7a623c03
MCC
369 if (csrow->nr_channels >= EDAC_NR_CHANNELS)
370 return -ENODEV;
7c9281d7 371
7a623c03
MCC
372 csrow->dev.type = &csrow_attr_type;
373 csrow->dev.bus = &mci->bus;
374 device_initialize(&csrow->dev);
375 csrow->dev.parent = &mci->dev;
376 dev_set_name(&csrow->dev, "csrow%d", index);
377 dev_set_drvdata(&csrow->dev, csrow);
7c9281d7 378
956b9ba1
JP
379 edac_dbg(0, "creating (virtual) csrow node %s\n",
380 dev_name(&csrow->dev));
7c9281d7 381
7a623c03
MCC
382 err = device_add(&csrow->dev);
383 if (err < 0)
384 return err;
7c9281d7 385
7a623c03 386 for (chan = 0; chan < csrow->nr_channels; chan++) {
e39f4ea9 387 /* Only expose populated DIMMs */
de3910eb 388 if (!csrow->channels[chan]->dimm->nr_pages)
e39f4ea9 389 continue;
7a623c03
MCC
390 err = device_create_file(&csrow->dev,
391 dynamic_csrow_dimm_attr[chan]);
392 if (err < 0)
393 goto error;
394 err = device_create_file(&csrow->dev,
395 dynamic_csrow_ce_count_attr[chan]);
396 if (err < 0) {
397 device_remove_file(&csrow->dev,
398 dynamic_csrow_dimm_attr[chan]);
399 goto error;
400 }
401 }
8096cfaf 402
7a623c03 403 return 0;
8096cfaf 404
7a623c03
MCC
405error:
406 for (--chan; chan >= 0; chan--) {
407 device_remove_file(&csrow->dev,
408 dynamic_csrow_dimm_attr[chan]);
409 device_remove_file(&csrow->dev,
410 dynamic_csrow_ce_count_attr[chan]);
411 }
412 put_device(&csrow->dev);
7c9281d7 413
7a623c03
MCC
414 return err;
415}
7c9281d7
DT
416
417/* Create a CSROW object under specifed edac_mc_device */
7a623c03 418static int edac_create_csrow_objects(struct mem_ctl_info *mci)
7c9281d7 419{
7a623c03
MCC
420 int err, i, chan;
421 struct csrow_info *csrow;
7c9281d7 422
7a623c03 423 for (i = 0; i < mci->nr_csrows; i++) {
de3910eb 424 csrow = mci->csrows[i];
e39f4ea9
MCC
425 if (!nr_pages_per_csrow(csrow))
426 continue;
de3910eb 427 err = edac_create_csrow_object(mci, mci->csrows[i], i);
7a623c03
MCC
428 if (err < 0)
429 goto error;
430 }
431 return 0;
8096cfaf 432
7a623c03
MCC
433error:
434 for (--i; i >= 0; i--) {
de3910eb 435 csrow = mci->csrows[i];
e39f4ea9
MCC
436 if (!nr_pages_per_csrow(csrow))
437 continue;
7a623c03 438 for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
de3910eb 439 if (!csrow->channels[chan]->dimm->nr_pages)
e39f4ea9 440 continue;
7a623c03
MCC
441 device_remove_file(&csrow->dev,
442 dynamic_csrow_dimm_attr[chan]);
443 device_remove_file(&csrow->dev,
444 dynamic_csrow_ce_count_attr[chan]);
445 }
de3910eb 446 put_device(&mci->csrows[i]->dev);
8096cfaf 447 }
7c9281d7 448
7a623c03
MCC
449 return err;
450}
8096cfaf 451
7a623c03
MCC
452static void edac_delete_csrow_objects(struct mem_ctl_info *mci)
453{
454 int i, chan;
455 struct csrow_info *csrow;
8096cfaf 456
7a623c03 457 for (i = mci->nr_csrows - 1; i >= 0; i--) {
de3910eb 458 csrow = mci->csrows[i];
e39f4ea9
MCC
459 if (!nr_pages_per_csrow(csrow))
460 continue;
7a623c03 461 for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
de3910eb 462 if (!csrow->channels[chan]->dimm->nr_pages)
e39f4ea9 463 continue;
956b9ba1
JP
464 edac_dbg(1, "Removing csrow %d channel %d sysfs nodes\n",
465 i, chan);
7a623c03
MCC
466 device_remove_file(&csrow->dev,
467 dynamic_csrow_dimm_attr[chan]);
468 device_remove_file(&csrow->dev,
469 dynamic_csrow_ce_count_attr[chan]);
7c9281d7 470 }
de3910eb
MCC
471 put_device(&mci->csrows[i]->dev);
472 device_del(&mci->csrows[i]->dev);
7c9281d7 473 }
7c9281d7 474}
19974710
MCC
475#endif
476
477/*
478 * Per-dimm (or per-rank) devices
479 */
480
481#define to_dimm(k) container_of(k, struct dimm_info, dev)
482
483/* show/store functions for DIMM Label attributes */
484static ssize_t dimmdev_location_show(struct device *dev,
485 struct device_attribute *mattr, char *data)
486{
487 struct dimm_info *dimm = to_dimm(dev);
19974710 488
6e84d359 489 return edac_dimm_info_location(dimm, data, PAGE_SIZE);
19974710
MCC
490}
491
492static ssize_t dimmdev_label_show(struct device *dev,
493 struct device_attribute *mattr, char *data)
494{
495 struct dimm_info *dimm = to_dimm(dev);
496
497 /* if field has not been initialized, there is nothing to send */
498 if (!dimm->label[0])
499 return 0;
500
501 return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", dimm->label);
502}
503
504static ssize_t dimmdev_label_store(struct device *dev,
505 struct device_attribute *mattr,
506 const char *data,
507 size_t count)
508{
509 struct dimm_info *dimm = to_dimm(dev);
510
511 ssize_t max_size = 0;
512
513 max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
514 strncpy(dimm->label, data, max_size);
515 dimm->label[max_size] = '\0';
516
517 return max_size;
518}
519
520static ssize_t dimmdev_size_show(struct device *dev,
521 struct device_attribute *mattr, char *data)
522{
523 struct dimm_info *dimm = to_dimm(dev);
524
525 return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages));
526}
527
528static ssize_t dimmdev_mem_type_show(struct device *dev,
529 struct device_attribute *mattr, char *data)
530{
531 struct dimm_info *dimm = to_dimm(dev);
532
533 return sprintf(data, "%s\n", mem_types[dimm->mtype]);
534}
535
536static ssize_t dimmdev_dev_type_show(struct device *dev,
537 struct device_attribute *mattr, char *data)
538{
539 struct dimm_info *dimm = to_dimm(dev);
540
541 return sprintf(data, "%s\n", dev_types[dimm->dtype]);
542}
543
544static ssize_t dimmdev_edac_mode_show(struct device *dev,
545 struct device_attribute *mattr,
546 char *data)
547{
548 struct dimm_info *dimm = to_dimm(dev);
549
550 return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]);
551}
552
553/* dimm/rank attribute files */
554static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR,
555 dimmdev_label_show, dimmdev_label_store);
556static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL);
557static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL);
558static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL);
559static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL);
560static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL);
561
562/* attributes of the dimm<id>/rank<id> object */
563static struct attribute *dimm_attrs[] = {
564 &dev_attr_dimm_label.attr,
565 &dev_attr_dimm_location.attr,
566 &dev_attr_size.attr,
567 &dev_attr_dimm_mem_type.attr,
568 &dev_attr_dimm_dev_type.attr,
569 &dev_attr_dimm_edac_mode.attr,
570 NULL,
571};
572
573static struct attribute_group dimm_attr_grp = {
574 .attrs = dimm_attrs,
575};
576
577static const struct attribute_group *dimm_attr_groups[] = {
578 &dimm_attr_grp,
579 NULL
580};
581
de3910eb 582static void dimm_attr_release(struct device *dev)
19974710 583{
de3910eb
MCC
584 struct dimm_info *dimm = container_of(dev, struct dimm_info, dev);
585
956b9ba1 586 edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev));
de3910eb 587 kfree(dimm);
19974710
MCC
588}
589
590static struct device_type dimm_attr_type = {
591 .groups = dimm_attr_groups,
592 .release = dimm_attr_release,
593};
594
595/* Create a DIMM object under specifed memory controller device */
596static int edac_create_dimm_object(struct mem_ctl_info *mci,
597 struct dimm_info *dimm,
598 int index)
599{
600 int err;
601 dimm->mci = mci;
602
603 dimm->dev.type = &dimm_attr_type;
604 dimm->dev.bus = &mci->bus;
605 device_initialize(&dimm->dev);
606
607 dimm->dev.parent = &mci->dev;
608 if (mci->mem_is_per_rank)
609 dev_set_name(&dimm->dev, "rank%d", index);
610 else
611 dev_set_name(&dimm->dev, "dimm%d", index);
612 dev_set_drvdata(&dimm->dev, dimm);
613 pm_runtime_forbid(&mci->dev);
614
615 err = device_add(&dimm->dev);
616
956b9ba1 617 edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev));
19974710
MCC
618
619 return err;
620}
7c9281d7 621
7a623c03
MCC
622/*
623 * Memory controller device
624 */
625
626#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
7c9281d7 627
7a623c03
MCC
628static ssize_t mci_reset_counters_store(struct device *dev,
629 struct device_attribute *mattr,
079708b9 630 const char *data, size_t count)
7c9281d7 631{
7a623c03
MCC
632 struct mem_ctl_info *mci = to_mci(dev);
633 int cnt, row, chan, i;
5926ff50
MCC
634 mci->ue_mc = 0;
635 mci->ce_mc = 0;
7a623c03
MCC
636 mci->ue_noinfo_count = 0;
637 mci->ce_noinfo_count = 0;
7c9281d7
DT
638
639 for (row = 0; row < mci->nr_csrows; row++) {
de3910eb 640 struct csrow_info *ri = mci->csrows[row];
7c9281d7
DT
641
642 ri->ue_count = 0;
643 ri->ce_count = 0;
644
645 for (chan = 0; chan < ri->nr_channels; chan++)
de3910eb 646 ri->channels[chan]->ce_count = 0;
7c9281d7
DT
647 }
648
7a623c03
MCC
649 cnt = 1;
650 for (i = 0; i < mci->n_layers; i++) {
651 cnt *= mci->layers[i].size;
652 memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32));
653 memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32));
654 }
655
7c9281d7
DT
656 mci->start_time = jiffies;
657 return count;
658}
659
39094443
BP
660/* Memory scrubbing interface:
661 *
662 * A MC driver can limit the scrubbing bandwidth based on the CPU type.
663 * Therefore, ->set_sdram_scrub_rate should be made to return the actual
664 * bandwidth that is accepted or 0 when scrubbing is to be disabled.
665 *
666 * Negative value still means that an error has occurred while setting
667 * the scrub rate.
668 */
7a623c03
MCC
669static ssize_t mci_sdram_scrub_rate_store(struct device *dev,
670 struct device_attribute *mattr,
eba042a8 671 const char *data, size_t count)
7c9281d7 672{
7a623c03 673 struct mem_ctl_info *mci = to_mci(dev);
eba042a8 674 unsigned long bandwidth = 0;
39094443 675 int new_bw = 0;
7c9281d7 676
39094443 677 if (!mci->set_sdram_scrub_rate)
5e8e19bf 678 return -ENODEV;
7c9281d7 679
eba042a8
BP
680 if (strict_strtoul(data, 10, &bandwidth) < 0)
681 return -EINVAL;
7c9281d7 682
39094443 683 new_bw = mci->set_sdram_scrub_rate(mci, bandwidth);
4949603a
MT
684 if (new_bw < 0) {
685 edac_printk(KERN_WARNING, EDAC_MC,
686 "Error setting scrub rate to: %lu\n", bandwidth);
687 return -EINVAL;
7c9281d7 688 }
39094443 689
4949603a 690 return count;
7c9281d7
DT
691}
692
39094443
BP
693/*
694 * ->get_sdram_scrub_rate() return value semantics same as above.
695 */
7a623c03
MCC
696static ssize_t mci_sdram_scrub_rate_show(struct device *dev,
697 struct device_attribute *mattr,
698 char *data)
7c9281d7 699{
7a623c03 700 struct mem_ctl_info *mci = to_mci(dev);
39094443 701 int bandwidth = 0;
eba042a8 702
39094443 703 if (!mci->get_sdram_scrub_rate)
5e8e19bf 704 return -ENODEV;
eba042a8 705
39094443
BP
706 bandwidth = mci->get_sdram_scrub_rate(mci);
707 if (bandwidth < 0) {
eba042a8 708 edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n");
39094443 709 return bandwidth;
7c9281d7 710 }
39094443 711
39094443 712 return sprintf(data, "%d\n", bandwidth);
7c9281d7
DT
713}
714
715/* default attribute files for the MCI object */
7a623c03
MCC
716static ssize_t mci_ue_count_show(struct device *dev,
717 struct device_attribute *mattr,
718 char *data)
7c9281d7 719{
7a623c03
MCC
720 struct mem_ctl_info *mci = to_mci(dev);
721
5926ff50 722 return sprintf(data, "%d\n", mci->ue_mc);
7c9281d7
DT
723}
724
7a623c03
MCC
725static ssize_t mci_ce_count_show(struct device *dev,
726 struct device_attribute *mattr,
727 char *data)
7c9281d7 728{
7a623c03
MCC
729 struct mem_ctl_info *mci = to_mci(dev);
730
5926ff50 731 return sprintf(data, "%d\n", mci->ce_mc);
7c9281d7
DT
732}
733
7a623c03
MCC
734static ssize_t mci_ce_noinfo_show(struct device *dev,
735 struct device_attribute *mattr,
736 char *data)
7c9281d7 737{
7a623c03
MCC
738 struct mem_ctl_info *mci = to_mci(dev);
739
079708b9 740 return sprintf(data, "%d\n", mci->ce_noinfo_count);
7c9281d7
DT
741}
742
7a623c03
MCC
743static ssize_t mci_ue_noinfo_show(struct device *dev,
744 struct device_attribute *mattr,
745 char *data)
7c9281d7 746{
7a623c03
MCC
747 struct mem_ctl_info *mci = to_mci(dev);
748
079708b9 749 return sprintf(data, "%d\n", mci->ue_noinfo_count);
7c9281d7
DT
750}
751
7a623c03
MCC
752static ssize_t mci_seconds_show(struct device *dev,
753 struct device_attribute *mattr,
754 char *data)
7c9281d7 755{
7a623c03
MCC
756 struct mem_ctl_info *mci = to_mci(dev);
757
079708b9 758 return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ);
7c9281d7
DT
759}
760
7a623c03
MCC
761static ssize_t mci_ctl_name_show(struct device *dev,
762 struct device_attribute *mattr,
763 char *data)
7c9281d7 764{
7a623c03
MCC
765 struct mem_ctl_info *mci = to_mci(dev);
766
079708b9 767 return sprintf(data, "%s\n", mci->ctl_name);
7c9281d7
DT
768}
769
7a623c03
MCC
770static ssize_t mci_size_mb_show(struct device *dev,
771 struct device_attribute *mattr,
772 char *data)
7c9281d7 773{
7a623c03 774 struct mem_ctl_info *mci = to_mci(dev);
a895bf8b 775 int total_pages = 0, csrow_idx, j;
7c9281d7 776
a895bf8b 777 for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) {
de3910eb 778 struct csrow_info *csrow = mci->csrows[csrow_idx];
7c9281d7 779
a895bf8b 780 for (j = 0; j < csrow->nr_channels; j++) {
de3910eb 781 struct dimm_info *dimm = csrow->channels[j]->dimm;
7c9281d7 782
a895bf8b
MCC
783 total_pages += dimm->nr_pages;
784 }
7c9281d7
DT
785 }
786
079708b9 787 return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages));
7c9281d7
DT
788}
789
8ad6c78a
MCC
790static ssize_t mci_max_location_show(struct device *dev,
791 struct device_attribute *mattr,
792 char *data)
793{
794 struct mem_ctl_info *mci = to_mci(dev);
795 int i;
796 char *p = data;
797
798 for (i = 0; i < mci->n_layers; i++) {
799 p += sprintf(p, "%s %d ",
800 edac_layer_name[mci->layers[i].type],
801 mci->layers[i].size - 1);
802 }
803
804 return p - data;
805}
806
452a6bf9
MCC
807#ifdef CONFIG_EDAC_DEBUG
808static ssize_t edac_fake_inject_write(struct file *file,
809 const char __user *data,
810 size_t count, loff_t *ppos)
811{
812 struct device *dev = file->private_data;
813 struct mem_ctl_info *mci = to_mci(dev);
814 static enum hw_event_mc_err_type type;
815
816 type = mci->fake_inject_ue ? HW_EVENT_ERR_UNCORRECTED
817 : HW_EVENT_ERR_CORRECTED;
818
819 printk(KERN_DEBUG
820 "Generating a %s fake error to %d.%d.%d to test core handling. NOTE: this won't test the driver-specific decoding logic.\n",
821 (type == HW_EVENT_ERR_UNCORRECTED) ? "UE" : "CE",
822 mci->fake_inject_layer[0],
823 mci->fake_inject_layer[1],
824 mci->fake_inject_layer[2]
825 );
826 edac_mc_handle_error(type, mci, 0, 0, 0,
827 mci->fake_inject_layer[0],
828 mci->fake_inject_layer[1],
829 mci->fake_inject_layer[2],
830 "FAKE ERROR", "for EDAC testing only", NULL);
831
832 return count;
833}
834
835static int debugfs_open(struct inode *inode, struct file *file)
836{
837 file->private_data = inode->i_private;
838 return 0;
839}
840
841static const struct file_operations debug_fake_inject_fops = {
842 .open = debugfs_open,
843 .write = edac_fake_inject_write,
844 .llseek = generic_file_llseek,
845};
846#endif
847
7c9281d7 848/* default Control file */
7a623c03 849DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store);
7c9281d7
DT
850
851/* default Attribute files */
7a623c03
MCC
852DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL);
853DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL);
854DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL);
855DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL);
856DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL);
857DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL);
858DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL);
8ad6c78a 859DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL);
7c9281d7
DT
860
861/* memory scrubber attribute file */
7a623c03 862DEVICE_ATTR(sdram_scrub_rate, S_IRUGO | S_IWUSR, mci_sdram_scrub_rate_show,
052dfb45 863 mci_sdram_scrub_rate_store);
7c9281d7 864
7a623c03
MCC
865static struct attribute *mci_attrs[] = {
866 &dev_attr_reset_counters.attr,
867 &dev_attr_mc_name.attr,
868 &dev_attr_size_mb.attr,
869 &dev_attr_seconds_since_reset.attr,
870 &dev_attr_ue_noinfo_count.attr,
871 &dev_attr_ce_noinfo_count.attr,
872 &dev_attr_ue_count.attr,
873 &dev_attr_ce_count.attr,
874 &dev_attr_sdram_scrub_rate.attr,
8ad6c78a 875 &dev_attr_max_location.attr,
7c9281d7
DT
876 NULL
877};
878
7a623c03
MCC
879static struct attribute_group mci_attr_grp = {
880 .attrs = mci_attrs,
cc301b3a
MCC
881};
882
7a623c03
MCC
883static const struct attribute_group *mci_attr_groups[] = {
884 &mci_attr_grp,
885 NULL
cc301b3a
MCC
886};
887
de3910eb 888static void mci_attr_release(struct device *dev)
42a8e397 889{
de3910eb
MCC
890 struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
891
956b9ba1 892 edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
de3910eb 893 kfree(mci);
42a8e397
DT
894}
895
7a623c03
MCC
896static struct device_type mci_attr_type = {
897 .groups = mci_attr_groups,
898 .release = mci_attr_release,
899};
8096cfaf 900
452a6bf9
MCC
901#ifdef CONFIG_EDAC_DEBUG
902int edac_create_debug_nodes(struct mem_ctl_info *mci)
903{
904 struct dentry *d, *parent;
905 char name[80];
906 int i;
907
908 d = debugfs_create_dir(mci->dev.kobj.name, mci->debugfs);
909 if (!d)
910 return -ENOMEM;
911 parent = d;
912
913 for (i = 0; i < mci->n_layers; i++) {
914 sprintf(name, "fake_inject_%s",
915 edac_layer_name[mci->layers[i].type]);
916 d = debugfs_create_u8(name, S_IRUGO | S_IWUSR, parent,
917 &mci->fake_inject_layer[i]);
918 if (!d)
919 goto nomem;
920 }
921
922 d = debugfs_create_bool("fake_inject_ue", S_IRUGO | S_IWUSR, parent,
923 &mci->fake_inject_ue);
924 if (!d)
925 goto nomem;
926
927 d = debugfs_create_file("fake_inject", S_IWUSR, parent,
928 &mci->dev,
929 &debug_fake_inject_fops);
930 if (!d)
931 goto nomem;
932
933 return 0;
934nomem:
935 debugfs_remove(mci->debugfs);
936 return -ENOMEM;
937}
938#endif
939
7c9281d7
DT
940/*
941 * Create a new Memory Controller kobject instance,
942 * mc<id> under the 'mc' directory
943 *
944 * Return:
945 * 0 Success
946 * !0 Failure
947 */
948int edac_create_sysfs_mci_device(struct mem_ctl_info *mci)
949{
7a623c03 950 int i, err;
7c9281d7 951
de3910eb
MCC
952 /*
953 * The memory controller needs its own bus, in order to avoid
954 * namespace conflicts at /sys/bus/edac.
955 */
956 mci->bus.name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx);
957 if (!mci->bus.name)
958 return -ENOMEM;
956b9ba1 959 edac_dbg(0, "creating bus %s\n", mci->bus.name);
de3910eb
MCC
960 err = bus_register(&mci->bus);
961 if (err < 0)
962 return err;
7c9281d7 963
7a623c03 964 /* get the /sys/devices/system/edac subsys reference */
7a623c03
MCC
965 mci->dev.type = &mci_attr_type;
966 device_initialize(&mci->dev);
7c9281d7 967
de3910eb 968 mci->dev.parent = mci_pdev;
7a623c03
MCC
969 mci->dev.bus = &mci->bus;
970 dev_set_name(&mci->dev, "mc%d", mci->mc_idx);
971 dev_set_drvdata(&mci->dev, mci);
972 pm_runtime_forbid(&mci->dev);
973
956b9ba1 974 edac_dbg(0, "creating device %s\n", dev_name(&mci->dev));
7a623c03
MCC
975 err = device_add(&mci->dev);
976 if (err < 0) {
977 bus_unregister(&mci->bus);
978 kfree(mci->bus.name);
979 return err;
42a8e397
DT
980 }
981
7a623c03
MCC
982 /*
983 * Create the dimm/rank devices
7c9281d7 984 */
7a623c03 985 for (i = 0; i < mci->tot_dimms; i++) {
de3910eb 986 struct dimm_info *dimm = mci->dimms[i];
7a623c03
MCC
987 /* Only expose populated DIMMs */
988 if (dimm->nr_pages == 0)
989 continue;
990#ifdef CONFIG_EDAC_DEBUG
956b9ba1 991 edac_dbg(1, "creating dimm%d, located at ", i);
7a623c03
MCC
992 if (edac_debug_level >= 1) {
993 int lay;
994 for (lay = 0; lay < mci->n_layers; lay++)
995 printk(KERN_CONT "%s %d ",
996 edac_layer_name[mci->layers[lay].type],
997 dimm->location[lay]);
998 printk(KERN_CONT "\n");
7c9281d7 999 }
7a623c03 1000#endif
19974710
MCC
1001 err = edac_create_dimm_object(mci, dimm, i);
1002 if (err) {
956b9ba1 1003 edac_dbg(1, "failure: create dimm %d obj\n", i);
19974710
MCC
1004 goto fail;
1005 }
7c9281d7
DT
1006 }
1007
19974710 1008#ifdef CONFIG_EDAC_LEGACY_SYSFS
7a623c03
MCC
1009 err = edac_create_csrow_objects(mci);
1010 if (err < 0)
1011 goto fail;
19974710 1012#endif
7a623c03 1013
452a6bf9
MCC
1014#ifdef CONFIG_EDAC_DEBUG
1015 edac_create_debug_nodes(mci);
1016#endif
7c9281d7
DT
1017 return 0;
1018
7a623c03 1019fail:
079708b9 1020 for (i--; i >= 0; i--) {
de3910eb 1021 struct dimm_info *dimm = mci->dimms[i];
7a623c03
MCC
1022 if (dimm->nr_pages == 0)
1023 continue;
1024 put_device(&dimm->dev);
1025 device_del(&dimm->dev);
7c9281d7 1026 }
7a623c03
MCC
1027 put_device(&mci->dev);
1028 device_del(&mci->dev);
1029 bus_unregister(&mci->bus);
1030 kfree(mci->bus.name);
7c9281d7
DT
1031 return err;
1032}
1033
1034/*
1035 * remove a Memory Controller instance
1036 */
1037void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
1038{
7a623c03 1039 int i;
7c9281d7 1040
956b9ba1 1041 edac_dbg(0, "\n");
7c9281d7 1042
452a6bf9
MCC
1043#ifdef CONFIG_EDAC_DEBUG
1044 debugfs_remove(mci->debugfs);
1045#endif
19974710 1046#ifdef CONFIG_EDAC_LEGACY_SYSFS
7a623c03 1047 edac_delete_csrow_objects(mci);
19974710 1048#endif
7c9281d7 1049
7a623c03 1050 for (i = 0; i < mci->tot_dimms; i++) {
de3910eb 1051 struct dimm_info *dimm = mci->dimms[i];
7a623c03
MCC
1052 if (dimm->nr_pages == 0)
1053 continue;
956b9ba1 1054 edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev));
7a623c03
MCC
1055 put_device(&dimm->dev);
1056 device_del(&dimm->dev);
6fe1108f 1057 }
7c9281d7 1058}
8096cfaf 1059
7a623c03
MCC
1060void edac_unregister_sysfs(struct mem_ctl_info *mci)
1061{
956b9ba1 1062 edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev));
7a623c03
MCC
1063 put_device(&mci->dev);
1064 device_del(&mci->dev);
1065 bus_unregister(&mci->bus);
1066 kfree(mci->bus.name);
1067}
8096cfaf 1068
de3910eb 1069static void mc_attr_release(struct device *dev)
7a623c03 1070{
de3910eb
MCC
1071 /*
1072 * There's no container structure here, as this is just the mci
1073 * parent device, used to create the /sys/devices/mc sysfs node.
1074 * So, there are no attributes on it.
1075 */
956b9ba1 1076 edac_dbg(1, "Releasing device %s\n", dev_name(dev));
de3910eb 1077 kfree(dev);
7a623c03 1078}
8096cfaf 1079
7a623c03
MCC
1080static struct device_type mc_attr_type = {
1081 .release = mc_attr_release,
1082};
8096cfaf 1083/*
7a623c03 1084 * Init/exit code for the module. Basically, creates/removes /sys/class/rc
8096cfaf 1085 */
7a623c03 1086int __init edac_mc_sysfs_init(void)
8096cfaf 1087{
fe5ff8b8 1088 struct bus_type *edac_subsys;
7a623c03 1089 int err;
8096cfaf 1090
fe5ff8b8
KS
1091 /* get the /sys/devices/system/edac subsys reference */
1092 edac_subsys = edac_get_sysfs_subsys();
1093 if (edac_subsys == NULL) {
956b9ba1 1094 edac_dbg(1, "no edac_subsys\n");
7a623c03 1095 return -EINVAL;
8096cfaf
DT
1096 }
1097
de3910eb
MCC
1098 mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL);
1099
1100 mci_pdev->bus = edac_subsys;
1101 mci_pdev->type = &mc_attr_type;
1102 device_initialize(mci_pdev);
1103 dev_set_name(mci_pdev, "mc");
8096cfaf 1104
de3910eb 1105 err = device_add(mci_pdev);
7a623c03
MCC
1106 if (err < 0)
1107 return err;
8096cfaf 1108
956b9ba1 1109 edac_dbg(0, "device %s created\n", dev_name(mci_pdev));
de3910eb 1110
8096cfaf 1111 return 0;
8096cfaf
DT
1112}
1113
7a623c03 1114void __exit edac_mc_sysfs_exit(void)
8096cfaf 1115{
de3910eb
MCC
1116 put_device(mci_pdev);
1117 device_del(mci_pdev);
fe5ff8b8 1118 edac_put_sysfs_subsys();
8096cfaf 1119}
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