Commit | Line | Data |
---|---|---|
7c9281d7 DT |
1 | /* |
2 | * edac_mc kernel module | |
42a8e397 DT |
3 | * (C) 2005-2007 Linux Networx (http://lnxi.com) |
4 | * | |
7c9281d7 DT |
5 | * This file may be distributed under the terms of the |
6 | * GNU General Public License. | |
7 | * | |
42a8e397 | 8 | * Written Doug Thompson <norsk5@xmission.com> www.softwarebitmaker.com |
7c9281d7 | 9 | * |
37e59f87 | 10 | * (c) 2012-2013 - Mauro Carvalho Chehab |
7a623c03 MCC |
11 | * The entire API were re-written, and ported to use struct device |
12 | * | |
7c9281d7 DT |
13 | */ |
14 | ||
7c9281d7 | 15 | #include <linux/ctype.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
30e1f7a8 | 17 | #include <linux/edac.h> |
8096cfaf | 18 | #include <linux/bug.h> |
7a623c03 | 19 | #include <linux/pm_runtime.h> |
452a6bf9 | 20 | #include <linux/uaccess.h> |
7c9281d7 | 21 | |
20bcb7a8 | 22 | #include "edac_core.h" |
7c9281d7 DT |
23 | #include "edac_module.h" |
24 | ||
25 | /* MC EDAC Controls, setable by module parameter, and sysfs */ | |
4de78c68 DJ |
26 | static int edac_mc_log_ue = 1; |
27 | static int edac_mc_log_ce = 1; | |
f044091c | 28 | static int edac_mc_panic_on_ue; |
4de78c68 | 29 | static int edac_mc_poll_msec = 1000; |
7c9281d7 DT |
30 | |
31 | /* Getter functions for above */ | |
4de78c68 | 32 | int edac_mc_get_log_ue(void) |
7c9281d7 | 33 | { |
4de78c68 | 34 | return edac_mc_log_ue; |
7c9281d7 DT |
35 | } |
36 | ||
4de78c68 | 37 | int edac_mc_get_log_ce(void) |
7c9281d7 | 38 | { |
4de78c68 | 39 | return edac_mc_log_ce; |
7c9281d7 DT |
40 | } |
41 | ||
4de78c68 | 42 | int edac_mc_get_panic_on_ue(void) |
7c9281d7 | 43 | { |
4de78c68 | 44 | return edac_mc_panic_on_ue; |
7c9281d7 DT |
45 | } |
46 | ||
81d87cb1 DJ |
47 | /* this is temporary */ |
48 | int edac_mc_get_poll_msec(void) | |
49 | { | |
4de78c68 | 50 | return edac_mc_poll_msec; |
7c9281d7 DT |
51 | } |
52 | ||
096846e2 AJ |
53 | static int edac_set_poll_msec(const char *val, struct kernel_param *kp) |
54 | { | |
9da21b15 | 55 | unsigned long l; |
096846e2 AJ |
56 | int ret; |
57 | ||
58 | if (!val) | |
59 | return -EINVAL; | |
60 | ||
9da21b15 | 61 | ret = kstrtoul(val, 0, &l); |
c542b53d JH |
62 | if (ret) |
63 | return ret; | |
9da21b15 BP |
64 | |
65 | if (l < 1000) | |
096846e2 | 66 | return -EINVAL; |
9da21b15 BP |
67 | |
68 | *((unsigned long *)kp->arg) = l; | |
096846e2 AJ |
69 | |
70 | /* notify edac_mc engine to reset the poll period */ | |
71 | edac_mc_reset_delay_period(l); | |
72 | ||
73 | return 0; | |
74 | } | |
75 | ||
7c9281d7 | 76 | /* Parameter declarations for above */ |
4de78c68 DJ |
77 | module_param(edac_mc_panic_on_ue, int, 0644); |
78 | MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on"); | |
79 | module_param(edac_mc_log_ue, int, 0644); | |
80 | MODULE_PARM_DESC(edac_mc_log_ue, | |
079708b9 | 81 | "Log uncorrectable error to console: 0=off 1=on"); |
4de78c68 DJ |
82 | module_param(edac_mc_log_ce, int, 0644); |
83 | MODULE_PARM_DESC(edac_mc_log_ce, | |
079708b9 | 84 | "Log correctable error to console: 0=off 1=on"); |
096846e2 AJ |
85 | module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int, |
86 | &edac_mc_poll_msec, 0644); | |
4de78c68 | 87 | MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds"); |
7c9281d7 | 88 | |
de3910eb | 89 | static struct device *mci_pdev; |
7a623c03 | 90 | |
7c9281d7 DT |
91 | /* |
92 | * various constants for Memory Controllers | |
93 | */ | |
8b7719e0 | 94 | static const char * const mem_types[] = { |
7c9281d7 DT |
95 | [MEM_EMPTY] = "Empty", |
96 | [MEM_RESERVED] = "Reserved", | |
97 | [MEM_UNKNOWN] = "Unknown", | |
98 | [MEM_FPM] = "FPM", | |
99 | [MEM_EDO] = "EDO", | |
100 | [MEM_BEDO] = "BEDO", | |
101 | [MEM_SDR] = "Unbuffered-SDR", | |
102 | [MEM_RDR] = "Registered-SDR", | |
103 | [MEM_DDR] = "Unbuffered-DDR", | |
104 | [MEM_RDDR] = "Registered-DDR", | |
1a9b85e6 DJ |
105 | [MEM_RMBS] = "RMBS", |
106 | [MEM_DDR2] = "Unbuffered-DDR2", | |
107 | [MEM_FB_DDR2] = "FullyBuffered-DDR2", | |
1d5f726c | 108 | [MEM_RDDR2] = "Registered-DDR2", |
b1cfebc9 YS |
109 | [MEM_XDR] = "XDR", |
110 | [MEM_DDR3] = "Unbuffered-DDR3", | |
7b827835 AR |
111 | [MEM_RDDR3] = "Registered-DDR3", |
112 | [MEM_DDR4] = "Unbuffered-DDR4", | |
113 | [MEM_RDDR4] = "Registered-DDR4" | |
7c9281d7 DT |
114 | }; |
115 | ||
8b7719e0 | 116 | static const char * const dev_types[] = { |
7c9281d7 DT |
117 | [DEV_UNKNOWN] = "Unknown", |
118 | [DEV_X1] = "x1", | |
119 | [DEV_X2] = "x2", | |
120 | [DEV_X4] = "x4", | |
121 | [DEV_X8] = "x8", | |
122 | [DEV_X16] = "x16", | |
123 | [DEV_X32] = "x32", | |
124 | [DEV_X64] = "x64" | |
125 | }; | |
126 | ||
8b7719e0 | 127 | static const char * const edac_caps[] = { |
7c9281d7 DT |
128 | [EDAC_UNKNOWN] = "Unknown", |
129 | [EDAC_NONE] = "None", | |
130 | [EDAC_RESERVED] = "Reserved", | |
131 | [EDAC_PARITY] = "PARITY", | |
132 | [EDAC_EC] = "EC", | |
133 | [EDAC_SECDED] = "SECDED", | |
134 | [EDAC_S2ECD2ED] = "S2ECD2ED", | |
135 | [EDAC_S4ECD4ED] = "S4ECD4ED", | |
136 | [EDAC_S8ECD8ED] = "S8ECD8ED", | |
137 | [EDAC_S16ECD16ED] = "S16ECD16ED" | |
138 | }; | |
139 | ||
19974710 | 140 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 MCC |
141 | /* |
142 | * EDAC sysfs CSROW data structures and methods | |
143 | */ | |
144 | ||
145 | #define to_csrow(k) container_of(k, struct csrow_info, dev) | |
146 | ||
147 | /* | |
148 | * We need it to avoid namespace conflicts between the legacy API | |
149 | * and the per-dimm/per-rank one | |
7c9281d7 | 150 | */ |
7a623c03 | 151 | #define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \ |
fbe2d361 | 152 | static struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store) |
7a623c03 MCC |
153 | |
154 | struct dev_ch_attribute { | |
155 | struct device_attribute attr; | |
156 | int channel; | |
157 | }; | |
158 | ||
159 | #define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \ | |
f11135d8 | 160 | static struct dev_ch_attribute dev_attr_legacy_##_name = \ |
7a623c03 MCC |
161 | { __ATTR(_name, _mode, _show, _store), (_var) } |
162 | ||
163 | #define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel) | |
7c9281d7 DT |
164 | |
165 | /* Set of more default csrow<id> attribute show/store functions */ | |
7a623c03 MCC |
166 | static ssize_t csrow_ue_count_show(struct device *dev, |
167 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 168 | { |
7a623c03 MCC |
169 | struct csrow_info *csrow = to_csrow(dev); |
170 | ||
079708b9 | 171 | return sprintf(data, "%u\n", csrow->ue_count); |
7c9281d7 DT |
172 | } |
173 | ||
7a623c03 MCC |
174 | static ssize_t csrow_ce_count_show(struct device *dev, |
175 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 176 | { |
7a623c03 MCC |
177 | struct csrow_info *csrow = to_csrow(dev); |
178 | ||
079708b9 | 179 | return sprintf(data, "%u\n", csrow->ce_count); |
7c9281d7 DT |
180 | } |
181 | ||
7a623c03 MCC |
182 | static ssize_t csrow_size_show(struct device *dev, |
183 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 184 | { |
7a623c03 | 185 | struct csrow_info *csrow = to_csrow(dev); |
a895bf8b MCC |
186 | int i; |
187 | u32 nr_pages = 0; | |
188 | ||
189 | for (i = 0; i < csrow->nr_channels; i++) | |
de3910eb | 190 | nr_pages += csrow->channels[i]->dimm->nr_pages; |
a895bf8b | 191 | return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages)); |
7c9281d7 DT |
192 | } |
193 | ||
7a623c03 MCC |
194 | static ssize_t csrow_mem_type_show(struct device *dev, |
195 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 196 | { |
7a623c03 MCC |
197 | struct csrow_info *csrow = to_csrow(dev); |
198 | ||
de3910eb | 199 | return sprintf(data, "%s\n", mem_types[csrow->channels[0]->dimm->mtype]); |
7c9281d7 DT |
200 | } |
201 | ||
7a623c03 MCC |
202 | static ssize_t csrow_dev_type_show(struct device *dev, |
203 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 204 | { |
7a623c03 MCC |
205 | struct csrow_info *csrow = to_csrow(dev); |
206 | ||
de3910eb | 207 | return sprintf(data, "%s\n", dev_types[csrow->channels[0]->dimm->dtype]); |
7c9281d7 DT |
208 | } |
209 | ||
7a623c03 MCC |
210 | static ssize_t csrow_edac_mode_show(struct device *dev, |
211 | struct device_attribute *mattr, | |
212 | char *data) | |
7c9281d7 | 213 | { |
7a623c03 MCC |
214 | struct csrow_info *csrow = to_csrow(dev); |
215 | ||
de3910eb | 216 | return sprintf(data, "%s\n", edac_caps[csrow->channels[0]->dimm->edac_mode]); |
7c9281d7 DT |
217 | } |
218 | ||
219 | /* show/store functions for DIMM Label attributes */ | |
7a623c03 MCC |
220 | static ssize_t channel_dimm_label_show(struct device *dev, |
221 | struct device_attribute *mattr, | |
222 | char *data) | |
7c9281d7 | 223 | { |
7a623c03 MCC |
224 | struct csrow_info *csrow = to_csrow(dev); |
225 | unsigned chan = to_channel(mattr); | |
de3910eb | 226 | struct rank_info *rank = csrow->channels[chan]; |
7a623c03 | 227 | |
124682c7 | 228 | /* if field has not been initialized, there is nothing to send */ |
7a623c03 | 229 | if (!rank->dimm->label[0]) |
124682c7 AJ |
230 | return 0; |
231 | ||
1ea62c59 | 232 | return snprintf(data, sizeof(rank->dimm->label) + 1, "%s\n", |
7a623c03 | 233 | rank->dimm->label); |
7c9281d7 DT |
234 | } |
235 | ||
7a623c03 MCC |
236 | static ssize_t channel_dimm_label_store(struct device *dev, |
237 | struct device_attribute *mattr, | |
238 | const char *data, size_t count) | |
7c9281d7 | 239 | { |
7a623c03 MCC |
240 | struct csrow_info *csrow = to_csrow(dev); |
241 | unsigned chan = to_channel(mattr); | |
de3910eb | 242 | struct rank_info *rank = csrow->channels[chan]; |
7a623c03 | 243 | |
7c9281d7 DT |
244 | ssize_t max_size = 0; |
245 | ||
079708b9 | 246 | max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1); |
7a623c03 MCC |
247 | strncpy(rank->dimm->label, data, max_size); |
248 | rank->dimm->label[max_size] = '\0'; | |
7c9281d7 DT |
249 | |
250 | return max_size; | |
251 | } | |
252 | ||
253 | /* show function for dynamic chX_ce_count attribute */ | |
7a623c03 MCC |
254 | static ssize_t channel_ce_count_show(struct device *dev, |
255 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 256 | { |
7a623c03 MCC |
257 | struct csrow_info *csrow = to_csrow(dev); |
258 | unsigned chan = to_channel(mattr); | |
de3910eb | 259 | struct rank_info *rank = csrow->channels[chan]; |
7a623c03 MCC |
260 | |
261 | return sprintf(data, "%u\n", rank->ce_count); | |
7c9281d7 DT |
262 | } |
263 | ||
7a623c03 MCC |
264 | /* cwrow<id>/attribute files */ |
265 | DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL); | |
266 | DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL); | |
267 | DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL); | |
268 | DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL); | |
269 | DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL); | |
270 | DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL); | |
7c9281d7 | 271 | |
7a623c03 MCC |
272 | /* default attributes of the CSROW<id> object */ |
273 | static struct attribute *csrow_attrs[] = { | |
274 | &dev_attr_legacy_dev_type.attr, | |
275 | &dev_attr_legacy_mem_type.attr, | |
276 | &dev_attr_legacy_edac_mode.attr, | |
277 | &dev_attr_legacy_size_mb.attr, | |
278 | &dev_attr_legacy_ue_count.attr, | |
279 | &dev_attr_legacy_ce_count.attr, | |
280 | NULL, | |
281 | }; | |
7c9281d7 | 282 | |
7a623c03 MCC |
283 | static struct attribute_group csrow_attr_grp = { |
284 | .attrs = csrow_attrs, | |
285 | }; | |
7c9281d7 | 286 | |
7a623c03 MCC |
287 | static const struct attribute_group *csrow_attr_groups[] = { |
288 | &csrow_attr_grp, | |
289 | NULL | |
290 | }; | |
7c9281d7 | 291 | |
de3910eb | 292 | static void csrow_attr_release(struct device *dev) |
7c9281d7 | 293 | { |
de3910eb MCC |
294 | struct csrow_info *csrow = container_of(dev, struct csrow_info, dev); |
295 | ||
956b9ba1 | 296 | edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev)); |
de3910eb | 297 | kfree(csrow); |
7c9281d7 DT |
298 | } |
299 | ||
7a623c03 MCC |
300 | static struct device_type csrow_attr_type = { |
301 | .groups = csrow_attr_groups, | |
302 | .release = csrow_attr_release, | |
7c9281d7 DT |
303 | }; |
304 | ||
7a623c03 MCC |
305 | /* |
306 | * possible dynamic channel DIMM Label attribute files | |
307 | * | |
308 | */ | |
7c9281d7 | 309 | |
7a623c03 | 310 | DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 311 | channel_dimm_label_show, channel_dimm_label_store, 0); |
7a623c03 | 312 | DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 313 | channel_dimm_label_show, channel_dimm_label_store, 1); |
7a623c03 | 314 | DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 315 | channel_dimm_label_show, channel_dimm_label_store, 2); |
7a623c03 | 316 | DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 317 | channel_dimm_label_show, channel_dimm_label_store, 3); |
7a623c03 | 318 | DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 319 | channel_dimm_label_show, channel_dimm_label_store, 4); |
7a623c03 | 320 | DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 321 | channel_dimm_label_show, channel_dimm_label_store, 5); |
7c9281d7 DT |
322 | |
323 | /* Total possible dynamic DIMM Label attribute file table */ | |
2c1946b6 TI |
324 | static struct attribute *dynamic_csrow_dimm_attr[] = { |
325 | &dev_attr_legacy_ch0_dimm_label.attr.attr, | |
326 | &dev_attr_legacy_ch1_dimm_label.attr.attr, | |
327 | &dev_attr_legacy_ch2_dimm_label.attr.attr, | |
328 | &dev_attr_legacy_ch3_dimm_label.attr.attr, | |
329 | &dev_attr_legacy_ch4_dimm_label.attr.attr, | |
330 | &dev_attr_legacy_ch5_dimm_label.attr.attr, | |
331 | NULL | |
7c9281d7 DT |
332 | }; |
333 | ||
334 | /* possible dynamic channel ce_count attribute files */ | |
c8c64d16 | 335 | DEVICE_CHANNEL(ch0_ce_count, S_IRUGO, |
7a623c03 | 336 | channel_ce_count_show, NULL, 0); |
c8c64d16 | 337 | DEVICE_CHANNEL(ch1_ce_count, S_IRUGO, |
7a623c03 | 338 | channel_ce_count_show, NULL, 1); |
c8c64d16 | 339 | DEVICE_CHANNEL(ch2_ce_count, S_IRUGO, |
7a623c03 | 340 | channel_ce_count_show, NULL, 2); |
c8c64d16 | 341 | DEVICE_CHANNEL(ch3_ce_count, S_IRUGO, |
7a623c03 | 342 | channel_ce_count_show, NULL, 3); |
c8c64d16 | 343 | DEVICE_CHANNEL(ch4_ce_count, S_IRUGO, |
7a623c03 | 344 | channel_ce_count_show, NULL, 4); |
c8c64d16 | 345 | DEVICE_CHANNEL(ch5_ce_count, S_IRUGO, |
7a623c03 | 346 | channel_ce_count_show, NULL, 5); |
7c9281d7 DT |
347 | |
348 | /* Total possible dynamic ce_count attribute file table */ | |
2c1946b6 TI |
349 | static struct attribute *dynamic_csrow_ce_count_attr[] = { |
350 | &dev_attr_legacy_ch0_ce_count.attr.attr, | |
351 | &dev_attr_legacy_ch1_ce_count.attr.attr, | |
352 | &dev_attr_legacy_ch2_ce_count.attr.attr, | |
353 | &dev_attr_legacy_ch3_ce_count.attr.attr, | |
354 | &dev_attr_legacy_ch4_ce_count.attr.attr, | |
355 | &dev_attr_legacy_ch5_ce_count.attr.attr, | |
356 | NULL | |
357 | }; | |
358 | ||
359 | static umode_t csrow_dev_is_visible(struct kobject *kobj, | |
360 | struct attribute *attr, int idx) | |
361 | { | |
362 | struct device *dev = kobj_to_dev(kobj); | |
363 | struct csrow_info *csrow = container_of(dev, struct csrow_info, dev); | |
364 | ||
365 | if (idx >= csrow->nr_channels) | |
366 | return 0; | |
367 | /* Only expose populated DIMMs */ | |
368 | if (!csrow->channels[idx]->dimm->nr_pages) | |
369 | return 0; | |
370 | return attr->mode; | |
371 | } | |
372 | ||
373 | ||
374 | static const struct attribute_group csrow_dev_dimm_group = { | |
375 | .attrs = dynamic_csrow_dimm_attr, | |
376 | .is_visible = csrow_dev_is_visible, | |
377 | }; | |
378 | ||
379 | static const struct attribute_group csrow_dev_ce_count_group = { | |
380 | .attrs = dynamic_csrow_ce_count_attr, | |
381 | .is_visible = csrow_dev_is_visible, | |
382 | }; | |
383 | ||
384 | static const struct attribute_group *csrow_dev_groups[] = { | |
385 | &csrow_dev_dimm_group, | |
386 | &csrow_dev_ce_count_group, | |
387 | NULL | |
7c9281d7 DT |
388 | }; |
389 | ||
e39f4ea9 MCC |
390 | static inline int nr_pages_per_csrow(struct csrow_info *csrow) |
391 | { | |
392 | int chan, nr_pages = 0; | |
393 | ||
394 | for (chan = 0; chan < csrow->nr_channels; chan++) | |
de3910eb | 395 | nr_pages += csrow->channels[chan]->dimm->nr_pages; |
e39f4ea9 MCC |
396 | |
397 | return nr_pages; | |
398 | } | |
399 | ||
7a623c03 MCC |
400 | /* Create a CSROW object under specifed edac_mc_device */ |
401 | static int edac_create_csrow_object(struct mem_ctl_info *mci, | |
402 | struct csrow_info *csrow, int index) | |
7c9281d7 | 403 | { |
7a623c03 | 404 | csrow->dev.type = &csrow_attr_type; |
88d84ac9 | 405 | csrow->dev.bus = mci->bus; |
2c1946b6 | 406 | csrow->dev.groups = csrow_dev_groups; |
7a623c03 MCC |
407 | device_initialize(&csrow->dev); |
408 | csrow->dev.parent = &mci->dev; | |
921a6899 | 409 | csrow->mci = mci; |
7a623c03 MCC |
410 | dev_set_name(&csrow->dev, "csrow%d", index); |
411 | dev_set_drvdata(&csrow->dev, csrow); | |
7c9281d7 | 412 | |
956b9ba1 JP |
413 | edac_dbg(0, "creating (virtual) csrow node %s\n", |
414 | dev_name(&csrow->dev)); | |
7c9281d7 | 415 | |
2c1946b6 | 416 | return device_add(&csrow->dev); |
7a623c03 | 417 | } |
7c9281d7 DT |
418 | |
419 | /* Create a CSROW object under specifed edac_mc_device */ | |
7a623c03 | 420 | static int edac_create_csrow_objects(struct mem_ctl_info *mci) |
7c9281d7 | 421 | { |
2c1946b6 | 422 | int err, i; |
7a623c03 | 423 | struct csrow_info *csrow; |
7c9281d7 | 424 | |
7a623c03 | 425 | for (i = 0; i < mci->nr_csrows; i++) { |
de3910eb | 426 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
427 | if (!nr_pages_per_csrow(csrow)) |
428 | continue; | |
de3910eb | 429 | err = edac_create_csrow_object(mci, mci->csrows[i], i); |
3d958823 MCC |
430 | if (err < 0) { |
431 | edac_dbg(1, | |
432 | "failure: create csrow objects for csrow %d\n", | |
433 | i); | |
7a623c03 | 434 | goto error; |
3d958823 | 435 | } |
7a623c03 MCC |
436 | } |
437 | return 0; | |
8096cfaf | 438 | |
7a623c03 MCC |
439 | error: |
440 | for (--i; i >= 0; i--) { | |
de3910eb | 441 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
442 | if (!nr_pages_per_csrow(csrow)) |
443 | continue; | |
de3910eb | 444 | put_device(&mci->csrows[i]->dev); |
8096cfaf | 445 | } |
7c9281d7 | 446 | |
7a623c03 MCC |
447 | return err; |
448 | } | |
8096cfaf | 449 | |
7a623c03 MCC |
450 | static void edac_delete_csrow_objects(struct mem_ctl_info *mci) |
451 | { | |
2c1946b6 | 452 | int i; |
7a623c03 | 453 | struct csrow_info *csrow; |
8096cfaf | 454 | |
7a623c03 | 455 | for (i = mci->nr_csrows - 1; i >= 0; i--) { |
de3910eb | 456 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
457 | if (!nr_pages_per_csrow(csrow)) |
458 | continue; | |
44d22e24 | 459 | device_unregister(&mci->csrows[i]->dev); |
7c9281d7 | 460 | } |
7c9281d7 | 461 | } |
19974710 MCC |
462 | #endif |
463 | ||
464 | /* | |
465 | * Per-dimm (or per-rank) devices | |
466 | */ | |
467 | ||
468 | #define to_dimm(k) container_of(k, struct dimm_info, dev) | |
469 | ||
470 | /* show/store functions for DIMM Label attributes */ | |
471 | static ssize_t dimmdev_location_show(struct device *dev, | |
472 | struct device_attribute *mattr, char *data) | |
473 | { | |
474 | struct dimm_info *dimm = to_dimm(dev); | |
19974710 | 475 | |
6e84d359 | 476 | return edac_dimm_info_location(dimm, data, PAGE_SIZE); |
19974710 MCC |
477 | } |
478 | ||
479 | static ssize_t dimmdev_label_show(struct device *dev, | |
480 | struct device_attribute *mattr, char *data) | |
481 | { | |
482 | struct dimm_info *dimm = to_dimm(dev); | |
483 | ||
484 | /* if field has not been initialized, there is nothing to send */ | |
485 | if (!dimm->label[0]) | |
486 | return 0; | |
487 | ||
1ea62c59 | 488 | return snprintf(data, sizeof(dimm->label) + 1, "%s\n", dimm->label); |
19974710 MCC |
489 | } |
490 | ||
491 | static ssize_t dimmdev_label_store(struct device *dev, | |
492 | struct device_attribute *mattr, | |
493 | const char *data, | |
494 | size_t count) | |
495 | { | |
496 | struct dimm_info *dimm = to_dimm(dev); | |
497 | ||
498 | ssize_t max_size = 0; | |
499 | ||
500 | max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1); | |
501 | strncpy(dimm->label, data, max_size); | |
502 | dimm->label[max_size] = '\0'; | |
503 | ||
504 | return max_size; | |
505 | } | |
506 | ||
507 | static ssize_t dimmdev_size_show(struct device *dev, | |
508 | struct device_attribute *mattr, char *data) | |
509 | { | |
510 | struct dimm_info *dimm = to_dimm(dev); | |
511 | ||
512 | return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages)); | |
513 | } | |
514 | ||
515 | static ssize_t dimmdev_mem_type_show(struct device *dev, | |
516 | struct device_attribute *mattr, char *data) | |
517 | { | |
518 | struct dimm_info *dimm = to_dimm(dev); | |
519 | ||
520 | return sprintf(data, "%s\n", mem_types[dimm->mtype]); | |
521 | } | |
522 | ||
523 | static ssize_t dimmdev_dev_type_show(struct device *dev, | |
524 | struct device_attribute *mattr, char *data) | |
525 | { | |
526 | struct dimm_info *dimm = to_dimm(dev); | |
527 | ||
528 | return sprintf(data, "%s\n", dev_types[dimm->dtype]); | |
529 | } | |
530 | ||
531 | static ssize_t dimmdev_edac_mode_show(struct device *dev, | |
532 | struct device_attribute *mattr, | |
533 | char *data) | |
534 | { | |
535 | struct dimm_info *dimm = to_dimm(dev); | |
536 | ||
537 | return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]); | |
538 | } | |
539 | ||
540 | /* dimm/rank attribute files */ | |
541 | static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR, | |
542 | dimmdev_label_show, dimmdev_label_store); | |
543 | static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL); | |
544 | static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL); | |
545 | static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL); | |
546 | static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL); | |
547 | static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL); | |
548 | ||
549 | /* attributes of the dimm<id>/rank<id> object */ | |
550 | static struct attribute *dimm_attrs[] = { | |
551 | &dev_attr_dimm_label.attr, | |
552 | &dev_attr_dimm_location.attr, | |
553 | &dev_attr_size.attr, | |
554 | &dev_attr_dimm_mem_type.attr, | |
555 | &dev_attr_dimm_dev_type.attr, | |
556 | &dev_attr_dimm_edac_mode.attr, | |
557 | NULL, | |
558 | }; | |
559 | ||
560 | static struct attribute_group dimm_attr_grp = { | |
561 | .attrs = dimm_attrs, | |
562 | }; | |
563 | ||
564 | static const struct attribute_group *dimm_attr_groups[] = { | |
565 | &dimm_attr_grp, | |
566 | NULL | |
567 | }; | |
568 | ||
de3910eb | 569 | static void dimm_attr_release(struct device *dev) |
19974710 | 570 | { |
de3910eb MCC |
571 | struct dimm_info *dimm = container_of(dev, struct dimm_info, dev); |
572 | ||
956b9ba1 | 573 | edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev)); |
de3910eb | 574 | kfree(dimm); |
19974710 MCC |
575 | } |
576 | ||
577 | static struct device_type dimm_attr_type = { | |
578 | .groups = dimm_attr_groups, | |
579 | .release = dimm_attr_release, | |
580 | }; | |
581 | ||
582 | /* Create a DIMM object under specifed memory controller device */ | |
583 | static int edac_create_dimm_object(struct mem_ctl_info *mci, | |
584 | struct dimm_info *dimm, | |
585 | int index) | |
586 | { | |
587 | int err; | |
588 | dimm->mci = mci; | |
589 | ||
590 | dimm->dev.type = &dimm_attr_type; | |
88d84ac9 | 591 | dimm->dev.bus = mci->bus; |
19974710 MCC |
592 | device_initialize(&dimm->dev); |
593 | ||
594 | dimm->dev.parent = &mci->dev; | |
9713faec | 595 | if (mci->csbased) |
19974710 MCC |
596 | dev_set_name(&dimm->dev, "rank%d", index); |
597 | else | |
598 | dev_set_name(&dimm->dev, "dimm%d", index); | |
599 | dev_set_drvdata(&dimm->dev, dimm); | |
600 | pm_runtime_forbid(&mci->dev); | |
601 | ||
602 | err = device_add(&dimm->dev); | |
603 | ||
956b9ba1 | 604 | edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev)); |
19974710 MCC |
605 | |
606 | return err; | |
607 | } | |
7c9281d7 | 608 | |
7a623c03 MCC |
609 | /* |
610 | * Memory controller device | |
611 | */ | |
612 | ||
613 | #define to_mci(k) container_of(k, struct mem_ctl_info, dev) | |
7c9281d7 | 614 | |
7a623c03 MCC |
615 | static ssize_t mci_reset_counters_store(struct device *dev, |
616 | struct device_attribute *mattr, | |
079708b9 | 617 | const char *data, size_t count) |
7c9281d7 | 618 | { |
7a623c03 MCC |
619 | struct mem_ctl_info *mci = to_mci(dev); |
620 | int cnt, row, chan, i; | |
5926ff50 MCC |
621 | mci->ue_mc = 0; |
622 | mci->ce_mc = 0; | |
7a623c03 MCC |
623 | mci->ue_noinfo_count = 0; |
624 | mci->ce_noinfo_count = 0; | |
7c9281d7 DT |
625 | |
626 | for (row = 0; row < mci->nr_csrows; row++) { | |
de3910eb | 627 | struct csrow_info *ri = mci->csrows[row]; |
7c9281d7 DT |
628 | |
629 | ri->ue_count = 0; | |
630 | ri->ce_count = 0; | |
631 | ||
632 | for (chan = 0; chan < ri->nr_channels; chan++) | |
de3910eb | 633 | ri->channels[chan]->ce_count = 0; |
7c9281d7 DT |
634 | } |
635 | ||
7a623c03 MCC |
636 | cnt = 1; |
637 | for (i = 0; i < mci->n_layers; i++) { | |
638 | cnt *= mci->layers[i].size; | |
639 | memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32)); | |
640 | memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32)); | |
641 | } | |
642 | ||
7c9281d7 DT |
643 | mci->start_time = jiffies; |
644 | return count; | |
645 | } | |
646 | ||
39094443 BP |
647 | /* Memory scrubbing interface: |
648 | * | |
649 | * A MC driver can limit the scrubbing bandwidth based on the CPU type. | |
650 | * Therefore, ->set_sdram_scrub_rate should be made to return the actual | |
651 | * bandwidth that is accepted or 0 when scrubbing is to be disabled. | |
652 | * | |
653 | * Negative value still means that an error has occurred while setting | |
654 | * the scrub rate. | |
655 | */ | |
7a623c03 MCC |
656 | static ssize_t mci_sdram_scrub_rate_store(struct device *dev, |
657 | struct device_attribute *mattr, | |
eba042a8 | 658 | const char *data, size_t count) |
7c9281d7 | 659 | { |
7a623c03 | 660 | struct mem_ctl_info *mci = to_mci(dev); |
eba042a8 | 661 | unsigned long bandwidth = 0; |
39094443 | 662 | int new_bw = 0; |
7c9281d7 | 663 | |
c7f62fc8 | 664 | if (kstrtoul(data, 10, &bandwidth) < 0) |
eba042a8 | 665 | return -EINVAL; |
7c9281d7 | 666 | |
39094443 | 667 | new_bw = mci->set_sdram_scrub_rate(mci, bandwidth); |
4949603a MT |
668 | if (new_bw < 0) { |
669 | edac_printk(KERN_WARNING, EDAC_MC, | |
670 | "Error setting scrub rate to: %lu\n", bandwidth); | |
671 | return -EINVAL; | |
7c9281d7 | 672 | } |
39094443 | 673 | |
4949603a | 674 | return count; |
7c9281d7 DT |
675 | } |
676 | ||
39094443 BP |
677 | /* |
678 | * ->get_sdram_scrub_rate() return value semantics same as above. | |
679 | */ | |
7a623c03 MCC |
680 | static ssize_t mci_sdram_scrub_rate_show(struct device *dev, |
681 | struct device_attribute *mattr, | |
682 | char *data) | |
7c9281d7 | 683 | { |
7a623c03 | 684 | struct mem_ctl_info *mci = to_mci(dev); |
39094443 | 685 | int bandwidth = 0; |
eba042a8 | 686 | |
39094443 BP |
687 | bandwidth = mci->get_sdram_scrub_rate(mci); |
688 | if (bandwidth < 0) { | |
eba042a8 | 689 | edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n"); |
39094443 | 690 | return bandwidth; |
7c9281d7 | 691 | } |
39094443 | 692 | |
39094443 | 693 | return sprintf(data, "%d\n", bandwidth); |
7c9281d7 DT |
694 | } |
695 | ||
696 | /* default attribute files for the MCI object */ | |
7a623c03 MCC |
697 | static ssize_t mci_ue_count_show(struct device *dev, |
698 | struct device_attribute *mattr, | |
699 | char *data) | |
7c9281d7 | 700 | { |
7a623c03 MCC |
701 | struct mem_ctl_info *mci = to_mci(dev); |
702 | ||
5926ff50 | 703 | return sprintf(data, "%d\n", mci->ue_mc); |
7c9281d7 DT |
704 | } |
705 | ||
7a623c03 MCC |
706 | static ssize_t mci_ce_count_show(struct device *dev, |
707 | struct device_attribute *mattr, | |
708 | char *data) | |
7c9281d7 | 709 | { |
7a623c03 MCC |
710 | struct mem_ctl_info *mci = to_mci(dev); |
711 | ||
5926ff50 | 712 | return sprintf(data, "%d\n", mci->ce_mc); |
7c9281d7 DT |
713 | } |
714 | ||
7a623c03 MCC |
715 | static ssize_t mci_ce_noinfo_show(struct device *dev, |
716 | struct device_attribute *mattr, | |
717 | char *data) | |
7c9281d7 | 718 | { |
7a623c03 MCC |
719 | struct mem_ctl_info *mci = to_mci(dev); |
720 | ||
079708b9 | 721 | return sprintf(data, "%d\n", mci->ce_noinfo_count); |
7c9281d7 DT |
722 | } |
723 | ||
7a623c03 MCC |
724 | static ssize_t mci_ue_noinfo_show(struct device *dev, |
725 | struct device_attribute *mattr, | |
726 | char *data) | |
7c9281d7 | 727 | { |
7a623c03 MCC |
728 | struct mem_ctl_info *mci = to_mci(dev); |
729 | ||
079708b9 | 730 | return sprintf(data, "%d\n", mci->ue_noinfo_count); |
7c9281d7 DT |
731 | } |
732 | ||
7a623c03 MCC |
733 | static ssize_t mci_seconds_show(struct device *dev, |
734 | struct device_attribute *mattr, | |
735 | char *data) | |
7c9281d7 | 736 | { |
7a623c03 MCC |
737 | struct mem_ctl_info *mci = to_mci(dev); |
738 | ||
079708b9 | 739 | return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ); |
7c9281d7 DT |
740 | } |
741 | ||
7a623c03 MCC |
742 | static ssize_t mci_ctl_name_show(struct device *dev, |
743 | struct device_attribute *mattr, | |
744 | char *data) | |
7c9281d7 | 745 | { |
7a623c03 MCC |
746 | struct mem_ctl_info *mci = to_mci(dev); |
747 | ||
079708b9 | 748 | return sprintf(data, "%s\n", mci->ctl_name); |
7c9281d7 DT |
749 | } |
750 | ||
7a623c03 MCC |
751 | static ssize_t mci_size_mb_show(struct device *dev, |
752 | struct device_attribute *mattr, | |
753 | char *data) | |
7c9281d7 | 754 | { |
7a623c03 | 755 | struct mem_ctl_info *mci = to_mci(dev); |
a895bf8b | 756 | int total_pages = 0, csrow_idx, j; |
7c9281d7 | 757 | |
a895bf8b | 758 | for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) { |
de3910eb | 759 | struct csrow_info *csrow = mci->csrows[csrow_idx]; |
7c9281d7 | 760 | |
1eef1282 MCC |
761 | for (j = 0; j < csrow->nr_channels; j++) { |
762 | struct dimm_info *dimm = csrow->channels[j]->dimm; | |
3c062276 | 763 | |
1eef1282 | 764 | total_pages += dimm->nr_pages; |
a895bf8b | 765 | } |
7c9281d7 DT |
766 | } |
767 | ||
079708b9 | 768 | return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages)); |
7c9281d7 DT |
769 | } |
770 | ||
8ad6c78a MCC |
771 | static ssize_t mci_max_location_show(struct device *dev, |
772 | struct device_attribute *mattr, | |
773 | char *data) | |
774 | { | |
775 | struct mem_ctl_info *mci = to_mci(dev); | |
776 | int i; | |
777 | char *p = data; | |
778 | ||
779 | for (i = 0; i < mci->n_layers; i++) { | |
780 | p += sprintf(p, "%s %d ", | |
781 | edac_layer_name[mci->layers[i].type], | |
782 | mci->layers[i].size - 1); | |
783 | } | |
784 | ||
785 | return p - data; | |
786 | } | |
787 | ||
7c9281d7 | 788 | /* default Control file */ |
f11135d8 | 789 | static DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store); |
7c9281d7 DT |
790 | |
791 | /* default Attribute files */ | |
f11135d8 BP |
792 | static DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL); |
793 | static DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL); | |
794 | static DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL); | |
795 | static DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL); | |
796 | static DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL); | |
797 | static DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL); | |
798 | static DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL); | |
799 | static DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL); | |
7c9281d7 DT |
800 | |
801 | /* memory scrubber attribute file */ | |
2c1946b6 TI |
802 | DEVICE_ATTR(sdram_scrub_rate, 0, mci_sdram_scrub_rate_show, |
803 | mci_sdram_scrub_rate_store); /* umode set later in is_visible */ | |
7c9281d7 | 804 | |
7a623c03 MCC |
805 | static struct attribute *mci_attrs[] = { |
806 | &dev_attr_reset_counters.attr, | |
807 | &dev_attr_mc_name.attr, | |
808 | &dev_attr_size_mb.attr, | |
809 | &dev_attr_seconds_since_reset.attr, | |
810 | &dev_attr_ue_noinfo_count.attr, | |
811 | &dev_attr_ce_noinfo_count.attr, | |
812 | &dev_attr_ue_count.attr, | |
813 | &dev_attr_ce_count.attr, | |
8ad6c78a | 814 | &dev_attr_max_location.attr, |
2c1946b6 | 815 | &dev_attr_sdram_scrub_rate.attr, |
7c9281d7 DT |
816 | NULL |
817 | }; | |
818 | ||
2c1946b6 TI |
819 | static umode_t mci_attr_is_visible(struct kobject *kobj, |
820 | struct attribute *attr, int idx) | |
821 | { | |
822 | struct device *dev = kobj_to_dev(kobj); | |
823 | struct mem_ctl_info *mci = to_mci(dev); | |
824 | umode_t mode = 0; | |
825 | ||
826 | if (attr != &dev_attr_sdram_scrub_rate.attr) | |
827 | return attr->mode; | |
828 | if (mci->get_sdram_scrub_rate) | |
829 | mode |= S_IRUGO; | |
830 | if (mci->set_sdram_scrub_rate) | |
831 | mode |= S_IWUSR; | |
832 | return mode; | |
833 | } | |
834 | ||
7a623c03 MCC |
835 | static struct attribute_group mci_attr_grp = { |
836 | .attrs = mci_attrs, | |
2c1946b6 | 837 | .is_visible = mci_attr_is_visible, |
cc301b3a MCC |
838 | }; |
839 | ||
7a623c03 MCC |
840 | static const struct attribute_group *mci_attr_groups[] = { |
841 | &mci_attr_grp, | |
842 | NULL | |
cc301b3a MCC |
843 | }; |
844 | ||
de3910eb | 845 | static void mci_attr_release(struct device *dev) |
42a8e397 | 846 | { |
de3910eb MCC |
847 | struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev); |
848 | ||
956b9ba1 | 849 | edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev)); |
de3910eb | 850 | kfree(mci); |
42a8e397 DT |
851 | } |
852 | ||
7a623c03 MCC |
853 | static struct device_type mci_attr_type = { |
854 | .groups = mci_attr_groups, | |
855 | .release = mci_attr_release, | |
856 | }; | |
8096cfaf | 857 | |
7c9281d7 DT |
858 | /* |
859 | * Create a new Memory Controller kobject instance, | |
860 | * mc<id> under the 'mc' directory | |
861 | * | |
862 | * Return: | |
863 | * 0 Success | |
864 | * !0 Failure | |
865 | */ | |
4e8d230d TI |
866 | int edac_create_sysfs_mci_device(struct mem_ctl_info *mci, |
867 | const struct attribute_group **groups) | |
7c9281d7 | 868 | { |
7a623c03 | 869 | int i, err; |
7c9281d7 | 870 | |
de3910eb MCC |
871 | /* |
872 | * The memory controller needs its own bus, in order to avoid | |
873 | * namespace conflicts at /sys/bus/edac. | |
874 | */ | |
88d84ac9 BP |
875 | mci->bus->name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx); |
876 | if (!mci->bus->name) | |
de3910eb | 877 | return -ENOMEM; |
88d84ac9 BP |
878 | |
879 | edac_dbg(0, "creating bus %s\n", mci->bus->name); | |
880 | ||
881 | err = bus_register(mci->bus); | |
de3910eb | 882 | if (err < 0) |
1bf1950c | 883 | goto fail_free_name; |
7c9281d7 | 884 | |
7a623c03 | 885 | /* get the /sys/devices/system/edac subsys reference */ |
7a623c03 MCC |
886 | mci->dev.type = &mci_attr_type; |
887 | device_initialize(&mci->dev); | |
7c9281d7 | 888 | |
de3910eb | 889 | mci->dev.parent = mci_pdev; |
88d84ac9 | 890 | mci->dev.bus = mci->bus; |
4e8d230d | 891 | mci->dev.groups = groups; |
7a623c03 MCC |
892 | dev_set_name(&mci->dev, "mc%d", mci->mc_idx); |
893 | dev_set_drvdata(&mci->dev, mci); | |
894 | pm_runtime_forbid(&mci->dev); | |
895 | ||
956b9ba1 | 896 | edac_dbg(0, "creating device %s\n", dev_name(&mci->dev)); |
7a623c03 MCC |
897 | err = device_add(&mci->dev); |
898 | if (err < 0) { | |
3d958823 | 899 | edac_dbg(1, "failure: create device %s\n", dev_name(&mci->dev)); |
1bf1950c | 900 | goto fail_unregister_bus; |
42a8e397 DT |
901 | } |
902 | ||
7a623c03 MCC |
903 | /* |
904 | * Create the dimm/rank devices | |
7c9281d7 | 905 | */ |
7a623c03 | 906 | for (i = 0; i < mci->tot_dimms; i++) { |
de3910eb | 907 | struct dimm_info *dimm = mci->dimms[i]; |
7a623c03 | 908 | /* Only expose populated DIMMs */ |
1bf1950c | 909 | if (!dimm->nr_pages) |
7a623c03 | 910 | continue; |
1bf1950c | 911 | |
7a623c03 | 912 | #ifdef CONFIG_EDAC_DEBUG |
956b9ba1 | 913 | edac_dbg(1, "creating dimm%d, located at ", i); |
7a623c03 MCC |
914 | if (edac_debug_level >= 1) { |
915 | int lay; | |
916 | for (lay = 0; lay < mci->n_layers; lay++) | |
917 | printk(KERN_CONT "%s %d ", | |
918 | edac_layer_name[mci->layers[lay].type], | |
919 | dimm->location[lay]); | |
920 | printk(KERN_CONT "\n"); | |
7c9281d7 | 921 | } |
7a623c03 | 922 | #endif |
19974710 MCC |
923 | err = edac_create_dimm_object(mci, dimm, i); |
924 | if (err) { | |
956b9ba1 | 925 | edac_dbg(1, "failure: create dimm %d obj\n", i); |
1bf1950c | 926 | goto fail_unregister_dimm; |
19974710 | 927 | } |
7c9281d7 DT |
928 | } |
929 | ||
19974710 | 930 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 MCC |
931 | err = edac_create_csrow_objects(mci); |
932 | if (err < 0) | |
1bf1950c | 933 | goto fail_unregister_dimm; |
19974710 | 934 | #endif |
7a623c03 | 935 | |
7ac8bf9b | 936 | edac_create_debugfs_nodes(mci); |
7c9281d7 DT |
937 | return 0; |
938 | ||
1bf1950c | 939 | fail_unregister_dimm: |
079708b9 | 940 | for (i--; i >= 0; i--) { |
de3910eb | 941 | struct dimm_info *dimm = mci->dimms[i]; |
1bf1950c | 942 | if (!dimm->nr_pages) |
7a623c03 | 943 | continue; |
1bf1950c | 944 | |
44d22e24 | 945 | device_unregister(&dimm->dev); |
7c9281d7 | 946 | } |
44d22e24 | 947 | device_unregister(&mci->dev); |
1bf1950c | 948 | fail_unregister_bus: |
88d84ac9 | 949 | bus_unregister(mci->bus); |
1bf1950c | 950 | fail_free_name: |
88d84ac9 | 951 | kfree(mci->bus->name); |
7c9281d7 DT |
952 | return err; |
953 | } | |
954 | ||
955 | /* | |
956 | * remove a Memory Controller instance | |
957 | */ | |
958 | void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci) | |
959 | { | |
7a623c03 | 960 | int i; |
7c9281d7 | 961 | |
956b9ba1 | 962 | edac_dbg(0, "\n"); |
7c9281d7 | 963 | |
452a6bf9 MCC |
964 | #ifdef CONFIG_EDAC_DEBUG |
965 | debugfs_remove(mci->debugfs); | |
966 | #endif | |
19974710 | 967 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 | 968 | edac_delete_csrow_objects(mci); |
19974710 | 969 | #endif |
7c9281d7 | 970 | |
7a623c03 | 971 | for (i = 0; i < mci->tot_dimms; i++) { |
de3910eb | 972 | struct dimm_info *dimm = mci->dimms[i]; |
7a623c03 MCC |
973 | if (dimm->nr_pages == 0) |
974 | continue; | |
956b9ba1 | 975 | edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev)); |
44d22e24 | 976 | device_unregister(&dimm->dev); |
6fe1108f | 977 | } |
7c9281d7 | 978 | } |
8096cfaf | 979 | |
7a623c03 MCC |
980 | void edac_unregister_sysfs(struct mem_ctl_info *mci) |
981 | { | |
956b9ba1 | 982 | edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev)); |
44d22e24 | 983 | device_unregister(&mci->dev); |
88d84ac9 BP |
984 | bus_unregister(mci->bus); |
985 | kfree(mci->bus->name); | |
7a623c03 | 986 | } |
8096cfaf | 987 | |
de3910eb | 988 | static void mc_attr_release(struct device *dev) |
7a623c03 | 989 | { |
de3910eb MCC |
990 | /* |
991 | * There's no container structure here, as this is just the mci | |
992 | * parent device, used to create the /sys/devices/mc sysfs node. | |
993 | * So, there are no attributes on it. | |
994 | */ | |
956b9ba1 | 995 | edac_dbg(1, "Releasing device %s\n", dev_name(dev)); |
de3910eb | 996 | kfree(dev); |
7a623c03 | 997 | } |
8096cfaf | 998 | |
7a623c03 MCC |
999 | static struct device_type mc_attr_type = { |
1000 | .release = mc_attr_release, | |
1001 | }; | |
8096cfaf | 1002 | /* |
7a623c03 | 1003 | * Init/exit code for the module. Basically, creates/removes /sys/class/rc |
8096cfaf | 1004 | */ |
7a623c03 | 1005 | int __init edac_mc_sysfs_init(void) |
8096cfaf | 1006 | { |
fe5ff8b8 | 1007 | struct bus_type *edac_subsys; |
7a623c03 | 1008 | int err; |
8096cfaf | 1009 | |
fe5ff8b8 KS |
1010 | /* get the /sys/devices/system/edac subsys reference */ |
1011 | edac_subsys = edac_get_sysfs_subsys(); | |
1012 | if (edac_subsys == NULL) { | |
956b9ba1 | 1013 | edac_dbg(1, "no edac_subsys\n"); |
2d56b109 DK |
1014 | err = -EINVAL; |
1015 | goto out; | |
8096cfaf DT |
1016 | } |
1017 | ||
de3910eb | 1018 | mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL); |
2d56b109 DK |
1019 | if (!mci_pdev) { |
1020 | err = -ENOMEM; | |
1021 | goto out_put_sysfs; | |
1022 | } | |
de3910eb MCC |
1023 | |
1024 | mci_pdev->bus = edac_subsys; | |
1025 | mci_pdev->type = &mc_attr_type; | |
1026 | device_initialize(mci_pdev); | |
1027 | dev_set_name(mci_pdev, "mc"); | |
8096cfaf | 1028 | |
de3910eb | 1029 | err = device_add(mci_pdev); |
7a623c03 | 1030 | if (err < 0) |
2d56b109 | 1031 | goto out_dev_free; |
8096cfaf | 1032 | |
956b9ba1 | 1033 | edac_dbg(0, "device %s created\n", dev_name(mci_pdev)); |
de3910eb | 1034 | |
8096cfaf | 1035 | return 0; |
2d56b109 DK |
1036 | |
1037 | out_dev_free: | |
1038 | kfree(mci_pdev); | |
1039 | out_put_sysfs: | |
1040 | edac_put_sysfs_subsys(); | |
1041 | out: | |
1042 | return err; | |
8096cfaf DT |
1043 | } |
1044 | ||
c6b97bcf | 1045 | void edac_mc_sysfs_exit(void) |
8096cfaf | 1046 | { |
44d22e24 | 1047 | device_unregister(mci_pdev); |
fe5ff8b8 | 1048 | edac_put_sysfs_subsys(); |
8096cfaf | 1049 | } |