Commit | Line | Data |
---|---|---|
7c9281d7 DT |
1 | /* |
2 | * edac_mc kernel module | |
42a8e397 DT |
3 | * (C) 2005-2007 Linux Networx (http://lnxi.com) |
4 | * | |
7c9281d7 DT |
5 | * This file may be distributed under the terms of the |
6 | * GNU General Public License. | |
7 | * | |
42a8e397 | 8 | * Written Doug Thompson <norsk5@xmission.com> www.softwarebitmaker.com |
7c9281d7 | 9 | * |
e7100478 | 10 | * (c) 2012-2013 - Mauro Carvalho Chehab <mchehab@redhat.com> |
7a623c03 MCC |
11 | * The entire API were re-written, and ported to use struct device |
12 | * | |
7c9281d7 DT |
13 | */ |
14 | ||
7c9281d7 | 15 | #include <linux/ctype.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
30e1f7a8 | 17 | #include <linux/edac.h> |
8096cfaf | 18 | #include <linux/bug.h> |
7a623c03 | 19 | #include <linux/pm_runtime.h> |
452a6bf9 | 20 | #include <linux/uaccess.h> |
7c9281d7 | 21 | |
20bcb7a8 | 22 | #include "edac_core.h" |
7c9281d7 DT |
23 | #include "edac_module.h" |
24 | ||
25 | /* MC EDAC Controls, setable by module parameter, and sysfs */ | |
4de78c68 DJ |
26 | static int edac_mc_log_ue = 1; |
27 | static int edac_mc_log_ce = 1; | |
f044091c | 28 | static int edac_mc_panic_on_ue; |
4de78c68 | 29 | static int edac_mc_poll_msec = 1000; |
7c9281d7 DT |
30 | |
31 | /* Getter functions for above */ | |
4de78c68 | 32 | int edac_mc_get_log_ue(void) |
7c9281d7 | 33 | { |
4de78c68 | 34 | return edac_mc_log_ue; |
7c9281d7 DT |
35 | } |
36 | ||
4de78c68 | 37 | int edac_mc_get_log_ce(void) |
7c9281d7 | 38 | { |
4de78c68 | 39 | return edac_mc_log_ce; |
7c9281d7 DT |
40 | } |
41 | ||
4de78c68 | 42 | int edac_mc_get_panic_on_ue(void) |
7c9281d7 | 43 | { |
4de78c68 | 44 | return edac_mc_panic_on_ue; |
7c9281d7 DT |
45 | } |
46 | ||
81d87cb1 DJ |
47 | /* this is temporary */ |
48 | int edac_mc_get_poll_msec(void) | |
49 | { | |
4de78c68 | 50 | return edac_mc_poll_msec; |
7c9281d7 DT |
51 | } |
52 | ||
096846e2 AJ |
53 | static int edac_set_poll_msec(const char *val, struct kernel_param *kp) |
54 | { | |
55 | long l; | |
56 | int ret; | |
57 | ||
58 | if (!val) | |
59 | return -EINVAL; | |
60 | ||
61 | ret = strict_strtol(val, 0, &l); | |
62 | if (ret == -EINVAL || ((int)l != l)) | |
63 | return -EINVAL; | |
64 | *((int *)kp->arg) = l; | |
65 | ||
66 | /* notify edac_mc engine to reset the poll period */ | |
67 | edac_mc_reset_delay_period(l); | |
68 | ||
69 | return 0; | |
70 | } | |
71 | ||
7c9281d7 | 72 | /* Parameter declarations for above */ |
4de78c68 DJ |
73 | module_param(edac_mc_panic_on_ue, int, 0644); |
74 | MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on"); | |
75 | module_param(edac_mc_log_ue, int, 0644); | |
76 | MODULE_PARM_DESC(edac_mc_log_ue, | |
079708b9 | 77 | "Log uncorrectable error to console: 0=off 1=on"); |
4de78c68 DJ |
78 | module_param(edac_mc_log_ce, int, 0644); |
79 | MODULE_PARM_DESC(edac_mc_log_ce, | |
079708b9 | 80 | "Log correctable error to console: 0=off 1=on"); |
096846e2 AJ |
81 | module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int, |
82 | &edac_mc_poll_msec, 0644); | |
4de78c68 | 83 | MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds"); |
7c9281d7 | 84 | |
de3910eb | 85 | static struct device *mci_pdev; |
7a623c03 | 86 | |
7c9281d7 DT |
87 | /* |
88 | * various constants for Memory Controllers | |
89 | */ | |
90 | static const char *mem_types[] = { | |
91 | [MEM_EMPTY] = "Empty", | |
92 | [MEM_RESERVED] = "Reserved", | |
93 | [MEM_UNKNOWN] = "Unknown", | |
94 | [MEM_FPM] = "FPM", | |
95 | [MEM_EDO] = "EDO", | |
96 | [MEM_BEDO] = "BEDO", | |
97 | [MEM_SDR] = "Unbuffered-SDR", | |
98 | [MEM_RDR] = "Registered-SDR", | |
99 | [MEM_DDR] = "Unbuffered-DDR", | |
100 | [MEM_RDDR] = "Registered-DDR", | |
1a9b85e6 DJ |
101 | [MEM_RMBS] = "RMBS", |
102 | [MEM_DDR2] = "Unbuffered-DDR2", | |
103 | [MEM_FB_DDR2] = "FullyBuffered-DDR2", | |
1d5f726c | 104 | [MEM_RDDR2] = "Registered-DDR2", |
b1cfebc9 YS |
105 | [MEM_XDR] = "XDR", |
106 | [MEM_DDR3] = "Unbuffered-DDR3", | |
107 | [MEM_RDDR3] = "Registered-DDR3" | |
7c9281d7 DT |
108 | }; |
109 | ||
110 | static const char *dev_types[] = { | |
111 | [DEV_UNKNOWN] = "Unknown", | |
112 | [DEV_X1] = "x1", | |
113 | [DEV_X2] = "x2", | |
114 | [DEV_X4] = "x4", | |
115 | [DEV_X8] = "x8", | |
116 | [DEV_X16] = "x16", | |
117 | [DEV_X32] = "x32", | |
118 | [DEV_X64] = "x64" | |
119 | }; | |
120 | ||
121 | static const char *edac_caps[] = { | |
122 | [EDAC_UNKNOWN] = "Unknown", | |
123 | [EDAC_NONE] = "None", | |
124 | [EDAC_RESERVED] = "Reserved", | |
125 | [EDAC_PARITY] = "PARITY", | |
126 | [EDAC_EC] = "EC", | |
127 | [EDAC_SECDED] = "SECDED", | |
128 | [EDAC_S2ECD2ED] = "S2ECD2ED", | |
129 | [EDAC_S4ECD4ED] = "S4ECD4ED", | |
130 | [EDAC_S8ECD8ED] = "S8ECD8ED", | |
131 | [EDAC_S16ECD16ED] = "S16ECD16ED" | |
132 | }; | |
133 | ||
19974710 | 134 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 MCC |
135 | /* |
136 | * EDAC sysfs CSROW data structures and methods | |
137 | */ | |
138 | ||
139 | #define to_csrow(k) container_of(k, struct csrow_info, dev) | |
140 | ||
141 | /* | |
142 | * We need it to avoid namespace conflicts between the legacy API | |
143 | * and the per-dimm/per-rank one | |
7c9281d7 | 144 | */ |
7a623c03 MCC |
145 | #define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \ |
146 | struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store) | |
147 | ||
148 | struct dev_ch_attribute { | |
149 | struct device_attribute attr; | |
150 | int channel; | |
151 | }; | |
152 | ||
153 | #define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \ | |
154 | struct dev_ch_attribute dev_attr_legacy_##_name = \ | |
155 | { __ATTR(_name, _mode, _show, _store), (_var) } | |
156 | ||
157 | #define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel) | |
7c9281d7 DT |
158 | |
159 | /* Set of more default csrow<id> attribute show/store functions */ | |
7a623c03 MCC |
160 | static ssize_t csrow_ue_count_show(struct device *dev, |
161 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 162 | { |
7a623c03 MCC |
163 | struct csrow_info *csrow = to_csrow(dev); |
164 | ||
079708b9 | 165 | return sprintf(data, "%u\n", csrow->ue_count); |
7c9281d7 DT |
166 | } |
167 | ||
7a623c03 MCC |
168 | static ssize_t csrow_ce_count_show(struct device *dev, |
169 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 170 | { |
7a623c03 MCC |
171 | struct csrow_info *csrow = to_csrow(dev); |
172 | ||
079708b9 | 173 | return sprintf(data, "%u\n", csrow->ce_count); |
7c9281d7 DT |
174 | } |
175 | ||
7a623c03 MCC |
176 | static ssize_t csrow_size_show(struct device *dev, |
177 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 178 | { |
7a623c03 | 179 | struct csrow_info *csrow = to_csrow(dev); |
a895bf8b MCC |
180 | int i; |
181 | u32 nr_pages = 0; | |
182 | ||
16a528ee BP |
183 | if (csrow->mci->csbased) |
184 | return sprintf(data, "%u\n", PAGES_TO_MiB(csrow->nr_pages)); | |
185 | ||
a895bf8b | 186 | for (i = 0; i < csrow->nr_channels; i++) |
de3910eb | 187 | nr_pages += csrow->channels[i]->dimm->nr_pages; |
a895bf8b | 188 | return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages)); |
7c9281d7 DT |
189 | } |
190 | ||
7a623c03 MCC |
191 | static ssize_t csrow_mem_type_show(struct device *dev, |
192 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 193 | { |
7a623c03 MCC |
194 | struct csrow_info *csrow = to_csrow(dev); |
195 | ||
de3910eb | 196 | return sprintf(data, "%s\n", mem_types[csrow->channels[0]->dimm->mtype]); |
7c9281d7 DT |
197 | } |
198 | ||
7a623c03 MCC |
199 | static ssize_t csrow_dev_type_show(struct device *dev, |
200 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 201 | { |
7a623c03 MCC |
202 | struct csrow_info *csrow = to_csrow(dev); |
203 | ||
de3910eb | 204 | return sprintf(data, "%s\n", dev_types[csrow->channels[0]->dimm->dtype]); |
7c9281d7 DT |
205 | } |
206 | ||
7a623c03 MCC |
207 | static ssize_t csrow_edac_mode_show(struct device *dev, |
208 | struct device_attribute *mattr, | |
209 | char *data) | |
7c9281d7 | 210 | { |
7a623c03 MCC |
211 | struct csrow_info *csrow = to_csrow(dev); |
212 | ||
de3910eb | 213 | return sprintf(data, "%s\n", edac_caps[csrow->channels[0]->dimm->edac_mode]); |
7c9281d7 DT |
214 | } |
215 | ||
216 | /* show/store functions for DIMM Label attributes */ | |
7a623c03 MCC |
217 | static ssize_t channel_dimm_label_show(struct device *dev, |
218 | struct device_attribute *mattr, | |
219 | char *data) | |
7c9281d7 | 220 | { |
7a623c03 MCC |
221 | struct csrow_info *csrow = to_csrow(dev); |
222 | unsigned chan = to_channel(mattr); | |
de3910eb | 223 | struct rank_info *rank = csrow->channels[chan]; |
7a623c03 | 224 | |
124682c7 | 225 | /* if field has not been initialized, there is nothing to send */ |
7a623c03 | 226 | if (!rank->dimm->label[0]) |
124682c7 AJ |
227 | return 0; |
228 | ||
229 | return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", | |
7a623c03 | 230 | rank->dimm->label); |
7c9281d7 DT |
231 | } |
232 | ||
7a623c03 MCC |
233 | static ssize_t channel_dimm_label_store(struct device *dev, |
234 | struct device_attribute *mattr, | |
235 | const char *data, size_t count) | |
7c9281d7 | 236 | { |
7a623c03 MCC |
237 | struct csrow_info *csrow = to_csrow(dev); |
238 | unsigned chan = to_channel(mattr); | |
de3910eb | 239 | struct rank_info *rank = csrow->channels[chan]; |
7a623c03 | 240 | |
7c9281d7 DT |
241 | ssize_t max_size = 0; |
242 | ||
079708b9 | 243 | max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1); |
7a623c03 MCC |
244 | strncpy(rank->dimm->label, data, max_size); |
245 | rank->dimm->label[max_size] = '\0'; | |
7c9281d7 DT |
246 | |
247 | return max_size; | |
248 | } | |
249 | ||
250 | /* show function for dynamic chX_ce_count attribute */ | |
7a623c03 MCC |
251 | static ssize_t channel_ce_count_show(struct device *dev, |
252 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 253 | { |
7a623c03 MCC |
254 | struct csrow_info *csrow = to_csrow(dev); |
255 | unsigned chan = to_channel(mattr); | |
de3910eb | 256 | struct rank_info *rank = csrow->channels[chan]; |
7a623c03 MCC |
257 | |
258 | return sprintf(data, "%u\n", rank->ce_count); | |
7c9281d7 DT |
259 | } |
260 | ||
7a623c03 MCC |
261 | /* cwrow<id>/attribute files */ |
262 | DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL); | |
263 | DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL); | |
264 | DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL); | |
265 | DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL); | |
266 | DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL); | |
267 | DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL); | |
7c9281d7 | 268 | |
7a623c03 MCC |
269 | /* default attributes of the CSROW<id> object */ |
270 | static struct attribute *csrow_attrs[] = { | |
271 | &dev_attr_legacy_dev_type.attr, | |
272 | &dev_attr_legacy_mem_type.attr, | |
273 | &dev_attr_legacy_edac_mode.attr, | |
274 | &dev_attr_legacy_size_mb.attr, | |
275 | &dev_attr_legacy_ue_count.attr, | |
276 | &dev_attr_legacy_ce_count.attr, | |
277 | NULL, | |
278 | }; | |
7c9281d7 | 279 | |
7a623c03 MCC |
280 | static struct attribute_group csrow_attr_grp = { |
281 | .attrs = csrow_attrs, | |
282 | }; | |
7c9281d7 | 283 | |
7a623c03 MCC |
284 | static const struct attribute_group *csrow_attr_groups[] = { |
285 | &csrow_attr_grp, | |
286 | NULL | |
287 | }; | |
7c9281d7 | 288 | |
de3910eb | 289 | static void csrow_attr_release(struct device *dev) |
7c9281d7 | 290 | { |
de3910eb MCC |
291 | struct csrow_info *csrow = container_of(dev, struct csrow_info, dev); |
292 | ||
956b9ba1 | 293 | edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev)); |
de3910eb | 294 | kfree(csrow); |
7c9281d7 DT |
295 | } |
296 | ||
7a623c03 MCC |
297 | static struct device_type csrow_attr_type = { |
298 | .groups = csrow_attr_groups, | |
299 | .release = csrow_attr_release, | |
7c9281d7 DT |
300 | }; |
301 | ||
7a623c03 MCC |
302 | /* |
303 | * possible dynamic channel DIMM Label attribute files | |
304 | * | |
305 | */ | |
7c9281d7 | 306 | |
7a623c03 | 307 | #define EDAC_NR_CHANNELS 6 |
7c9281d7 | 308 | |
7a623c03 | 309 | DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 310 | channel_dimm_label_show, channel_dimm_label_store, 0); |
7a623c03 | 311 | DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 312 | channel_dimm_label_show, channel_dimm_label_store, 1); |
7a623c03 | 313 | DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 314 | channel_dimm_label_show, channel_dimm_label_store, 2); |
7a623c03 | 315 | DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 316 | channel_dimm_label_show, channel_dimm_label_store, 3); |
7a623c03 | 317 | DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 318 | channel_dimm_label_show, channel_dimm_label_store, 4); |
7a623c03 | 319 | DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 320 | channel_dimm_label_show, channel_dimm_label_store, 5); |
7c9281d7 DT |
321 | |
322 | /* Total possible dynamic DIMM Label attribute file table */ | |
7a623c03 MCC |
323 | static struct device_attribute *dynamic_csrow_dimm_attr[] = { |
324 | &dev_attr_legacy_ch0_dimm_label.attr, | |
325 | &dev_attr_legacy_ch1_dimm_label.attr, | |
326 | &dev_attr_legacy_ch2_dimm_label.attr, | |
327 | &dev_attr_legacy_ch3_dimm_label.attr, | |
328 | &dev_attr_legacy_ch4_dimm_label.attr, | |
329 | &dev_attr_legacy_ch5_dimm_label.attr | |
7c9281d7 DT |
330 | }; |
331 | ||
332 | /* possible dynamic channel ce_count attribute files */ | |
7a623c03 MCC |
333 | DEVICE_CHANNEL(ch0_ce_count, S_IRUGO | S_IWUSR, |
334 | channel_ce_count_show, NULL, 0); | |
335 | DEVICE_CHANNEL(ch1_ce_count, S_IRUGO | S_IWUSR, | |
336 | channel_ce_count_show, NULL, 1); | |
337 | DEVICE_CHANNEL(ch2_ce_count, S_IRUGO | S_IWUSR, | |
338 | channel_ce_count_show, NULL, 2); | |
339 | DEVICE_CHANNEL(ch3_ce_count, S_IRUGO | S_IWUSR, | |
340 | channel_ce_count_show, NULL, 3); | |
341 | DEVICE_CHANNEL(ch4_ce_count, S_IRUGO | S_IWUSR, | |
342 | channel_ce_count_show, NULL, 4); | |
343 | DEVICE_CHANNEL(ch5_ce_count, S_IRUGO | S_IWUSR, | |
344 | channel_ce_count_show, NULL, 5); | |
7c9281d7 DT |
345 | |
346 | /* Total possible dynamic ce_count attribute file table */ | |
7a623c03 MCC |
347 | static struct device_attribute *dynamic_csrow_ce_count_attr[] = { |
348 | &dev_attr_legacy_ch0_ce_count.attr, | |
349 | &dev_attr_legacy_ch1_ce_count.attr, | |
350 | &dev_attr_legacy_ch2_ce_count.attr, | |
351 | &dev_attr_legacy_ch3_ce_count.attr, | |
352 | &dev_attr_legacy_ch4_ce_count.attr, | |
353 | &dev_attr_legacy_ch5_ce_count.attr | |
7c9281d7 DT |
354 | }; |
355 | ||
e39f4ea9 MCC |
356 | static inline int nr_pages_per_csrow(struct csrow_info *csrow) |
357 | { | |
358 | int chan, nr_pages = 0; | |
359 | ||
360 | for (chan = 0; chan < csrow->nr_channels; chan++) | |
de3910eb | 361 | nr_pages += csrow->channels[chan]->dimm->nr_pages; |
e39f4ea9 MCC |
362 | |
363 | return nr_pages; | |
364 | } | |
365 | ||
7a623c03 MCC |
366 | /* Create a CSROW object under specifed edac_mc_device */ |
367 | static int edac_create_csrow_object(struct mem_ctl_info *mci, | |
368 | struct csrow_info *csrow, int index) | |
7c9281d7 | 369 | { |
7a623c03 | 370 | int err, chan; |
7c9281d7 | 371 | |
7a623c03 MCC |
372 | if (csrow->nr_channels >= EDAC_NR_CHANNELS) |
373 | return -ENODEV; | |
7c9281d7 | 374 | |
7a623c03 MCC |
375 | csrow->dev.type = &csrow_attr_type; |
376 | csrow->dev.bus = &mci->bus; | |
377 | device_initialize(&csrow->dev); | |
378 | csrow->dev.parent = &mci->dev; | |
921a6899 | 379 | csrow->mci = mci; |
7a623c03 MCC |
380 | dev_set_name(&csrow->dev, "csrow%d", index); |
381 | dev_set_drvdata(&csrow->dev, csrow); | |
7c9281d7 | 382 | |
956b9ba1 JP |
383 | edac_dbg(0, "creating (virtual) csrow node %s\n", |
384 | dev_name(&csrow->dev)); | |
7c9281d7 | 385 | |
7a623c03 MCC |
386 | err = device_add(&csrow->dev); |
387 | if (err < 0) | |
388 | return err; | |
7c9281d7 | 389 | |
7a623c03 | 390 | for (chan = 0; chan < csrow->nr_channels; chan++) { |
e39f4ea9 | 391 | /* Only expose populated DIMMs */ |
de3910eb | 392 | if (!csrow->channels[chan]->dimm->nr_pages) |
e39f4ea9 | 393 | continue; |
7a623c03 MCC |
394 | err = device_create_file(&csrow->dev, |
395 | dynamic_csrow_dimm_attr[chan]); | |
396 | if (err < 0) | |
397 | goto error; | |
398 | err = device_create_file(&csrow->dev, | |
399 | dynamic_csrow_ce_count_attr[chan]); | |
400 | if (err < 0) { | |
401 | device_remove_file(&csrow->dev, | |
402 | dynamic_csrow_dimm_attr[chan]); | |
403 | goto error; | |
404 | } | |
405 | } | |
8096cfaf | 406 | |
7a623c03 | 407 | return 0; |
8096cfaf | 408 | |
7a623c03 MCC |
409 | error: |
410 | for (--chan; chan >= 0; chan--) { | |
411 | device_remove_file(&csrow->dev, | |
412 | dynamic_csrow_dimm_attr[chan]); | |
413 | device_remove_file(&csrow->dev, | |
414 | dynamic_csrow_ce_count_attr[chan]); | |
415 | } | |
416 | put_device(&csrow->dev); | |
7c9281d7 | 417 | |
7a623c03 MCC |
418 | return err; |
419 | } | |
7c9281d7 DT |
420 | |
421 | /* Create a CSROW object under specifed edac_mc_device */ | |
7a623c03 | 422 | static int edac_create_csrow_objects(struct mem_ctl_info *mci) |
7c9281d7 | 423 | { |
7a623c03 MCC |
424 | int err, i, chan; |
425 | struct csrow_info *csrow; | |
7c9281d7 | 426 | |
7a623c03 | 427 | for (i = 0; i < mci->nr_csrows; i++) { |
de3910eb | 428 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
429 | if (!nr_pages_per_csrow(csrow)) |
430 | continue; | |
de3910eb | 431 | err = edac_create_csrow_object(mci, mci->csrows[i], i); |
7a623c03 MCC |
432 | if (err < 0) |
433 | goto error; | |
434 | } | |
435 | return 0; | |
8096cfaf | 436 | |
7a623c03 MCC |
437 | error: |
438 | for (--i; i >= 0; i--) { | |
de3910eb | 439 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
440 | if (!nr_pages_per_csrow(csrow)) |
441 | continue; | |
7a623c03 | 442 | for (chan = csrow->nr_channels - 1; chan >= 0; chan--) { |
de3910eb | 443 | if (!csrow->channels[chan]->dimm->nr_pages) |
e39f4ea9 | 444 | continue; |
7a623c03 MCC |
445 | device_remove_file(&csrow->dev, |
446 | dynamic_csrow_dimm_attr[chan]); | |
447 | device_remove_file(&csrow->dev, | |
448 | dynamic_csrow_ce_count_attr[chan]); | |
449 | } | |
de3910eb | 450 | put_device(&mci->csrows[i]->dev); |
8096cfaf | 451 | } |
7c9281d7 | 452 | |
7a623c03 MCC |
453 | return err; |
454 | } | |
8096cfaf | 455 | |
7a623c03 MCC |
456 | static void edac_delete_csrow_objects(struct mem_ctl_info *mci) |
457 | { | |
458 | int i, chan; | |
459 | struct csrow_info *csrow; | |
8096cfaf | 460 | |
7a623c03 | 461 | for (i = mci->nr_csrows - 1; i >= 0; i--) { |
de3910eb | 462 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
463 | if (!nr_pages_per_csrow(csrow)) |
464 | continue; | |
7a623c03 | 465 | for (chan = csrow->nr_channels - 1; chan >= 0; chan--) { |
de3910eb | 466 | if (!csrow->channels[chan]->dimm->nr_pages) |
e39f4ea9 | 467 | continue; |
956b9ba1 JP |
468 | edac_dbg(1, "Removing csrow %d channel %d sysfs nodes\n", |
469 | i, chan); | |
7a623c03 MCC |
470 | device_remove_file(&csrow->dev, |
471 | dynamic_csrow_dimm_attr[chan]); | |
472 | device_remove_file(&csrow->dev, | |
473 | dynamic_csrow_ce_count_attr[chan]); | |
7c9281d7 | 474 | } |
44d22e24 | 475 | device_unregister(&mci->csrows[i]->dev); |
7c9281d7 | 476 | } |
7c9281d7 | 477 | } |
19974710 MCC |
478 | #endif |
479 | ||
480 | /* | |
481 | * Per-dimm (or per-rank) devices | |
482 | */ | |
483 | ||
484 | #define to_dimm(k) container_of(k, struct dimm_info, dev) | |
485 | ||
486 | /* show/store functions for DIMM Label attributes */ | |
487 | static ssize_t dimmdev_location_show(struct device *dev, | |
488 | struct device_attribute *mattr, char *data) | |
489 | { | |
490 | struct dimm_info *dimm = to_dimm(dev); | |
19974710 | 491 | |
6e84d359 | 492 | return edac_dimm_info_location(dimm, data, PAGE_SIZE); |
19974710 MCC |
493 | } |
494 | ||
495 | static ssize_t dimmdev_label_show(struct device *dev, | |
496 | struct device_attribute *mattr, char *data) | |
497 | { | |
498 | struct dimm_info *dimm = to_dimm(dev); | |
499 | ||
500 | /* if field has not been initialized, there is nothing to send */ | |
501 | if (!dimm->label[0]) | |
502 | return 0; | |
503 | ||
504 | return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", dimm->label); | |
505 | } | |
506 | ||
507 | static ssize_t dimmdev_label_store(struct device *dev, | |
508 | struct device_attribute *mattr, | |
509 | const char *data, | |
510 | size_t count) | |
511 | { | |
512 | struct dimm_info *dimm = to_dimm(dev); | |
513 | ||
514 | ssize_t max_size = 0; | |
515 | ||
516 | max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1); | |
517 | strncpy(dimm->label, data, max_size); | |
518 | dimm->label[max_size] = '\0'; | |
519 | ||
520 | return max_size; | |
521 | } | |
522 | ||
523 | static ssize_t dimmdev_size_show(struct device *dev, | |
524 | struct device_attribute *mattr, char *data) | |
525 | { | |
526 | struct dimm_info *dimm = to_dimm(dev); | |
527 | ||
528 | return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages)); | |
529 | } | |
530 | ||
531 | static ssize_t dimmdev_mem_type_show(struct device *dev, | |
532 | struct device_attribute *mattr, char *data) | |
533 | { | |
534 | struct dimm_info *dimm = to_dimm(dev); | |
535 | ||
536 | return sprintf(data, "%s\n", mem_types[dimm->mtype]); | |
537 | } | |
538 | ||
539 | static ssize_t dimmdev_dev_type_show(struct device *dev, | |
540 | struct device_attribute *mattr, char *data) | |
541 | { | |
542 | struct dimm_info *dimm = to_dimm(dev); | |
543 | ||
544 | return sprintf(data, "%s\n", dev_types[dimm->dtype]); | |
545 | } | |
546 | ||
547 | static ssize_t dimmdev_edac_mode_show(struct device *dev, | |
548 | struct device_attribute *mattr, | |
549 | char *data) | |
550 | { | |
551 | struct dimm_info *dimm = to_dimm(dev); | |
552 | ||
553 | return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]); | |
554 | } | |
555 | ||
556 | /* dimm/rank attribute files */ | |
557 | static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR, | |
558 | dimmdev_label_show, dimmdev_label_store); | |
559 | static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL); | |
560 | static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL); | |
561 | static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL); | |
562 | static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL); | |
563 | static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL); | |
564 | ||
565 | /* attributes of the dimm<id>/rank<id> object */ | |
566 | static struct attribute *dimm_attrs[] = { | |
567 | &dev_attr_dimm_label.attr, | |
568 | &dev_attr_dimm_location.attr, | |
569 | &dev_attr_size.attr, | |
570 | &dev_attr_dimm_mem_type.attr, | |
571 | &dev_attr_dimm_dev_type.attr, | |
572 | &dev_attr_dimm_edac_mode.attr, | |
573 | NULL, | |
574 | }; | |
575 | ||
576 | static struct attribute_group dimm_attr_grp = { | |
577 | .attrs = dimm_attrs, | |
578 | }; | |
579 | ||
580 | static const struct attribute_group *dimm_attr_groups[] = { | |
581 | &dimm_attr_grp, | |
582 | NULL | |
583 | }; | |
584 | ||
de3910eb | 585 | static void dimm_attr_release(struct device *dev) |
19974710 | 586 | { |
de3910eb MCC |
587 | struct dimm_info *dimm = container_of(dev, struct dimm_info, dev); |
588 | ||
956b9ba1 | 589 | edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev)); |
de3910eb | 590 | kfree(dimm); |
19974710 MCC |
591 | } |
592 | ||
593 | static struct device_type dimm_attr_type = { | |
594 | .groups = dimm_attr_groups, | |
595 | .release = dimm_attr_release, | |
596 | }; | |
597 | ||
598 | /* Create a DIMM object under specifed memory controller device */ | |
599 | static int edac_create_dimm_object(struct mem_ctl_info *mci, | |
600 | struct dimm_info *dimm, | |
601 | int index) | |
602 | { | |
603 | int err; | |
604 | dimm->mci = mci; | |
605 | ||
606 | dimm->dev.type = &dimm_attr_type; | |
607 | dimm->dev.bus = &mci->bus; | |
608 | device_initialize(&dimm->dev); | |
609 | ||
610 | dimm->dev.parent = &mci->dev; | |
611 | if (mci->mem_is_per_rank) | |
612 | dev_set_name(&dimm->dev, "rank%d", index); | |
613 | else | |
614 | dev_set_name(&dimm->dev, "dimm%d", index); | |
615 | dev_set_drvdata(&dimm->dev, dimm); | |
616 | pm_runtime_forbid(&mci->dev); | |
617 | ||
618 | err = device_add(&dimm->dev); | |
619 | ||
956b9ba1 | 620 | edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev)); |
19974710 MCC |
621 | |
622 | return err; | |
623 | } | |
7c9281d7 | 624 | |
7a623c03 MCC |
625 | /* |
626 | * Memory controller device | |
627 | */ | |
628 | ||
629 | #define to_mci(k) container_of(k, struct mem_ctl_info, dev) | |
7c9281d7 | 630 | |
7a623c03 MCC |
631 | static ssize_t mci_reset_counters_store(struct device *dev, |
632 | struct device_attribute *mattr, | |
079708b9 | 633 | const char *data, size_t count) |
7c9281d7 | 634 | { |
7a623c03 MCC |
635 | struct mem_ctl_info *mci = to_mci(dev); |
636 | int cnt, row, chan, i; | |
5926ff50 MCC |
637 | mci->ue_mc = 0; |
638 | mci->ce_mc = 0; | |
7a623c03 MCC |
639 | mci->ue_noinfo_count = 0; |
640 | mci->ce_noinfo_count = 0; | |
7c9281d7 DT |
641 | |
642 | for (row = 0; row < mci->nr_csrows; row++) { | |
de3910eb | 643 | struct csrow_info *ri = mci->csrows[row]; |
7c9281d7 DT |
644 | |
645 | ri->ue_count = 0; | |
646 | ri->ce_count = 0; | |
647 | ||
648 | for (chan = 0; chan < ri->nr_channels; chan++) | |
de3910eb | 649 | ri->channels[chan]->ce_count = 0; |
7c9281d7 DT |
650 | } |
651 | ||
7a623c03 MCC |
652 | cnt = 1; |
653 | for (i = 0; i < mci->n_layers; i++) { | |
654 | cnt *= mci->layers[i].size; | |
655 | memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32)); | |
656 | memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32)); | |
657 | } | |
658 | ||
7c9281d7 DT |
659 | mci->start_time = jiffies; |
660 | return count; | |
661 | } | |
662 | ||
39094443 BP |
663 | /* Memory scrubbing interface: |
664 | * | |
665 | * A MC driver can limit the scrubbing bandwidth based on the CPU type. | |
666 | * Therefore, ->set_sdram_scrub_rate should be made to return the actual | |
667 | * bandwidth that is accepted or 0 when scrubbing is to be disabled. | |
668 | * | |
669 | * Negative value still means that an error has occurred while setting | |
670 | * the scrub rate. | |
671 | */ | |
7a623c03 MCC |
672 | static ssize_t mci_sdram_scrub_rate_store(struct device *dev, |
673 | struct device_attribute *mattr, | |
eba042a8 | 674 | const char *data, size_t count) |
7c9281d7 | 675 | { |
7a623c03 | 676 | struct mem_ctl_info *mci = to_mci(dev); |
eba042a8 | 677 | unsigned long bandwidth = 0; |
39094443 | 678 | int new_bw = 0; |
7c9281d7 | 679 | |
eba042a8 BP |
680 | if (strict_strtoul(data, 10, &bandwidth) < 0) |
681 | return -EINVAL; | |
7c9281d7 | 682 | |
39094443 | 683 | new_bw = mci->set_sdram_scrub_rate(mci, bandwidth); |
4949603a MT |
684 | if (new_bw < 0) { |
685 | edac_printk(KERN_WARNING, EDAC_MC, | |
686 | "Error setting scrub rate to: %lu\n", bandwidth); | |
687 | return -EINVAL; | |
7c9281d7 | 688 | } |
39094443 | 689 | |
4949603a | 690 | return count; |
7c9281d7 DT |
691 | } |
692 | ||
39094443 BP |
693 | /* |
694 | * ->get_sdram_scrub_rate() return value semantics same as above. | |
695 | */ | |
7a623c03 MCC |
696 | static ssize_t mci_sdram_scrub_rate_show(struct device *dev, |
697 | struct device_attribute *mattr, | |
698 | char *data) | |
7c9281d7 | 699 | { |
7a623c03 | 700 | struct mem_ctl_info *mci = to_mci(dev); |
39094443 | 701 | int bandwidth = 0; |
eba042a8 | 702 | |
39094443 BP |
703 | bandwidth = mci->get_sdram_scrub_rate(mci); |
704 | if (bandwidth < 0) { | |
eba042a8 | 705 | edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n"); |
39094443 | 706 | return bandwidth; |
7c9281d7 | 707 | } |
39094443 | 708 | |
39094443 | 709 | return sprintf(data, "%d\n", bandwidth); |
7c9281d7 DT |
710 | } |
711 | ||
712 | /* default attribute files for the MCI object */ | |
7a623c03 MCC |
713 | static ssize_t mci_ue_count_show(struct device *dev, |
714 | struct device_attribute *mattr, | |
715 | char *data) | |
7c9281d7 | 716 | { |
7a623c03 MCC |
717 | struct mem_ctl_info *mci = to_mci(dev); |
718 | ||
5926ff50 | 719 | return sprintf(data, "%d\n", mci->ue_mc); |
7c9281d7 DT |
720 | } |
721 | ||
7a623c03 MCC |
722 | static ssize_t mci_ce_count_show(struct device *dev, |
723 | struct device_attribute *mattr, | |
724 | char *data) | |
7c9281d7 | 725 | { |
7a623c03 MCC |
726 | struct mem_ctl_info *mci = to_mci(dev); |
727 | ||
5926ff50 | 728 | return sprintf(data, "%d\n", mci->ce_mc); |
7c9281d7 DT |
729 | } |
730 | ||
7a623c03 MCC |
731 | static ssize_t mci_ce_noinfo_show(struct device *dev, |
732 | struct device_attribute *mattr, | |
733 | char *data) | |
7c9281d7 | 734 | { |
7a623c03 MCC |
735 | struct mem_ctl_info *mci = to_mci(dev); |
736 | ||
079708b9 | 737 | return sprintf(data, "%d\n", mci->ce_noinfo_count); |
7c9281d7 DT |
738 | } |
739 | ||
7a623c03 MCC |
740 | static ssize_t mci_ue_noinfo_show(struct device *dev, |
741 | struct device_attribute *mattr, | |
742 | char *data) | |
7c9281d7 | 743 | { |
7a623c03 MCC |
744 | struct mem_ctl_info *mci = to_mci(dev); |
745 | ||
079708b9 | 746 | return sprintf(data, "%d\n", mci->ue_noinfo_count); |
7c9281d7 DT |
747 | } |
748 | ||
7a623c03 MCC |
749 | static ssize_t mci_seconds_show(struct device *dev, |
750 | struct device_attribute *mattr, | |
751 | char *data) | |
7c9281d7 | 752 | { |
7a623c03 MCC |
753 | struct mem_ctl_info *mci = to_mci(dev); |
754 | ||
079708b9 | 755 | return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ); |
7c9281d7 DT |
756 | } |
757 | ||
7a623c03 MCC |
758 | static ssize_t mci_ctl_name_show(struct device *dev, |
759 | struct device_attribute *mattr, | |
760 | char *data) | |
7c9281d7 | 761 | { |
7a623c03 MCC |
762 | struct mem_ctl_info *mci = to_mci(dev); |
763 | ||
079708b9 | 764 | return sprintf(data, "%s\n", mci->ctl_name); |
7c9281d7 DT |
765 | } |
766 | ||
7a623c03 MCC |
767 | static ssize_t mci_size_mb_show(struct device *dev, |
768 | struct device_attribute *mattr, | |
769 | char *data) | |
7c9281d7 | 770 | { |
7a623c03 | 771 | struct mem_ctl_info *mci = to_mci(dev); |
a895bf8b | 772 | int total_pages = 0, csrow_idx, j; |
7c9281d7 | 773 | |
a895bf8b | 774 | for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) { |
de3910eb | 775 | struct csrow_info *csrow = mci->csrows[csrow_idx]; |
7c9281d7 | 776 | |
3c062276 JH |
777 | if (csrow->mci->csbased) { |
778 | total_pages += csrow->nr_pages; | |
779 | } else { | |
780 | for (j = 0; j < csrow->nr_channels; j++) { | |
781 | struct dimm_info *dimm = csrow->channels[j]->dimm; | |
782 | ||
783 | total_pages += dimm->nr_pages; | |
784 | } | |
a895bf8b | 785 | } |
7c9281d7 DT |
786 | } |
787 | ||
079708b9 | 788 | return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages)); |
7c9281d7 DT |
789 | } |
790 | ||
8ad6c78a MCC |
791 | static ssize_t mci_max_location_show(struct device *dev, |
792 | struct device_attribute *mattr, | |
793 | char *data) | |
794 | { | |
795 | struct mem_ctl_info *mci = to_mci(dev); | |
796 | int i; | |
797 | char *p = data; | |
798 | ||
799 | for (i = 0; i < mci->n_layers; i++) { | |
800 | p += sprintf(p, "%s %d ", | |
801 | edac_layer_name[mci->layers[i].type], | |
802 | mci->layers[i].size - 1); | |
803 | } | |
804 | ||
805 | return p - data; | |
806 | } | |
807 | ||
452a6bf9 MCC |
808 | #ifdef CONFIG_EDAC_DEBUG |
809 | static ssize_t edac_fake_inject_write(struct file *file, | |
810 | const char __user *data, | |
811 | size_t count, loff_t *ppos) | |
812 | { | |
813 | struct device *dev = file->private_data; | |
814 | struct mem_ctl_info *mci = to_mci(dev); | |
815 | static enum hw_event_mc_err_type type; | |
38ced28b MCC |
816 | u16 errcount = mci->fake_inject_count; |
817 | ||
818 | if (!errcount) | |
819 | errcount = 1; | |
452a6bf9 MCC |
820 | |
821 | type = mci->fake_inject_ue ? HW_EVENT_ERR_UNCORRECTED | |
822 | : HW_EVENT_ERR_CORRECTED; | |
823 | ||
824 | printk(KERN_DEBUG | |
38ced28b MCC |
825 | "Generating %d %s fake error%s to %d.%d.%d to test core handling. NOTE: this won't test the driver-specific decoding logic.\n", |
826 | errcount, | |
452a6bf9 | 827 | (type == HW_EVENT_ERR_UNCORRECTED) ? "UE" : "CE", |
38ced28b | 828 | errcount > 1 ? "s" : "", |
452a6bf9 MCC |
829 | mci->fake_inject_layer[0], |
830 | mci->fake_inject_layer[1], | |
831 | mci->fake_inject_layer[2] | |
832 | ); | |
38ced28b | 833 | edac_mc_handle_error(type, mci, errcount, 0, 0, 0, |
452a6bf9 MCC |
834 | mci->fake_inject_layer[0], |
835 | mci->fake_inject_layer[1], | |
836 | mci->fake_inject_layer[2], | |
03f7eae8 | 837 | "FAKE ERROR", "for EDAC testing only"); |
452a6bf9 MCC |
838 | |
839 | return count; | |
840 | } | |
841 | ||
452a6bf9 | 842 | static const struct file_operations debug_fake_inject_fops = { |
db7312a2 | 843 | .open = simple_open, |
452a6bf9 MCC |
844 | .write = edac_fake_inject_write, |
845 | .llseek = generic_file_llseek, | |
846 | }; | |
847 | #endif | |
848 | ||
7c9281d7 | 849 | /* default Control file */ |
7a623c03 | 850 | DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store); |
7c9281d7 DT |
851 | |
852 | /* default Attribute files */ | |
7a623c03 MCC |
853 | DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL); |
854 | DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL); | |
855 | DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL); | |
856 | DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL); | |
857 | DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL); | |
858 | DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL); | |
859 | DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL); | |
8ad6c78a | 860 | DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL); |
7c9281d7 DT |
861 | |
862 | /* memory scrubber attribute file */ | |
e7100478 | 863 | DEVICE_ATTR(sdram_scrub_rate, 0, NULL, NULL); |
7c9281d7 | 864 | |
7a623c03 MCC |
865 | static struct attribute *mci_attrs[] = { |
866 | &dev_attr_reset_counters.attr, | |
867 | &dev_attr_mc_name.attr, | |
868 | &dev_attr_size_mb.attr, | |
869 | &dev_attr_seconds_since_reset.attr, | |
870 | &dev_attr_ue_noinfo_count.attr, | |
871 | &dev_attr_ce_noinfo_count.attr, | |
872 | &dev_attr_ue_count.attr, | |
873 | &dev_attr_ce_count.attr, | |
8ad6c78a | 874 | &dev_attr_max_location.attr, |
7c9281d7 DT |
875 | NULL |
876 | }; | |
877 | ||
7a623c03 MCC |
878 | static struct attribute_group mci_attr_grp = { |
879 | .attrs = mci_attrs, | |
cc301b3a MCC |
880 | }; |
881 | ||
7a623c03 MCC |
882 | static const struct attribute_group *mci_attr_groups[] = { |
883 | &mci_attr_grp, | |
884 | NULL | |
cc301b3a MCC |
885 | }; |
886 | ||
de3910eb | 887 | static void mci_attr_release(struct device *dev) |
42a8e397 | 888 | { |
de3910eb MCC |
889 | struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev); |
890 | ||
956b9ba1 | 891 | edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev)); |
de3910eb | 892 | kfree(mci); |
42a8e397 DT |
893 | } |
894 | ||
7a623c03 MCC |
895 | static struct device_type mci_attr_type = { |
896 | .groups = mci_attr_groups, | |
897 | .release = mci_attr_release, | |
898 | }; | |
8096cfaf | 899 | |
452a6bf9 | 900 | #ifdef CONFIG_EDAC_DEBUG |
e7930ba4 RH |
901 | static struct dentry *edac_debugfs; |
902 | ||
903 | int __init edac_debugfs_init(void) | |
904 | { | |
905 | edac_debugfs = debugfs_create_dir("edac", NULL); | |
906 | if (IS_ERR(edac_debugfs)) { | |
907 | edac_debugfs = NULL; | |
908 | return -ENOMEM; | |
909 | } | |
910 | return 0; | |
911 | } | |
912 | ||
913 | void __exit edac_debugfs_exit(void) | |
914 | { | |
915 | debugfs_remove(edac_debugfs); | |
916 | } | |
917 | ||
452a6bf9 MCC |
918 | int edac_create_debug_nodes(struct mem_ctl_info *mci) |
919 | { | |
920 | struct dentry *d, *parent; | |
921 | char name[80]; | |
922 | int i; | |
923 | ||
e7930ba4 RH |
924 | if (!edac_debugfs) |
925 | return -ENODEV; | |
926 | ||
927 | d = debugfs_create_dir(mci->dev.kobj.name, edac_debugfs); | |
452a6bf9 MCC |
928 | if (!d) |
929 | return -ENOMEM; | |
930 | parent = d; | |
931 | ||
932 | for (i = 0; i < mci->n_layers; i++) { | |
933 | sprintf(name, "fake_inject_%s", | |
934 | edac_layer_name[mci->layers[i].type]); | |
935 | d = debugfs_create_u8(name, S_IRUGO | S_IWUSR, parent, | |
936 | &mci->fake_inject_layer[i]); | |
937 | if (!d) | |
938 | goto nomem; | |
939 | } | |
940 | ||
941 | d = debugfs_create_bool("fake_inject_ue", S_IRUGO | S_IWUSR, parent, | |
942 | &mci->fake_inject_ue); | |
943 | if (!d) | |
944 | goto nomem; | |
945 | ||
38ced28b MCC |
946 | d = debugfs_create_u16("fake_inject_count", S_IRUGO | S_IWUSR, parent, |
947 | &mci->fake_inject_count); | |
948 | if (!d) | |
949 | goto nomem; | |
950 | ||
452a6bf9 MCC |
951 | d = debugfs_create_file("fake_inject", S_IWUSR, parent, |
952 | &mci->dev, | |
953 | &debug_fake_inject_fops); | |
954 | if (!d) | |
955 | goto nomem; | |
956 | ||
e7930ba4 | 957 | mci->debugfs = parent; |
452a6bf9 MCC |
958 | return 0; |
959 | nomem: | |
960 | debugfs_remove(mci->debugfs); | |
961 | return -ENOMEM; | |
962 | } | |
963 | #endif | |
964 | ||
7c9281d7 DT |
965 | /* |
966 | * Create a new Memory Controller kobject instance, | |
967 | * mc<id> under the 'mc' directory | |
968 | * | |
969 | * Return: | |
970 | * 0 Success | |
971 | * !0 Failure | |
972 | */ | |
973 | int edac_create_sysfs_mci_device(struct mem_ctl_info *mci) | |
974 | { | |
7a623c03 | 975 | int i, err; |
7c9281d7 | 976 | |
de3910eb MCC |
977 | /* |
978 | * The memory controller needs its own bus, in order to avoid | |
979 | * namespace conflicts at /sys/bus/edac. | |
980 | */ | |
981 | mci->bus.name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx); | |
982 | if (!mci->bus.name) | |
983 | return -ENOMEM; | |
956b9ba1 | 984 | edac_dbg(0, "creating bus %s\n", mci->bus.name); |
de3910eb MCC |
985 | err = bus_register(&mci->bus); |
986 | if (err < 0) | |
987 | return err; | |
7c9281d7 | 988 | |
7a623c03 | 989 | /* get the /sys/devices/system/edac subsys reference */ |
7a623c03 MCC |
990 | mci->dev.type = &mci_attr_type; |
991 | device_initialize(&mci->dev); | |
7c9281d7 | 992 | |
de3910eb | 993 | mci->dev.parent = mci_pdev; |
7a623c03 MCC |
994 | mci->dev.bus = &mci->bus; |
995 | dev_set_name(&mci->dev, "mc%d", mci->mc_idx); | |
996 | dev_set_drvdata(&mci->dev, mci); | |
997 | pm_runtime_forbid(&mci->dev); | |
998 | ||
956b9ba1 | 999 | edac_dbg(0, "creating device %s\n", dev_name(&mci->dev)); |
7a623c03 MCC |
1000 | err = device_add(&mci->dev); |
1001 | if (err < 0) { | |
1002 | bus_unregister(&mci->bus); | |
1003 | kfree(mci->bus.name); | |
1004 | return err; | |
42a8e397 DT |
1005 | } |
1006 | ||
e7100478 MCC |
1007 | if (mci->set_sdram_scrub_rate || mci->get_sdram_scrub_rate) { |
1008 | if (mci->get_sdram_scrub_rate) { | |
1009 | dev_attr_sdram_scrub_rate.attr.mode |= S_IRUGO; | |
1010 | dev_attr_sdram_scrub_rate.show = &mci_sdram_scrub_rate_show; | |
1011 | } | |
1012 | if (mci->set_sdram_scrub_rate) { | |
1013 | dev_attr_sdram_scrub_rate.attr.mode |= S_IWUSR; | |
1014 | dev_attr_sdram_scrub_rate.store = &mci_sdram_scrub_rate_store; | |
1015 | } | |
1016 | err = device_create_file(&mci->dev, | |
1017 | &dev_attr_sdram_scrub_rate); | |
1018 | if (err) { | |
1019 | edac_dbg(1, "failure: create sdram_scrub_rate\n"); | |
1020 | goto fail2; | |
1021 | } | |
1022 | } | |
7a623c03 MCC |
1023 | /* |
1024 | * Create the dimm/rank devices | |
7c9281d7 | 1025 | */ |
7a623c03 | 1026 | for (i = 0; i < mci->tot_dimms; i++) { |
de3910eb | 1027 | struct dimm_info *dimm = mci->dimms[i]; |
7a623c03 MCC |
1028 | /* Only expose populated DIMMs */ |
1029 | if (dimm->nr_pages == 0) | |
1030 | continue; | |
1031 | #ifdef CONFIG_EDAC_DEBUG | |
956b9ba1 | 1032 | edac_dbg(1, "creating dimm%d, located at ", i); |
7a623c03 MCC |
1033 | if (edac_debug_level >= 1) { |
1034 | int lay; | |
1035 | for (lay = 0; lay < mci->n_layers; lay++) | |
1036 | printk(KERN_CONT "%s %d ", | |
1037 | edac_layer_name[mci->layers[lay].type], | |
1038 | dimm->location[lay]); | |
1039 | printk(KERN_CONT "\n"); | |
7c9281d7 | 1040 | } |
7a623c03 | 1041 | #endif |
19974710 MCC |
1042 | err = edac_create_dimm_object(mci, dimm, i); |
1043 | if (err) { | |
956b9ba1 | 1044 | edac_dbg(1, "failure: create dimm %d obj\n", i); |
19974710 MCC |
1045 | goto fail; |
1046 | } | |
7c9281d7 DT |
1047 | } |
1048 | ||
19974710 | 1049 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 MCC |
1050 | err = edac_create_csrow_objects(mci); |
1051 | if (err < 0) | |
1052 | goto fail; | |
19974710 | 1053 | #endif |
7a623c03 | 1054 | |
452a6bf9 MCC |
1055 | #ifdef CONFIG_EDAC_DEBUG |
1056 | edac_create_debug_nodes(mci); | |
1057 | #endif | |
7c9281d7 DT |
1058 | return 0; |
1059 | ||
7a623c03 | 1060 | fail: |
079708b9 | 1061 | for (i--; i >= 0; i--) { |
de3910eb | 1062 | struct dimm_info *dimm = mci->dimms[i]; |
7a623c03 MCC |
1063 | if (dimm->nr_pages == 0) |
1064 | continue; | |
44d22e24 | 1065 | device_unregister(&dimm->dev); |
7c9281d7 | 1066 | } |
e7100478 | 1067 | fail2: |
44d22e24 | 1068 | device_unregister(&mci->dev); |
7a623c03 MCC |
1069 | bus_unregister(&mci->bus); |
1070 | kfree(mci->bus.name); | |
7c9281d7 DT |
1071 | return err; |
1072 | } | |
1073 | ||
1074 | /* | |
1075 | * remove a Memory Controller instance | |
1076 | */ | |
1077 | void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci) | |
1078 | { | |
7a623c03 | 1079 | int i; |
7c9281d7 | 1080 | |
956b9ba1 | 1081 | edac_dbg(0, "\n"); |
7c9281d7 | 1082 | |
452a6bf9 MCC |
1083 | #ifdef CONFIG_EDAC_DEBUG |
1084 | debugfs_remove(mci->debugfs); | |
1085 | #endif | |
19974710 | 1086 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 | 1087 | edac_delete_csrow_objects(mci); |
19974710 | 1088 | #endif |
7c9281d7 | 1089 | |
7a623c03 | 1090 | for (i = 0; i < mci->tot_dimms; i++) { |
de3910eb | 1091 | struct dimm_info *dimm = mci->dimms[i]; |
7a623c03 MCC |
1092 | if (dimm->nr_pages == 0) |
1093 | continue; | |
956b9ba1 | 1094 | edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev)); |
44d22e24 | 1095 | device_unregister(&dimm->dev); |
6fe1108f | 1096 | } |
7c9281d7 | 1097 | } |
8096cfaf | 1098 | |
7a623c03 MCC |
1099 | void edac_unregister_sysfs(struct mem_ctl_info *mci) |
1100 | { | |
956b9ba1 | 1101 | edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev)); |
44d22e24 | 1102 | device_unregister(&mci->dev); |
7a623c03 MCC |
1103 | bus_unregister(&mci->bus); |
1104 | kfree(mci->bus.name); | |
1105 | } | |
8096cfaf | 1106 | |
de3910eb | 1107 | static void mc_attr_release(struct device *dev) |
7a623c03 | 1108 | { |
de3910eb MCC |
1109 | /* |
1110 | * There's no container structure here, as this is just the mci | |
1111 | * parent device, used to create the /sys/devices/mc sysfs node. | |
1112 | * So, there are no attributes on it. | |
1113 | */ | |
956b9ba1 | 1114 | edac_dbg(1, "Releasing device %s\n", dev_name(dev)); |
de3910eb | 1115 | kfree(dev); |
7a623c03 | 1116 | } |
8096cfaf | 1117 | |
7a623c03 MCC |
1118 | static struct device_type mc_attr_type = { |
1119 | .release = mc_attr_release, | |
1120 | }; | |
8096cfaf | 1121 | /* |
7a623c03 | 1122 | * Init/exit code for the module. Basically, creates/removes /sys/class/rc |
8096cfaf | 1123 | */ |
7a623c03 | 1124 | int __init edac_mc_sysfs_init(void) |
8096cfaf | 1125 | { |
fe5ff8b8 | 1126 | struct bus_type *edac_subsys; |
7a623c03 | 1127 | int err; |
8096cfaf | 1128 | |
fe5ff8b8 KS |
1129 | /* get the /sys/devices/system/edac subsys reference */ |
1130 | edac_subsys = edac_get_sysfs_subsys(); | |
1131 | if (edac_subsys == NULL) { | |
956b9ba1 | 1132 | edac_dbg(1, "no edac_subsys\n"); |
2d56b109 DK |
1133 | err = -EINVAL; |
1134 | goto out; | |
8096cfaf DT |
1135 | } |
1136 | ||
de3910eb | 1137 | mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL); |
2d56b109 DK |
1138 | if (!mci_pdev) { |
1139 | err = -ENOMEM; | |
1140 | goto out_put_sysfs; | |
1141 | } | |
de3910eb MCC |
1142 | |
1143 | mci_pdev->bus = edac_subsys; | |
1144 | mci_pdev->type = &mc_attr_type; | |
1145 | device_initialize(mci_pdev); | |
1146 | dev_set_name(mci_pdev, "mc"); | |
8096cfaf | 1147 | |
de3910eb | 1148 | err = device_add(mci_pdev); |
7a623c03 | 1149 | if (err < 0) |
2d56b109 | 1150 | goto out_dev_free; |
8096cfaf | 1151 | |
956b9ba1 | 1152 | edac_dbg(0, "device %s created\n", dev_name(mci_pdev)); |
de3910eb | 1153 | |
8096cfaf | 1154 | return 0; |
2d56b109 DK |
1155 | |
1156 | out_dev_free: | |
1157 | kfree(mci_pdev); | |
1158 | out_put_sysfs: | |
1159 | edac_put_sysfs_subsys(); | |
1160 | out: | |
1161 | return err; | |
8096cfaf DT |
1162 | } |
1163 | ||
7a623c03 | 1164 | void __exit edac_mc_sysfs_exit(void) |
8096cfaf | 1165 | { |
44d22e24 | 1166 | device_unregister(mci_pdev); |
fe5ff8b8 | 1167 | edac_put_sysfs_subsys(); |
8096cfaf | 1168 | } |