Commit | Line | Data |
---|---|---|
7c9281d7 DT |
1 | /* |
2 | * edac_mc kernel module | |
42a8e397 DT |
3 | * (C) 2005-2007 Linux Networx (http://lnxi.com) |
4 | * | |
7c9281d7 DT |
5 | * This file may be distributed under the terms of the |
6 | * GNU General Public License. | |
7 | * | |
42a8e397 | 8 | * Written Doug Thompson <norsk5@xmission.com> www.softwarebitmaker.com |
7c9281d7 | 9 | * |
7a623c03 MCC |
10 | * (c) 2012 - Mauro Carvalho Chehab <mchehab@redhat.com> |
11 | * The entire API were re-written, and ported to use struct device | |
12 | * | |
7c9281d7 DT |
13 | */ |
14 | ||
7c9281d7 | 15 | #include <linux/ctype.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
30e1f7a8 | 17 | #include <linux/edac.h> |
8096cfaf | 18 | #include <linux/bug.h> |
7a623c03 | 19 | #include <linux/pm_runtime.h> |
452a6bf9 | 20 | #include <linux/uaccess.h> |
7c9281d7 | 21 | |
20bcb7a8 | 22 | #include "edac_core.h" |
7c9281d7 DT |
23 | #include "edac_module.h" |
24 | ||
25 | /* MC EDAC Controls, setable by module parameter, and sysfs */ | |
4de78c68 DJ |
26 | static int edac_mc_log_ue = 1; |
27 | static int edac_mc_log_ce = 1; | |
f044091c | 28 | static int edac_mc_panic_on_ue; |
4de78c68 | 29 | static int edac_mc_poll_msec = 1000; |
7c9281d7 DT |
30 | |
31 | /* Getter functions for above */ | |
4de78c68 | 32 | int edac_mc_get_log_ue(void) |
7c9281d7 | 33 | { |
4de78c68 | 34 | return edac_mc_log_ue; |
7c9281d7 DT |
35 | } |
36 | ||
4de78c68 | 37 | int edac_mc_get_log_ce(void) |
7c9281d7 | 38 | { |
4de78c68 | 39 | return edac_mc_log_ce; |
7c9281d7 DT |
40 | } |
41 | ||
4de78c68 | 42 | int edac_mc_get_panic_on_ue(void) |
7c9281d7 | 43 | { |
4de78c68 | 44 | return edac_mc_panic_on_ue; |
7c9281d7 DT |
45 | } |
46 | ||
81d87cb1 DJ |
47 | /* this is temporary */ |
48 | int edac_mc_get_poll_msec(void) | |
49 | { | |
4de78c68 | 50 | return edac_mc_poll_msec; |
7c9281d7 DT |
51 | } |
52 | ||
096846e2 AJ |
53 | static int edac_set_poll_msec(const char *val, struct kernel_param *kp) |
54 | { | |
55 | long l; | |
56 | int ret; | |
57 | ||
58 | if (!val) | |
59 | return -EINVAL; | |
60 | ||
61 | ret = strict_strtol(val, 0, &l); | |
62 | if (ret == -EINVAL || ((int)l != l)) | |
63 | return -EINVAL; | |
64 | *((int *)kp->arg) = l; | |
65 | ||
66 | /* notify edac_mc engine to reset the poll period */ | |
67 | edac_mc_reset_delay_period(l); | |
68 | ||
69 | return 0; | |
70 | } | |
71 | ||
7c9281d7 | 72 | /* Parameter declarations for above */ |
4de78c68 DJ |
73 | module_param(edac_mc_panic_on_ue, int, 0644); |
74 | MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on"); | |
75 | module_param(edac_mc_log_ue, int, 0644); | |
76 | MODULE_PARM_DESC(edac_mc_log_ue, | |
079708b9 | 77 | "Log uncorrectable error to console: 0=off 1=on"); |
4de78c68 DJ |
78 | module_param(edac_mc_log_ce, int, 0644); |
79 | MODULE_PARM_DESC(edac_mc_log_ce, | |
079708b9 | 80 | "Log correctable error to console: 0=off 1=on"); |
096846e2 AJ |
81 | module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int, |
82 | &edac_mc_poll_msec, 0644); | |
4de78c68 | 83 | MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds"); |
7c9281d7 | 84 | |
de3910eb | 85 | static struct device *mci_pdev; |
7a623c03 | 86 | |
7c9281d7 DT |
87 | /* |
88 | * various constants for Memory Controllers | |
89 | */ | |
90 | static const char *mem_types[] = { | |
91 | [MEM_EMPTY] = "Empty", | |
92 | [MEM_RESERVED] = "Reserved", | |
93 | [MEM_UNKNOWN] = "Unknown", | |
94 | [MEM_FPM] = "FPM", | |
95 | [MEM_EDO] = "EDO", | |
96 | [MEM_BEDO] = "BEDO", | |
97 | [MEM_SDR] = "Unbuffered-SDR", | |
98 | [MEM_RDR] = "Registered-SDR", | |
99 | [MEM_DDR] = "Unbuffered-DDR", | |
100 | [MEM_RDDR] = "Registered-DDR", | |
1a9b85e6 DJ |
101 | [MEM_RMBS] = "RMBS", |
102 | [MEM_DDR2] = "Unbuffered-DDR2", | |
103 | [MEM_FB_DDR2] = "FullyBuffered-DDR2", | |
1d5f726c | 104 | [MEM_RDDR2] = "Registered-DDR2", |
b1cfebc9 YS |
105 | [MEM_XDR] = "XDR", |
106 | [MEM_DDR3] = "Unbuffered-DDR3", | |
107 | [MEM_RDDR3] = "Registered-DDR3" | |
7c9281d7 DT |
108 | }; |
109 | ||
110 | static const char *dev_types[] = { | |
111 | [DEV_UNKNOWN] = "Unknown", | |
112 | [DEV_X1] = "x1", | |
113 | [DEV_X2] = "x2", | |
114 | [DEV_X4] = "x4", | |
115 | [DEV_X8] = "x8", | |
116 | [DEV_X16] = "x16", | |
117 | [DEV_X32] = "x32", | |
118 | [DEV_X64] = "x64" | |
119 | }; | |
120 | ||
121 | static const char *edac_caps[] = { | |
122 | [EDAC_UNKNOWN] = "Unknown", | |
123 | [EDAC_NONE] = "None", | |
124 | [EDAC_RESERVED] = "Reserved", | |
125 | [EDAC_PARITY] = "PARITY", | |
126 | [EDAC_EC] = "EC", | |
127 | [EDAC_SECDED] = "SECDED", | |
128 | [EDAC_S2ECD2ED] = "S2ECD2ED", | |
129 | [EDAC_S4ECD4ED] = "S4ECD4ED", | |
130 | [EDAC_S8ECD8ED] = "S8ECD8ED", | |
131 | [EDAC_S16ECD16ED] = "S16ECD16ED" | |
132 | }; | |
133 | ||
19974710 | 134 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 MCC |
135 | /* |
136 | * EDAC sysfs CSROW data structures and methods | |
137 | */ | |
138 | ||
139 | #define to_csrow(k) container_of(k, struct csrow_info, dev) | |
140 | ||
141 | /* | |
142 | * We need it to avoid namespace conflicts between the legacy API | |
143 | * and the per-dimm/per-rank one | |
7c9281d7 | 144 | */ |
7a623c03 MCC |
145 | #define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \ |
146 | struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store) | |
147 | ||
148 | struct dev_ch_attribute { | |
149 | struct device_attribute attr; | |
150 | int channel; | |
151 | }; | |
152 | ||
153 | #define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \ | |
154 | struct dev_ch_attribute dev_attr_legacy_##_name = \ | |
155 | { __ATTR(_name, _mode, _show, _store), (_var) } | |
156 | ||
157 | #define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel) | |
7c9281d7 DT |
158 | |
159 | /* Set of more default csrow<id> attribute show/store functions */ | |
7a623c03 MCC |
160 | static ssize_t csrow_ue_count_show(struct device *dev, |
161 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 162 | { |
7a623c03 MCC |
163 | struct csrow_info *csrow = to_csrow(dev); |
164 | ||
079708b9 | 165 | return sprintf(data, "%u\n", csrow->ue_count); |
7c9281d7 DT |
166 | } |
167 | ||
7a623c03 MCC |
168 | static ssize_t csrow_ce_count_show(struct device *dev, |
169 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 170 | { |
7a623c03 MCC |
171 | struct csrow_info *csrow = to_csrow(dev); |
172 | ||
079708b9 | 173 | return sprintf(data, "%u\n", csrow->ce_count); |
7c9281d7 DT |
174 | } |
175 | ||
7a623c03 MCC |
176 | static ssize_t csrow_size_show(struct device *dev, |
177 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 178 | { |
7a623c03 | 179 | struct csrow_info *csrow = to_csrow(dev); |
a895bf8b MCC |
180 | int i; |
181 | u32 nr_pages = 0; | |
182 | ||
183 | for (i = 0; i < csrow->nr_channels; i++) | |
de3910eb | 184 | nr_pages += csrow->channels[i]->dimm->nr_pages; |
a895bf8b | 185 | return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages)); |
7c9281d7 DT |
186 | } |
187 | ||
7a623c03 MCC |
188 | static ssize_t csrow_mem_type_show(struct device *dev, |
189 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 190 | { |
7a623c03 MCC |
191 | struct csrow_info *csrow = to_csrow(dev); |
192 | ||
de3910eb | 193 | return sprintf(data, "%s\n", mem_types[csrow->channels[0]->dimm->mtype]); |
7c9281d7 DT |
194 | } |
195 | ||
7a623c03 MCC |
196 | static ssize_t csrow_dev_type_show(struct device *dev, |
197 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 198 | { |
7a623c03 MCC |
199 | struct csrow_info *csrow = to_csrow(dev); |
200 | ||
de3910eb | 201 | return sprintf(data, "%s\n", dev_types[csrow->channels[0]->dimm->dtype]); |
7c9281d7 DT |
202 | } |
203 | ||
7a623c03 MCC |
204 | static ssize_t csrow_edac_mode_show(struct device *dev, |
205 | struct device_attribute *mattr, | |
206 | char *data) | |
7c9281d7 | 207 | { |
7a623c03 MCC |
208 | struct csrow_info *csrow = to_csrow(dev); |
209 | ||
de3910eb | 210 | return sprintf(data, "%s\n", edac_caps[csrow->channels[0]->dimm->edac_mode]); |
7c9281d7 DT |
211 | } |
212 | ||
213 | /* show/store functions for DIMM Label attributes */ | |
7a623c03 MCC |
214 | static ssize_t channel_dimm_label_show(struct device *dev, |
215 | struct device_attribute *mattr, | |
216 | char *data) | |
7c9281d7 | 217 | { |
7a623c03 MCC |
218 | struct csrow_info *csrow = to_csrow(dev); |
219 | unsigned chan = to_channel(mattr); | |
de3910eb | 220 | struct rank_info *rank = csrow->channels[chan]; |
7a623c03 | 221 | |
124682c7 | 222 | /* if field has not been initialized, there is nothing to send */ |
7a623c03 | 223 | if (!rank->dimm->label[0]) |
124682c7 AJ |
224 | return 0; |
225 | ||
226 | return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", | |
7a623c03 | 227 | rank->dimm->label); |
7c9281d7 DT |
228 | } |
229 | ||
7a623c03 MCC |
230 | static ssize_t channel_dimm_label_store(struct device *dev, |
231 | struct device_attribute *mattr, | |
232 | const char *data, size_t count) | |
7c9281d7 | 233 | { |
7a623c03 MCC |
234 | struct csrow_info *csrow = to_csrow(dev); |
235 | unsigned chan = to_channel(mattr); | |
de3910eb | 236 | struct rank_info *rank = csrow->channels[chan]; |
7a623c03 | 237 | |
7c9281d7 DT |
238 | ssize_t max_size = 0; |
239 | ||
079708b9 | 240 | max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1); |
7a623c03 MCC |
241 | strncpy(rank->dimm->label, data, max_size); |
242 | rank->dimm->label[max_size] = '\0'; | |
7c9281d7 DT |
243 | |
244 | return max_size; | |
245 | } | |
246 | ||
247 | /* show function for dynamic chX_ce_count attribute */ | |
7a623c03 MCC |
248 | static ssize_t channel_ce_count_show(struct device *dev, |
249 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 250 | { |
7a623c03 MCC |
251 | struct csrow_info *csrow = to_csrow(dev); |
252 | unsigned chan = to_channel(mattr); | |
de3910eb | 253 | struct rank_info *rank = csrow->channels[chan]; |
7a623c03 MCC |
254 | |
255 | return sprintf(data, "%u\n", rank->ce_count); | |
7c9281d7 DT |
256 | } |
257 | ||
7a623c03 MCC |
258 | /* cwrow<id>/attribute files */ |
259 | DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL); | |
260 | DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL); | |
261 | DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL); | |
262 | DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL); | |
263 | DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL); | |
264 | DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL); | |
7c9281d7 | 265 | |
7a623c03 MCC |
266 | /* default attributes of the CSROW<id> object */ |
267 | static struct attribute *csrow_attrs[] = { | |
268 | &dev_attr_legacy_dev_type.attr, | |
269 | &dev_attr_legacy_mem_type.attr, | |
270 | &dev_attr_legacy_edac_mode.attr, | |
271 | &dev_attr_legacy_size_mb.attr, | |
272 | &dev_attr_legacy_ue_count.attr, | |
273 | &dev_attr_legacy_ce_count.attr, | |
274 | NULL, | |
275 | }; | |
7c9281d7 | 276 | |
7a623c03 MCC |
277 | static struct attribute_group csrow_attr_grp = { |
278 | .attrs = csrow_attrs, | |
279 | }; | |
7c9281d7 | 280 | |
7a623c03 MCC |
281 | static const struct attribute_group *csrow_attr_groups[] = { |
282 | &csrow_attr_grp, | |
283 | NULL | |
284 | }; | |
7c9281d7 | 285 | |
de3910eb | 286 | static void csrow_attr_release(struct device *dev) |
7c9281d7 | 287 | { |
de3910eb MCC |
288 | struct csrow_info *csrow = container_of(dev, struct csrow_info, dev); |
289 | ||
956b9ba1 | 290 | edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev)); |
de3910eb | 291 | kfree(csrow); |
7c9281d7 DT |
292 | } |
293 | ||
7a623c03 MCC |
294 | static struct device_type csrow_attr_type = { |
295 | .groups = csrow_attr_groups, | |
296 | .release = csrow_attr_release, | |
7c9281d7 DT |
297 | }; |
298 | ||
7a623c03 MCC |
299 | /* |
300 | * possible dynamic channel DIMM Label attribute files | |
301 | * | |
302 | */ | |
7c9281d7 | 303 | |
7a623c03 | 304 | #define EDAC_NR_CHANNELS 6 |
7c9281d7 | 305 | |
7a623c03 | 306 | DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 307 | channel_dimm_label_show, channel_dimm_label_store, 0); |
7a623c03 | 308 | DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 309 | channel_dimm_label_show, channel_dimm_label_store, 1); |
7a623c03 | 310 | DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 311 | channel_dimm_label_show, channel_dimm_label_store, 2); |
7a623c03 | 312 | DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 313 | channel_dimm_label_show, channel_dimm_label_store, 3); |
7a623c03 | 314 | DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 315 | channel_dimm_label_show, channel_dimm_label_store, 4); |
7a623c03 | 316 | DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 317 | channel_dimm_label_show, channel_dimm_label_store, 5); |
7c9281d7 DT |
318 | |
319 | /* Total possible dynamic DIMM Label attribute file table */ | |
7a623c03 MCC |
320 | static struct device_attribute *dynamic_csrow_dimm_attr[] = { |
321 | &dev_attr_legacy_ch0_dimm_label.attr, | |
322 | &dev_attr_legacy_ch1_dimm_label.attr, | |
323 | &dev_attr_legacy_ch2_dimm_label.attr, | |
324 | &dev_attr_legacy_ch3_dimm_label.attr, | |
325 | &dev_attr_legacy_ch4_dimm_label.attr, | |
326 | &dev_attr_legacy_ch5_dimm_label.attr | |
7c9281d7 DT |
327 | }; |
328 | ||
329 | /* possible dynamic channel ce_count attribute files */ | |
7a623c03 MCC |
330 | DEVICE_CHANNEL(ch0_ce_count, S_IRUGO | S_IWUSR, |
331 | channel_ce_count_show, NULL, 0); | |
332 | DEVICE_CHANNEL(ch1_ce_count, S_IRUGO | S_IWUSR, | |
333 | channel_ce_count_show, NULL, 1); | |
334 | DEVICE_CHANNEL(ch2_ce_count, S_IRUGO | S_IWUSR, | |
335 | channel_ce_count_show, NULL, 2); | |
336 | DEVICE_CHANNEL(ch3_ce_count, S_IRUGO | S_IWUSR, | |
337 | channel_ce_count_show, NULL, 3); | |
338 | DEVICE_CHANNEL(ch4_ce_count, S_IRUGO | S_IWUSR, | |
339 | channel_ce_count_show, NULL, 4); | |
340 | DEVICE_CHANNEL(ch5_ce_count, S_IRUGO | S_IWUSR, | |
341 | channel_ce_count_show, NULL, 5); | |
7c9281d7 DT |
342 | |
343 | /* Total possible dynamic ce_count attribute file table */ | |
7a623c03 MCC |
344 | static struct device_attribute *dynamic_csrow_ce_count_attr[] = { |
345 | &dev_attr_legacy_ch0_ce_count.attr, | |
346 | &dev_attr_legacy_ch1_ce_count.attr, | |
347 | &dev_attr_legacy_ch2_ce_count.attr, | |
348 | &dev_attr_legacy_ch3_ce_count.attr, | |
349 | &dev_attr_legacy_ch4_ce_count.attr, | |
350 | &dev_attr_legacy_ch5_ce_count.attr | |
7c9281d7 DT |
351 | }; |
352 | ||
e39f4ea9 MCC |
353 | static inline int nr_pages_per_csrow(struct csrow_info *csrow) |
354 | { | |
355 | int chan, nr_pages = 0; | |
356 | ||
357 | for (chan = 0; chan < csrow->nr_channels; chan++) | |
de3910eb | 358 | nr_pages += csrow->channels[chan]->dimm->nr_pages; |
e39f4ea9 MCC |
359 | |
360 | return nr_pages; | |
361 | } | |
362 | ||
7a623c03 MCC |
363 | /* Create a CSROW object under specifed edac_mc_device */ |
364 | static int edac_create_csrow_object(struct mem_ctl_info *mci, | |
365 | struct csrow_info *csrow, int index) | |
7c9281d7 | 366 | { |
7a623c03 | 367 | int err, chan; |
7c9281d7 | 368 | |
7a623c03 MCC |
369 | if (csrow->nr_channels >= EDAC_NR_CHANNELS) |
370 | return -ENODEV; | |
7c9281d7 | 371 | |
7a623c03 MCC |
372 | csrow->dev.type = &csrow_attr_type; |
373 | csrow->dev.bus = &mci->bus; | |
374 | device_initialize(&csrow->dev); | |
375 | csrow->dev.parent = &mci->dev; | |
376 | dev_set_name(&csrow->dev, "csrow%d", index); | |
377 | dev_set_drvdata(&csrow->dev, csrow); | |
7c9281d7 | 378 | |
956b9ba1 JP |
379 | edac_dbg(0, "creating (virtual) csrow node %s\n", |
380 | dev_name(&csrow->dev)); | |
7c9281d7 | 381 | |
7a623c03 MCC |
382 | err = device_add(&csrow->dev); |
383 | if (err < 0) | |
384 | return err; | |
7c9281d7 | 385 | |
7a623c03 | 386 | for (chan = 0; chan < csrow->nr_channels; chan++) { |
e39f4ea9 | 387 | /* Only expose populated DIMMs */ |
de3910eb | 388 | if (!csrow->channels[chan]->dimm->nr_pages) |
e39f4ea9 | 389 | continue; |
7a623c03 MCC |
390 | err = device_create_file(&csrow->dev, |
391 | dynamic_csrow_dimm_attr[chan]); | |
392 | if (err < 0) | |
393 | goto error; | |
394 | err = device_create_file(&csrow->dev, | |
395 | dynamic_csrow_ce_count_attr[chan]); | |
396 | if (err < 0) { | |
397 | device_remove_file(&csrow->dev, | |
398 | dynamic_csrow_dimm_attr[chan]); | |
399 | goto error; | |
400 | } | |
401 | } | |
8096cfaf | 402 | |
7a623c03 | 403 | return 0; |
8096cfaf | 404 | |
7a623c03 MCC |
405 | error: |
406 | for (--chan; chan >= 0; chan--) { | |
407 | device_remove_file(&csrow->dev, | |
408 | dynamic_csrow_dimm_attr[chan]); | |
409 | device_remove_file(&csrow->dev, | |
410 | dynamic_csrow_ce_count_attr[chan]); | |
411 | } | |
412 | put_device(&csrow->dev); | |
7c9281d7 | 413 | |
7a623c03 MCC |
414 | return err; |
415 | } | |
7c9281d7 DT |
416 | |
417 | /* Create a CSROW object under specifed edac_mc_device */ | |
7a623c03 | 418 | static int edac_create_csrow_objects(struct mem_ctl_info *mci) |
7c9281d7 | 419 | { |
7a623c03 MCC |
420 | int err, i, chan; |
421 | struct csrow_info *csrow; | |
7c9281d7 | 422 | |
7a623c03 | 423 | for (i = 0; i < mci->nr_csrows; i++) { |
de3910eb | 424 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
425 | if (!nr_pages_per_csrow(csrow)) |
426 | continue; | |
de3910eb | 427 | err = edac_create_csrow_object(mci, mci->csrows[i], i); |
7a623c03 MCC |
428 | if (err < 0) |
429 | goto error; | |
430 | } | |
431 | return 0; | |
8096cfaf | 432 | |
7a623c03 MCC |
433 | error: |
434 | for (--i; i >= 0; i--) { | |
de3910eb | 435 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
436 | if (!nr_pages_per_csrow(csrow)) |
437 | continue; | |
7a623c03 | 438 | for (chan = csrow->nr_channels - 1; chan >= 0; chan--) { |
de3910eb | 439 | if (!csrow->channels[chan]->dimm->nr_pages) |
e39f4ea9 | 440 | continue; |
7a623c03 MCC |
441 | device_remove_file(&csrow->dev, |
442 | dynamic_csrow_dimm_attr[chan]); | |
443 | device_remove_file(&csrow->dev, | |
444 | dynamic_csrow_ce_count_attr[chan]); | |
445 | } | |
de3910eb | 446 | put_device(&mci->csrows[i]->dev); |
8096cfaf | 447 | } |
7c9281d7 | 448 | |
7a623c03 MCC |
449 | return err; |
450 | } | |
8096cfaf | 451 | |
7a623c03 MCC |
452 | static void edac_delete_csrow_objects(struct mem_ctl_info *mci) |
453 | { | |
454 | int i, chan; | |
455 | struct csrow_info *csrow; | |
8096cfaf | 456 | |
7a623c03 | 457 | for (i = mci->nr_csrows - 1; i >= 0; i--) { |
de3910eb | 458 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
459 | if (!nr_pages_per_csrow(csrow)) |
460 | continue; | |
7a623c03 | 461 | for (chan = csrow->nr_channels - 1; chan >= 0; chan--) { |
de3910eb | 462 | if (!csrow->channels[chan]->dimm->nr_pages) |
e39f4ea9 | 463 | continue; |
956b9ba1 JP |
464 | edac_dbg(1, "Removing csrow %d channel %d sysfs nodes\n", |
465 | i, chan); | |
7a623c03 MCC |
466 | device_remove_file(&csrow->dev, |
467 | dynamic_csrow_dimm_attr[chan]); | |
468 | device_remove_file(&csrow->dev, | |
469 | dynamic_csrow_ce_count_attr[chan]); | |
7c9281d7 | 470 | } |
de3910eb MCC |
471 | put_device(&mci->csrows[i]->dev); |
472 | device_del(&mci->csrows[i]->dev); | |
7c9281d7 | 473 | } |
7c9281d7 | 474 | } |
19974710 MCC |
475 | #endif |
476 | ||
477 | /* | |
478 | * Per-dimm (or per-rank) devices | |
479 | */ | |
480 | ||
481 | #define to_dimm(k) container_of(k, struct dimm_info, dev) | |
482 | ||
483 | /* show/store functions for DIMM Label attributes */ | |
484 | static ssize_t dimmdev_location_show(struct device *dev, | |
485 | struct device_attribute *mattr, char *data) | |
486 | { | |
487 | struct dimm_info *dimm = to_dimm(dev); | |
488 | struct mem_ctl_info *mci = dimm->mci; | |
489 | int i; | |
490 | char *p = data; | |
491 | ||
492 | for (i = 0; i < mci->n_layers; i++) { | |
493 | p += sprintf(p, "%s %d ", | |
494 | edac_layer_name[mci->layers[i].type], | |
495 | dimm->location[i]); | |
496 | } | |
497 | ||
498 | return p - data; | |
499 | } | |
500 | ||
501 | static ssize_t dimmdev_label_show(struct device *dev, | |
502 | struct device_attribute *mattr, char *data) | |
503 | { | |
504 | struct dimm_info *dimm = to_dimm(dev); | |
505 | ||
506 | /* if field has not been initialized, there is nothing to send */ | |
507 | if (!dimm->label[0]) | |
508 | return 0; | |
509 | ||
510 | return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", dimm->label); | |
511 | } | |
512 | ||
513 | static ssize_t dimmdev_label_store(struct device *dev, | |
514 | struct device_attribute *mattr, | |
515 | const char *data, | |
516 | size_t count) | |
517 | { | |
518 | struct dimm_info *dimm = to_dimm(dev); | |
519 | ||
520 | ssize_t max_size = 0; | |
521 | ||
522 | max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1); | |
523 | strncpy(dimm->label, data, max_size); | |
524 | dimm->label[max_size] = '\0'; | |
525 | ||
526 | return max_size; | |
527 | } | |
528 | ||
529 | static ssize_t dimmdev_size_show(struct device *dev, | |
530 | struct device_attribute *mattr, char *data) | |
531 | { | |
532 | struct dimm_info *dimm = to_dimm(dev); | |
533 | ||
534 | return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages)); | |
535 | } | |
536 | ||
537 | static ssize_t dimmdev_mem_type_show(struct device *dev, | |
538 | struct device_attribute *mattr, char *data) | |
539 | { | |
540 | struct dimm_info *dimm = to_dimm(dev); | |
541 | ||
542 | return sprintf(data, "%s\n", mem_types[dimm->mtype]); | |
543 | } | |
544 | ||
545 | static ssize_t dimmdev_dev_type_show(struct device *dev, | |
546 | struct device_attribute *mattr, char *data) | |
547 | { | |
548 | struct dimm_info *dimm = to_dimm(dev); | |
549 | ||
550 | return sprintf(data, "%s\n", dev_types[dimm->dtype]); | |
551 | } | |
552 | ||
553 | static ssize_t dimmdev_edac_mode_show(struct device *dev, | |
554 | struct device_attribute *mattr, | |
555 | char *data) | |
556 | { | |
557 | struct dimm_info *dimm = to_dimm(dev); | |
558 | ||
559 | return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]); | |
560 | } | |
561 | ||
562 | /* dimm/rank attribute files */ | |
563 | static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR, | |
564 | dimmdev_label_show, dimmdev_label_store); | |
565 | static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL); | |
566 | static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL); | |
567 | static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL); | |
568 | static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL); | |
569 | static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL); | |
570 | ||
571 | /* attributes of the dimm<id>/rank<id> object */ | |
572 | static struct attribute *dimm_attrs[] = { | |
573 | &dev_attr_dimm_label.attr, | |
574 | &dev_attr_dimm_location.attr, | |
575 | &dev_attr_size.attr, | |
576 | &dev_attr_dimm_mem_type.attr, | |
577 | &dev_attr_dimm_dev_type.attr, | |
578 | &dev_attr_dimm_edac_mode.attr, | |
579 | NULL, | |
580 | }; | |
581 | ||
582 | static struct attribute_group dimm_attr_grp = { | |
583 | .attrs = dimm_attrs, | |
584 | }; | |
585 | ||
586 | static const struct attribute_group *dimm_attr_groups[] = { | |
587 | &dimm_attr_grp, | |
588 | NULL | |
589 | }; | |
590 | ||
de3910eb | 591 | static void dimm_attr_release(struct device *dev) |
19974710 | 592 | { |
de3910eb MCC |
593 | struct dimm_info *dimm = container_of(dev, struct dimm_info, dev); |
594 | ||
956b9ba1 | 595 | edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev)); |
de3910eb | 596 | kfree(dimm); |
19974710 MCC |
597 | } |
598 | ||
599 | static struct device_type dimm_attr_type = { | |
600 | .groups = dimm_attr_groups, | |
601 | .release = dimm_attr_release, | |
602 | }; | |
603 | ||
604 | /* Create a DIMM object under specifed memory controller device */ | |
605 | static int edac_create_dimm_object(struct mem_ctl_info *mci, | |
606 | struct dimm_info *dimm, | |
607 | int index) | |
608 | { | |
609 | int err; | |
610 | dimm->mci = mci; | |
611 | ||
612 | dimm->dev.type = &dimm_attr_type; | |
613 | dimm->dev.bus = &mci->bus; | |
614 | device_initialize(&dimm->dev); | |
615 | ||
616 | dimm->dev.parent = &mci->dev; | |
617 | if (mci->mem_is_per_rank) | |
618 | dev_set_name(&dimm->dev, "rank%d", index); | |
619 | else | |
620 | dev_set_name(&dimm->dev, "dimm%d", index); | |
621 | dev_set_drvdata(&dimm->dev, dimm); | |
622 | pm_runtime_forbid(&mci->dev); | |
623 | ||
624 | err = device_add(&dimm->dev); | |
625 | ||
956b9ba1 | 626 | edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev)); |
19974710 MCC |
627 | |
628 | return err; | |
629 | } | |
7c9281d7 | 630 | |
7a623c03 MCC |
631 | /* |
632 | * Memory controller device | |
633 | */ | |
634 | ||
635 | #define to_mci(k) container_of(k, struct mem_ctl_info, dev) | |
7c9281d7 | 636 | |
7a623c03 MCC |
637 | static ssize_t mci_reset_counters_store(struct device *dev, |
638 | struct device_attribute *mattr, | |
079708b9 | 639 | const char *data, size_t count) |
7c9281d7 | 640 | { |
7a623c03 MCC |
641 | struct mem_ctl_info *mci = to_mci(dev); |
642 | int cnt, row, chan, i; | |
5926ff50 MCC |
643 | mci->ue_mc = 0; |
644 | mci->ce_mc = 0; | |
7a623c03 MCC |
645 | mci->ue_noinfo_count = 0; |
646 | mci->ce_noinfo_count = 0; | |
7c9281d7 DT |
647 | |
648 | for (row = 0; row < mci->nr_csrows; row++) { | |
de3910eb | 649 | struct csrow_info *ri = mci->csrows[row]; |
7c9281d7 DT |
650 | |
651 | ri->ue_count = 0; | |
652 | ri->ce_count = 0; | |
653 | ||
654 | for (chan = 0; chan < ri->nr_channels; chan++) | |
de3910eb | 655 | ri->channels[chan]->ce_count = 0; |
7c9281d7 DT |
656 | } |
657 | ||
7a623c03 MCC |
658 | cnt = 1; |
659 | for (i = 0; i < mci->n_layers; i++) { | |
660 | cnt *= mci->layers[i].size; | |
661 | memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32)); | |
662 | memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32)); | |
663 | } | |
664 | ||
7c9281d7 DT |
665 | mci->start_time = jiffies; |
666 | return count; | |
667 | } | |
668 | ||
39094443 BP |
669 | /* Memory scrubbing interface: |
670 | * | |
671 | * A MC driver can limit the scrubbing bandwidth based on the CPU type. | |
672 | * Therefore, ->set_sdram_scrub_rate should be made to return the actual | |
673 | * bandwidth that is accepted or 0 when scrubbing is to be disabled. | |
674 | * | |
675 | * Negative value still means that an error has occurred while setting | |
676 | * the scrub rate. | |
677 | */ | |
7a623c03 MCC |
678 | static ssize_t mci_sdram_scrub_rate_store(struct device *dev, |
679 | struct device_attribute *mattr, | |
eba042a8 | 680 | const char *data, size_t count) |
7c9281d7 | 681 | { |
7a623c03 | 682 | struct mem_ctl_info *mci = to_mci(dev); |
eba042a8 | 683 | unsigned long bandwidth = 0; |
39094443 | 684 | int new_bw = 0; |
7c9281d7 | 685 | |
39094443 | 686 | if (!mci->set_sdram_scrub_rate) |
5e8e19bf | 687 | return -ENODEV; |
7c9281d7 | 688 | |
eba042a8 BP |
689 | if (strict_strtoul(data, 10, &bandwidth) < 0) |
690 | return -EINVAL; | |
7c9281d7 | 691 | |
39094443 | 692 | new_bw = mci->set_sdram_scrub_rate(mci, bandwidth); |
4949603a MT |
693 | if (new_bw < 0) { |
694 | edac_printk(KERN_WARNING, EDAC_MC, | |
695 | "Error setting scrub rate to: %lu\n", bandwidth); | |
696 | return -EINVAL; | |
7c9281d7 | 697 | } |
39094443 | 698 | |
4949603a | 699 | return count; |
7c9281d7 DT |
700 | } |
701 | ||
39094443 BP |
702 | /* |
703 | * ->get_sdram_scrub_rate() return value semantics same as above. | |
704 | */ | |
7a623c03 MCC |
705 | static ssize_t mci_sdram_scrub_rate_show(struct device *dev, |
706 | struct device_attribute *mattr, | |
707 | char *data) | |
7c9281d7 | 708 | { |
7a623c03 | 709 | struct mem_ctl_info *mci = to_mci(dev); |
39094443 | 710 | int bandwidth = 0; |
eba042a8 | 711 | |
39094443 | 712 | if (!mci->get_sdram_scrub_rate) |
5e8e19bf | 713 | return -ENODEV; |
eba042a8 | 714 | |
39094443 BP |
715 | bandwidth = mci->get_sdram_scrub_rate(mci); |
716 | if (bandwidth < 0) { | |
eba042a8 | 717 | edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n"); |
39094443 | 718 | return bandwidth; |
7c9281d7 | 719 | } |
39094443 | 720 | |
39094443 | 721 | return sprintf(data, "%d\n", bandwidth); |
7c9281d7 DT |
722 | } |
723 | ||
724 | /* default attribute files for the MCI object */ | |
7a623c03 MCC |
725 | static ssize_t mci_ue_count_show(struct device *dev, |
726 | struct device_attribute *mattr, | |
727 | char *data) | |
7c9281d7 | 728 | { |
7a623c03 MCC |
729 | struct mem_ctl_info *mci = to_mci(dev); |
730 | ||
5926ff50 | 731 | return sprintf(data, "%d\n", mci->ue_mc); |
7c9281d7 DT |
732 | } |
733 | ||
7a623c03 MCC |
734 | static ssize_t mci_ce_count_show(struct device *dev, |
735 | struct device_attribute *mattr, | |
736 | char *data) | |
7c9281d7 | 737 | { |
7a623c03 MCC |
738 | struct mem_ctl_info *mci = to_mci(dev); |
739 | ||
5926ff50 | 740 | return sprintf(data, "%d\n", mci->ce_mc); |
7c9281d7 DT |
741 | } |
742 | ||
7a623c03 MCC |
743 | static ssize_t mci_ce_noinfo_show(struct device *dev, |
744 | struct device_attribute *mattr, | |
745 | char *data) | |
7c9281d7 | 746 | { |
7a623c03 MCC |
747 | struct mem_ctl_info *mci = to_mci(dev); |
748 | ||
079708b9 | 749 | return sprintf(data, "%d\n", mci->ce_noinfo_count); |
7c9281d7 DT |
750 | } |
751 | ||
7a623c03 MCC |
752 | static ssize_t mci_ue_noinfo_show(struct device *dev, |
753 | struct device_attribute *mattr, | |
754 | char *data) | |
7c9281d7 | 755 | { |
7a623c03 MCC |
756 | struct mem_ctl_info *mci = to_mci(dev); |
757 | ||
079708b9 | 758 | return sprintf(data, "%d\n", mci->ue_noinfo_count); |
7c9281d7 DT |
759 | } |
760 | ||
7a623c03 MCC |
761 | static ssize_t mci_seconds_show(struct device *dev, |
762 | struct device_attribute *mattr, | |
763 | char *data) | |
7c9281d7 | 764 | { |
7a623c03 MCC |
765 | struct mem_ctl_info *mci = to_mci(dev); |
766 | ||
079708b9 | 767 | return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ); |
7c9281d7 DT |
768 | } |
769 | ||
7a623c03 MCC |
770 | static ssize_t mci_ctl_name_show(struct device *dev, |
771 | struct device_attribute *mattr, | |
772 | char *data) | |
7c9281d7 | 773 | { |
7a623c03 MCC |
774 | struct mem_ctl_info *mci = to_mci(dev); |
775 | ||
079708b9 | 776 | return sprintf(data, "%s\n", mci->ctl_name); |
7c9281d7 DT |
777 | } |
778 | ||
7a623c03 MCC |
779 | static ssize_t mci_size_mb_show(struct device *dev, |
780 | struct device_attribute *mattr, | |
781 | char *data) | |
7c9281d7 | 782 | { |
7a623c03 | 783 | struct mem_ctl_info *mci = to_mci(dev); |
a895bf8b | 784 | int total_pages = 0, csrow_idx, j; |
7c9281d7 | 785 | |
a895bf8b | 786 | for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) { |
de3910eb | 787 | struct csrow_info *csrow = mci->csrows[csrow_idx]; |
7c9281d7 | 788 | |
a895bf8b | 789 | for (j = 0; j < csrow->nr_channels; j++) { |
de3910eb | 790 | struct dimm_info *dimm = csrow->channels[j]->dimm; |
7c9281d7 | 791 | |
a895bf8b MCC |
792 | total_pages += dimm->nr_pages; |
793 | } | |
7c9281d7 DT |
794 | } |
795 | ||
079708b9 | 796 | return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages)); |
7c9281d7 DT |
797 | } |
798 | ||
8ad6c78a MCC |
799 | static ssize_t mci_max_location_show(struct device *dev, |
800 | struct device_attribute *mattr, | |
801 | char *data) | |
802 | { | |
803 | struct mem_ctl_info *mci = to_mci(dev); | |
804 | int i; | |
805 | char *p = data; | |
806 | ||
807 | for (i = 0; i < mci->n_layers; i++) { | |
808 | p += sprintf(p, "%s %d ", | |
809 | edac_layer_name[mci->layers[i].type], | |
810 | mci->layers[i].size - 1); | |
811 | } | |
812 | ||
813 | return p - data; | |
814 | } | |
815 | ||
452a6bf9 MCC |
816 | #ifdef CONFIG_EDAC_DEBUG |
817 | static ssize_t edac_fake_inject_write(struct file *file, | |
818 | const char __user *data, | |
819 | size_t count, loff_t *ppos) | |
820 | { | |
821 | struct device *dev = file->private_data; | |
822 | struct mem_ctl_info *mci = to_mci(dev); | |
823 | static enum hw_event_mc_err_type type; | |
824 | ||
825 | type = mci->fake_inject_ue ? HW_EVENT_ERR_UNCORRECTED | |
826 | : HW_EVENT_ERR_CORRECTED; | |
827 | ||
828 | printk(KERN_DEBUG | |
829 | "Generating a %s fake error to %d.%d.%d to test core handling. NOTE: this won't test the driver-specific decoding logic.\n", | |
830 | (type == HW_EVENT_ERR_UNCORRECTED) ? "UE" : "CE", | |
831 | mci->fake_inject_layer[0], | |
832 | mci->fake_inject_layer[1], | |
833 | mci->fake_inject_layer[2] | |
834 | ); | |
835 | edac_mc_handle_error(type, mci, 0, 0, 0, | |
836 | mci->fake_inject_layer[0], | |
837 | mci->fake_inject_layer[1], | |
838 | mci->fake_inject_layer[2], | |
839 | "FAKE ERROR", "for EDAC testing only", NULL); | |
840 | ||
841 | return count; | |
842 | } | |
843 | ||
844 | static int debugfs_open(struct inode *inode, struct file *file) | |
845 | { | |
846 | file->private_data = inode->i_private; | |
847 | return 0; | |
848 | } | |
849 | ||
850 | static const struct file_operations debug_fake_inject_fops = { | |
851 | .open = debugfs_open, | |
852 | .write = edac_fake_inject_write, | |
853 | .llseek = generic_file_llseek, | |
854 | }; | |
855 | #endif | |
856 | ||
7c9281d7 | 857 | /* default Control file */ |
7a623c03 | 858 | DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store); |
7c9281d7 DT |
859 | |
860 | /* default Attribute files */ | |
7a623c03 MCC |
861 | DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL); |
862 | DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL); | |
863 | DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL); | |
864 | DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL); | |
865 | DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL); | |
866 | DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL); | |
867 | DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL); | |
8ad6c78a | 868 | DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL); |
7c9281d7 DT |
869 | |
870 | /* memory scrubber attribute file */ | |
7a623c03 | 871 | DEVICE_ATTR(sdram_scrub_rate, S_IRUGO | S_IWUSR, mci_sdram_scrub_rate_show, |
052dfb45 | 872 | mci_sdram_scrub_rate_store); |
7c9281d7 | 873 | |
7a623c03 MCC |
874 | static struct attribute *mci_attrs[] = { |
875 | &dev_attr_reset_counters.attr, | |
876 | &dev_attr_mc_name.attr, | |
877 | &dev_attr_size_mb.attr, | |
878 | &dev_attr_seconds_since_reset.attr, | |
879 | &dev_attr_ue_noinfo_count.attr, | |
880 | &dev_attr_ce_noinfo_count.attr, | |
881 | &dev_attr_ue_count.attr, | |
882 | &dev_attr_ce_count.attr, | |
883 | &dev_attr_sdram_scrub_rate.attr, | |
8ad6c78a | 884 | &dev_attr_max_location.attr, |
7c9281d7 DT |
885 | NULL |
886 | }; | |
887 | ||
7a623c03 MCC |
888 | static struct attribute_group mci_attr_grp = { |
889 | .attrs = mci_attrs, | |
cc301b3a MCC |
890 | }; |
891 | ||
7a623c03 MCC |
892 | static const struct attribute_group *mci_attr_groups[] = { |
893 | &mci_attr_grp, | |
894 | NULL | |
cc301b3a MCC |
895 | }; |
896 | ||
de3910eb | 897 | static void mci_attr_release(struct device *dev) |
42a8e397 | 898 | { |
de3910eb MCC |
899 | struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev); |
900 | ||
956b9ba1 | 901 | edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev)); |
de3910eb | 902 | kfree(mci); |
42a8e397 DT |
903 | } |
904 | ||
7a623c03 MCC |
905 | static struct device_type mci_attr_type = { |
906 | .groups = mci_attr_groups, | |
907 | .release = mci_attr_release, | |
908 | }; | |
8096cfaf | 909 | |
452a6bf9 MCC |
910 | #ifdef CONFIG_EDAC_DEBUG |
911 | int edac_create_debug_nodes(struct mem_ctl_info *mci) | |
912 | { | |
913 | struct dentry *d, *parent; | |
914 | char name[80]; | |
915 | int i; | |
916 | ||
917 | d = debugfs_create_dir(mci->dev.kobj.name, mci->debugfs); | |
918 | if (!d) | |
919 | return -ENOMEM; | |
920 | parent = d; | |
921 | ||
922 | for (i = 0; i < mci->n_layers; i++) { | |
923 | sprintf(name, "fake_inject_%s", | |
924 | edac_layer_name[mci->layers[i].type]); | |
925 | d = debugfs_create_u8(name, S_IRUGO | S_IWUSR, parent, | |
926 | &mci->fake_inject_layer[i]); | |
927 | if (!d) | |
928 | goto nomem; | |
929 | } | |
930 | ||
931 | d = debugfs_create_bool("fake_inject_ue", S_IRUGO | S_IWUSR, parent, | |
932 | &mci->fake_inject_ue); | |
933 | if (!d) | |
934 | goto nomem; | |
935 | ||
936 | d = debugfs_create_file("fake_inject", S_IWUSR, parent, | |
937 | &mci->dev, | |
938 | &debug_fake_inject_fops); | |
939 | if (!d) | |
940 | goto nomem; | |
941 | ||
942 | return 0; | |
943 | nomem: | |
944 | debugfs_remove(mci->debugfs); | |
945 | return -ENOMEM; | |
946 | } | |
947 | #endif | |
948 | ||
7c9281d7 DT |
949 | /* |
950 | * Create a new Memory Controller kobject instance, | |
951 | * mc<id> under the 'mc' directory | |
952 | * | |
953 | * Return: | |
954 | * 0 Success | |
955 | * !0 Failure | |
956 | */ | |
957 | int edac_create_sysfs_mci_device(struct mem_ctl_info *mci) | |
958 | { | |
7a623c03 | 959 | int i, err; |
7c9281d7 | 960 | |
de3910eb MCC |
961 | /* |
962 | * The memory controller needs its own bus, in order to avoid | |
963 | * namespace conflicts at /sys/bus/edac. | |
964 | */ | |
965 | mci->bus.name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx); | |
966 | if (!mci->bus.name) | |
967 | return -ENOMEM; | |
956b9ba1 | 968 | edac_dbg(0, "creating bus %s\n", mci->bus.name); |
de3910eb MCC |
969 | err = bus_register(&mci->bus); |
970 | if (err < 0) | |
971 | return err; | |
7c9281d7 | 972 | |
7a623c03 | 973 | /* get the /sys/devices/system/edac subsys reference */ |
7a623c03 MCC |
974 | mci->dev.type = &mci_attr_type; |
975 | device_initialize(&mci->dev); | |
7c9281d7 | 976 | |
de3910eb | 977 | mci->dev.parent = mci_pdev; |
7a623c03 MCC |
978 | mci->dev.bus = &mci->bus; |
979 | dev_set_name(&mci->dev, "mc%d", mci->mc_idx); | |
980 | dev_set_drvdata(&mci->dev, mci); | |
981 | pm_runtime_forbid(&mci->dev); | |
982 | ||
956b9ba1 | 983 | edac_dbg(0, "creating device %s\n", dev_name(&mci->dev)); |
7a623c03 MCC |
984 | err = device_add(&mci->dev); |
985 | if (err < 0) { | |
986 | bus_unregister(&mci->bus); | |
987 | kfree(mci->bus.name); | |
988 | return err; | |
42a8e397 DT |
989 | } |
990 | ||
7a623c03 MCC |
991 | /* |
992 | * Create the dimm/rank devices | |
7c9281d7 | 993 | */ |
7a623c03 | 994 | for (i = 0; i < mci->tot_dimms; i++) { |
de3910eb | 995 | struct dimm_info *dimm = mci->dimms[i]; |
7a623c03 MCC |
996 | /* Only expose populated DIMMs */ |
997 | if (dimm->nr_pages == 0) | |
998 | continue; | |
999 | #ifdef CONFIG_EDAC_DEBUG | |
956b9ba1 | 1000 | edac_dbg(1, "creating dimm%d, located at ", i); |
7a623c03 MCC |
1001 | if (edac_debug_level >= 1) { |
1002 | int lay; | |
1003 | for (lay = 0; lay < mci->n_layers; lay++) | |
1004 | printk(KERN_CONT "%s %d ", | |
1005 | edac_layer_name[mci->layers[lay].type], | |
1006 | dimm->location[lay]); | |
1007 | printk(KERN_CONT "\n"); | |
7c9281d7 | 1008 | } |
7a623c03 | 1009 | #endif |
19974710 MCC |
1010 | err = edac_create_dimm_object(mci, dimm, i); |
1011 | if (err) { | |
956b9ba1 | 1012 | edac_dbg(1, "failure: create dimm %d obj\n", i); |
19974710 MCC |
1013 | goto fail; |
1014 | } | |
7c9281d7 DT |
1015 | } |
1016 | ||
19974710 | 1017 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 MCC |
1018 | err = edac_create_csrow_objects(mci); |
1019 | if (err < 0) | |
1020 | goto fail; | |
19974710 | 1021 | #endif |
7a623c03 | 1022 | |
452a6bf9 MCC |
1023 | #ifdef CONFIG_EDAC_DEBUG |
1024 | edac_create_debug_nodes(mci); | |
1025 | #endif | |
7c9281d7 DT |
1026 | return 0; |
1027 | ||
7a623c03 | 1028 | fail: |
079708b9 | 1029 | for (i--; i >= 0; i--) { |
de3910eb | 1030 | struct dimm_info *dimm = mci->dimms[i]; |
7a623c03 MCC |
1031 | if (dimm->nr_pages == 0) |
1032 | continue; | |
1033 | put_device(&dimm->dev); | |
1034 | device_del(&dimm->dev); | |
7c9281d7 | 1035 | } |
7a623c03 MCC |
1036 | put_device(&mci->dev); |
1037 | device_del(&mci->dev); | |
1038 | bus_unregister(&mci->bus); | |
1039 | kfree(mci->bus.name); | |
7c9281d7 DT |
1040 | return err; |
1041 | } | |
1042 | ||
1043 | /* | |
1044 | * remove a Memory Controller instance | |
1045 | */ | |
1046 | void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci) | |
1047 | { | |
7a623c03 | 1048 | int i; |
7c9281d7 | 1049 | |
956b9ba1 | 1050 | edac_dbg(0, "\n"); |
7c9281d7 | 1051 | |
452a6bf9 MCC |
1052 | #ifdef CONFIG_EDAC_DEBUG |
1053 | debugfs_remove(mci->debugfs); | |
1054 | #endif | |
19974710 | 1055 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 | 1056 | edac_delete_csrow_objects(mci); |
19974710 | 1057 | #endif |
7c9281d7 | 1058 | |
7a623c03 | 1059 | for (i = 0; i < mci->tot_dimms; i++) { |
de3910eb | 1060 | struct dimm_info *dimm = mci->dimms[i]; |
7a623c03 MCC |
1061 | if (dimm->nr_pages == 0) |
1062 | continue; | |
956b9ba1 | 1063 | edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev)); |
7a623c03 MCC |
1064 | put_device(&dimm->dev); |
1065 | device_del(&dimm->dev); | |
6fe1108f | 1066 | } |
7c9281d7 | 1067 | } |
8096cfaf | 1068 | |
7a623c03 MCC |
1069 | void edac_unregister_sysfs(struct mem_ctl_info *mci) |
1070 | { | |
956b9ba1 | 1071 | edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev)); |
7a623c03 MCC |
1072 | put_device(&mci->dev); |
1073 | device_del(&mci->dev); | |
1074 | bus_unregister(&mci->bus); | |
1075 | kfree(mci->bus.name); | |
1076 | } | |
8096cfaf | 1077 | |
de3910eb | 1078 | static void mc_attr_release(struct device *dev) |
7a623c03 | 1079 | { |
de3910eb MCC |
1080 | /* |
1081 | * There's no container structure here, as this is just the mci | |
1082 | * parent device, used to create the /sys/devices/mc sysfs node. | |
1083 | * So, there are no attributes on it. | |
1084 | */ | |
956b9ba1 | 1085 | edac_dbg(1, "Releasing device %s\n", dev_name(dev)); |
de3910eb | 1086 | kfree(dev); |
7a623c03 | 1087 | } |
8096cfaf | 1088 | |
7a623c03 MCC |
1089 | static struct device_type mc_attr_type = { |
1090 | .release = mc_attr_release, | |
1091 | }; | |
8096cfaf | 1092 | /* |
7a623c03 | 1093 | * Init/exit code for the module. Basically, creates/removes /sys/class/rc |
8096cfaf | 1094 | */ |
7a623c03 | 1095 | int __init edac_mc_sysfs_init(void) |
8096cfaf | 1096 | { |
fe5ff8b8 | 1097 | struct bus_type *edac_subsys; |
7a623c03 | 1098 | int err; |
8096cfaf | 1099 | |
fe5ff8b8 KS |
1100 | /* get the /sys/devices/system/edac subsys reference */ |
1101 | edac_subsys = edac_get_sysfs_subsys(); | |
1102 | if (edac_subsys == NULL) { | |
956b9ba1 | 1103 | edac_dbg(1, "no edac_subsys\n"); |
7a623c03 | 1104 | return -EINVAL; |
8096cfaf DT |
1105 | } |
1106 | ||
de3910eb MCC |
1107 | mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL); |
1108 | ||
1109 | mci_pdev->bus = edac_subsys; | |
1110 | mci_pdev->type = &mc_attr_type; | |
1111 | device_initialize(mci_pdev); | |
1112 | dev_set_name(mci_pdev, "mc"); | |
8096cfaf | 1113 | |
de3910eb | 1114 | err = device_add(mci_pdev); |
7a623c03 MCC |
1115 | if (err < 0) |
1116 | return err; | |
8096cfaf | 1117 | |
956b9ba1 | 1118 | edac_dbg(0, "device %s created\n", dev_name(mci_pdev)); |
de3910eb | 1119 | |
8096cfaf | 1120 | return 0; |
8096cfaf DT |
1121 | } |
1122 | ||
7a623c03 | 1123 | void __exit edac_mc_sysfs_exit(void) |
8096cfaf | 1124 | { |
de3910eb MCC |
1125 | put_device(mci_pdev); |
1126 | device_del(mci_pdev); | |
fe5ff8b8 | 1127 | edac_put_sysfs_subsys(); |
8096cfaf | 1128 | } |