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52707f91 MCC |
1 | /* Intel i7 core/Nehalem Memory Controller kernel module |
2 | * | |
e7bf068a | 3 | * This driver supports the memory controllers found on the Intel |
52707f91 MCC |
4 | * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx, |
5 | * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield | |
6 | * and Westmere-EP. | |
a0c36a1f MCC |
7 | * |
8 | * This file may be distributed under the terms of the | |
9 | * GNU General Public License version 2 only. | |
10 | * | |
52707f91 | 11 | * Copyright (c) 2009-2010 by: |
37e59f87 | 12 | * Mauro Carvalho Chehab |
a0c36a1f MCC |
13 | * |
14 | * Red Hat Inc. http://www.redhat.com | |
15 | * | |
16 | * Forked and adapted from the i5400_edac driver | |
17 | * | |
18 | * Based on the following public Intel datasheets: | |
19 | * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor | |
20 | * Datasheet, Volume 2: | |
21 | * http://download.intel.com/design/processor/datashts/320835.pdf | |
22 | * Intel Xeon Processor 5500 Series Datasheet Volume 2 | |
23 | * http://www.intel.com/Assets/PDF/datasheet/321322.pdf | |
24 | * also available at: | |
25 | * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf | |
26 | */ | |
27 | ||
a0c36a1f MCC |
28 | #include <linux/module.h> |
29 | #include <linux/init.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/pci_ids.h> | |
32 | #include <linux/slab.h> | |
3b918c12 | 33 | #include <linux/delay.h> |
535e9c78 | 34 | #include <linux/dmi.h> |
a0c36a1f MCC |
35 | #include <linux/edac.h> |
36 | #include <linux/mmzone.h> | |
f4742949 | 37 | #include <linux/smp.h> |
4140c542 | 38 | #include <asm/mce.h> |
14d2c083 | 39 | #include <asm/processor.h> |
4fad8098 | 40 | #include <asm/div64.h> |
a0c36a1f MCC |
41 | |
42 | #include "edac_core.h" | |
43 | ||
18c29002 MCC |
44 | /* Static vars */ |
45 | static LIST_HEAD(i7core_edac_list); | |
46 | static DEFINE_MUTEX(i7core_edac_lock); | |
47 | static int probed; | |
48 | ||
54a08ab1 MCC |
49 | static int use_pci_fixup; |
50 | module_param(use_pci_fixup, int, 0444); | |
51 | MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices"); | |
f4742949 MCC |
52 | /* |
53 | * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core | |
54 | * registers start at bus 255, and are not reported by BIOS. | |
55 | * We currently find devices with only 2 sockets. In order to support more QPI | |
56 | * Quick Path Interconnect, just increment this number. | |
57 | */ | |
58 | #define MAX_SOCKET_BUSES 2 | |
59 | ||
60 | ||
a0c36a1f MCC |
61 | /* |
62 | * Alter this version for the module when modifications are made | |
63 | */ | |
152ba394 | 64 | #define I7CORE_REVISION " Ver: 1.0.0" |
a0c36a1f MCC |
65 | #define EDAC_MOD_STR "i7core_edac" |
66 | ||
a0c36a1f MCC |
67 | /* |
68 | * Debug macros | |
69 | */ | |
70 | #define i7core_printk(level, fmt, arg...) \ | |
71 | edac_printk(level, "i7core", fmt, ##arg) | |
72 | ||
73 | #define i7core_mc_printk(mci, level, fmt, arg...) \ | |
74 | edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg) | |
75 | ||
76 | /* | |
77 | * i7core Memory Controller Registers | |
78 | */ | |
79 | ||
e9bd2e73 MCC |
80 | /* OFFSETS for Device 0 Function 0 */ |
81 | ||
82 | #define MC_CFG_CONTROL 0x90 | |
e8b6a127 SG |
83 | #define MC_CFG_UNLOCK 0x02 |
84 | #define MC_CFG_LOCK 0x00 | |
e9bd2e73 | 85 | |
a0c36a1f MCC |
86 | /* OFFSETS for Device 3 Function 0 */ |
87 | ||
88 | #define MC_CONTROL 0x48 | |
89 | #define MC_STATUS 0x4c | |
90 | #define MC_MAX_DOD 0x64 | |
91 | ||
442305b1 | 92 | /* |
15ed103a | 93 | * OFFSETS for Device 3 Function 4, as indicated on Xeon 5500 datasheet: |
442305b1 MCC |
94 | * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf |
95 | */ | |
96 | ||
97 | #define MC_TEST_ERR_RCV1 0x60 | |
98 | #define DIMM2_COR_ERR(r) ((r) & 0x7fff) | |
99 | ||
100 | #define MC_TEST_ERR_RCV0 0x64 | |
101 | #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff) | |
102 | #define DIMM0_COR_ERR(r) ((r) & 0x7fff) | |
103 | ||
15ed103a | 104 | /* OFFSETS for Device 3 Function 2, as indicated on Xeon 5500 datasheet */ |
e8b6a127 SG |
105 | #define MC_SSRCONTROL 0x48 |
106 | #define SSR_MODE_DISABLE 0x00 | |
107 | #define SSR_MODE_ENABLE 0x01 | |
108 | #define SSR_MODE_MASK 0x03 | |
109 | ||
110 | #define MC_SCRUB_CONTROL 0x4c | |
111 | #define STARTSCRUB (1 << 24) | |
535e9c78 | 112 | #define SCRUBINTERVAL_MASK 0xffffff |
e8b6a127 | 113 | |
b4e8f0b6 MCC |
114 | #define MC_COR_ECC_CNT_0 0x80 |
115 | #define MC_COR_ECC_CNT_1 0x84 | |
116 | #define MC_COR_ECC_CNT_2 0x88 | |
117 | #define MC_COR_ECC_CNT_3 0x8c | |
118 | #define MC_COR_ECC_CNT_4 0x90 | |
119 | #define MC_COR_ECC_CNT_5 0x94 | |
120 | ||
121 | #define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff) | |
122 | #define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff) | |
123 | ||
124 | ||
a0c36a1f MCC |
125 | /* OFFSETS for Devices 4,5 and 6 Function 0 */ |
126 | ||
0b2b7b7e MCC |
127 | #define MC_CHANNEL_DIMM_INIT_PARAMS 0x58 |
128 | #define THREE_DIMMS_PRESENT (1 << 24) | |
129 | #define SINGLE_QUAD_RANK_PRESENT (1 << 23) | |
130 | #define QUAD_RANK_PRESENT (1 << 22) | |
131 | #define REGISTERED_DIMM (1 << 15) | |
132 | ||
f122a892 MCC |
133 | #define MC_CHANNEL_MAPPER 0x60 |
134 | #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1) | |
135 | #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1) | |
136 | ||
0b2b7b7e MCC |
137 | #define MC_CHANNEL_RANK_PRESENT 0x7c |
138 | #define RANK_PRESENT_MASK 0xffff | |
139 | ||
a0c36a1f | 140 | #define MC_CHANNEL_ADDR_MATCH 0xf0 |
194a40fe MCC |
141 | #define MC_CHANNEL_ERROR_MASK 0xf8 |
142 | #define MC_CHANNEL_ERROR_INJECT 0xfc | |
143 | #define INJECT_ADDR_PARITY 0x10 | |
144 | #define INJECT_ECC 0x08 | |
145 | #define MASK_CACHELINE 0x06 | |
146 | #define MASK_FULL_CACHELINE 0x06 | |
147 | #define MASK_MSB32_CACHELINE 0x04 | |
148 | #define MASK_LSB32_CACHELINE 0x02 | |
149 | #define NO_MASK_CACHELINE 0x00 | |
150 | #define REPEAT_EN 0x01 | |
a0c36a1f | 151 | |
0b2b7b7e | 152 | /* OFFSETS for Devices 4,5 and 6 Function 1 */ |
b990538a | 153 | |
0b2b7b7e MCC |
154 | #define MC_DOD_CH_DIMM0 0x48 |
155 | #define MC_DOD_CH_DIMM1 0x4c | |
156 | #define MC_DOD_CH_DIMM2 0x50 | |
157 | #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10)) | |
158 | #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10) | |
159 | #define DIMM_PRESENT_MASK (1 << 9) | |
160 | #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9) | |
854d3349 MCC |
161 | #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7)) |
162 | #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7) | |
163 | #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5)) | |
164 | #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5) | |
41fcb7fe | 165 | #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2)) |
5566cb7c | 166 | #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2) |
854d3349 MCC |
167 | #define MC_DOD_NUMCOL_MASK 3 |
168 | #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK) | |
0b2b7b7e | 169 | |
f122a892 MCC |
170 | #define MC_RANK_PRESENT 0x7c |
171 | ||
0b2b7b7e MCC |
172 | #define MC_SAG_CH_0 0x80 |
173 | #define MC_SAG_CH_1 0x84 | |
174 | #define MC_SAG_CH_2 0x88 | |
175 | #define MC_SAG_CH_3 0x8c | |
176 | #define MC_SAG_CH_4 0x90 | |
177 | #define MC_SAG_CH_5 0x94 | |
178 | #define MC_SAG_CH_6 0x98 | |
179 | #define MC_SAG_CH_7 0x9c | |
180 | ||
181 | #define MC_RIR_LIMIT_CH_0 0x40 | |
182 | #define MC_RIR_LIMIT_CH_1 0x44 | |
183 | #define MC_RIR_LIMIT_CH_2 0x48 | |
184 | #define MC_RIR_LIMIT_CH_3 0x4C | |
185 | #define MC_RIR_LIMIT_CH_4 0x50 | |
186 | #define MC_RIR_LIMIT_CH_5 0x54 | |
187 | #define MC_RIR_LIMIT_CH_6 0x58 | |
188 | #define MC_RIR_LIMIT_CH_7 0x5C | |
189 | #define MC_RIR_LIMIT_MASK ((1 << 10) - 1) | |
190 | ||
191 | #define MC_RIR_WAY_CH 0x80 | |
192 | #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7) | |
193 | #define MC_RIR_WAY_RANK_MASK 0x7 | |
194 | ||
a0c36a1f MCC |
195 | /* |
196 | * i7core structs | |
197 | */ | |
198 | ||
199 | #define NUM_CHANS 3 | |
442305b1 MCC |
200 | #define MAX_DIMMS 3 /* Max DIMMS per channel */ |
201 | #define MAX_MCR_FUNC 4 | |
202 | #define MAX_CHAN_FUNC 3 | |
a0c36a1f MCC |
203 | |
204 | struct i7core_info { | |
205 | u32 mc_control; | |
206 | u32 mc_status; | |
207 | u32 max_dod; | |
f122a892 | 208 | u32 ch_map; |
a0c36a1f MCC |
209 | }; |
210 | ||
194a40fe MCC |
211 | |
212 | struct i7core_inject { | |
213 | int enable; | |
214 | ||
215 | u32 section; | |
216 | u32 type; | |
217 | u32 eccmask; | |
218 | ||
219 | /* Error address mask */ | |
220 | int channel, dimm, rank, bank, page, col; | |
221 | }; | |
222 | ||
0b2b7b7e | 223 | struct i7core_channel { |
0bf09e82 MCC |
224 | bool is_3dimms_present; |
225 | bool is_single_4rank; | |
226 | bool has_4rank; | |
442305b1 | 227 | u32 dimms; |
0b2b7b7e MCC |
228 | }; |
229 | ||
8f331907 | 230 | struct pci_id_descr { |
66607706 MCC |
231 | int dev; |
232 | int func; | |
233 | int dev_id; | |
de06eeef | 234 | int optional; |
8f331907 MCC |
235 | }; |
236 | ||
bd9e19ca | 237 | struct pci_id_table { |
1288c18f MCC |
238 | const struct pci_id_descr *descr; |
239 | int n_devs; | |
bd9e19ca VM |
240 | }; |
241 | ||
f4742949 MCC |
242 | struct i7core_dev { |
243 | struct list_head list; | |
244 | u8 socket; | |
245 | struct pci_dev **pdev; | |
de06eeef | 246 | int n_devs; |
f4742949 MCC |
247 | struct mem_ctl_info *mci; |
248 | }; | |
249 | ||
a0c36a1f | 250 | struct i7core_pvt { |
356f0a30 | 251 | struct device *addrmatch_dev, *chancounts_dev; |
5c4cdb5a | 252 | |
f4742949 MCC |
253 | struct pci_dev *pci_noncore; |
254 | struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1]; | |
255 | struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1]; | |
256 | ||
257 | struct i7core_dev *i7core_dev; | |
67166af4 | 258 | |
a0c36a1f | 259 | struct i7core_info info; |
194a40fe | 260 | struct i7core_inject inject; |
f4742949 | 261 | struct i7core_channel channel[NUM_CHANS]; |
67166af4 | 262 | |
f4742949 | 263 | int ce_count_available; |
b4e8f0b6 MCC |
264 | |
265 | /* ECC corrected errors counts per udimm */ | |
f4742949 MCC |
266 | unsigned long udimm_ce_count[MAX_DIMMS]; |
267 | int udimm_last_ce_count[MAX_DIMMS]; | |
b4e8f0b6 | 268 | /* ECC corrected errors counts per rdimm */ |
f4742949 MCC |
269 | unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS]; |
270 | int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS]; | |
442305b1 | 271 | |
27100db0 | 272 | bool is_registered, enable_scrub; |
14d2c083 | 273 | |
535e9c78 NC |
274 | /* DCLK Frequency used for computing scrub rate */ |
275 | int dclk_freq; | |
276 | ||
939747bd MCC |
277 | /* Struct to control EDAC polling */ |
278 | struct edac_pci_ctl_info *i7core_pci; | |
a0c36a1f MCC |
279 | }; |
280 | ||
8f331907 MCC |
281 | #define PCI_DESCR(device, function, device_id) \ |
282 | .dev = (device), \ | |
283 | .func = (function), \ | |
284 | .dev_id = (device_id) | |
285 | ||
1288c18f | 286 | static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = { |
8f331907 MCC |
287 | /* Memory controller */ |
288 | { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) }, | |
289 | { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) }, | |
224e871f | 290 | /* Exists only for RDIMM */ |
de06eeef | 291 | { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1 }, |
8f331907 MCC |
292 | { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) }, |
293 | ||
294 | /* Channel 0 */ | |
295 | { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) }, | |
296 | { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) }, | |
297 | { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) }, | |
298 | { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) }, | |
299 | ||
300 | /* Channel 1 */ | |
301 | { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) }, | |
302 | { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) }, | |
303 | { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) }, | |
304 | { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) }, | |
305 | ||
306 | /* Channel 2 */ | |
307 | { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) }, | |
308 | { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) }, | |
309 | { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) }, | |
310 | { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) }, | |
224e871f MCC |
311 | |
312 | /* Generic Non-core registers */ | |
313 | /* | |
314 | * This is the PCI device on i7core and on Xeon 35xx (8086:2c41) | |
315 | * On Xeon 55xx, however, it has a different id (8086:2c40). So, | |
316 | * the probing code needs to test for the other address in case of | |
317 | * failure of this one | |
318 | */ | |
319 | { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE) }, | |
320 | ||
a0c36a1f | 321 | }; |
8f331907 | 322 | |
1288c18f | 323 | static const struct pci_id_descr pci_dev_descr_lynnfield[] = { |
52a2e4fc MCC |
324 | { PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR) }, |
325 | { PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD) }, | |
326 | { PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST) }, | |
327 | ||
328 | { PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) }, | |
329 | { PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) }, | |
330 | { PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) }, | |
331 | { PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC) }, | |
332 | ||
508fa179 MCC |
333 | { PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) }, |
334 | { PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) }, | |
335 | { PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) }, | |
336 | { PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC) }, | |
224e871f MCC |
337 | |
338 | /* | |
339 | * This is the PCI device has an alternate address on some | |
340 | * processors like Core i7 860 | |
341 | */ | |
342 | { PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE) }, | |
52a2e4fc MCC |
343 | }; |
344 | ||
1288c18f | 345 | static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = { |
bd9e19ca VM |
346 | /* Memory controller */ |
347 | { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2) }, | |
348 | { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2) }, | |
349 | /* Exists only for RDIMM */ | |
350 | { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1 }, | |
351 | { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) }, | |
352 | ||
353 | /* Channel 0 */ | |
354 | { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) }, | |
355 | { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) }, | |
356 | { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) }, | |
357 | { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2) }, | |
358 | ||
359 | /* Channel 1 */ | |
360 | { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) }, | |
361 | { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) }, | |
362 | { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) }, | |
363 | { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2) }, | |
364 | ||
365 | /* Channel 2 */ | |
366 | { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) }, | |
367 | { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) }, | |
368 | { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) }, | |
369 | { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) }, | |
224e871f MCC |
370 | |
371 | /* Generic Non-core registers */ | |
372 | { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2) }, | |
373 | ||
bd9e19ca VM |
374 | }; |
375 | ||
1288c18f MCC |
376 | #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) } |
377 | static const struct pci_id_table pci_dev_table[] = { | |
bd9e19ca VM |
378 | PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem), |
379 | PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield), | |
380 | PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere), | |
3c52cc57 | 381 | {0,} /* 0 terminated list. */ |
bd9e19ca VM |
382 | }; |
383 | ||
8f331907 MCC |
384 | /* |
385 | * pci_device_id table for which devices we are looking for | |
8f331907 | 386 | */ |
ba935f40 | 387 | static const struct pci_device_id i7core_pci_tbl[] = { |
d1fd4fb6 | 388 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)}, |
f05da2f7 | 389 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)}, |
8f331907 MCC |
390 | {0,} /* 0 terminated list. */ |
391 | }; | |
392 | ||
a0c36a1f | 393 | /**************************************************************************** |
15ed103a | 394 | Ancillary status routines |
a0c36a1f MCC |
395 | ****************************************************************************/ |
396 | ||
397 | /* MC_CONTROL bits */ | |
ef708b53 MCC |
398 | #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch))) |
399 | #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1)) | |
a0c36a1f MCC |
400 | |
401 | /* MC_STATUS bits */ | |
61053fde | 402 | #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4)) |
ef708b53 | 403 | #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch)) |
a0c36a1f MCC |
404 | |
405 | /* MC_MAX_DOD read functions */ | |
854d3349 | 406 | static inline int numdimms(u32 dimms) |
a0c36a1f | 407 | { |
854d3349 | 408 | return (dimms & 0x3) + 1; |
a0c36a1f MCC |
409 | } |
410 | ||
854d3349 | 411 | static inline int numrank(u32 rank) |
a0c36a1f | 412 | { |
c31d34fe | 413 | static const int ranks[] = { 1, 2, 4, -EINVAL }; |
a0c36a1f | 414 | |
854d3349 | 415 | return ranks[rank & 0x3]; |
a0c36a1f MCC |
416 | } |
417 | ||
854d3349 | 418 | static inline int numbank(u32 bank) |
a0c36a1f | 419 | { |
c31d34fe | 420 | static const int banks[] = { 4, 8, 16, -EINVAL }; |
a0c36a1f | 421 | |
854d3349 | 422 | return banks[bank & 0x3]; |
a0c36a1f MCC |
423 | } |
424 | ||
854d3349 | 425 | static inline int numrow(u32 row) |
a0c36a1f | 426 | { |
c31d34fe | 427 | static const int rows[] = { |
a0c36a1f MCC |
428 | 1 << 12, 1 << 13, 1 << 14, 1 << 15, |
429 | 1 << 16, -EINVAL, -EINVAL, -EINVAL, | |
430 | }; | |
431 | ||
854d3349 | 432 | return rows[row & 0x7]; |
a0c36a1f MCC |
433 | } |
434 | ||
854d3349 | 435 | static inline int numcol(u32 col) |
a0c36a1f | 436 | { |
c31d34fe | 437 | static const int cols[] = { |
a0c36a1f MCC |
438 | 1 << 10, 1 << 11, 1 << 12, -EINVAL, |
439 | }; | |
854d3349 | 440 | return cols[col & 0x3]; |
a0c36a1f MCC |
441 | } |
442 | ||
f4742949 | 443 | static struct i7core_dev *get_i7core_dev(u8 socket) |
66607706 MCC |
444 | { |
445 | struct i7core_dev *i7core_dev; | |
446 | ||
447 | list_for_each_entry(i7core_dev, &i7core_edac_list, list) { | |
448 | if (i7core_dev->socket == socket) | |
449 | return i7core_dev; | |
450 | } | |
451 | ||
452 | return NULL; | |
453 | } | |
454 | ||
848b2f7e HS |
455 | static struct i7core_dev *alloc_i7core_dev(u8 socket, |
456 | const struct pci_id_table *table) | |
457 | { | |
458 | struct i7core_dev *i7core_dev; | |
459 | ||
460 | i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL); | |
461 | if (!i7core_dev) | |
462 | return NULL; | |
463 | ||
464 | i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * table->n_devs, | |
465 | GFP_KERNEL); | |
466 | if (!i7core_dev->pdev) { | |
467 | kfree(i7core_dev); | |
468 | return NULL; | |
469 | } | |
470 | ||
471 | i7core_dev->socket = socket; | |
472 | i7core_dev->n_devs = table->n_devs; | |
473 | list_add_tail(&i7core_dev->list, &i7core_edac_list); | |
474 | ||
475 | return i7core_dev; | |
476 | } | |
477 | ||
2aa9be44 HS |
478 | static void free_i7core_dev(struct i7core_dev *i7core_dev) |
479 | { | |
480 | list_del(&i7core_dev->list); | |
481 | kfree(i7core_dev->pdev); | |
482 | kfree(i7core_dev); | |
483 | } | |
484 | ||
a0c36a1f MCC |
485 | /**************************************************************************** |
486 | Memory check routines | |
487 | ****************************************************************************/ | |
eb94fc40 | 488 | |
084a4fcc | 489 | static int get_dimm_config(struct mem_ctl_info *mci) |
a0c36a1f MCC |
490 | { |
491 | struct i7core_pvt *pvt = mci->pvt_info; | |
854d3349 | 492 | struct pci_dev *pdev; |
ba6c5c62 | 493 | int i, j; |
1c6fed80 | 494 | enum edac_type mode; |
854d3349 | 495 | enum mem_type mtype; |
084a4fcc | 496 | struct dimm_info *dimm; |
a0c36a1f | 497 | |
854d3349 | 498 | /* Get data from the MC register, function 0 */ |
f4742949 | 499 | pdev = pvt->pci_mcr[0]; |
7dd6953c | 500 | if (!pdev) |
8f331907 MCC |
501 | return -ENODEV; |
502 | ||
f122a892 | 503 | /* Device 3 function 0 reads */ |
7dd6953c MCC |
504 | pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control); |
505 | pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status); | |
506 | pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod); | |
507 | pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map); | |
f122a892 | 508 | |
956b9ba1 JP |
509 | edac_dbg(0, "QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n", |
510 | pvt->i7core_dev->socket, pvt->info.mc_control, | |
511 | pvt->info.mc_status, pvt->info.max_dod, pvt->info.ch_map); | |
a0c36a1f | 512 | |
1c6fed80 | 513 | if (ECC_ENABLED(pvt)) { |
956b9ba1 | 514 | edac_dbg(0, "ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4); |
1c6fed80 MCC |
515 | if (ECCx8(pvt)) |
516 | mode = EDAC_S8ECD8ED; | |
517 | else | |
518 | mode = EDAC_S4ECD4ED; | |
519 | } else { | |
956b9ba1 | 520 | edac_dbg(0, "ECC disabled\n"); |
1c6fed80 MCC |
521 | mode = EDAC_NONE; |
522 | } | |
a0c36a1f MCC |
523 | |
524 | /* FIXME: need to handle the error codes */ | |
956b9ba1 JP |
525 | edac_dbg(0, "DOD Max limits: DIMMS: %d, %d-ranked, %d-banked x%x x 0x%x\n", |
526 | numdimms(pvt->info.max_dod), | |
527 | numrank(pvt->info.max_dod >> 2), | |
528 | numbank(pvt->info.max_dod >> 4), | |
529 | numrow(pvt->info.max_dod >> 6), | |
530 | numcol(pvt->info.max_dod >> 9)); | |
a0c36a1f | 531 | |
0b2b7b7e | 532 | for (i = 0; i < NUM_CHANS; i++) { |
854d3349 | 533 | u32 data, dimm_dod[3], value[8]; |
0b2b7b7e | 534 | |
52a2e4fc MCC |
535 | if (!pvt->pci_ch[i][0]) |
536 | continue; | |
537 | ||
0b2b7b7e | 538 | if (!CH_ACTIVE(pvt, i)) { |
956b9ba1 | 539 | edac_dbg(0, "Channel %i is not active\n", i); |
0b2b7b7e MCC |
540 | continue; |
541 | } | |
542 | if (CH_DISABLED(pvt, i)) { | |
956b9ba1 | 543 | edac_dbg(0, "Channel %i is disabled\n", i); |
0b2b7b7e MCC |
544 | continue; |
545 | } | |
546 | ||
f122a892 | 547 | /* Devices 4-6 function 0 */ |
f4742949 | 548 | pci_read_config_dword(pvt->pci_ch[i][0], |
0b2b7b7e MCC |
549 | MC_CHANNEL_DIMM_INIT_PARAMS, &data); |
550 | ||
0bf09e82 MCC |
551 | |
552 | if (data & THREE_DIMMS_PRESENT) | |
553 | pvt->channel[i].is_3dimms_present = true; | |
554 | ||
555 | if (data & SINGLE_QUAD_RANK_PRESENT) | |
556 | pvt->channel[i].is_single_4rank = true; | |
557 | ||
558 | if (data & QUAD_RANK_PRESENT) | |
559 | pvt->channel[i].has_4rank = true; | |
0b2b7b7e | 560 | |
854d3349 MCC |
561 | if (data & REGISTERED_DIMM) |
562 | mtype = MEM_RDDR3; | |
14d2c083 | 563 | else |
854d3349 | 564 | mtype = MEM_DDR3; |
854d3349 MCC |
565 | |
566 | /* Devices 4-6 function 1 */ | |
f4742949 | 567 | pci_read_config_dword(pvt->pci_ch[i][1], |
854d3349 | 568 | MC_DOD_CH_DIMM0, &dimm_dod[0]); |
f4742949 | 569 | pci_read_config_dword(pvt->pci_ch[i][1], |
854d3349 | 570 | MC_DOD_CH_DIMM1, &dimm_dod[1]); |
f4742949 | 571 | pci_read_config_dword(pvt->pci_ch[i][1], |
854d3349 | 572 | MC_DOD_CH_DIMM2, &dimm_dod[2]); |
0b2b7b7e | 573 | |
956b9ba1 JP |
574 | edac_dbg(0, "Ch%d phy rd%d, wr%d (0x%08x): %s%s%s%cDIMMs\n", |
575 | i, | |
576 | RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i), | |
577 | data, | |
578 | pvt->channel[i].is_3dimms_present ? "3DIMMS " : "", | |
579 | pvt->channel[i].is_3dimms_present ? "SINGLE_4R " : "", | |
580 | pvt->channel[i].has_4rank ? "HAS_4R " : "", | |
581 | (data & REGISTERED_DIMM) ? 'R' : 'U'); | |
854d3349 MCC |
582 | |
583 | for (j = 0; j < 3; j++) { | |
584 | u32 banks, ranks, rows, cols; | |
5566cb7c | 585 | u32 size, npages; |
854d3349 MCC |
586 | |
587 | if (!DIMM_PRESENT(dimm_dod[j])) | |
588 | continue; | |
589 | ||
0975c16f MCC |
590 | dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, |
591 | i, j, 0); | |
854d3349 MCC |
592 | banks = numbank(MC_DOD_NUMBANK(dimm_dod[j])); |
593 | ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j])); | |
594 | rows = numrow(MC_DOD_NUMROW(dimm_dod[j])); | |
595 | cols = numcol(MC_DOD_NUMCOL(dimm_dod[j])); | |
596 | ||
5566cb7c MCC |
597 | /* DDR3 has 8 I/O banks */ |
598 | size = (rows * cols * banks * ranks) >> (20 - 3); | |
599 | ||
956b9ba1 JP |
600 | edac_dbg(0, "\tdimm %d %d Mb offset: %x, bank: %d, rank: %d, row: %#x, col: %#x\n", |
601 | j, size, | |
602 | RANKOFFSET(dimm_dod[j]), | |
603 | banks, ranks, rows, cols); | |
854d3349 | 604 | |
e9144601 | 605 | npages = MiB_TO_PAGES(size); |
5566cb7c | 606 | |
a895bf8b | 607 | dimm->nr_pages = npages; |
b4e8f0b6 | 608 | |
854d3349 MCC |
609 | switch (banks) { |
610 | case 4: | |
084a4fcc | 611 | dimm->dtype = DEV_X4; |
854d3349 MCC |
612 | break; |
613 | case 8: | |
084a4fcc | 614 | dimm->dtype = DEV_X8; |
854d3349 MCC |
615 | break; |
616 | case 16: | |
084a4fcc | 617 | dimm->dtype = DEV_X16; |
854d3349 MCC |
618 | break; |
619 | default: | |
084a4fcc | 620 | dimm->dtype = DEV_UNKNOWN; |
854d3349 MCC |
621 | } |
622 | ||
084a4fcc MCC |
623 | snprintf(dimm->label, sizeof(dimm->label), |
624 | "CPU#%uChannel#%u_DIMM#%u", | |
625 | pvt->i7core_dev->socket, i, j); | |
626 | dimm->grain = 8; | |
627 | dimm->edac_mode = mode; | |
628 | dimm->mtype = mtype; | |
854d3349 | 629 | } |
1c6fed80 | 630 | |
854d3349 MCC |
631 | pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]); |
632 | pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]); | |
633 | pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]); | |
634 | pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]); | |
635 | pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]); | |
636 | pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]); | |
637 | pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]); | |
638 | pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]); | |
956b9ba1 | 639 | edac_dbg(1, "\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i); |
854d3349 | 640 | for (j = 0; j < 8; j++) |
956b9ba1 JP |
641 | edac_dbg(1, "\t\t%#x\t%#x\t%#x\n", |
642 | (value[j] >> 27) & 0x1, | |
643 | (value[j] >> 24) & 0x7, | |
644 | (value[j] & ((1 << 24) - 1))); | |
0b2b7b7e MCC |
645 | } |
646 | ||
a0c36a1f MCC |
647 | return 0; |
648 | } | |
649 | ||
194a40fe MCC |
650 | /**************************************************************************** |
651 | Error insertion routines | |
652 | ****************************************************************************/ | |
653 | ||
5c4cdb5a MCC |
654 | #define to_mci(k) container_of(k, struct mem_ctl_info, dev) |
655 | ||
194a40fe MCC |
656 | /* The i7core has independent error injection features per channel. |
657 | However, to have a simpler code, we don't allow enabling error injection | |
658 | on more than one channel. | |
659 | Also, since a change at an inject parameter will be applied only at enable, | |
660 | we're disabling error injection on all write calls to the sysfs nodes that | |
661 | controls the error code injection. | |
662 | */ | |
1288c18f | 663 | static int disable_inject(const struct mem_ctl_info *mci) |
194a40fe MCC |
664 | { |
665 | struct i7core_pvt *pvt = mci->pvt_info; | |
666 | ||
667 | pvt->inject.enable = 0; | |
668 | ||
f4742949 | 669 | if (!pvt->pci_ch[pvt->inject.channel][0]) |
8f331907 MCC |
670 | return -ENODEV; |
671 | ||
f4742949 | 672 | pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0], |
4157d9f5 | 673 | MC_CHANNEL_ERROR_INJECT, 0); |
8f331907 MCC |
674 | |
675 | return 0; | |
194a40fe MCC |
676 | } |
677 | ||
678 | /* | |
679 | * i7core inject inject.section | |
680 | * | |
681 | * accept and store error injection inject.section value | |
682 | * bit 0 - refers to the lower 32-byte half cacheline | |
683 | * bit 1 - refers to the upper 32-byte half cacheline | |
684 | */ | |
5c4cdb5a MCC |
685 | static ssize_t i7core_inject_section_store(struct device *dev, |
686 | struct device_attribute *mattr, | |
194a40fe MCC |
687 | const char *data, size_t count) |
688 | { | |
5c4cdb5a | 689 | struct mem_ctl_info *mci = to_mci(dev); |
194a40fe MCC |
690 | struct i7core_pvt *pvt = mci->pvt_info; |
691 | unsigned long value; | |
692 | int rc; | |
693 | ||
694 | if (pvt->inject.enable) | |
41fcb7fe | 695 | disable_inject(mci); |
194a40fe | 696 | |
c7f62fc8 | 697 | rc = kstrtoul(data, 10, &value); |
194a40fe | 698 | if ((rc < 0) || (value > 3)) |
2068def5 | 699 | return -EIO; |
194a40fe MCC |
700 | |
701 | pvt->inject.section = (u32) value; | |
702 | return count; | |
703 | } | |
704 | ||
5c4cdb5a MCC |
705 | static ssize_t i7core_inject_section_show(struct device *dev, |
706 | struct device_attribute *mattr, | |
707 | char *data) | |
194a40fe | 708 | { |
5c4cdb5a | 709 | struct mem_ctl_info *mci = to_mci(dev); |
194a40fe MCC |
710 | struct i7core_pvt *pvt = mci->pvt_info; |
711 | return sprintf(data, "0x%08x\n", pvt->inject.section); | |
712 | } | |
713 | ||
714 | /* | |
715 | * i7core inject.type | |
716 | * | |
717 | * accept and store error injection inject.section value | |
718 | * bit 0 - repeat enable - Enable error repetition | |
719 | * bit 1 - inject ECC error | |
720 | * bit 2 - inject parity error | |
721 | */ | |
5c4cdb5a MCC |
722 | static ssize_t i7core_inject_type_store(struct device *dev, |
723 | struct device_attribute *mattr, | |
194a40fe MCC |
724 | const char *data, size_t count) |
725 | { | |
5c4cdb5a MCC |
726 | struct mem_ctl_info *mci = to_mci(dev); |
727 | struct i7core_pvt *pvt = mci->pvt_info; | |
194a40fe MCC |
728 | unsigned long value; |
729 | int rc; | |
730 | ||
731 | if (pvt->inject.enable) | |
41fcb7fe | 732 | disable_inject(mci); |
194a40fe | 733 | |
c7f62fc8 | 734 | rc = kstrtoul(data, 10, &value); |
194a40fe | 735 | if ((rc < 0) || (value > 7)) |
2068def5 | 736 | return -EIO; |
194a40fe MCC |
737 | |
738 | pvt->inject.type = (u32) value; | |
739 | return count; | |
740 | } | |
741 | ||
5c4cdb5a MCC |
742 | static ssize_t i7core_inject_type_show(struct device *dev, |
743 | struct device_attribute *mattr, | |
744 | char *data) | |
194a40fe | 745 | { |
5c4cdb5a | 746 | struct mem_ctl_info *mci = to_mci(dev); |
194a40fe | 747 | struct i7core_pvt *pvt = mci->pvt_info; |
5c4cdb5a | 748 | |
194a40fe MCC |
749 | return sprintf(data, "0x%08x\n", pvt->inject.type); |
750 | } | |
751 | ||
752 | /* | |
753 | * i7core_inject_inject.eccmask_store | |
754 | * | |
755 | * The type of error (UE/CE) will depend on the inject.eccmask value: | |
756 | * Any bits set to a 1 will flip the corresponding ECC bit | |
757 | * Correctable errors can be injected by flipping 1 bit or the bits within | |
758 | * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or | |
759 | * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an | |
760 | * uncorrectable error to be injected. | |
761 | */ | |
5c4cdb5a MCC |
762 | static ssize_t i7core_inject_eccmask_store(struct device *dev, |
763 | struct device_attribute *mattr, | |
764 | const char *data, size_t count) | |
194a40fe | 765 | { |
5c4cdb5a | 766 | struct mem_ctl_info *mci = to_mci(dev); |
194a40fe MCC |
767 | struct i7core_pvt *pvt = mci->pvt_info; |
768 | unsigned long value; | |
769 | int rc; | |
770 | ||
771 | if (pvt->inject.enable) | |
41fcb7fe | 772 | disable_inject(mci); |
194a40fe | 773 | |
c7f62fc8 | 774 | rc = kstrtoul(data, 10, &value); |
194a40fe | 775 | if (rc < 0) |
2068def5 | 776 | return -EIO; |
194a40fe MCC |
777 | |
778 | pvt->inject.eccmask = (u32) value; | |
779 | return count; | |
780 | } | |
781 | ||
5c4cdb5a MCC |
782 | static ssize_t i7core_inject_eccmask_show(struct device *dev, |
783 | struct device_attribute *mattr, | |
784 | char *data) | |
194a40fe | 785 | { |
5c4cdb5a | 786 | struct mem_ctl_info *mci = to_mci(dev); |
194a40fe | 787 | struct i7core_pvt *pvt = mci->pvt_info; |
5c4cdb5a | 788 | |
194a40fe MCC |
789 | return sprintf(data, "0x%08x\n", pvt->inject.eccmask); |
790 | } | |
791 | ||
792 | /* | |
793 | * i7core_addrmatch | |
794 | * | |
795 | * The type of error (UE/CE) will depend on the inject.eccmask value: | |
796 | * Any bits set to a 1 will flip the corresponding ECC bit | |
797 | * Correctable errors can be injected by flipping 1 bit or the bits within | |
798 | * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or | |
799 | * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an | |
800 | * uncorrectable error to be injected. | |
801 | */ | |
194a40fe | 802 | |
a5538e53 MCC |
803 | #define DECLARE_ADDR_MATCH(param, limit) \ |
804 | static ssize_t i7core_inject_store_##param( \ | |
5c4cdb5a MCC |
805 | struct device *dev, \ |
806 | struct device_attribute *mattr, \ | |
807 | const char *data, size_t count) \ | |
a5538e53 | 808 | { \ |
42709efb | 809 | struct mem_ctl_info *mci = dev_get_drvdata(dev); \ |
cc301b3a | 810 | struct i7core_pvt *pvt; \ |
a5538e53 MCC |
811 | long value; \ |
812 | int rc; \ | |
813 | \ | |
956b9ba1 | 814 | edac_dbg(1, "\n"); \ |
cc301b3a MCC |
815 | pvt = mci->pvt_info; \ |
816 | \ | |
a5538e53 MCC |
817 | if (pvt->inject.enable) \ |
818 | disable_inject(mci); \ | |
819 | \ | |
4f87fad1 | 820 | if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\ |
a5538e53 MCC |
821 | value = -1; \ |
822 | else { \ | |
c7f62fc8 | 823 | rc = kstrtoul(data, 10, &value); \ |
a5538e53 MCC |
824 | if ((rc < 0) || (value >= limit)) \ |
825 | return -EIO; \ | |
826 | } \ | |
827 | \ | |
828 | pvt->inject.param = value; \ | |
829 | \ | |
830 | return count; \ | |
831 | } \ | |
832 | \ | |
833 | static ssize_t i7core_inject_show_##param( \ | |
5c4cdb5a MCC |
834 | struct device *dev, \ |
835 | struct device_attribute *mattr, \ | |
836 | char *data) \ | |
a5538e53 | 837 | { \ |
42709efb | 838 | struct mem_ctl_info *mci = dev_get_drvdata(dev); \ |
cc301b3a MCC |
839 | struct i7core_pvt *pvt; \ |
840 | \ | |
841 | pvt = mci->pvt_info; \ | |
956b9ba1 | 842 | edac_dbg(1, "pvt=%p\n", pvt); \ |
a5538e53 MCC |
843 | if (pvt->inject.param < 0) \ |
844 | return sprintf(data, "any\n"); \ | |
845 | else \ | |
846 | return sprintf(data, "%d\n", pvt->inject.param);\ | |
194a40fe MCC |
847 | } |
848 | ||
a5538e53 | 849 | #define ATTR_ADDR_MATCH(param) \ |
5c4cdb5a MCC |
850 | static DEVICE_ATTR(param, S_IRUGO | S_IWUSR, \ |
851 | i7core_inject_show_##param, \ | |
852 | i7core_inject_store_##param) | |
194a40fe | 853 | |
a5538e53 MCC |
854 | DECLARE_ADDR_MATCH(channel, 3); |
855 | DECLARE_ADDR_MATCH(dimm, 3); | |
856 | DECLARE_ADDR_MATCH(rank, 4); | |
857 | DECLARE_ADDR_MATCH(bank, 32); | |
858 | DECLARE_ADDR_MATCH(page, 0x10000); | |
859 | DECLARE_ADDR_MATCH(col, 0x4000); | |
194a40fe | 860 | |
5c4cdb5a MCC |
861 | ATTR_ADDR_MATCH(channel); |
862 | ATTR_ADDR_MATCH(dimm); | |
863 | ATTR_ADDR_MATCH(rank); | |
864 | ATTR_ADDR_MATCH(bank); | |
865 | ATTR_ADDR_MATCH(page); | |
866 | ATTR_ADDR_MATCH(col); | |
867 | ||
1288c18f | 868 | static int write_and_test(struct pci_dev *dev, const int where, const u32 val) |
276b824c MCC |
869 | { |
870 | u32 read; | |
871 | int count; | |
872 | ||
956b9ba1 JP |
873 | edac_dbg(0, "setting pci %02x:%02x.%x reg=%02x value=%08x\n", |
874 | dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), | |
875 | where, val); | |
4157d9f5 | 876 | |
276b824c MCC |
877 | for (count = 0; count < 10; count++) { |
878 | if (count) | |
b990538a | 879 | msleep(100); |
276b824c MCC |
880 | pci_write_config_dword(dev, where, val); |
881 | pci_read_config_dword(dev, where, &read); | |
882 | ||
883 | if (read == val) | |
884 | return 0; | |
885 | } | |
886 | ||
4157d9f5 MCC |
887 | i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x " |
888 | "write=%08x. Read=%08x\n", | |
889 | dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), | |
890 | where, val, read); | |
276b824c MCC |
891 | |
892 | return -EINVAL; | |
893 | } | |
894 | ||
194a40fe MCC |
895 | /* |
896 | * This routine prepares the Memory Controller for error injection. | |
897 | * The error will be injected when some process tries to write to the | |
898 | * memory that matches the given criteria. | |
899 | * The criteria can be set in terms of a mask where dimm, rank, bank, page | |
900 | * and col can be specified. | |
901 | * A -1 value for any of the mask items will make the MCU to ignore | |
902 | * that matching criteria for error injection. | |
903 | * | |
904 | * It should be noticed that the error will only happen after a write operation | |
905 | * on a memory that matches the condition. if REPEAT_EN is not enabled at | |
906 | * inject mask, then it will produce just one error. Otherwise, it will repeat | |
907 | * until the injectmask would be cleaned. | |
908 | * | |
909 | * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD | |
910 | * is reliable enough to check if the MC is using the | |
911 | * three channels. However, this is not clear at the datasheet. | |
912 | */ | |
5c4cdb5a MCC |
913 | static ssize_t i7core_inject_enable_store(struct device *dev, |
914 | struct device_attribute *mattr, | |
915 | const char *data, size_t count) | |
194a40fe | 916 | { |
5c4cdb5a | 917 | struct mem_ctl_info *mci = to_mci(dev); |
194a40fe MCC |
918 | struct i7core_pvt *pvt = mci->pvt_info; |
919 | u32 injectmask; | |
920 | u64 mask = 0; | |
921 | int rc; | |
922 | long enable; | |
923 | ||
f4742949 | 924 | if (!pvt->pci_ch[pvt->inject.channel][0]) |
8f331907 MCC |
925 | return 0; |
926 | ||
c7f62fc8 | 927 | rc = kstrtoul(data, 10, &enable); |
194a40fe MCC |
928 | if ((rc < 0)) |
929 | return 0; | |
930 | ||
931 | if (enable) { | |
932 | pvt->inject.enable = 1; | |
933 | } else { | |
934 | disable_inject(mci); | |
935 | return count; | |
936 | } | |
937 | ||
938 | /* Sets pvt->inject.dimm mask */ | |
939 | if (pvt->inject.dimm < 0) | |
486dd09f | 940 | mask |= 1LL << 41; |
194a40fe | 941 | else { |
f4742949 | 942 | if (pvt->channel[pvt->inject.channel].dimms > 2) |
486dd09f | 943 | mask |= (pvt->inject.dimm & 0x3LL) << 35; |
194a40fe | 944 | else |
486dd09f | 945 | mask |= (pvt->inject.dimm & 0x1LL) << 36; |
194a40fe MCC |
946 | } |
947 | ||
948 | /* Sets pvt->inject.rank mask */ | |
949 | if (pvt->inject.rank < 0) | |
486dd09f | 950 | mask |= 1LL << 40; |
194a40fe | 951 | else { |
f4742949 | 952 | if (pvt->channel[pvt->inject.channel].dimms > 2) |
486dd09f | 953 | mask |= (pvt->inject.rank & 0x1LL) << 34; |
194a40fe | 954 | else |
486dd09f | 955 | mask |= (pvt->inject.rank & 0x3LL) << 34; |
194a40fe MCC |
956 | } |
957 | ||
958 | /* Sets pvt->inject.bank mask */ | |
959 | if (pvt->inject.bank < 0) | |
486dd09f | 960 | mask |= 1LL << 39; |
194a40fe | 961 | else |
486dd09f | 962 | mask |= (pvt->inject.bank & 0x15LL) << 30; |
194a40fe MCC |
963 | |
964 | /* Sets pvt->inject.page mask */ | |
965 | if (pvt->inject.page < 0) | |
486dd09f | 966 | mask |= 1LL << 38; |
194a40fe | 967 | else |
486dd09f | 968 | mask |= (pvt->inject.page & 0xffff) << 14; |
194a40fe MCC |
969 | |
970 | /* Sets pvt->inject.column mask */ | |
971 | if (pvt->inject.col < 0) | |
486dd09f | 972 | mask |= 1LL << 37; |
194a40fe | 973 | else |
486dd09f | 974 | mask |= (pvt->inject.col & 0x3fff); |
194a40fe | 975 | |
276b824c MCC |
976 | /* |
977 | * bit 0: REPEAT_EN | |
978 | * bits 1-2: MASK_HALF_CACHELINE | |
979 | * bit 3: INJECT_ECC | |
980 | * bit 4: INJECT_ADDR_PARITY | |
981 | */ | |
982 | ||
983 | injectmask = (pvt->inject.type & 1) | | |
984 | (pvt->inject.section & 0x3) << 1 | | |
985 | (pvt->inject.type & 0x6) << (3 - 1); | |
986 | ||
987 | /* Unlock writes to registers - this register is write only */ | |
f4742949 | 988 | pci_write_config_dword(pvt->pci_noncore, |
67166af4 | 989 | MC_CFG_CONTROL, 0x2); |
e9bd2e73 | 990 | |
f4742949 | 991 | write_and_test(pvt->pci_ch[pvt->inject.channel][0], |
194a40fe | 992 | MC_CHANNEL_ADDR_MATCH, mask); |
f4742949 | 993 | write_and_test(pvt->pci_ch[pvt->inject.channel][0], |
7b029d03 | 994 | MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L); |
7b029d03 | 995 | |
f4742949 | 996 | write_and_test(pvt->pci_ch[pvt->inject.channel][0], |
194a40fe MCC |
997 | MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask); |
998 | ||
f4742949 | 999 | write_and_test(pvt->pci_ch[pvt->inject.channel][0], |
4157d9f5 | 1000 | MC_CHANNEL_ERROR_INJECT, injectmask); |
276b824c | 1001 | |
194a40fe | 1002 | /* |
276b824c MCC |
1003 | * This is something undocumented, based on my tests |
1004 | * Without writing 8 to this register, errors aren't injected. Not sure | |
1005 | * why. | |
194a40fe | 1006 | */ |
f4742949 | 1007 | pci_write_config_dword(pvt->pci_noncore, |
276b824c | 1008 | MC_CFG_CONTROL, 8); |
194a40fe | 1009 | |
956b9ba1 JP |
1010 | edac_dbg(0, "Error inject addr match 0x%016llx, ecc 0x%08x, inject 0x%08x\n", |
1011 | mask, pvt->inject.eccmask, injectmask); | |
194a40fe | 1012 | |
7b029d03 | 1013 | |
194a40fe MCC |
1014 | return count; |
1015 | } | |
1016 | ||
5c4cdb5a MCC |
1017 | static ssize_t i7core_inject_enable_show(struct device *dev, |
1018 | struct device_attribute *mattr, | |
1019 | char *data) | |
194a40fe | 1020 | { |
5c4cdb5a | 1021 | struct mem_ctl_info *mci = to_mci(dev); |
194a40fe | 1022 | struct i7core_pvt *pvt = mci->pvt_info; |
7b029d03 MCC |
1023 | u32 injectmask; |
1024 | ||
52a2e4fc MCC |
1025 | if (!pvt->pci_ch[pvt->inject.channel][0]) |
1026 | return 0; | |
1027 | ||
f4742949 | 1028 | pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0], |
4157d9f5 | 1029 | MC_CHANNEL_ERROR_INJECT, &injectmask); |
7b029d03 | 1030 | |
956b9ba1 | 1031 | edac_dbg(0, "Inject error read: 0x%018x\n", injectmask); |
7b029d03 MCC |
1032 | |
1033 | if (injectmask & 0x0c) | |
1034 | pvt->inject.enable = 1; | |
1035 | ||
194a40fe MCC |
1036 | return sprintf(data, "%d\n", pvt->inject.enable); |
1037 | } | |
1038 | ||
f338d736 MCC |
1039 | #define DECLARE_COUNTER(param) \ |
1040 | static ssize_t i7core_show_counter_##param( \ | |
5c4cdb5a MCC |
1041 | struct device *dev, \ |
1042 | struct device_attribute *mattr, \ | |
1043 | char *data) \ | |
f338d736 | 1044 | { \ |
42709efb | 1045 | struct mem_ctl_info *mci = dev_get_drvdata(dev); \ |
f338d736 MCC |
1046 | struct i7core_pvt *pvt = mci->pvt_info; \ |
1047 | \ | |
956b9ba1 | 1048 | edac_dbg(1, "\n"); \ |
f338d736 MCC |
1049 | if (!pvt->ce_count_available || (pvt->is_registered)) \ |
1050 | return sprintf(data, "data unavailable\n"); \ | |
1051 | return sprintf(data, "%lu\n", \ | |
1052 | pvt->udimm_ce_count[param]); \ | |
1053 | } | |
442305b1 | 1054 | |
f338d736 | 1055 | #define ATTR_COUNTER(param) \ |
5c4cdb5a MCC |
1056 | static DEVICE_ATTR(udimm##param, S_IRUGO | S_IWUSR, \ |
1057 | i7core_show_counter_##param, \ | |
1058 | NULL) | |
442305b1 | 1059 | |
f338d736 MCC |
1060 | DECLARE_COUNTER(0); |
1061 | DECLARE_COUNTER(1); | |
1062 | DECLARE_COUNTER(2); | |
442305b1 | 1063 | |
5c4cdb5a MCC |
1064 | ATTR_COUNTER(0); |
1065 | ATTR_COUNTER(1); | |
1066 | ATTR_COUNTER(2); | |
1067 | ||
194a40fe | 1068 | /* |
5c4cdb5a | 1069 | * inject_addrmatch device sysfs struct |
194a40fe | 1070 | */ |
a5538e53 | 1071 | |
5c4cdb5a MCC |
1072 | static struct attribute *i7core_addrmatch_attrs[] = { |
1073 | &dev_attr_channel.attr, | |
1074 | &dev_attr_dimm.attr, | |
1075 | &dev_attr_rank.attr, | |
1076 | &dev_attr_bank.attr, | |
1077 | &dev_attr_page.attr, | |
1078 | &dev_attr_col.attr, | |
1079 | NULL | |
a5538e53 MCC |
1080 | }; |
1081 | ||
5c4cdb5a MCC |
1082 | static struct attribute_group addrmatch_grp = { |
1083 | .attrs = i7core_addrmatch_attrs, | |
a5538e53 MCC |
1084 | }; |
1085 | ||
5c4cdb5a MCC |
1086 | static const struct attribute_group *addrmatch_groups[] = { |
1087 | &addrmatch_grp, | |
1088 | NULL | |
f338d736 MCC |
1089 | }; |
1090 | ||
5c4cdb5a MCC |
1091 | static void addrmatch_release(struct device *device) |
1092 | { | |
956b9ba1 | 1093 | edac_dbg(1, "Releasing device %s\n", dev_name(device)); |
356f0a30 | 1094 | kfree(device); |
5c4cdb5a MCC |
1095 | } |
1096 | ||
1097 | static struct device_type addrmatch_type = { | |
1098 | .groups = addrmatch_groups, | |
1099 | .release = addrmatch_release, | |
f338d736 MCC |
1100 | }; |
1101 | ||
5c4cdb5a MCC |
1102 | /* |
1103 | * all_channel_counts sysfs struct | |
1104 | */ | |
1105 | ||
1106 | static struct attribute *i7core_udimm_counters_attrs[] = { | |
1107 | &dev_attr_udimm0.attr, | |
1108 | &dev_attr_udimm1.attr, | |
1109 | &dev_attr_udimm2.attr, | |
1110 | NULL | |
1288c18f MCC |
1111 | }; |
1112 | ||
5c4cdb5a MCC |
1113 | static struct attribute_group all_channel_counts_grp = { |
1114 | .attrs = i7core_udimm_counters_attrs, | |
194a40fe MCC |
1115 | }; |
1116 | ||
5c4cdb5a MCC |
1117 | static const struct attribute_group *all_channel_counts_groups[] = { |
1118 | &all_channel_counts_grp, | |
1119 | NULL | |
194a40fe MCC |
1120 | }; |
1121 | ||
5c4cdb5a MCC |
1122 | static void all_channel_counts_release(struct device *device) |
1123 | { | |
956b9ba1 | 1124 | edac_dbg(1, "Releasing device %s\n", dev_name(device)); |
356f0a30 | 1125 | kfree(device); |
5c4cdb5a MCC |
1126 | } |
1127 | ||
1128 | static struct device_type all_channel_counts_type = { | |
1129 | .groups = all_channel_counts_groups, | |
1130 | .release = all_channel_counts_release, | |
1131 | }; | |
1132 | ||
1133 | /* | |
1134 | * inject sysfs attributes | |
1135 | */ | |
1136 | ||
1137 | static DEVICE_ATTR(inject_section, S_IRUGO | S_IWUSR, | |
1138 | i7core_inject_section_show, i7core_inject_section_store); | |
1139 | ||
1140 | static DEVICE_ATTR(inject_type, S_IRUGO | S_IWUSR, | |
1141 | i7core_inject_type_show, i7core_inject_type_store); | |
1142 | ||
1143 | ||
1144 | static DEVICE_ATTR(inject_eccmask, S_IRUGO | S_IWUSR, | |
1145 | i7core_inject_eccmask_show, i7core_inject_eccmask_store); | |
1146 | ||
1147 | static DEVICE_ATTR(inject_enable, S_IRUGO | S_IWUSR, | |
1148 | i7core_inject_enable_show, i7core_inject_enable_store); | |
1149 | ||
2eace188 TI |
1150 | static struct attribute *i7core_dev_attrs[] = { |
1151 | &dev_attr_inject_section.attr, | |
1152 | &dev_attr_inject_type.attr, | |
1153 | &dev_attr_inject_eccmask.attr, | |
1154 | &dev_attr_inject_enable.attr, | |
1155 | NULL | |
1156 | }; | |
1157 | ||
1158 | ATTRIBUTE_GROUPS(i7core_dev); | |
1159 | ||
5c4cdb5a MCC |
1160 | static int i7core_create_sysfs_devices(struct mem_ctl_info *mci) |
1161 | { | |
1162 | struct i7core_pvt *pvt = mci->pvt_info; | |
1163 | int rc; | |
1164 | ||
356f0a30 MCC |
1165 | pvt->addrmatch_dev = kzalloc(sizeof(*pvt->addrmatch_dev), GFP_KERNEL); |
1166 | if (!pvt->addrmatch_dev) | |
e97d7e38 | 1167 | return -ENOMEM; |
356f0a30 MCC |
1168 | |
1169 | pvt->addrmatch_dev->type = &addrmatch_type; | |
1170 | pvt->addrmatch_dev->bus = mci->dev.bus; | |
1171 | device_initialize(pvt->addrmatch_dev); | |
1172 | pvt->addrmatch_dev->parent = &mci->dev; | |
1173 | dev_set_name(pvt->addrmatch_dev, "inject_addrmatch"); | |
1174 | dev_set_drvdata(pvt->addrmatch_dev, mci); | |
5c4cdb5a | 1175 | |
956b9ba1 | 1176 | edac_dbg(1, "creating %s\n", dev_name(pvt->addrmatch_dev)); |
5c4cdb5a | 1177 | |
356f0a30 | 1178 | rc = device_add(pvt->addrmatch_dev); |
5c4cdb5a MCC |
1179 | if (rc < 0) |
1180 | return rc; | |
1181 | ||
1182 | if (!pvt->is_registered) { | |
356f0a30 MCC |
1183 | pvt->chancounts_dev = kzalloc(sizeof(*pvt->chancounts_dev), |
1184 | GFP_KERNEL); | |
1185 | if (!pvt->chancounts_dev) { | |
1186 | put_device(pvt->addrmatch_dev); | |
1187 | device_del(pvt->addrmatch_dev); | |
e97d7e38 | 1188 | return -ENOMEM; |
356f0a30 MCC |
1189 | } |
1190 | ||
1191 | pvt->chancounts_dev->type = &all_channel_counts_type; | |
1192 | pvt->chancounts_dev->bus = mci->dev.bus; | |
1193 | device_initialize(pvt->chancounts_dev); | |
1194 | pvt->chancounts_dev->parent = &mci->dev; | |
1195 | dev_set_name(pvt->chancounts_dev, "all_channel_counts"); | |
1196 | dev_set_drvdata(pvt->chancounts_dev, mci); | |
5c4cdb5a | 1197 | |
956b9ba1 | 1198 | edac_dbg(1, "creating %s\n", dev_name(pvt->chancounts_dev)); |
5c4cdb5a | 1199 | |
356f0a30 | 1200 | rc = device_add(pvt->chancounts_dev); |
5c4cdb5a MCC |
1201 | if (rc < 0) |
1202 | return rc; | |
1203 | } | |
1204 | return 0; | |
1205 | } | |
1206 | ||
1207 | static void i7core_delete_sysfs_devices(struct mem_ctl_info *mci) | |
1208 | { | |
1209 | struct i7core_pvt *pvt = mci->pvt_info; | |
1210 | ||
956b9ba1 | 1211 | edac_dbg(1, "\n"); |
5c4cdb5a | 1212 | |
5c4cdb5a | 1213 | if (!pvt->is_registered) { |
356f0a30 MCC |
1214 | put_device(pvt->chancounts_dev); |
1215 | device_del(pvt->chancounts_dev); | |
5c4cdb5a | 1216 | } |
356f0a30 MCC |
1217 | put_device(pvt->addrmatch_dev); |
1218 | device_del(pvt->addrmatch_dev); | |
5c4cdb5a MCC |
1219 | } |
1220 | ||
a0c36a1f MCC |
1221 | /**************************************************************************** |
1222 | Device initialization routines: put/get, init/exit | |
1223 | ****************************************************************************/ | |
1224 | ||
1225 | /* | |
64c10f6e | 1226 | * i7core_put_all_devices 'put' all the devices that we have |
a0c36a1f MCC |
1227 | * reserved via 'get' |
1228 | */ | |
13d6e9b6 | 1229 | static void i7core_put_devices(struct i7core_dev *i7core_dev) |
a0c36a1f | 1230 | { |
13d6e9b6 | 1231 | int i; |
a0c36a1f | 1232 | |
956b9ba1 | 1233 | edac_dbg(0, "\n"); |
de06eeef | 1234 | for (i = 0; i < i7core_dev->n_devs; i++) { |
22e6bcbd MCC |
1235 | struct pci_dev *pdev = i7core_dev->pdev[i]; |
1236 | if (!pdev) | |
1237 | continue; | |
956b9ba1 JP |
1238 | edac_dbg(0, "Removing dev %02x:%02x.%d\n", |
1239 | pdev->bus->number, | |
1240 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); | |
22e6bcbd MCC |
1241 | pci_dev_put(pdev); |
1242 | } | |
13d6e9b6 | 1243 | } |
66607706 | 1244 | |
13d6e9b6 MCC |
1245 | static void i7core_put_all_devices(void) |
1246 | { | |
42538680 | 1247 | struct i7core_dev *i7core_dev, *tmp; |
13d6e9b6 | 1248 | |
39300e71 | 1249 | list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) { |
13d6e9b6 | 1250 | i7core_put_devices(i7core_dev); |
2aa9be44 | 1251 | free_i7core_dev(i7core_dev); |
39300e71 | 1252 | } |
a0c36a1f MCC |
1253 | } |
1254 | ||
1288c18f | 1255 | static void __init i7core_xeon_pci_fixup(const struct pci_id_table *table) |
bc2d7245 KM |
1256 | { |
1257 | struct pci_dev *pdev = NULL; | |
1258 | int i; | |
54a08ab1 | 1259 | |
bc2d7245 | 1260 | /* |
e7bf068a | 1261 | * On Xeon 55xx, the Intel Quick Path Arch Generic Non-core pci buses |
bc2d7245 KM |
1262 | * aren't announced by acpi. So, we need to use a legacy scan probing |
1263 | * to detect them | |
1264 | */ | |
bd9e19ca VM |
1265 | while (table && table->descr) { |
1266 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL); | |
1267 | if (unlikely(!pdev)) { | |
1268 | for (i = 0; i < MAX_SOCKET_BUSES; i++) | |
1269 | pcibios_scan_specific_bus(255-i); | |
1270 | } | |
bda14289 | 1271 | pci_dev_put(pdev); |
bd9e19ca | 1272 | table++; |
bc2d7245 KM |
1273 | } |
1274 | } | |
1275 | ||
bda14289 MCC |
1276 | static unsigned i7core_pci_lastbus(void) |
1277 | { | |
1278 | int last_bus = 0, bus; | |
1279 | struct pci_bus *b = NULL; | |
1280 | ||
1281 | while ((b = pci_find_next_bus(b)) != NULL) { | |
1282 | bus = b->number; | |
956b9ba1 | 1283 | edac_dbg(0, "Found bus %d\n", bus); |
bda14289 MCC |
1284 | if (bus > last_bus) |
1285 | last_bus = bus; | |
1286 | } | |
1287 | ||
956b9ba1 | 1288 | edac_dbg(0, "Last bus %d\n", last_bus); |
bda14289 MCC |
1289 | |
1290 | return last_bus; | |
1291 | } | |
1292 | ||
a0c36a1f | 1293 | /* |
64c10f6e | 1294 | * i7core_get_all_devices Find and perform 'get' operation on the MCH's |
a0c36a1f MCC |
1295 | * device/functions we want to reference for this driver |
1296 | * | |
1297 | * Need to 'get' device 16 func 1 and func 2 | |
1298 | */ | |
b197cba0 HS |
1299 | static int i7core_get_onedevice(struct pci_dev **prev, |
1300 | const struct pci_id_table *table, | |
1301 | const unsigned devno, | |
1302 | const unsigned last_bus) | |
a0c36a1f | 1303 | { |
66607706 | 1304 | struct i7core_dev *i7core_dev; |
b197cba0 | 1305 | const struct pci_id_descr *dev_descr = &table->descr[devno]; |
66607706 | 1306 | |
8f331907 | 1307 | struct pci_dev *pdev = NULL; |
67166af4 MCC |
1308 | u8 bus = 0; |
1309 | u8 socket = 0; | |
a0c36a1f | 1310 | |
c77720b9 | 1311 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
de06eeef | 1312 | dev_descr->dev_id, *prev); |
c77720b9 | 1313 | |
224e871f | 1314 | /* |
15ed103a | 1315 | * On Xeon 55xx, the Intel QuickPath Arch Generic Non-core regs |
224e871f MCC |
1316 | * is at addr 8086:2c40, instead of 8086:2c41. So, we need |
1317 | * to probe for the alternate address in case of failure | |
1318 | */ | |
c0f5eeed JD |
1319 | if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev) { |
1320 | pci_dev_get(*prev); /* pci_get_device will put it */ | |
224e871f MCC |
1321 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
1322 | PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev); | |
c0f5eeed | 1323 | } |
224e871f | 1324 | |
c0f5eeed JD |
1325 | if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && |
1326 | !pdev) { | |
1327 | pci_dev_get(*prev); /* pci_get_device will put it */ | |
224e871f MCC |
1328 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
1329 | PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT, | |
1330 | *prev); | |
c0f5eeed | 1331 | } |
224e871f | 1332 | |
c77720b9 MCC |
1333 | if (!pdev) { |
1334 | if (*prev) { | |
1335 | *prev = pdev; | |
1336 | return 0; | |
d1fd4fb6 MCC |
1337 | } |
1338 | ||
de06eeef | 1339 | if (dev_descr->optional) |
c77720b9 | 1340 | return 0; |
310cbb72 | 1341 | |
bd9e19ca VM |
1342 | if (devno == 0) |
1343 | return -ENODEV; | |
1344 | ||
ab089374 | 1345 | i7core_printk(KERN_INFO, |
c77720b9 | 1346 | "Device not found: dev %02x.%d PCI ID %04x:%04x\n", |
de06eeef MCC |
1347 | dev_descr->dev, dev_descr->func, |
1348 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); | |
67166af4 | 1349 | |
c77720b9 MCC |
1350 | /* End of list, leave */ |
1351 | return -ENODEV; | |
1352 | } | |
1353 | bus = pdev->bus->number; | |
67166af4 | 1354 | |
bda14289 | 1355 | socket = last_bus - bus; |
c77720b9 | 1356 | |
66607706 MCC |
1357 | i7core_dev = get_i7core_dev(socket); |
1358 | if (!i7core_dev) { | |
848b2f7e | 1359 | i7core_dev = alloc_i7core_dev(socket, table); |
2896637b HS |
1360 | if (!i7core_dev) { |
1361 | pci_dev_put(pdev); | |
66607706 | 1362 | return -ENOMEM; |
2896637b | 1363 | } |
c77720b9 | 1364 | } |
67166af4 | 1365 | |
66607706 | 1366 | if (i7core_dev->pdev[devno]) { |
c77720b9 MCC |
1367 | i7core_printk(KERN_ERR, |
1368 | "Duplicated device for " | |
1369 | "dev %02x:%02x.%d PCI ID %04x:%04x\n", | |
de06eeef MCC |
1370 | bus, dev_descr->dev, dev_descr->func, |
1371 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); | |
c77720b9 MCC |
1372 | pci_dev_put(pdev); |
1373 | return -ENODEV; | |
1374 | } | |
67166af4 | 1375 | |
66607706 | 1376 | i7core_dev->pdev[devno] = pdev; |
c77720b9 MCC |
1377 | |
1378 | /* Sanity check */ | |
de06eeef MCC |
1379 | if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev || |
1380 | PCI_FUNC(pdev->devfn) != dev_descr->func)) { | |
c77720b9 MCC |
1381 | i7core_printk(KERN_ERR, |
1382 | "Device PCI ID %04x:%04x " | |
1383 | "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n", | |
de06eeef | 1384 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id, |
c77720b9 | 1385 | bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), |
de06eeef | 1386 | bus, dev_descr->dev, dev_descr->func); |
c77720b9 MCC |
1387 | return -ENODEV; |
1388 | } | |
ef708b53 | 1389 | |
c77720b9 MCC |
1390 | /* Be sure that the device is enabled */ |
1391 | if (unlikely(pci_enable_device(pdev) < 0)) { | |
1392 | i7core_printk(KERN_ERR, | |
1393 | "Couldn't enable " | |
1394 | "dev %02x:%02x.%d PCI ID %04x:%04x\n", | |
de06eeef MCC |
1395 | bus, dev_descr->dev, dev_descr->func, |
1396 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); | |
c77720b9 MCC |
1397 | return -ENODEV; |
1398 | } | |
ef708b53 | 1399 | |
956b9ba1 JP |
1400 | edac_dbg(0, "Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n", |
1401 | socket, bus, dev_descr->dev, | |
1402 | dev_descr->func, | |
1403 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); | |
8f331907 | 1404 | |
a3e15416 MCC |
1405 | /* |
1406 | * As stated on drivers/pci/search.c, the reference count for | |
1407 | * @from is always decremented if it is not %NULL. So, as we need | |
1408 | * to get all devices up to null, we need to do a get for the device | |
1409 | */ | |
1410 | pci_dev_get(pdev); | |
1411 | ||
c77720b9 | 1412 | *prev = pdev; |
ef708b53 | 1413 | |
c77720b9 MCC |
1414 | return 0; |
1415 | } | |
a0c36a1f | 1416 | |
64c10f6e | 1417 | static int i7core_get_all_devices(void) |
c77720b9 | 1418 | { |
3c52cc57 | 1419 | int i, rc, last_bus; |
c77720b9 | 1420 | struct pci_dev *pdev = NULL; |
3c52cc57 | 1421 | const struct pci_id_table *table = pci_dev_table; |
bd9e19ca | 1422 | |
bda14289 MCC |
1423 | last_bus = i7core_pci_lastbus(); |
1424 | ||
3c52cc57 | 1425 | while (table && table->descr) { |
bd9e19ca VM |
1426 | for (i = 0; i < table->n_devs; i++) { |
1427 | pdev = NULL; | |
1428 | do { | |
b197cba0 | 1429 | rc = i7core_get_onedevice(&pdev, table, i, |
bda14289 | 1430 | last_bus); |
bd9e19ca VM |
1431 | if (rc < 0) { |
1432 | if (i == 0) { | |
1433 | i = table->n_devs; | |
1434 | break; | |
1435 | } | |
1436 | i7core_put_all_devices(); | |
1437 | return -ENODEV; | |
1438 | } | |
1439 | } while (pdev); | |
1440 | } | |
3c52cc57 | 1441 | table++; |
c77720b9 | 1442 | } |
66607706 | 1443 | |
ef708b53 | 1444 | return 0; |
ef708b53 MCC |
1445 | } |
1446 | ||
f4742949 MCC |
1447 | static int mci_bind_devs(struct mem_ctl_info *mci, |
1448 | struct i7core_dev *i7core_dev) | |
ef708b53 MCC |
1449 | { |
1450 | struct i7core_pvt *pvt = mci->pvt_info; | |
1451 | struct pci_dev *pdev; | |
f4742949 | 1452 | int i, func, slot; |
27100db0 | 1453 | char *family; |
ef708b53 | 1454 | |
27100db0 MCC |
1455 | pvt->is_registered = false; |
1456 | pvt->enable_scrub = false; | |
de06eeef | 1457 | for (i = 0; i < i7core_dev->n_devs; i++) { |
f4742949 MCC |
1458 | pdev = i7core_dev->pdev[i]; |
1459 | if (!pdev) | |
66607706 MCC |
1460 | continue; |
1461 | ||
f4742949 MCC |
1462 | func = PCI_FUNC(pdev->devfn); |
1463 | slot = PCI_SLOT(pdev->devfn); | |
1464 | if (slot == 3) { | |
1465 | if (unlikely(func > MAX_MCR_FUNC)) | |
1466 | goto error; | |
1467 | pvt->pci_mcr[func] = pdev; | |
1468 | } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) { | |
1469 | if (unlikely(func > MAX_CHAN_FUNC)) | |
ef708b53 | 1470 | goto error; |
f4742949 | 1471 | pvt->pci_ch[slot - 4][func] = pdev; |
27100db0 | 1472 | } else if (!slot && !func) { |
f4742949 | 1473 | pvt->pci_noncore = pdev; |
27100db0 MCC |
1474 | |
1475 | /* Detect the processor family */ | |
1476 | switch (pdev->device) { | |
1477 | case PCI_DEVICE_ID_INTEL_I7_NONCORE: | |
1478 | family = "Xeon 35xx/ i7core"; | |
1479 | pvt->enable_scrub = false; | |
1480 | break; | |
1481 | case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT: | |
1482 | family = "i7-800/i5-700"; | |
1483 | pvt->enable_scrub = false; | |
1484 | break; | |
1485 | case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE: | |
1486 | family = "Xeon 34xx"; | |
1487 | pvt->enable_scrub = false; | |
1488 | break; | |
1489 | case PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT: | |
1490 | family = "Xeon 55xx"; | |
1491 | pvt->enable_scrub = true; | |
1492 | break; | |
1493 | case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2: | |
1494 | family = "Xeon 56xx / i7-900"; | |
1495 | pvt->enable_scrub = true; | |
1496 | break; | |
1497 | default: | |
1498 | family = "unknown"; | |
1499 | pvt->enable_scrub = false; | |
1500 | } | |
956b9ba1 | 1501 | edac_dbg(0, "Detected a processor type %s\n", family); |
27100db0 | 1502 | } else |
f4742949 | 1503 | goto error; |
ef708b53 | 1504 | |
956b9ba1 JP |
1505 | edac_dbg(0, "Associated fn %d.%d, dev = %p, socket %d\n", |
1506 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
1507 | pdev, i7core_dev->socket); | |
14d2c083 | 1508 | |
f4742949 MCC |
1509 | if (PCI_SLOT(pdev->devfn) == 3 && |
1510 | PCI_FUNC(pdev->devfn) == 2) | |
27100db0 | 1511 | pvt->is_registered = true; |
a0c36a1f | 1512 | } |
e9bd2e73 | 1513 | |
a0c36a1f | 1514 | return 0; |
ef708b53 MCC |
1515 | |
1516 | error: | |
1517 | i7core_printk(KERN_ERR, "Device %d, function %d " | |
1518 | "is out of the expected range\n", | |
1519 | slot, func); | |
1520 | return -EINVAL; | |
a0c36a1f MCC |
1521 | } |
1522 | ||
442305b1 MCC |
1523 | /**************************************************************************** |
1524 | Error check routines | |
1525 | ****************************************************************************/ | |
b4e8f0b6 MCC |
1526 | |
1527 | static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci, | |
1288c18f MCC |
1528 | const int chan, |
1529 | const int new0, | |
1530 | const int new1, | |
1531 | const int new2) | |
b4e8f0b6 MCC |
1532 | { |
1533 | struct i7core_pvt *pvt = mci->pvt_info; | |
1534 | int add0 = 0, add1 = 0, add2 = 0; | |
1535 | /* Updates CE counters if it is not the first time here */ | |
f4742949 | 1536 | if (pvt->ce_count_available) { |
b4e8f0b6 MCC |
1537 | /* Updates CE counters */ |
1538 | ||
f4742949 MCC |
1539 | add2 = new2 - pvt->rdimm_last_ce_count[chan][2]; |
1540 | add1 = new1 - pvt->rdimm_last_ce_count[chan][1]; | |
1541 | add0 = new0 - pvt->rdimm_last_ce_count[chan][0]; | |
b4e8f0b6 MCC |
1542 | |
1543 | if (add2 < 0) | |
1544 | add2 += 0x7fff; | |
f4742949 | 1545 | pvt->rdimm_ce_count[chan][2] += add2; |
b4e8f0b6 MCC |
1546 | |
1547 | if (add1 < 0) | |
1548 | add1 += 0x7fff; | |
f4742949 | 1549 | pvt->rdimm_ce_count[chan][1] += add1; |
b4e8f0b6 MCC |
1550 | |
1551 | if (add0 < 0) | |
1552 | add0 += 0x7fff; | |
f4742949 | 1553 | pvt->rdimm_ce_count[chan][0] += add0; |
b4e8f0b6 | 1554 | } else |
f4742949 | 1555 | pvt->ce_count_available = 1; |
b4e8f0b6 MCC |
1556 | |
1557 | /* Store the new values */ | |
f4742949 MCC |
1558 | pvt->rdimm_last_ce_count[chan][2] = new2; |
1559 | pvt->rdimm_last_ce_count[chan][1] = new1; | |
1560 | pvt->rdimm_last_ce_count[chan][0] = new0; | |
b4e8f0b6 MCC |
1561 | |
1562 | /*updated the edac core */ | |
1563 | if (add0 != 0) | |
00d18339 MCC |
1564 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, add0, |
1565 | 0, 0, 0, | |
1566 | chan, 0, -1, "error", ""); | |
b4e8f0b6 | 1567 | if (add1 != 0) |
00d18339 MCC |
1568 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, add1, |
1569 | 0, 0, 0, | |
1570 | chan, 1, -1, "error", ""); | |
b4e8f0b6 | 1571 | if (add2 != 0) |
00d18339 MCC |
1572 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, add2, |
1573 | 0, 0, 0, | |
1574 | chan, 2, -1, "error", ""); | |
b4e8f0b6 MCC |
1575 | } |
1576 | ||
f4742949 | 1577 | static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci) |
b4e8f0b6 MCC |
1578 | { |
1579 | struct i7core_pvt *pvt = mci->pvt_info; | |
1580 | u32 rcv[3][2]; | |
1581 | int i, new0, new1, new2; | |
1582 | ||
1583 | /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/ | |
f4742949 | 1584 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0, |
b4e8f0b6 | 1585 | &rcv[0][0]); |
f4742949 | 1586 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1, |
b4e8f0b6 | 1587 | &rcv[0][1]); |
f4742949 | 1588 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2, |
b4e8f0b6 | 1589 | &rcv[1][0]); |
f4742949 | 1590 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3, |
b4e8f0b6 | 1591 | &rcv[1][1]); |
f4742949 | 1592 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4, |
b4e8f0b6 | 1593 | &rcv[2][0]); |
f4742949 | 1594 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5, |
b4e8f0b6 MCC |
1595 | &rcv[2][1]); |
1596 | for (i = 0 ; i < 3; i++) { | |
956b9ba1 JP |
1597 | edac_dbg(3, "MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n", |
1598 | (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]); | |
b4e8f0b6 | 1599 | /*if the channel has 3 dimms*/ |
f4742949 | 1600 | if (pvt->channel[i].dimms > 2) { |
b4e8f0b6 MCC |
1601 | new0 = DIMM_BOT_COR_ERR(rcv[i][0]); |
1602 | new1 = DIMM_TOP_COR_ERR(rcv[i][0]); | |
1603 | new2 = DIMM_BOT_COR_ERR(rcv[i][1]); | |
1604 | } else { | |
1605 | new0 = DIMM_TOP_COR_ERR(rcv[i][0]) + | |
1606 | DIMM_BOT_COR_ERR(rcv[i][0]); | |
1607 | new1 = DIMM_TOP_COR_ERR(rcv[i][1]) + | |
1608 | DIMM_BOT_COR_ERR(rcv[i][1]); | |
1609 | new2 = 0; | |
1610 | } | |
1611 | ||
f4742949 | 1612 | i7core_rdimm_update_ce_count(mci, i, new0, new1, new2); |
b4e8f0b6 MCC |
1613 | } |
1614 | } | |
442305b1 MCC |
1615 | |
1616 | /* This function is based on the device 3 function 4 registers as described on: | |
1617 | * Intel Xeon Processor 5500 Series Datasheet Volume 2 | |
1618 | * http://www.intel.com/Assets/PDF/datasheet/321322.pdf | |
1619 | * also available at: | |
1620 | * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf | |
1621 | */ | |
f4742949 | 1622 | static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci) |
442305b1 MCC |
1623 | { |
1624 | struct i7core_pvt *pvt = mci->pvt_info; | |
1625 | u32 rcv1, rcv0; | |
1626 | int new0, new1, new2; | |
1627 | ||
f4742949 | 1628 | if (!pvt->pci_mcr[4]) { |
956b9ba1 | 1629 | edac_dbg(0, "MCR registers not found\n"); |
442305b1 MCC |
1630 | return; |
1631 | } | |
1632 | ||
b4e8f0b6 | 1633 | /* Corrected test errors */ |
f4742949 MCC |
1634 | pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1); |
1635 | pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0); | |
442305b1 MCC |
1636 | |
1637 | /* Store the new values */ | |
1638 | new2 = DIMM2_COR_ERR(rcv1); | |
1639 | new1 = DIMM1_COR_ERR(rcv0); | |
1640 | new0 = DIMM0_COR_ERR(rcv0); | |
1641 | ||
442305b1 | 1642 | /* Updates CE counters if it is not the first time here */ |
f4742949 | 1643 | if (pvt->ce_count_available) { |
442305b1 MCC |
1644 | /* Updates CE counters */ |
1645 | int add0, add1, add2; | |
1646 | ||
f4742949 MCC |
1647 | add2 = new2 - pvt->udimm_last_ce_count[2]; |
1648 | add1 = new1 - pvt->udimm_last_ce_count[1]; | |
1649 | add0 = new0 - pvt->udimm_last_ce_count[0]; | |
442305b1 MCC |
1650 | |
1651 | if (add2 < 0) | |
1652 | add2 += 0x7fff; | |
f4742949 | 1653 | pvt->udimm_ce_count[2] += add2; |
442305b1 MCC |
1654 | |
1655 | if (add1 < 0) | |
1656 | add1 += 0x7fff; | |
f4742949 | 1657 | pvt->udimm_ce_count[1] += add1; |
442305b1 MCC |
1658 | |
1659 | if (add0 < 0) | |
1660 | add0 += 0x7fff; | |
f4742949 | 1661 | pvt->udimm_ce_count[0] += add0; |
b4e8f0b6 MCC |
1662 | |
1663 | if (add0 | add1 | add2) | |
1664 | i7core_printk(KERN_ERR, "New Corrected error(s): " | |
1665 | "dimm0: +%d, dimm1: +%d, dimm2 +%d\n", | |
1666 | add0, add1, add2); | |
442305b1 | 1667 | } else |
f4742949 | 1668 | pvt->ce_count_available = 1; |
442305b1 MCC |
1669 | |
1670 | /* Store the new values */ | |
f4742949 MCC |
1671 | pvt->udimm_last_ce_count[2] = new2; |
1672 | pvt->udimm_last_ce_count[1] = new1; | |
1673 | pvt->udimm_last_ce_count[0] = new0; | |
442305b1 MCC |
1674 | } |
1675 | ||
8a2f118e MCC |
1676 | /* |
1677 | * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32 | |
1678 | * Architectures Software Developer’s Manual Volume 3B. | |
f237fcf2 MCC |
1679 | * Nehalem are defined as family 0x06, model 0x1a |
1680 | * | |
1681 | * The MCA registers used here are the following ones: | |
8a2f118e | 1682 | * struct mce field MCA Register |
f237fcf2 MCC |
1683 | * m->status MSR_IA32_MC8_STATUS |
1684 | * m->addr MSR_IA32_MC8_ADDR | |
1685 | * m->misc MSR_IA32_MC8_MISC | |
8a2f118e MCC |
1686 | * In the case of Nehalem, the error information is masked at .status and .misc |
1687 | * fields | |
1688 | */ | |
d5381642 | 1689 | static void i7core_mce_output_error(struct mem_ctl_info *mci, |
1288c18f | 1690 | const struct mce *m) |
d5381642 | 1691 | { |
b4e8f0b6 | 1692 | struct i7core_pvt *pvt = mci->pvt_info; |
f118920b | 1693 | char *optype, *err; |
0975c16f | 1694 | enum hw_event_mc_err_type tp_event; |
8a2f118e | 1695 | unsigned long error = m->status & 0x1ff0000l; |
0975c16f MCC |
1696 | bool uncorrected_error = m->mcgstatus & 1ll << 61; |
1697 | bool ripv = m->mcgstatus & 1; | |
a639539f | 1698 | u32 optypenum = (m->status >> 4) & 0x07; |
8cf2d239 | 1699 | u32 core_err_cnt = (m->status >> 38) & 0x7fff; |
8a2f118e MCC |
1700 | u32 dimm = (m->misc >> 16) & 0x3; |
1701 | u32 channel = (m->misc >> 18) & 0x3; | |
1702 | u32 syndrome = m->misc >> 32; | |
1703 | u32 errnum = find_first_bit(&error, 32); | |
1704 | ||
0975c16f | 1705 | if (uncorrected_error) { |
f118920b | 1706 | if (ripv) |
0975c16f | 1707 | tp_event = HW_EVENT_ERR_FATAL; |
f118920b | 1708 | else |
0975c16f | 1709 | tp_event = HW_EVENT_ERR_UNCORRECTED; |
0975c16f | 1710 | } else { |
0975c16f MCC |
1711 | tp_event = HW_EVENT_ERR_CORRECTED; |
1712 | } | |
c5d34528 | 1713 | |
a639539f | 1714 | switch (optypenum) { |
b990538a MCC |
1715 | case 0: |
1716 | optype = "generic undef request"; | |
1717 | break; | |
1718 | case 1: | |
1719 | optype = "read error"; | |
1720 | break; | |
1721 | case 2: | |
1722 | optype = "write error"; | |
1723 | break; | |
1724 | case 3: | |
1725 | optype = "addr/cmd error"; | |
1726 | break; | |
1727 | case 4: | |
1728 | optype = "scrubbing error"; | |
1729 | break; | |
1730 | default: | |
1731 | optype = "reserved"; | |
1732 | break; | |
a639539f MCC |
1733 | } |
1734 | ||
8a2f118e MCC |
1735 | switch (errnum) { |
1736 | case 16: | |
1737 | err = "read ECC error"; | |
1738 | break; | |
1739 | case 17: | |
1740 | err = "RAS ECC error"; | |
1741 | break; | |
1742 | case 18: | |
1743 | err = "write parity error"; | |
1744 | break; | |
1745 | case 19: | |
1746 | err = "redundacy loss"; | |
1747 | break; | |
1748 | case 20: | |
1749 | err = "reserved"; | |
1750 | break; | |
1751 | case 21: | |
1752 | err = "memory range error"; | |
1753 | break; | |
1754 | case 22: | |
1755 | err = "RTID out of range"; | |
1756 | break; | |
1757 | case 23: | |
1758 | err = "address parity error"; | |
1759 | break; | |
1760 | case 24: | |
1761 | err = "byte enable parity error"; | |
1762 | break; | |
1763 | default: | |
1764 | err = "unknown"; | |
d5381642 | 1765 | } |
d5381642 | 1766 | |
0975c16f MCC |
1767 | /* |
1768 | * Call the helper to output message | |
1769 | * FIXME: what to do if core_err_cnt > 1? Currently, it generates | |
1770 | * only one event | |
1771 | */ | |
1772 | if (uncorrected_error || !pvt->is_registered) | |
00d18339 | 1773 | edac_mc_handle_error(tp_event, mci, core_err_cnt, |
0975c16f MCC |
1774 | m->addr >> PAGE_SHIFT, |
1775 | m->addr & ~PAGE_MASK, | |
1776 | syndrome, | |
1777 | channel, dimm, -1, | |
00d18339 | 1778 | err, optype); |
d5381642 MCC |
1779 | } |
1780 | ||
87d1d272 MCC |
1781 | /* |
1782 | * i7core_check_error Retrieve and process errors reported by the | |
1783 | * hardware. Called by the Core module. | |
1784 | */ | |
53595345 | 1785 | static void i7core_check_error(struct mem_ctl_info *mci, struct mce *m) |
87d1d272 | 1786 | { |
d5381642 | 1787 | struct i7core_pvt *pvt = mci->pvt_info; |
d5381642 | 1788 | |
53595345 | 1789 | i7core_mce_output_error(mci, m); |
d5381642 | 1790 | |
ca9c90ba MCC |
1791 | /* |
1792 | * Now, let's increment CE error counts | |
1793 | */ | |
f4742949 MCC |
1794 | if (!pvt->is_registered) |
1795 | i7core_udimm_check_mc_ecc_err(mci); | |
1796 | else | |
1797 | i7core_rdimm_check_mc_ecc_err(mci); | |
87d1d272 MCC |
1798 | } |
1799 | ||
d5381642 | 1800 | /* |
53595345 TL |
1801 | * Check that logging is enabled and that this is the right type |
1802 | * of error for us to handle. | |
d5381642 | 1803 | */ |
4140c542 BP |
1804 | static int i7core_mce_check_error(struct notifier_block *nb, unsigned long val, |
1805 | void *data) | |
d5381642 | 1806 | { |
4140c542 BP |
1807 | struct mce *mce = (struct mce *)data; |
1808 | struct i7core_dev *i7_dev; | |
1809 | struct mem_ctl_info *mci; | |
1810 | struct i7core_pvt *pvt; | |
1811 | ||
1812 | i7_dev = get_i7core_dev(mce->socketid); | |
1813 | if (!i7_dev) | |
c4fc1956 | 1814 | return NOTIFY_DONE; |
4140c542 BP |
1815 | |
1816 | mci = i7_dev->mci; | |
1817 | pvt = mci->pvt_info; | |
d5381642 | 1818 | |
8a2f118e MCC |
1819 | /* |
1820 | * Just let mcelog handle it if the error is | |
1821 | * outside the memory controller | |
1822 | */ | |
1823 | if (((mce->status & 0xffff) >> 7) != 1) | |
4140c542 | 1824 | return NOTIFY_DONE; |
8a2f118e | 1825 | |
f237fcf2 MCC |
1826 | /* Bank 8 registers are the only ones that we know how to handle */ |
1827 | if (mce->bank != 8) | |
4140c542 | 1828 | return NOTIFY_DONE; |
f237fcf2 | 1829 | |
53595345 | 1830 | i7core_check_error(mci, mce); |
c5d34528 | 1831 | |
e7bf068a | 1832 | /* Advise mcelog that the errors were handled */ |
4140c542 | 1833 | return NOTIFY_STOP; |
d5381642 MCC |
1834 | } |
1835 | ||
4140c542 BP |
1836 | static struct notifier_block i7_mce_dec = { |
1837 | .notifier_call = i7core_mce_check_error, | |
1838 | }; | |
1839 | ||
535e9c78 NC |
1840 | struct memdev_dmi_entry { |
1841 | u8 type; | |
1842 | u8 length; | |
1843 | u16 handle; | |
1844 | u16 phys_mem_array_handle; | |
1845 | u16 mem_err_info_handle; | |
1846 | u16 total_width; | |
1847 | u16 data_width; | |
1848 | u16 size; | |
1849 | u8 form; | |
1850 | u8 device_set; | |
1851 | u8 device_locator; | |
1852 | u8 bank_locator; | |
1853 | u8 memory_type; | |
1854 | u16 type_detail; | |
1855 | u16 speed; | |
1856 | u8 manufacturer; | |
1857 | u8 serial_number; | |
1858 | u8 asset_tag; | |
1859 | u8 part_number; | |
1860 | u8 attributes; | |
1861 | u32 extended_size; | |
1862 | u16 conf_mem_clk_speed; | |
1863 | } __attribute__((__packed__)); | |
1864 | ||
1865 | ||
1866 | /* | |
1867 | * Decode the DRAM Clock Frequency, be paranoid, make sure that all | |
1868 | * memory devices show the same speed, and if they don't then consider | |
1869 | * all speeds to be invalid. | |
1870 | */ | |
1871 | static void decode_dclk(const struct dmi_header *dh, void *_dclk_freq) | |
1872 | { | |
1873 | int *dclk_freq = _dclk_freq; | |
1874 | u16 dmi_mem_clk_speed; | |
1875 | ||
1876 | if (*dclk_freq == -1) | |
1877 | return; | |
1878 | ||
1879 | if (dh->type == DMI_ENTRY_MEM_DEVICE) { | |
1880 | struct memdev_dmi_entry *memdev_dmi_entry = | |
1881 | (struct memdev_dmi_entry *)dh; | |
1882 | unsigned long conf_mem_clk_speed_offset = | |
1883 | (unsigned long)&memdev_dmi_entry->conf_mem_clk_speed - | |
1884 | (unsigned long)&memdev_dmi_entry->type; | |
1885 | unsigned long speed_offset = | |
1886 | (unsigned long)&memdev_dmi_entry->speed - | |
1887 | (unsigned long)&memdev_dmi_entry->type; | |
1888 | ||
1889 | /* Check that a DIMM is present */ | |
1890 | if (memdev_dmi_entry->size == 0) | |
1891 | return; | |
1892 | ||
1893 | /* | |
1894 | * Pick the configured speed if it's available, otherwise | |
1895 | * pick the DIMM speed, or we don't have a speed. | |
1896 | */ | |
1897 | if (memdev_dmi_entry->length > conf_mem_clk_speed_offset) { | |
1898 | dmi_mem_clk_speed = | |
1899 | memdev_dmi_entry->conf_mem_clk_speed; | |
1900 | } else if (memdev_dmi_entry->length > speed_offset) { | |
1901 | dmi_mem_clk_speed = memdev_dmi_entry->speed; | |
1902 | } else { | |
1903 | *dclk_freq = -1; | |
1904 | return; | |
1905 | } | |
1906 | ||
1907 | if (*dclk_freq == 0) { | |
1908 | /* First pass, speed was 0 */ | |
1909 | if (dmi_mem_clk_speed > 0) { | |
1910 | /* Set speed if a valid speed is read */ | |
1911 | *dclk_freq = dmi_mem_clk_speed; | |
1912 | } else { | |
1913 | /* Otherwise we don't have a valid speed */ | |
1914 | *dclk_freq = -1; | |
1915 | } | |
1916 | } else if (*dclk_freq > 0 && | |
1917 | *dclk_freq != dmi_mem_clk_speed) { | |
1918 | /* | |
1919 | * If we have a speed, check that all DIMMS are the same | |
1920 | * speed, otherwise set the speed as invalid. | |
1921 | */ | |
1922 | *dclk_freq = -1; | |
1923 | } | |
1924 | } | |
1925 | } | |
1926 | ||
1927 | /* | |
1928 | * The default DCLK frequency is used as a fallback if we | |
1929 | * fail to find anything reliable in the DMI. The value | |
1930 | * is taken straight from the datasheet. | |
1931 | */ | |
1932 | #define DEFAULT_DCLK_FREQ 800 | |
1933 | ||
1934 | static int get_dclk_freq(void) | |
1935 | { | |
1936 | int dclk_freq = 0; | |
1937 | ||
1938 | dmi_walk(decode_dclk, (void *)&dclk_freq); | |
1939 | ||
1940 | if (dclk_freq < 1) | |
1941 | return DEFAULT_DCLK_FREQ; | |
1942 | ||
1943 | return dclk_freq; | |
1944 | } | |
1945 | ||
e8b6a127 SG |
1946 | /* |
1947 | * set_sdram_scrub_rate This routine sets byte/sec bandwidth scrub rate | |
1948 | * to hardware according to SCRUBINTERVAL formula | |
1949 | * found in datasheet. | |
1950 | */ | |
1951 | static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 new_bw) | |
1952 | { | |
1953 | struct i7core_pvt *pvt = mci->pvt_info; | |
1954 | struct pci_dev *pdev; | |
e8b6a127 SG |
1955 | u32 dw_scrub; |
1956 | u32 dw_ssr; | |
1957 | ||
1958 | /* Get data from the MC register, function 2 */ | |
1959 | pdev = pvt->pci_mcr[2]; | |
1960 | if (!pdev) | |
1961 | return -ENODEV; | |
1962 | ||
1963 | pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &dw_scrub); | |
1964 | ||
1965 | if (new_bw == 0) { | |
1966 | /* Prepare to disable petrol scrub */ | |
1967 | dw_scrub &= ~STARTSCRUB; | |
1968 | /* Stop the patrol scrub engine */ | |
535e9c78 NC |
1969 | write_and_test(pdev, MC_SCRUB_CONTROL, |
1970 | dw_scrub & ~SCRUBINTERVAL_MASK); | |
e8b6a127 SG |
1971 | |
1972 | /* Get current status of scrub rate and set bit to disable */ | |
1973 | pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr); | |
1974 | dw_ssr &= ~SSR_MODE_MASK; | |
1975 | dw_ssr |= SSR_MODE_DISABLE; | |
1976 | } else { | |
535e9c78 NC |
1977 | const int cache_line_size = 64; |
1978 | const u32 freq_dclk_mhz = pvt->dclk_freq; | |
1979 | unsigned long long scrub_interval; | |
e8b6a127 SG |
1980 | /* |
1981 | * Translate the desired scrub rate to a register value and | |
535e9c78 | 1982 | * program the corresponding register value. |
e8b6a127 | 1983 | */ |
535e9c78 | 1984 | scrub_interval = (unsigned long long)freq_dclk_mhz * |
4fad8098 SD |
1985 | cache_line_size * 1000000; |
1986 | do_div(scrub_interval, new_bw); | |
535e9c78 NC |
1987 | |
1988 | if (!scrub_interval || scrub_interval > SCRUBINTERVAL_MASK) | |
1989 | return -EINVAL; | |
1990 | ||
1991 | dw_scrub = SCRUBINTERVAL_MASK & scrub_interval; | |
e8b6a127 SG |
1992 | |
1993 | /* Start the patrol scrub engine */ | |
1994 | pci_write_config_dword(pdev, MC_SCRUB_CONTROL, | |
1995 | STARTSCRUB | dw_scrub); | |
1996 | ||
1997 | /* Get current status of scrub rate and set bit to enable */ | |
1998 | pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr); | |
1999 | dw_ssr &= ~SSR_MODE_MASK; | |
2000 | dw_ssr |= SSR_MODE_ENABLE; | |
2001 | } | |
2002 | /* Disable or enable scrubbing */ | |
2003 | pci_write_config_dword(pdev, MC_SSRCONTROL, dw_ssr); | |
2004 | ||
2005 | return new_bw; | |
2006 | } | |
2007 | ||
2008 | /* | |
2009 | * get_sdram_scrub_rate This routine convert current scrub rate value | |
15ed103a | 2010 | * into byte/sec bandwidth according to |
e8b6a127 SG |
2011 | * SCRUBINTERVAL formula found in datasheet. |
2012 | */ | |
2013 | static int get_sdram_scrub_rate(struct mem_ctl_info *mci) | |
2014 | { | |
2015 | struct i7core_pvt *pvt = mci->pvt_info; | |
2016 | struct pci_dev *pdev; | |
2017 | const u32 cache_line_size = 64; | |
535e9c78 NC |
2018 | const u32 freq_dclk_mhz = pvt->dclk_freq; |
2019 | unsigned long long scrub_rate; | |
e8b6a127 SG |
2020 | u32 scrubval; |
2021 | ||
2022 | /* Get data from the MC register, function 2 */ | |
2023 | pdev = pvt->pci_mcr[2]; | |
2024 | if (!pdev) | |
2025 | return -ENODEV; | |
2026 | ||
2027 | /* Get current scrub control data */ | |
2028 | pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &scrubval); | |
2029 | ||
2030 | /* Mask highest 8-bits to 0 */ | |
535e9c78 | 2031 | scrubval &= SCRUBINTERVAL_MASK; |
e8b6a127 SG |
2032 | if (!scrubval) |
2033 | return 0; | |
2034 | ||
2035 | /* Calculate scrub rate value into byte/sec bandwidth */ | |
535e9c78 | 2036 | scrub_rate = (unsigned long long)freq_dclk_mhz * |
4fad8098 SD |
2037 | 1000000 * cache_line_size; |
2038 | do_div(scrub_rate, scrubval); | |
535e9c78 | 2039 | return (int)scrub_rate; |
e8b6a127 SG |
2040 | } |
2041 | ||
2042 | static void enable_sdram_scrub_setting(struct mem_ctl_info *mci) | |
2043 | { | |
2044 | struct i7core_pvt *pvt = mci->pvt_info; | |
2045 | u32 pci_lock; | |
2046 | ||
2047 | /* Unlock writes to pci registers */ | |
2048 | pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock); | |
2049 | pci_lock &= ~0x3; | |
2050 | pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, | |
2051 | pci_lock | MC_CFG_UNLOCK); | |
2052 | ||
2053 | mci->set_sdram_scrub_rate = set_sdram_scrub_rate; | |
2054 | mci->get_sdram_scrub_rate = get_sdram_scrub_rate; | |
2055 | } | |
2056 | ||
2057 | static void disable_sdram_scrub_setting(struct mem_ctl_info *mci) | |
2058 | { | |
2059 | struct i7core_pvt *pvt = mci->pvt_info; | |
2060 | u32 pci_lock; | |
2061 | ||
2062 | /* Lock writes to pci registers */ | |
2063 | pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock); | |
2064 | pci_lock &= ~0x3; | |
2065 | pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, | |
2066 | pci_lock | MC_CFG_LOCK); | |
2067 | } | |
2068 | ||
a3aa0a4a HS |
2069 | static void i7core_pci_ctl_create(struct i7core_pvt *pvt) |
2070 | { | |
2071 | pvt->i7core_pci = edac_pci_create_generic_ctl( | |
2072 | &pvt->i7core_dev->pdev[0]->dev, | |
2073 | EDAC_MOD_STR); | |
2074 | if (unlikely(!pvt->i7core_pci)) | |
f9902f24 MCC |
2075 | i7core_printk(KERN_WARNING, |
2076 | "Unable to setup PCI error report via EDAC\n"); | |
a3aa0a4a HS |
2077 | } |
2078 | ||
2079 | static void i7core_pci_ctl_release(struct i7core_pvt *pvt) | |
2080 | { | |
2081 | if (likely(pvt->i7core_pci)) | |
2082 | edac_pci_release_generic_ctl(pvt->i7core_pci); | |
2083 | else | |
2084 | i7core_printk(KERN_ERR, | |
2085 | "Couldn't find mem_ctl_info for socket %d\n", | |
2086 | pvt->i7core_dev->socket); | |
2087 | pvt->i7core_pci = NULL; | |
2088 | } | |
2089 | ||
1c6edbbe HS |
2090 | static void i7core_unregister_mci(struct i7core_dev *i7core_dev) |
2091 | { | |
2092 | struct mem_ctl_info *mci = i7core_dev->mci; | |
2093 | struct i7core_pvt *pvt; | |
2094 | ||
2095 | if (unlikely(!mci || !mci->pvt_info)) { | |
956b9ba1 | 2096 | edac_dbg(0, "MC: dev = %p\n", &i7core_dev->pdev[0]->dev); |
1c6edbbe HS |
2097 | |
2098 | i7core_printk(KERN_ERR, "Couldn't find mci handler\n"); | |
2099 | return; | |
2100 | } | |
2101 | ||
2102 | pvt = mci->pvt_info; | |
2103 | ||
956b9ba1 | 2104 | edac_dbg(0, "MC: mci = %p, dev = %p\n", mci, &i7core_dev->pdev[0]->dev); |
1c6edbbe | 2105 | |
e8b6a127 | 2106 | /* Disable scrubrate setting */ |
27100db0 MCC |
2107 | if (pvt->enable_scrub) |
2108 | disable_sdram_scrub_setting(mci); | |
e8b6a127 | 2109 | |
1c6edbbe HS |
2110 | /* Disable EDAC polling */ |
2111 | i7core_pci_ctl_release(pvt); | |
2112 | ||
2113 | /* Remove MC sysfs nodes */ | |
5c4cdb5a | 2114 | i7core_delete_sysfs_devices(mci); |
fd687502 | 2115 | edac_mc_del_mc(mci->pdev); |
1c6edbbe | 2116 | |
956b9ba1 | 2117 | edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); |
1c6edbbe HS |
2118 | kfree(mci->ctl_name); |
2119 | edac_mc_free(mci); | |
2120 | i7core_dev->mci = NULL; | |
2121 | } | |
2122 | ||
aace4283 | 2123 | static int i7core_register_mci(struct i7core_dev *i7core_dev) |
a0c36a1f MCC |
2124 | { |
2125 | struct mem_ctl_info *mci; | |
2126 | struct i7core_pvt *pvt; | |
0975c16f MCC |
2127 | int rc; |
2128 | struct edac_mc_layer layers[2]; | |
a0c36a1f | 2129 | |
a0c36a1f | 2130 | /* allocate a new MC control structure */ |
0975c16f MCC |
2131 | |
2132 | layers[0].type = EDAC_MC_LAYER_CHANNEL; | |
2133 | layers[0].size = NUM_CHANS; | |
2134 | layers[0].is_virt_csrow = false; | |
2135 | layers[1].type = EDAC_MC_LAYER_SLOT; | |
2136 | layers[1].size = MAX_DIMMS; | |
2137 | layers[1].is_virt_csrow = true; | |
ca0907b9 | 2138 | mci = edac_mc_alloc(i7core_dev->socket, ARRAY_SIZE(layers), layers, |
0975c16f | 2139 | sizeof(*pvt)); |
f4742949 MCC |
2140 | if (unlikely(!mci)) |
2141 | return -ENOMEM; | |
a0c36a1f | 2142 | |
956b9ba1 | 2143 | edac_dbg(0, "MC: mci = %p, dev = %p\n", mci, &i7core_dev->pdev[0]->dev); |
a0c36a1f | 2144 | |
a0c36a1f | 2145 | pvt = mci->pvt_info; |
ef708b53 | 2146 | memset(pvt, 0, sizeof(*pvt)); |
67166af4 | 2147 | |
6d37d240 MCC |
2148 | /* Associates i7core_dev and mci for future usage */ |
2149 | pvt->i7core_dev = i7core_dev; | |
2150 | i7core_dev->mci = mci; | |
2151 | ||
41fcb7fe MCC |
2152 | /* |
2153 | * FIXME: how to handle RDDR3 at MCI level? It is possible to have | |
2154 | * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different | |
2155 | * memory channels | |
2156 | */ | |
2157 | mci->mtype_cap = MEM_FLAG_DDR3; | |
a0c36a1f MCC |
2158 | mci->edac_ctl_cap = EDAC_FLAG_NONE; |
2159 | mci->edac_cap = EDAC_FLAG_NONE; | |
2160 | mci->mod_name = "i7core_edac.c"; | |
2161 | mci->mod_ver = I7CORE_REVISION; | |
f4742949 MCC |
2162 | mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d", |
2163 | i7core_dev->socket); | |
2164 | mci->dev_name = pci_name(i7core_dev->pdev[0]); | |
a0c36a1f | 2165 | mci->ctl_page_to_phys = NULL; |
1288c18f | 2166 | |
ef708b53 | 2167 | /* Store pci devices at mci for faster access */ |
f4742949 | 2168 | rc = mci_bind_devs(mci, i7core_dev); |
41fcb7fe | 2169 | if (unlikely(rc < 0)) |
628c5ddf | 2170 | goto fail0; |
ef708b53 | 2171 | |
5939813b | 2172 | |
ef708b53 | 2173 | /* Get dimm basic config */ |
2e5185f7 | 2174 | get_dimm_config(mci); |
5939813b | 2175 | /* record ptr to the generic device */ |
fd687502 | 2176 | mci->pdev = &i7core_dev->pdev[0]->dev; |
ef708b53 | 2177 | |
e8b6a127 | 2178 | /* Enable scrubrate setting */ |
27100db0 MCC |
2179 | if (pvt->enable_scrub) |
2180 | enable_sdram_scrub_setting(mci); | |
e8b6a127 | 2181 | |
a0c36a1f | 2182 | /* add this new MC control structure to EDAC's list of MCs */ |
2eace188 | 2183 | if (unlikely(edac_mc_add_mc_with_groups(mci, i7core_dev_groups))) { |
956b9ba1 | 2184 | edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); |
a0c36a1f MCC |
2185 | /* FIXME: perhaps some code should go here that disables error |
2186 | * reporting if we just enabled it | |
2187 | */ | |
b7c76151 MCC |
2188 | |
2189 | rc = -EINVAL; | |
628c5ddf | 2190 | goto fail0; |
a0c36a1f | 2191 | } |
5c4cdb5a | 2192 | if (i7core_create_sysfs_devices(mci)) { |
956b9ba1 | 2193 | edac_dbg(0, "MC: failed to create sysfs nodes\n"); |
5c4cdb5a MCC |
2194 | edac_mc_del_mc(mci->pdev); |
2195 | rc = -EINVAL; | |
2196 | goto fail0; | |
2197 | } | |
a0c36a1f | 2198 | |
194a40fe | 2199 | /* Default error mask is any memory */ |
ef708b53 | 2200 | pvt->inject.channel = 0; |
194a40fe MCC |
2201 | pvt->inject.dimm = -1; |
2202 | pvt->inject.rank = -1; | |
2203 | pvt->inject.bank = -1; | |
2204 | pvt->inject.page = -1; | |
2205 | pvt->inject.col = -1; | |
2206 | ||
a3aa0a4a HS |
2207 | /* allocating generic PCI control info */ |
2208 | i7core_pci_ctl_create(pvt); | |
2209 | ||
535e9c78 NC |
2210 | /* DCLK for scrub rate setting */ |
2211 | pvt->dclk_freq = get_dclk_freq(); | |
2212 | ||
628c5ddf HS |
2213 | return 0; |
2214 | ||
628c5ddf HS |
2215 | fail0: |
2216 | kfree(mci->ctl_name); | |
2217 | edac_mc_free(mci); | |
1c6edbbe | 2218 | i7core_dev->mci = NULL; |
f4742949 MCC |
2219 | return rc; |
2220 | } | |
2221 | ||
2222 | /* | |
2223 | * i7core_probe Probe for ONE instance of device to see if it is | |
2224 | * present. | |
2225 | * return: | |
2226 | * 0 for FOUND a device | |
2227 | * < 0 for error code | |
2228 | */ | |
2d95d815 | 2229 | |
9b3c6e85 | 2230 | static int i7core_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
f4742949 | 2231 | { |
40557591 | 2232 | int rc, count = 0; |
f4742949 MCC |
2233 | struct i7core_dev *i7core_dev; |
2234 | ||
2d95d815 MCC |
2235 | /* get the pci devices we want to reserve for our use */ |
2236 | mutex_lock(&i7core_edac_lock); | |
2237 | ||
f4742949 | 2238 | /* |
d4c27795 | 2239 | * All memory controllers are allocated at the first pass. |
f4742949 | 2240 | */ |
2d95d815 MCC |
2241 | if (unlikely(probed >= 1)) { |
2242 | mutex_unlock(&i7core_edac_lock); | |
76a7bd81 | 2243 | return -ENODEV; |
2d95d815 MCC |
2244 | } |
2245 | probed++; | |
de06eeef | 2246 | |
64c10f6e | 2247 | rc = i7core_get_all_devices(); |
f4742949 MCC |
2248 | if (unlikely(rc < 0)) |
2249 | goto fail0; | |
2250 | ||
2251 | list_for_each_entry(i7core_dev, &i7core_edac_list, list) { | |
40557591 | 2252 | count++; |
aace4283 | 2253 | rc = i7core_register_mci(i7core_dev); |
d4c27795 MCC |
2254 | if (unlikely(rc < 0)) |
2255 | goto fail1; | |
d5381642 MCC |
2256 | } |
2257 | ||
40557591 MCC |
2258 | /* |
2259 | * Nehalem-EX uses a different memory controller. However, as the | |
2260 | * memory controller is not visible on some Nehalem/Nehalem-EP, we | |
2261 | * need to indirectly probe via a X58 PCI device. The same devices | |
2262 | * are found on (some) Nehalem-EX. So, on those machines, the | |
2263 | * probe routine needs to return -ENODEV, as the actual Memory | |
2264 | * Controller registers won't be detected. | |
2265 | */ | |
2266 | if (!count) { | |
2267 | rc = -ENODEV; | |
2268 | goto fail1; | |
2269 | } | |
2270 | ||
2271 | i7core_printk(KERN_INFO, | |
2272 | "Driver loaded, %d memory controller(s) found.\n", | |
2273 | count); | |
8f331907 | 2274 | |
66607706 | 2275 | mutex_unlock(&i7core_edac_lock); |
a0c36a1f MCC |
2276 | return 0; |
2277 | ||
66607706 | 2278 | fail1: |
88ef5ea9 MCC |
2279 | list_for_each_entry(i7core_dev, &i7core_edac_list, list) |
2280 | i7core_unregister_mci(i7core_dev); | |
2281 | ||
13d6e9b6 | 2282 | i7core_put_all_devices(); |
66607706 MCC |
2283 | fail0: |
2284 | mutex_unlock(&i7core_edac_lock); | |
b7c76151 | 2285 | return rc; |
a0c36a1f MCC |
2286 | } |
2287 | ||
2288 | /* | |
2289 | * i7core_remove destructor for one instance of device | |
2290 | * | |
2291 | */ | |
9b3c6e85 | 2292 | static void i7core_remove(struct pci_dev *pdev) |
a0c36a1f | 2293 | { |
64c10f6e | 2294 | struct i7core_dev *i7core_dev; |
a0c36a1f | 2295 | |
956b9ba1 | 2296 | edac_dbg(0, "\n"); |
a0c36a1f | 2297 | |
22e6bcbd MCC |
2298 | /* |
2299 | * we have a trouble here: pdev value for removal will be wrong, since | |
2300 | * it will point to the X58 register used to detect that the machine | |
2301 | * is a Nehalem or upper design. However, due to the way several PCI | |
2302 | * devices are grouped together to provide MC functionality, we need | |
2303 | * to use a different method for releasing the devices | |
2304 | */ | |
87d1d272 | 2305 | |
66607706 | 2306 | mutex_lock(&i7core_edac_lock); |
71fe0170 HS |
2307 | |
2308 | if (unlikely(!probed)) { | |
2309 | mutex_unlock(&i7core_edac_lock); | |
2310 | return; | |
2311 | } | |
2312 | ||
88ef5ea9 MCC |
2313 | list_for_each_entry(i7core_dev, &i7core_edac_list, list) |
2314 | i7core_unregister_mci(i7core_dev); | |
64c10f6e HS |
2315 | |
2316 | /* Release PCI resources */ | |
2317 | i7core_put_all_devices(); | |
2318 | ||
2d95d815 MCC |
2319 | probed--; |
2320 | ||
66607706 | 2321 | mutex_unlock(&i7core_edac_lock); |
a0c36a1f MCC |
2322 | } |
2323 | ||
a0c36a1f MCC |
2324 | MODULE_DEVICE_TABLE(pci, i7core_pci_tbl); |
2325 | ||
2326 | /* | |
2327 | * i7core_driver pci_driver structure for this module | |
2328 | * | |
2329 | */ | |
2330 | static struct pci_driver i7core_driver = { | |
2331 | .name = "i7core_edac", | |
2332 | .probe = i7core_probe, | |
9b3c6e85 | 2333 | .remove = i7core_remove, |
a0c36a1f MCC |
2334 | .id_table = i7core_pci_tbl, |
2335 | }; | |
2336 | ||
2337 | /* | |
2338 | * i7core_init Module entry function | |
2339 | * Try to initialize this module for its devices | |
2340 | */ | |
2341 | static int __init i7core_init(void) | |
2342 | { | |
2343 | int pci_rc; | |
2344 | ||
956b9ba1 | 2345 | edac_dbg(2, "\n"); |
a0c36a1f MCC |
2346 | |
2347 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ | |
2348 | opstate_init(); | |
2349 | ||
54a08ab1 MCC |
2350 | if (use_pci_fixup) |
2351 | i7core_xeon_pci_fixup(pci_dev_table); | |
bc2d7245 | 2352 | |
a0c36a1f MCC |
2353 | pci_rc = pci_register_driver(&i7core_driver); |
2354 | ||
e35fca47 CG |
2355 | if (pci_rc >= 0) { |
2356 | mce_register_decode_chain(&i7_mce_dec); | |
3ef288a9 | 2357 | return 0; |
e35fca47 | 2358 | } |
3ef288a9 MCC |
2359 | |
2360 | i7core_printk(KERN_ERR, "Failed to register device with error %d.\n", | |
2361 | pci_rc); | |
2362 | ||
2363 | return pci_rc; | |
a0c36a1f MCC |
2364 | } |
2365 | ||
2366 | /* | |
2367 | * i7core_exit() Module exit function | |
2368 | * Unregister the driver | |
2369 | */ | |
2370 | static void __exit i7core_exit(void) | |
2371 | { | |
956b9ba1 | 2372 | edac_dbg(2, "\n"); |
a0c36a1f | 2373 | pci_unregister_driver(&i7core_driver); |
e35fca47 | 2374 | mce_unregister_decode_chain(&i7_mce_dec); |
a0c36a1f MCC |
2375 | } |
2376 | ||
2377 | module_init(i7core_init); | |
2378 | module_exit(i7core_exit); | |
2379 | ||
2380 | MODULE_LICENSE("GPL"); | |
37e59f87 | 2381 | MODULE_AUTHOR("Mauro Carvalho Chehab"); |
a0c36a1f MCC |
2382 | MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); |
2383 | MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - " | |
2384 | I7CORE_REVISION); | |
2385 | ||
2386 | module_param(edac_op_state, int, 0444); | |
2387 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |