Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2011 Advanced Micro Devices, Inc. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Christian König <deathsimple@vodafone.de> | |
29 | */ | |
30 | ||
31 | #include <linux/firmware.h> | |
32 | #include <linux/module.h> | |
33 | #include <drm/drmP.h> | |
34 | #include <drm/drm.h> | |
35 | ||
36 | #include "amdgpu.h" | |
37 | #include "amdgpu_pm.h" | |
38 | #include "amdgpu_uvd.h" | |
39 | #include "cikd.h" | |
40 | #include "uvd/uvd_4_2_d.h" | |
41 | ||
42 | /* 1 second timeout */ | |
43 | #define UVD_IDLE_TIMEOUT_MS 1000 | |
8e008dd7 SJ |
44 | /* Polaris10/11 firmware version */ |
45 | #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) | |
d38ceaf9 AD |
46 | |
47 | /* Firmware Names */ | |
48 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
49 | #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin" | |
edf600da CK |
50 | #define FIRMWARE_KABINI "radeon/kabini_uvd.bin" |
51 | #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin" | |
52 | #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin" | |
d38ceaf9 AD |
53 | #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin" |
54 | #endif | |
c65444fe JZ |
55 | #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" |
56 | #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" | |
974ee3db | 57 | #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" |
a39c8cea | 58 | #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" |
2cc0c0b5 | 59 | #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" |
925a51c4 | 60 | #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" |
d38ceaf9 AD |
61 | |
62 | /** | |
63 | * amdgpu_uvd_cs_ctx - Command submission parser context | |
64 | * | |
65 | * Used for emulating virtual memory support on UVD 4.2. | |
66 | */ | |
67 | struct amdgpu_uvd_cs_ctx { | |
68 | struct amdgpu_cs_parser *parser; | |
69 | unsigned reg, count; | |
70 | unsigned data0, data1; | |
71 | unsigned idx; | |
72 | unsigned ib_idx; | |
73 | ||
74 | /* does the IB has a msg command */ | |
75 | bool has_msg_cmd; | |
76 | ||
77 | /* minimum buffer sizes */ | |
78 | unsigned *buf_sizes; | |
79 | }; | |
80 | ||
81 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
82 | MODULE_FIRMWARE(FIRMWARE_BONAIRE); | |
83 | MODULE_FIRMWARE(FIRMWARE_KABINI); | |
84 | MODULE_FIRMWARE(FIRMWARE_KAVERI); | |
85 | MODULE_FIRMWARE(FIRMWARE_HAWAII); | |
86 | MODULE_FIRMWARE(FIRMWARE_MULLINS); | |
87 | #endif | |
88 | MODULE_FIRMWARE(FIRMWARE_TONGA); | |
89 | MODULE_FIRMWARE(FIRMWARE_CARRIZO); | |
974ee3db | 90 | MODULE_FIRMWARE(FIRMWARE_FIJI); |
a39c8cea | 91 | MODULE_FIRMWARE(FIRMWARE_STONEY); |
2cc0c0b5 FC |
92 | MODULE_FIRMWARE(FIRMWARE_POLARIS10); |
93 | MODULE_FIRMWARE(FIRMWARE_POLARIS11); | |
d38ceaf9 AD |
94 | |
95 | static void amdgpu_uvd_note_usage(struct amdgpu_device *adev); | |
96 | static void amdgpu_uvd_idle_work_handler(struct work_struct *work); | |
97 | ||
98 | int amdgpu_uvd_sw_init(struct amdgpu_device *adev) | |
99 | { | |
ead833ec CK |
100 | struct amdgpu_ring *ring; |
101 | struct amd_sched_rq *rq; | |
d38ceaf9 AD |
102 | unsigned long bo_size; |
103 | const char *fw_name; | |
104 | const struct common_firmware_header *hdr; | |
105 | unsigned version_major, version_minor, family_id; | |
106 | int i, r; | |
107 | ||
108 | INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); | |
109 | ||
110 | switch (adev->asic_type) { | |
111 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
112 | case CHIP_BONAIRE: | |
113 | fw_name = FIRMWARE_BONAIRE; | |
114 | break; | |
115 | case CHIP_KABINI: | |
116 | fw_name = FIRMWARE_KABINI; | |
117 | break; | |
118 | case CHIP_KAVERI: | |
119 | fw_name = FIRMWARE_KAVERI; | |
120 | break; | |
121 | case CHIP_HAWAII: | |
122 | fw_name = FIRMWARE_HAWAII; | |
123 | break; | |
124 | case CHIP_MULLINS: | |
125 | fw_name = FIRMWARE_MULLINS; | |
126 | break; | |
127 | #endif | |
128 | case CHIP_TONGA: | |
129 | fw_name = FIRMWARE_TONGA; | |
130 | break; | |
974ee3db DZ |
131 | case CHIP_FIJI: |
132 | fw_name = FIRMWARE_FIJI; | |
133 | break; | |
d38ceaf9 AD |
134 | case CHIP_CARRIZO: |
135 | fw_name = FIRMWARE_CARRIZO; | |
136 | break; | |
a39c8cea SL |
137 | case CHIP_STONEY: |
138 | fw_name = FIRMWARE_STONEY; | |
139 | break; | |
2cc0c0b5 FC |
140 | case CHIP_POLARIS10: |
141 | fw_name = FIRMWARE_POLARIS10; | |
38d75817 | 142 | break; |
2cc0c0b5 FC |
143 | case CHIP_POLARIS11: |
144 | fw_name = FIRMWARE_POLARIS11; | |
38d75817 | 145 | break; |
d38ceaf9 AD |
146 | default: |
147 | return -EINVAL; | |
148 | } | |
149 | ||
150 | r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); | |
151 | if (r) { | |
152 | dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", | |
153 | fw_name); | |
154 | return r; | |
155 | } | |
156 | ||
157 | r = amdgpu_ucode_validate(adev->uvd.fw); | |
158 | if (r) { | |
159 | dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", | |
160 | fw_name); | |
161 | release_firmware(adev->uvd.fw); | |
162 | adev->uvd.fw = NULL; | |
163 | return r; | |
164 | } | |
165 | ||
c0365541 AN |
166 | /* Set the default UVD handles that the firmware can handle */ |
167 | adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; | |
168 | ||
d38ceaf9 AD |
169 | hdr = (const struct common_firmware_header *)adev->uvd.fw->data; |
170 | family_id = le32_to_cpu(hdr->ucode_version) & 0xff; | |
171 | version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; | |
172 | version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; | |
173 | DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", | |
174 | version_major, version_minor, family_id); | |
175 | ||
c0365541 AN |
176 | /* |
177 | * Limit the number of UVD handles depending on microcode major | |
178 | * and minor versions. The firmware version which has 40 UVD | |
179 | * instances support is 1.80. So all subsequent versions should | |
180 | * also have the same support. | |
181 | */ | |
182 | if ((version_major > 0x01) || | |
183 | ((version_major == 0x01) && (version_minor >= 0x50))) | |
184 | adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; | |
185 | ||
562e2689 SJ |
186 | adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | |
187 | (family_id << 8)); | |
188 | ||
8e008dd7 SJ |
189 | if ((adev->asic_type == CHIP_POLARIS10 || |
190 | adev->asic_type == CHIP_POLARIS11) && | |
191 | (adev->uvd.fw_version < FW_1_66_16)) | |
192 | DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n", | |
193 | version_major, version_minor); | |
194 | ||
d38ceaf9 | 195 | bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) |
c0365541 AN |
196 | + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE |
197 | + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; | |
d38ceaf9 | 198 | r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true, |
857d913d AD |
199 | AMDGPU_GEM_DOMAIN_VRAM, |
200 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, | |
72d7668b | 201 | NULL, NULL, &adev->uvd.vcpu_bo); |
d38ceaf9 AD |
202 | if (r) { |
203 | dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); | |
204 | return r; | |
205 | } | |
206 | ||
207 | r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false); | |
208 | if (r) { | |
209 | amdgpu_bo_unref(&adev->uvd.vcpu_bo); | |
210 | dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r); | |
211 | return r; | |
212 | } | |
213 | ||
214 | r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM, | |
215 | &adev->uvd.gpu_addr); | |
216 | if (r) { | |
217 | amdgpu_bo_unreserve(adev->uvd.vcpu_bo); | |
218 | amdgpu_bo_unref(&adev->uvd.vcpu_bo); | |
219 | dev_err(adev->dev, "(%d) UVD bo pin failed\n", r); | |
220 | return r; | |
221 | } | |
222 | ||
223 | r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr); | |
224 | if (r) { | |
225 | dev_err(adev->dev, "(%d) UVD map failed\n", r); | |
226 | return r; | |
227 | } | |
228 | ||
229 | amdgpu_bo_unreserve(adev->uvd.vcpu_bo); | |
230 | ||
ead833ec CK |
231 | ring = &adev->uvd.ring; |
232 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; | |
233 | r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity, | |
234 | rq, amdgpu_sched_jobs); | |
235 | if (r != 0) { | |
236 | DRM_ERROR("Failed setting up UVD run queue.\n"); | |
237 | return r; | |
238 | } | |
239 | ||
c0365541 | 240 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
d38ceaf9 AD |
241 | atomic_set(&adev->uvd.handles[i], 0); |
242 | adev->uvd.filp[i] = NULL; | |
243 | } | |
244 | ||
245 | /* from uvd v5.0 HW addressing capacity increased to 64 bits */ | |
5fc3aeeb | 246 | if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) |
d38ceaf9 AD |
247 | adev->uvd.address_64_bit = true; |
248 | ||
249 | return 0; | |
250 | } | |
251 | ||
252 | int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) | |
253 | { | |
254 | int r; | |
255 | ||
05f19eb5 | 256 | kfree(adev->uvd.saved_bo); |
d38ceaf9 | 257 | |
ead833ec CK |
258 | amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity); |
259 | ||
05f19eb5 ML |
260 | if (adev->uvd.vcpu_bo) { |
261 | r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false); | |
262 | if (!r) { | |
263 | amdgpu_bo_kunmap(adev->uvd.vcpu_bo); | |
264 | amdgpu_bo_unpin(adev->uvd.vcpu_bo); | |
265 | amdgpu_bo_unreserve(adev->uvd.vcpu_bo); | |
266 | } | |
d38ceaf9 | 267 | |
05f19eb5 ML |
268 | amdgpu_bo_unref(&adev->uvd.vcpu_bo); |
269 | } | |
d38ceaf9 AD |
270 | |
271 | amdgpu_ring_fini(&adev->uvd.ring); | |
272 | ||
273 | release_firmware(adev->uvd.fw); | |
274 | ||
275 | return 0; | |
276 | } | |
277 | ||
278 | int amdgpu_uvd_suspend(struct amdgpu_device *adev) | |
279 | { | |
3f99dd81 LL |
280 | unsigned size; |
281 | void *ptr; | |
3f99dd81 | 282 | int i; |
d38ceaf9 AD |
283 | |
284 | if (adev->uvd.vcpu_bo == NULL) | |
285 | return 0; | |
286 | ||
c0365541 | 287 | for (i = 0; i < adev->uvd.max_handles; ++i) |
3f99dd81 LL |
288 | if (atomic_read(&adev->uvd.handles[i])) |
289 | break; | |
290 | ||
291 | if (i == AMDGPU_MAX_UVD_HANDLES) | |
292 | return 0; | |
293 | ||
85cc88f0 RZ |
294 | cancel_delayed_work_sync(&adev->uvd.idle_work); |
295 | ||
3f99dd81 | 296 | size = amdgpu_bo_size(adev->uvd.vcpu_bo); |
3f99dd81 | 297 | ptr = adev->uvd.cpu_addr; |
d38ceaf9 | 298 | |
3f99dd81 LL |
299 | adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL); |
300 | if (!adev->uvd.saved_bo) | |
301 | return -ENOMEM; | |
d38ceaf9 | 302 | |
3f99dd81 | 303 | memcpy(adev->uvd.saved_bo, ptr, size); |
d38ceaf9 AD |
304 | |
305 | return 0; | |
306 | } | |
307 | ||
308 | int amdgpu_uvd_resume(struct amdgpu_device *adev) | |
309 | { | |
310 | unsigned size; | |
311 | void *ptr; | |
d38ceaf9 AD |
312 | |
313 | if (adev->uvd.vcpu_bo == NULL) | |
314 | return -EINVAL; | |
315 | ||
d38ceaf9 | 316 | size = amdgpu_bo_size(adev->uvd.vcpu_bo); |
d38ceaf9 | 317 | ptr = adev->uvd.cpu_addr; |
d38ceaf9 | 318 | |
3f99dd81 LL |
319 | if (adev->uvd.saved_bo != NULL) { |
320 | memcpy(ptr, adev->uvd.saved_bo, size); | |
321 | kfree(adev->uvd.saved_bo); | |
322 | adev->uvd.saved_bo = NULL; | |
d23be4e3 LL |
323 | } else { |
324 | const struct common_firmware_header *hdr; | |
325 | unsigned offset; | |
326 | ||
327 | hdr = (const struct common_firmware_header *)adev->uvd.fw->data; | |
328 | offset = le32_to_cpu(hdr->ucode_array_offset_bytes); | |
329 | memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset, | |
330 | (adev->uvd.fw->size) - offset); | |
331 | size -= le32_to_cpu(hdr->ucode_size_bytes); | |
332 | ptr += le32_to_cpu(hdr->ucode_size_bytes); | |
3f99dd81 | 333 | memset(ptr, 0, size); |
d23be4e3 | 334 | } |
d38ceaf9 AD |
335 | |
336 | return 0; | |
337 | } | |
338 | ||
339 | void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) | |
340 | { | |
341 | struct amdgpu_ring *ring = &adev->uvd.ring; | |
342 | int i, r; | |
343 | ||
c0365541 | 344 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
d38ceaf9 AD |
345 | uint32_t handle = atomic_read(&adev->uvd.handles[i]); |
346 | if (handle != 0 && adev->uvd.filp[i] == filp) { | |
0e3f154a | 347 | struct fence *fence; |
d38ceaf9 AD |
348 | |
349 | amdgpu_uvd_note_usage(adev); | |
350 | ||
d7af97db CK |
351 | r = amdgpu_uvd_get_destroy_msg(ring, handle, |
352 | false, &fence); | |
d38ceaf9 AD |
353 | if (r) { |
354 | DRM_ERROR("Error destroying UVD (%d)!\n", r); | |
355 | continue; | |
356 | } | |
357 | ||
0e3f154a CZ |
358 | fence_wait(fence, false); |
359 | fence_put(fence); | |
d38ceaf9 AD |
360 | |
361 | adev->uvd.filp[i] = NULL; | |
362 | atomic_set(&adev->uvd.handles[i], 0); | |
363 | } | |
364 | } | |
365 | } | |
366 | ||
367 | static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo) | |
368 | { | |
369 | int i; | |
370 | for (i = 0; i < rbo->placement.num_placement; ++i) { | |
371 | rbo->placements[i].fpfn = 0 >> PAGE_SHIFT; | |
372 | rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; | |
373 | } | |
374 | } | |
375 | ||
376 | /** | |
377 | * amdgpu_uvd_cs_pass1 - first parsing round | |
378 | * | |
379 | * @ctx: UVD parser context | |
380 | * | |
381 | * Make sure UVD message and feedback buffers are in VRAM and | |
382 | * nobody is violating an 256MB boundary. | |
383 | */ | |
384 | static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) | |
385 | { | |
386 | struct amdgpu_bo_va_mapping *mapping; | |
387 | struct amdgpu_bo *bo; | |
388 | uint32_t cmd, lo, hi; | |
389 | uint64_t addr; | |
390 | int r = 0; | |
391 | ||
392 | lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); | |
393 | hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); | |
394 | addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); | |
395 | ||
396 | mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); | |
397 | if (mapping == NULL) { | |
398 | DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); | |
399 | return -EINVAL; | |
400 | } | |
401 | ||
402 | if (!ctx->parser->adev->uvd.address_64_bit) { | |
403 | /* check if it's a message or feedback command */ | |
404 | cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; | |
405 | if (cmd == 0x0 || cmd == 0x3) { | |
406 | /* yes, force it into VRAM */ | |
407 | uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; | |
408 | amdgpu_ttm_placement_from_domain(bo, domain); | |
409 | } | |
410 | amdgpu_uvd_force_into_uvd_segment(bo); | |
411 | ||
412 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); | |
413 | } | |
414 | ||
415 | return r; | |
416 | } | |
417 | ||
418 | /** | |
419 | * amdgpu_uvd_cs_msg_decode - handle UVD decode message | |
420 | * | |
421 | * @msg: pointer to message structure | |
422 | * @buf_sizes: returned buffer sizes | |
423 | * | |
424 | * Peek into the decode message and calculate the necessary buffer sizes. | |
425 | */ | |
8e008dd7 SJ |
426 | static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, |
427 | unsigned buf_sizes[]) | |
d38ceaf9 AD |
428 | { |
429 | unsigned stream_type = msg[4]; | |
430 | unsigned width = msg[6]; | |
431 | unsigned height = msg[7]; | |
432 | unsigned dpb_size = msg[9]; | |
433 | unsigned pitch = msg[28]; | |
434 | unsigned level = msg[57]; | |
435 | ||
436 | unsigned width_in_mb = width / 16; | |
437 | unsigned height_in_mb = ALIGN(height / 16, 2); | |
438 | unsigned fs_in_mb = width_in_mb * height_in_mb; | |
439 | ||
21df89a5 JZ |
440 | unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; |
441 | unsigned min_ctx_size = 0; | |
d38ceaf9 AD |
442 | |
443 | image_size = width * height; | |
444 | image_size += image_size / 2; | |
445 | image_size = ALIGN(image_size, 1024); | |
446 | ||
447 | switch (stream_type) { | |
448 | case 0: /* H264 */ | |
d38ceaf9 AD |
449 | switch(level) { |
450 | case 30: | |
451 | num_dpb_buffer = 8100 / fs_in_mb; | |
452 | break; | |
453 | case 31: | |
454 | num_dpb_buffer = 18000 / fs_in_mb; | |
455 | break; | |
456 | case 32: | |
457 | num_dpb_buffer = 20480 / fs_in_mb; | |
458 | break; | |
459 | case 41: | |
460 | num_dpb_buffer = 32768 / fs_in_mb; | |
461 | break; | |
462 | case 42: | |
463 | num_dpb_buffer = 34816 / fs_in_mb; | |
464 | break; | |
465 | case 50: | |
466 | num_dpb_buffer = 110400 / fs_in_mb; | |
467 | break; | |
468 | case 51: | |
469 | num_dpb_buffer = 184320 / fs_in_mb; | |
470 | break; | |
471 | default: | |
472 | num_dpb_buffer = 184320 / fs_in_mb; | |
473 | break; | |
474 | } | |
475 | num_dpb_buffer++; | |
476 | if (num_dpb_buffer > 17) | |
477 | num_dpb_buffer = 17; | |
478 | ||
479 | /* reference picture buffer */ | |
480 | min_dpb_size = image_size * num_dpb_buffer; | |
481 | ||
482 | /* macroblock context buffer */ | |
483 | min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; | |
484 | ||
485 | /* IT surface buffer */ | |
486 | min_dpb_size += width_in_mb * height_in_mb * 32; | |
487 | break; | |
488 | ||
489 | case 1: /* VC1 */ | |
490 | ||
491 | /* reference picture buffer */ | |
492 | min_dpb_size = image_size * 3; | |
493 | ||
494 | /* CONTEXT_BUFFER */ | |
495 | min_dpb_size += width_in_mb * height_in_mb * 128; | |
496 | ||
497 | /* IT surface buffer */ | |
498 | min_dpb_size += width_in_mb * 64; | |
499 | ||
500 | /* DB surface buffer */ | |
501 | min_dpb_size += width_in_mb * 128; | |
502 | ||
503 | /* BP */ | |
504 | tmp = max(width_in_mb, height_in_mb); | |
505 | min_dpb_size += ALIGN(tmp * 7 * 16, 64); | |
506 | break; | |
507 | ||
508 | case 3: /* MPEG2 */ | |
509 | ||
510 | /* reference picture buffer */ | |
511 | min_dpb_size = image_size * 3; | |
512 | break; | |
513 | ||
514 | case 4: /* MPEG4 */ | |
515 | ||
516 | /* reference picture buffer */ | |
517 | min_dpb_size = image_size * 3; | |
518 | ||
519 | /* CM */ | |
520 | min_dpb_size += width_in_mb * height_in_mb * 64; | |
521 | ||
522 | /* IT surface buffer */ | |
523 | min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); | |
524 | break; | |
525 | ||
8e008dd7 SJ |
526 | case 7: /* H264 Perf */ |
527 | switch(level) { | |
528 | case 30: | |
529 | num_dpb_buffer = 8100 / fs_in_mb; | |
530 | break; | |
531 | case 31: | |
532 | num_dpb_buffer = 18000 / fs_in_mb; | |
533 | break; | |
534 | case 32: | |
535 | num_dpb_buffer = 20480 / fs_in_mb; | |
536 | break; | |
537 | case 41: | |
538 | num_dpb_buffer = 32768 / fs_in_mb; | |
539 | break; | |
540 | case 42: | |
541 | num_dpb_buffer = 34816 / fs_in_mb; | |
542 | break; | |
543 | case 50: | |
544 | num_dpb_buffer = 110400 / fs_in_mb; | |
545 | break; | |
546 | case 51: | |
547 | num_dpb_buffer = 184320 / fs_in_mb; | |
548 | break; | |
549 | default: | |
550 | num_dpb_buffer = 184320 / fs_in_mb; | |
551 | break; | |
552 | } | |
553 | num_dpb_buffer++; | |
554 | if (num_dpb_buffer > 17) | |
555 | num_dpb_buffer = 17; | |
556 | ||
557 | /* reference picture buffer */ | |
558 | min_dpb_size = image_size * num_dpb_buffer; | |
559 | ||
560 | if (adev->asic_type < CHIP_POLARIS10){ | |
561 | /* macroblock context buffer */ | |
562 | min_dpb_size += | |
563 | width_in_mb * height_in_mb * num_dpb_buffer * 192; | |
564 | ||
565 | /* IT surface buffer */ | |
566 | min_dpb_size += width_in_mb * height_in_mb * 32; | |
567 | } else { | |
568 | /* macroblock context buffer */ | |
569 | min_ctx_size = | |
570 | width_in_mb * height_in_mb * num_dpb_buffer * 192; | |
571 | } | |
572 | break; | |
573 | ||
86fa0bdc CK |
574 | case 16: /* H265 */ |
575 | image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; | |
576 | image_size = ALIGN(image_size, 256); | |
577 | ||
578 | num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; | |
579 | min_dpb_size = image_size * num_dpb_buffer; | |
8c8bac59 BZ |
580 | min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) |
581 | * 16 * num_dpb_buffer + 52 * 1024; | |
86fa0bdc CK |
582 | break; |
583 | ||
d38ceaf9 AD |
584 | default: |
585 | DRM_ERROR("UVD codec not handled %d!\n", stream_type); | |
586 | return -EINVAL; | |
587 | } | |
588 | ||
589 | if (width > pitch) { | |
590 | DRM_ERROR("Invalid UVD decoding target pitch!\n"); | |
591 | return -EINVAL; | |
592 | } | |
593 | ||
594 | if (dpb_size < min_dpb_size) { | |
595 | DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", | |
596 | dpb_size, min_dpb_size); | |
597 | return -EINVAL; | |
598 | } | |
599 | ||
600 | buf_sizes[0x1] = dpb_size; | |
601 | buf_sizes[0x2] = image_size; | |
8c8bac59 | 602 | buf_sizes[0x4] = min_ctx_size; |
d38ceaf9 AD |
603 | return 0; |
604 | } | |
605 | ||
606 | /** | |
607 | * amdgpu_uvd_cs_msg - handle UVD message | |
608 | * | |
609 | * @ctx: UVD parser context | |
610 | * @bo: buffer object containing the message | |
611 | * @offset: offset into the buffer object | |
612 | * | |
613 | * Peek into the UVD message and extract the session id. | |
614 | * Make sure that we don't open up to many sessions. | |
615 | */ | |
616 | static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, | |
617 | struct amdgpu_bo *bo, unsigned offset) | |
618 | { | |
619 | struct amdgpu_device *adev = ctx->parser->adev; | |
620 | int32_t *msg, msg_type, handle; | |
d38ceaf9 | 621 | void *ptr; |
4127a59e CK |
622 | long r; |
623 | int i; | |
d38ceaf9 AD |
624 | |
625 | if (offset & 0x3F) { | |
626 | DRM_ERROR("UVD messages must be 64 byte aligned!\n"); | |
627 | return -EINVAL; | |
628 | } | |
629 | ||
d38ceaf9 AD |
630 | r = amdgpu_bo_kmap(bo, &ptr); |
631 | if (r) { | |
4127a59e | 632 | DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r); |
d38ceaf9 AD |
633 | return r; |
634 | } | |
635 | ||
636 | msg = ptr + offset; | |
637 | ||
638 | msg_type = msg[1]; | |
639 | handle = msg[2]; | |
640 | ||
641 | if (handle == 0) { | |
642 | DRM_ERROR("Invalid UVD handle!\n"); | |
643 | return -EINVAL; | |
644 | } | |
645 | ||
5146419e LL |
646 | switch (msg_type) { |
647 | case 0: | |
648 | /* it's a create msg, calc image size (width * height) */ | |
649 | amdgpu_bo_kunmap(bo); | |
650 | ||
651 | /* try to alloc a new handle */ | |
c0365541 | 652 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
5146419e LL |
653 | if (atomic_read(&adev->uvd.handles[i]) == handle) { |
654 | DRM_ERROR("Handle 0x%x already in use!\n", handle); | |
655 | return -EINVAL; | |
656 | } | |
657 | ||
658 | if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { | |
659 | adev->uvd.filp[i] = ctx->parser->filp; | |
660 | return 0; | |
661 | } | |
662 | } | |
663 | ||
664 | DRM_ERROR("No more free UVD handles!\n"); | |
665 | return -EINVAL; | |
666 | ||
667 | case 1: | |
d38ceaf9 | 668 | /* it's a decode msg, calc buffer sizes */ |
8e008dd7 | 669 | r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); |
d38ceaf9 AD |
670 | amdgpu_bo_kunmap(bo); |
671 | if (r) | |
672 | return r; | |
673 | ||
5146419e | 674 | /* validate the handle */ |
c0365541 | 675 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
5146419e LL |
676 | if (atomic_read(&adev->uvd.handles[i]) == handle) { |
677 | if (adev->uvd.filp[i] != ctx->parser->filp) { | |
678 | DRM_ERROR("UVD handle collision detected!\n"); | |
679 | return -EINVAL; | |
680 | } | |
681 | return 0; | |
682 | } | |
683 | } | |
684 | ||
685 | DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); | |
686 | return -ENOENT; | |
687 | ||
688 | case 2: | |
d38ceaf9 | 689 | /* it's a destroy msg, free the handle */ |
c0365541 | 690 | for (i = 0; i < adev->uvd.max_handles; ++i) |
d38ceaf9 AD |
691 | atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); |
692 | amdgpu_bo_kunmap(bo); | |
693 | return 0; | |
d38ceaf9 | 694 | |
5146419e LL |
695 | default: |
696 | DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); | |
697 | return -EINVAL; | |
d38ceaf9 | 698 | } |
5146419e | 699 | BUG(); |
d38ceaf9 AD |
700 | return -EINVAL; |
701 | } | |
702 | ||
703 | /** | |
704 | * amdgpu_uvd_cs_pass2 - second parsing round | |
705 | * | |
706 | * @ctx: UVD parser context | |
707 | * | |
708 | * Patch buffer addresses, make sure buffer sizes are correct. | |
709 | */ | |
710 | static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) | |
711 | { | |
712 | struct amdgpu_bo_va_mapping *mapping; | |
713 | struct amdgpu_bo *bo; | |
d38ceaf9 AD |
714 | uint32_t cmd, lo, hi; |
715 | uint64_t start, end; | |
716 | uint64_t addr; | |
717 | int r; | |
718 | ||
719 | lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); | |
720 | hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); | |
721 | addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); | |
722 | ||
723 | mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); | |
724 | if (mapping == NULL) | |
725 | return -EINVAL; | |
726 | ||
727 | start = amdgpu_bo_gpu_offset(bo); | |
728 | ||
729 | end = (mapping->it.last + 1 - mapping->it.start); | |
730 | end = end * AMDGPU_GPU_PAGE_SIZE + start; | |
731 | ||
732 | addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE; | |
733 | start += addr; | |
734 | ||
7270f839 CK |
735 | amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0, |
736 | lower_32_bits(start)); | |
737 | amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1, | |
738 | upper_32_bits(start)); | |
d38ceaf9 AD |
739 | |
740 | cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; | |
741 | if (cmd < 0x4) { | |
742 | if ((end - start) < ctx->buf_sizes[cmd]) { | |
743 | DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, | |
744 | (unsigned)(end - start), | |
745 | ctx->buf_sizes[cmd]); | |
746 | return -EINVAL; | |
747 | } | |
748 | ||
8c8bac59 BZ |
749 | } else if (cmd == 0x206) { |
750 | if ((end - start) < ctx->buf_sizes[4]) { | |
751 | DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, | |
752 | (unsigned)(end - start), | |
753 | ctx->buf_sizes[4]); | |
754 | return -EINVAL; | |
755 | } | |
d38ceaf9 AD |
756 | } else if ((cmd != 0x100) && (cmd != 0x204)) { |
757 | DRM_ERROR("invalid UVD command %X!\n", cmd); | |
758 | return -EINVAL; | |
759 | } | |
760 | ||
761 | if (!ctx->parser->adev->uvd.address_64_bit) { | |
762 | if ((start >> 28) != ((end - 1) >> 28)) { | |
763 | DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", | |
764 | start, end); | |
765 | return -EINVAL; | |
766 | } | |
767 | ||
768 | if ((cmd == 0 || cmd == 0x3) && | |
769 | (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) { | |
770 | DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", | |
771 | start, end); | |
772 | return -EINVAL; | |
773 | } | |
774 | } | |
775 | ||
776 | if (cmd == 0) { | |
777 | ctx->has_msg_cmd = true; | |
778 | r = amdgpu_uvd_cs_msg(ctx, bo, addr); | |
779 | if (r) | |
780 | return r; | |
781 | } else if (!ctx->has_msg_cmd) { | |
782 | DRM_ERROR("Message needed before other commands are send!\n"); | |
783 | return -EINVAL; | |
784 | } | |
785 | ||
786 | return 0; | |
787 | } | |
788 | ||
789 | /** | |
790 | * amdgpu_uvd_cs_reg - parse register writes | |
791 | * | |
792 | * @ctx: UVD parser context | |
793 | * @cb: callback function | |
794 | * | |
795 | * Parse the register writes, call cb on each complete command. | |
796 | */ | |
797 | static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, | |
798 | int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) | |
799 | { | |
50838c8c | 800 | struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; |
d38ceaf9 AD |
801 | int i, r; |
802 | ||
803 | ctx->idx++; | |
804 | for (i = 0; i <= ctx->count; ++i) { | |
805 | unsigned reg = ctx->reg + i; | |
806 | ||
807 | if (ctx->idx >= ib->length_dw) { | |
808 | DRM_ERROR("Register command after end of CS!\n"); | |
809 | return -EINVAL; | |
810 | } | |
811 | ||
812 | switch (reg) { | |
813 | case mmUVD_GPCOM_VCPU_DATA0: | |
814 | ctx->data0 = ctx->idx; | |
815 | break; | |
816 | case mmUVD_GPCOM_VCPU_DATA1: | |
817 | ctx->data1 = ctx->idx; | |
818 | break; | |
819 | case mmUVD_GPCOM_VCPU_CMD: | |
820 | r = cb(ctx); | |
821 | if (r) | |
822 | return r; | |
823 | break; | |
824 | case mmUVD_ENGINE_CNTL: | |
825 | break; | |
826 | default: | |
827 | DRM_ERROR("Invalid reg 0x%X!\n", reg); | |
828 | return -EINVAL; | |
829 | } | |
830 | ctx->idx++; | |
831 | } | |
832 | return 0; | |
833 | } | |
834 | ||
835 | /** | |
836 | * amdgpu_uvd_cs_packets - parse UVD packets | |
837 | * | |
838 | * @ctx: UVD parser context | |
839 | * @cb: callback function | |
840 | * | |
841 | * Parse the command stream packets. | |
842 | */ | |
843 | static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, | |
844 | int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) | |
845 | { | |
50838c8c | 846 | struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; |
d38ceaf9 AD |
847 | int r; |
848 | ||
849 | for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { | |
850 | uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); | |
851 | unsigned type = CP_PACKET_GET_TYPE(cmd); | |
852 | switch (type) { | |
853 | case PACKET_TYPE0: | |
854 | ctx->reg = CP_PACKET0_GET_REG(cmd); | |
855 | ctx->count = CP_PACKET_GET_COUNT(cmd); | |
856 | r = amdgpu_uvd_cs_reg(ctx, cb); | |
857 | if (r) | |
858 | return r; | |
859 | break; | |
860 | case PACKET_TYPE2: | |
861 | ++ctx->idx; | |
862 | break; | |
863 | default: | |
864 | DRM_ERROR("Unknown packet type %d !\n", type); | |
865 | return -EINVAL; | |
866 | } | |
867 | } | |
868 | return 0; | |
869 | } | |
870 | ||
871 | /** | |
872 | * amdgpu_uvd_ring_parse_cs - UVD command submission parser | |
873 | * | |
874 | * @parser: Command submission parser context | |
875 | * | |
876 | * Parse the command stream, patch in addresses as necessary. | |
877 | */ | |
878 | int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) | |
879 | { | |
880 | struct amdgpu_uvd_cs_ctx ctx = {}; | |
881 | unsigned buf_sizes[] = { | |
882 | [0x00000000] = 2048, | |
8c8bac59 BZ |
883 | [0x00000001] = 0xFFFFFFFF, |
884 | [0x00000002] = 0xFFFFFFFF, | |
d38ceaf9 | 885 | [0x00000003] = 2048, |
8c8bac59 | 886 | [0x00000004] = 0xFFFFFFFF, |
d38ceaf9 | 887 | }; |
50838c8c | 888 | struct amdgpu_ib *ib = &parser->job->ibs[ib_idx]; |
d38ceaf9 AD |
889 | int r; |
890 | ||
891 | if (ib->length_dw % 16) { | |
892 | DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", | |
893 | ib->length_dw); | |
894 | return -EINVAL; | |
895 | } | |
896 | ||
897 | ctx.parser = parser; | |
898 | ctx.buf_sizes = buf_sizes; | |
899 | ctx.ib_idx = ib_idx; | |
900 | ||
901 | /* first round, make sure the buffers are actually in the UVD segment */ | |
902 | r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); | |
903 | if (r) | |
904 | return r; | |
905 | ||
906 | /* second round, patch buffer addresses into the command stream */ | |
907 | r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); | |
908 | if (r) | |
909 | return r; | |
910 | ||
911 | if (!ctx.has_msg_cmd) { | |
912 | DRM_ERROR("UVD-IBs need a msg command!\n"); | |
913 | return -EINVAL; | |
914 | } | |
915 | ||
916 | amdgpu_uvd_note_usage(ctx.parser->adev); | |
917 | ||
918 | return 0; | |
919 | } | |
920 | ||
d7af97db CK |
921 | static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, |
922 | bool direct, struct fence **fence) | |
d38ceaf9 AD |
923 | { |
924 | struct ttm_validate_buffer tv; | |
925 | struct ww_acquire_ctx ticket; | |
926 | struct list_head head; | |
d71518b5 CK |
927 | struct amdgpu_job *job; |
928 | struct amdgpu_ib *ib; | |
1763552e | 929 | struct fence *f = NULL; |
7b5ec431 | 930 | struct amdgpu_device *adev = ring->adev; |
d38ceaf9 AD |
931 | uint64_t addr; |
932 | int i, r; | |
933 | ||
934 | memset(&tv, 0, sizeof(tv)); | |
935 | tv.bo = &bo->tbo; | |
936 | ||
937 | INIT_LIST_HEAD(&head); | |
938 | list_add(&tv.head, &head); | |
939 | ||
940 | r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL); | |
941 | if (r) | |
942 | return r; | |
943 | ||
944 | if (!bo->adev->uvd.address_64_bit) { | |
945 | amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); | |
946 | amdgpu_uvd_force_into_uvd_segment(bo); | |
947 | } | |
948 | ||
949 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); | |
950 | if (r) | |
951 | goto err; | |
d71518b5 CK |
952 | |
953 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); | |
7b5ec431 | 954 | if (r) |
d71518b5 | 955 | goto err; |
d38ceaf9 | 956 | |
d71518b5 | 957 | ib = &job->ibs[0]; |
d38ceaf9 | 958 | addr = amdgpu_bo_gpu_offset(bo); |
7b5ec431 CZ |
959 | ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0); |
960 | ib->ptr[1] = addr; | |
961 | ib->ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0); | |
962 | ib->ptr[3] = addr >> 32; | |
963 | ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); | |
964 | ib->ptr[5] = 0; | |
d38ceaf9 | 965 | for (i = 6; i < 16; ++i) |
7b5ec431 CZ |
966 | ib->ptr[i] = PACKET2(0); |
967 | ib->length_dw = 16; | |
d38ceaf9 | 968 | |
d7af97db | 969 | if (direct) { |
c5637837 | 970 | r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f); |
73cfa5f5 | 971 | job->fence = f; |
d7af97db CK |
972 | if (r) |
973 | goto err_free; | |
974 | ||
975 | amdgpu_job_free(job); | |
976 | } else { | |
ead833ec | 977 | r = amdgpu_job_submit(job, ring, &adev->uvd.entity, |
d7af97db CK |
978 | AMDGPU_FENCE_OWNER_UNDEFINED, &f); |
979 | if (r) | |
980 | goto err_free; | |
981 | } | |
d38ceaf9 | 982 | |
1763552e | 983 | ttm_eu_fence_buffer_objects(&ticket, &head, f); |
d38ceaf9 | 984 | |
7b5ec431 | 985 | if (fence) |
1763552e | 986 | *fence = fence_get(f); |
d38ceaf9 | 987 | amdgpu_bo_unref(&bo); |
281b4223 | 988 | fence_put(f); |
7b5ec431 | 989 | |
7b5ec431 | 990 | return 0; |
d71518b5 CK |
991 | |
992 | err_free: | |
993 | amdgpu_job_free(job); | |
994 | ||
d38ceaf9 AD |
995 | err: |
996 | ttm_eu_backoff_reservation(&ticket, &head); | |
997 | return r; | |
998 | } | |
999 | ||
1000 | /* multiple fence commands without any stream commands in between can | |
1001 | crash the vcpu so just try to emmit a dummy create/destroy msg to | |
1002 | avoid this */ | |
1003 | int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, | |
0e3f154a | 1004 | struct fence **fence) |
d38ceaf9 AD |
1005 | { |
1006 | struct amdgpu_device *adev = ring->adev; | |
1007 | struct amdgpu_bo *bo; | |
1008 | uint32_t *msg; | |
1009 | int r, i; | |
1010 | ||
1011 | r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, | |
857d913d AD |
1012 | AMDGPU_GEM_DOMAIN_VRAM, |
1013 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, | |
72d7668b | 1014 | NULL, NULL, &bo); |
d38ceaf9 AD |
1015 | if (r) |
1016 | return r; | |
1017 | ||
1018 | r = amdgpu_bo_reserve(bo, false); | |
1019 | if (r) { | |
1020 | amdgpu_bo_unref(&bo); | |
1021 | return r; | |
1022 | } | |
1023 | ||
1024 | r = amdgpu_bo_kmap(bo, (void **)&msg); | |
1025 | if (r) { | |
1026 | amdgpu_bo_unreserve(bo); | |
1027 | amdgpu_bo_unref(&bo); | |
1028 | return r; | |
1029 | } | |
1030 | ||
1031 | /* stitch together an UVD create msg */ | |
1032 | msg[0] = cpu_to_le32(0x00000de4); | |
1033 | msg[1] = cpu_to_le32(0x00000000); | |
1034 | msg[2] = cpu_to_le32(handle); | |
1035 | msg[3] = cpu_to_le32(0x00000000); | |
1036 | msg[4] = cpu_to_le32(0x00000000); | |
1037 | msg[5] = cpu_to_le32(0x00000000); | |
1038 | msg[6] = cpu_to_le32(0x00000000); | |
1039 | msg[7] = cpu_to_le32(0x00000780); | |
1040 | msg[8] = cpu_to_le32(0x00000440); | |
1041 | msg[9] = cpu_to_le32(0x00000000); | |
1042 | msg[10] = cpu_to_le32(0x01b37000); | |
1043 | for (i = 11; i < 1024; ++i) | |
1044 | msg[i] = cpu_to_le32(0x0); | |
1045 | ||
1046 | amdgpu_bo_kunmap(bo); | |
1047 | amdgpu_bo_unreserve(bo); | |
1048 | ||
d7af97db | 1049 | return amdgpu_uvd_send_msg(ring, bo, true, fence); |
d38ceaf9 AD |
1050 | } |
1051 | ||
1052 | int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, | |
d7af97db | 1053 | bool direct, struct fence **fence) |
d38ceaf9 AD |
1054 | { |
1055 | struct amdgpu_device *adev = ring->adev; | |
1056 | struct amdgpu_bo *bo; | |
1057 | uint32_t *msg; | |
1058 | int r, i; | |
1059 | ||
1060 | r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, | |
857d913d AD |
1061 | AMDGPU_GEM_DOMAIN_VRAM, |
1062 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, | |
72d7668b | 1063 | NULL, NULL, &bo); |
d38ceaf9 AD |
1064 | if (r) |
1065 | return r; | |
1066 | ||
1067 | r = amdgpu_bo_reserve(bo, false); | |
1068 | if (r) { | |
1069 | amdgpu_bo_unref(&bo); | |
1070 | return r; | |
1071 | } | |
1072 | ||
1073 | r = amdgpu_bo_kmap(bo, (void **)&msg); | |
1074 | if (r) { | |
1075 | amdgpu_bo_unreserve(bo); | |
1076 | amdgpu_bo_unref(&bo); | |
1077 | return r; | |
1078 | } | |
1079 | ||
1080 | /* stitch together an UVD destroy msg */ | |
1081 | msg[0] = cpu_to_le32(0x00000de4); | |
1082 | msg[1] = cpu_to_le32(0x00000002); | |
1083 | msg[2] = cpu_to_le32(handle); | |
1084 | msg[3] = cpu_to_le32(0x00000000); | |
1085 | for (i = 4; i < 1024; ++i) | |
1086 | msg[i] = cpu_to_le32(0x0); | |
1087 | ||
1088 | amdgpu_bo_kunmap(bo); | |
1089 | amdgpu_bo_unreserve(bo); | |
1090 | ||
d7af97db | 1091 | return amdgpu_uvd_send_msg(ring, bo, direct, fence); |
d38ceaf9 AD |
1092 | } |
1093 | ||
1094 | static void amdgpu_uvd_idle_work_handler(struct work_struct *work) | |
1095 | { | |
1096 | struct amdgpu_device *adev = | |
1097 | container_of(work, struct amdgpu_device, uvd.idle_work.work); | |
1098 | unsigned i, fences, handles = 0; | |
1099 | ||
1100 | fences = amdgpu_fence_count_emitted(&adev->uvd.ring); | |
1101 | ||
c0365541 | 1102 | for (i = 0; i < adev->uvd.max_handles; ++i) |
d38ceaf9 AD |
1103 | if (atomic_read(&adev->uvd.handles[i])) |
1104 | ++handles; | |
1105 | ||
1106 | if (fences == 0 && handles == 0) { | |
1107 | if (adev->pm.dpm_enabled) { | |
1108 | amdgpu_dpm_enable_uvd(adev, false); | |
a7f14a18 RZ |
1109 | /* just work around for uvd clock remain high even |
1110 | * when uvd dpm disabled on Polaris10 */ | |
1111 | if (adev->asic_type == CHIP_POLARIS10) | |
1112 | amdgpu_asic_set_uvd_clocks(adev, 0, 0); | |
d38ceaf9 AD |
1113 | } else { |
1114 | amdgpu_asic_set_uvd_clocks(adev, 0, 0); | |
1115 | } | |
1116 | } else { | |
1117 | schedule_delayed_work(&adev->uvd.idle_work, | |
1118 | msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); | |
1119 | } | |
1120 | } | |
1121 | ||
1122 | static void amdgpu_uvd_note_usage(struct amdgpu_device *adev) | |
1123 | { | |
1124 | bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); | |
1125 | set_clocks &= schedule_delayed_work(&adev->uvd.idle_work, | |
1126 | msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); | |
1127 | ||
1128 | if (set_clocks) { | |
1129 | if (adev->pm.dpm_enabled) { | |
1130 | amdgpu_dpm_enable_uvd(adev, true); | |
1131 | } else { | |
1132 | amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); | |
1133 | } | |
1134 | } | |
1135 | } |