Commit | Line | Data |
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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
32d82067 | 35 | #include <linux/uaccess.h> |
54cf91dc | 36 | |
a415d355 CW |
37 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
38 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
e6a84468 | 39 | #define __EXEC_OBJECT_NEEDS_MAP (1<<29) |
d23db88c CW |
40 | #define __EXEC_OBJECT_NEEDS_BIAS (1<<28) |
41 | ||
42 | #define BATCH_OFFSET_BIAS (256*1024) | |
a415d355 | 43 | |
27173f1f BW |
44 | struct eb_vmas { |
45 | struct list_head vmas; | |
67731b87 | 46 | int and; |
eef90ccb | 47 | union { |
27173f1f | 48 | struct i915_vma *lut[0]; |
eef90ccb CW |
49 | struct hlist_head buckets[0]; |
50 | }; | |
67731b87 CW |
51 | }; |
52 | ||
27173f1f | 53 | static struct eb_vmas * |
17601cbc | 54 | eb_create(struct drm_i915_gem_execbuffer2 *args) |
67731b87 | 55 | { |
27173f1f | 56 | struct eb_vmas *eb = NULL; |
eef90ccb CW |
57 | |
58 | if (args->flags & I915_EXEC_HANDLE_LUT) { | |
b205ca57 | 59 | unsigned size = args->buffer_count; |
27173f1f BW |
60 | size *= sizeof(struct i915_vma *); |
61 | size += sizeof(struct eb_vmas); | |
eef90ccb CW |
62 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
63 | } | |
64 | ||
65 | if (eb == NULL) { | |
b205ca57 DV |
66 | unsigned size = args->buffer_count; |
67 | unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
27b7c63a | 68 | BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); |
eef90ccb CW |
69 | while (count > 2*size) |
70 | count >>= 1; | |
71 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
27173f1f | 72 | sizeof(struct eb_vmas), |
eef90ccb CW |
73 | GFP_TEMPORARY); |
74 | if (eb == NULL) | |
75 | return eb; | |
76 | ||
77 | eb->and = count - 1; | |
78 | } else | |
79 | eb->and = -args->buffer_count; | |
80 | ||
27173f1f | 81 | INIT_LIST_HEAD(&eb->vmas); |
67731b87 CW |
82 | return eb; |
83 | } | |
84 | ||
85 | static void | |
27173f1f | 86 | eb_reset(struct eb_vmas *eb) |
67731b87 | 87 | { |
eef90ccb CW |
88 | if (eb->and >= 0) |
89 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
67731b87 CW |
90 | } |
91 | ||
3b96eff4 | 92 | static int |
27173f1f BW |
93 | eb_lookup_vmas(struct eb_vmas *eb, |
94 | struct drm_i915_gem_exec_object2 *exec, | |
95 | const struct drm_i915_gem_execbuffer2 *args, | |
96 | struct i915_address_space *vm, | |
97 | struct drm_file *file) | |
3b96eff4 | 98 | { |
27173f1f BW |
99 | struct drm_i915_gem_object *obj; |
100 | struct list_head objects; | |
9ae9ab52 | 101 | int i, ret; |
3b96eff4 | 102 | |
27173f1f | 103 | INIT_LIST_HEAD(&objects); |
3b96eff4 | 104 | spin_lock(&file->table_lock); |
27173f1f BW |
105 | /* Grab a reference to the object and release the lock so we can lookup |
106 | * or create the VMA without using GFP_ATOMIC */ | |
eef90ccb | 107 | for (i = 0; i < args->buffer_count; i++) { |
3b96eff4 CW |
108 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); |
109 | if (obj == NULL) { | |
110 | spin_unlock(&file->table_lock); | |
111 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
112 | exec[i].handle, i); | |
27173f1f | 113 | ret = -ENOENT; |
9ae9ab52 | 114 | goto err; |
3b96eff4 CW |
115 | } |
116 | ||
27173f1f | 117 | if (!list_empty(&obj->obj_exec_link)) { |
3b96eff4 CW |
118 | spin_unlock(&file->table_lock); |
119 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
120 | obj, exec[i].handle, i); | |
27173f1f | 121 | ret = -EINVAL; |
9ae9ab52 | 122 | goto err; |
3b96eff4 CW |
123 | } |
124 | ||
125 | drm_gem_object_reference(&obj->base); | |
27173f1f BW |
126 | list_add_tail(&obj->obj_exec_link, &objects); |
127 | } | |
128 | spin_unlock(&file->table_lock); | |
3b96eff4 | 129 | |
27173f1f | 130 | i = 0; |
9ae9ab52 | 131 | while (!list_empty(&objects)) { |
27173f1f | 132 | struct i915_vma *vma; |
6f65e29a | 133 | |
9ae9ab52 CW |
134 | obj = list_first_entry(&objects, |
135 | struct drm_i915_gem_object, | |
136 | obj_exec_link); | |
137 | ||
e656a6cb DV |
138 | /* |
139 | * NOTE: We can leak any vmas created here when something fails | |
140 | * later on. But that's no issue since vma_unbind can deal with | |
141 | * vmas which are not actually bound. And since only | |
142 | * lookup_or_create exists as an interface to get at the vma | |
143 | * from the (obj, vm) we don't run the risk of creating | |
144 | * duplicated vmas for the same vm. | |
145 | */ | |
da51a1e7 | 146 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
27173f1f | 147 | if (IS_ERR(vma)) { |
27173f1f BW |
148 | DRM_DEBUG("Failed to lookup VMA\n"); |
149 | ret = PTR_ERR(vma); | |
9ae9ab52 | 150 | goto err; |
27173f1f BW |
151 | } |
152 | ||
9ae9ab52 | 153 | /* Transfer ownership from the objects list to the vmas list. */ |
27173f1f | 154 | list_add_tail(&vma->exec_list, &eb->vmas); |
9ae9ab52 | 155 | list_del_init(&obj->obj_exec_link); |
27173f1f BW |
156 | |
157 | vma->exec_entry = &exec[i]; | |
eef90ccb | 158 | if (eb->and < 0) { |
27173f1f | 159 | eb->lut[i] = vma; |
eef90ccb CW |
160 | } else { |
161 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; | |
27173f1f BW |
162 | vma->exec_handle = handle; |
163 | hlist_add_head(&vma->exec_node, | |
eef90ccb CW |
164 | &eb->buckets[handle & eb->and]); |
165 | } | |
27173f1f | 166 | ++i; |
3b96eff4 | 167 | } |
3b96eff4 | 168 | |
9ae9ab52 | 169 | return 0; |
27173f1f | 170 | |
27173f1f | 171 | |
9ae9ab52 | 172 | err: |
27173f1f BW |
173 | while (!list_empty(&objects)) { |
174 | obj = list_first_entry(&objects, | |
175 | struct drm_i915_gem_object, | |
176 | obj_exec_link); | |
177 | list_del_init(&obj->obj_exec_link); | |
9ae9ab52 | 178 | drm_gem_object_unreference(&obj->base); |
27173f1f | 179 | } |
9ae9ab52 CW |
180 | /* |
181 | * Objects already transfered to the vmas list will be unreferenced by | |
182 | * eb_destroy. | |
183 | */ | |
184 | ||
27173f1f | 185 | return ret; |
3b96eff4 CW |
186 | } |
187 | ||
27173f1f | 188 | static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle) |
67731b87 | 189 | { |
eef90ccb CW |
190 | if (eb->and < 0) { |
191 | if (handle >= -eb->and) | |
192 | return NULL; | |
193 | return eb->lut[handle]; | |
194 | } else { | |
195 | struct hlist_head *head; | |
196 | struct hlist_node *node; | |
67731b87 | 197 | |
eef90ccb CW |
198 | head = &eb->buckets[handle & eb->and]; |
199 | hlist_for_each(node, head) { | |
27173f1f | 200 | struct i915_vma *vma; |
67731b87 | 201 | |
27173f1f BW |
202 | vma = hlist_entry(node, struct i915_vma, exec_node); |
203 | if (vma->exec_handle == handle) | |
204 | return vma; | |
eef90ccb CW |
205 | } |
206 | return NULL; | |
207 | } | |
67731b87 CW |
208 | } |
209 | ||
a415d355 CW |
210 | static void |
211 | i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) | |
212 | { | |
213 | struct drm_i915_gem_exec_object2 *entry; | |
214 | struct drm_i915_gem_object *obj = vma->obj; | |
215 | ||
216 | if (!drm_mm_node_allocated(&vma->node)) | |
217 | return; | |
218 | ||
219 | entry = vma->exec_entry; | |
220 | ||
221 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
222 | i915_gem_object_unpin_fence(obj); | |
223 | ||
224 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
3d7f0f9d | 225 | vma->pin_count--; |
a415d355 | 226 | |
de4e783a | 227 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); |
a415d355 CW |
228 | } |
229 | ||
230 | static void eb_destroy(struct eb_vmas *eb) | |
231 | { | |
27173f1f BW |
232 | while (!list_empty(&eb->vmas)) { |
233 | struct i915_vma *vma; | |
bcffc3fa | 234 | |
27173f1f BW |
235 | vma = list_first_entry(&eb->vmas, |
236 | struct i915_vma, | |
bcffc3fa | 237 | exec_list); |
27173f1f | 238 | list_del_init(&vma->exec_list); |
a415d355 | 239 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 240 | drm_gem_object_unreference(&vma->obj->base); |
bcffc3fa | 241 | } |
67731b87 CW |
242 | kfree(eb); |
243 | } | |
244 | ||
dabdfe02 CW |
245 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
246 | { | |
2cc86b82 CW |
247 | return (HAS_LLC(obj->base.dev) || |
248 | obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
dabdfe02 CW |
249 | obj->cache_level != I915_CACHE_NONE); |
250 | } | |
251 | ||
5032d871 RB |
252 | static int |
253 | relocate_entry_cpu(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
254 | struct drm_i915_gem_relocation_entry *reloc, |
255 | uint64_t target_offset) | |
5032d871 | 256 | { |
3c94ceee | 257 | struct drm_device *dev = obj->base.dev; |
5032d871 | 258 | uint32_t page_offset = offset_in_page(reloc->offset); |
d9ceb957 | 259 | uint64_t delta = reloc->delta + target_offset; |
5032d871 | 260 | char *vaddr; |
8b78f0e5 | 261 | int ret; |
5032d871 | 262 | |
2cc86b82 | 263 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
5032d871 RB |
264 | if (ret) |
265 | return ret; | |
266 | ||
033908ae | 267 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, |
5032d871 | 268 | reloc->offset >> PAGE_SHIFT)); |
d9ceb957 | 269 | *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta); |
3c94ceee BW |
270 | |
271 | if (INTEL_INFO(dev)->gen >= 8) { | |
272 | page_offset = offset_in_page(page_offset + sizeof(uint32_t)); | |
273 | ||
274 | if (page_offset == 0) { | |
275 | kunmap_atomic(vaddr); | |
033908ae | 276 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, |
3c94ceee BW |
277 | (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); |
278 | } | |
279 | ||
d9ceb957 | 280 | *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta); |
3c94ceee BW |
281 | } |
282 | ||
5032d871 RB |
283 | kunmap_atomic(vaddr); |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
288 | static int | |
289 | relocate_entry_gtt(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
290 | struct drm_i915_gem_relocation_entry *reloc, |
291 | uint64_t target_offset) | |
5032d871 RB |
292 | { |
293 | struct drm_device *dev = obj->base.dev; | |
294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d9ceb957 | 295 | uint64_t delta = reloc->delta + target_offset; |
906843c3 | 296 | uint64_t offset; |
5032d871 | 297 | void __iomem *reloc_page; |
8b78f0e5 | 298 | int ret; |
5032d871 RB |
299 | |
300 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
301 | if (ret) | |
302 | return ret; | |
303 | ||
304 | ret = i915_gem_object_put_fence(obj); | |
305 | if (ret) | |
306 | return ret; | |
307 | ||
308 | /* Map the page containing the relocation we're going to perform. */ | |
906843c3 CW |
309 | offset = i915_gem_obj_ggtt_offset(obj); |
310 | offset += reloc->offset; | |
5032d871 | 311 | reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, |
906843c3 CW |
312 | offset & PAGE_MASK); |
313 | iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset)); | |
3c94ceee BW |
314 | |
315 | if (INTEL_INFO(dev)->gen >= 8) { | |
906843c3 | 316 | offset += sizeof(uint32_t); |
3c94ceee | 317 | |
906843c3 | 318 | if (offset_in_page(offset) == 0) { |
3c94ceee | 319 | io_mapping_unmap_atomic(reloc_page); |
906843c3 CW |
320 | reloc_page = |
321 | io_mapping_map_atomic_wc(dev_priv->gtt.mappable, | |
322 | offset); | |
3c94ceee BW |
323 | } |
324 | ||
906843c3 CW |
325 | iowrite32(upper_32_bits(delta), |
326 | reloc_page + offset_in_page(offset)); | |
3c94ceee BW |
327 | } |
328 | ||
5032d871 RB |
329 | io_mapping_unmap_atomic(reloc_page); |
330 | ||
331 | return 0; | |
332 | } | |
333 | ||
edf4427b CW |
334 | static void |
335 | clflush_write32(void *addr, uint32_t value) | |
336 | { | |
337 | /* This is not a fast path, so KISS. */ | |
338 | drm_clflush_virt_range(addr, sizeof(uint32_t)); | |
339 | *(uint32_t *)addr = value; | |
340 | drm_clflush_virt_range(addr, sizeof(uint32_t)); | |
341 | } | |
342 | ||
343 | static int | |
344 | relocate_entry_clflush(struct drm_i915_gem_object *obj, | |
345 | struct drm_i915_gem_relocation_entry *reloc, | |
346 | uint64_t target_offset) | |
347 | { | |
348 | struct drm_device *dev = obj->base.dev; | |
349 | uint32_t page_offset = offset_in_page(reloc->offset); | |
350 | uint64_t delta = (int)reloc->delta + target_offset; | |
351 | char *vaddr; | |
352 | int ret; | |
353 | ||
354 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
355 | if (ret) | |
356 | return ret; | |
357 | ||
033908ae | 358 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, |
edf4427b CW |
359 | reloc->offset >> PAGE_SHIFT)); |
360 | clflush_write32(vaddr + page_offset, lower_32_bits(delta)); | |
361 | ||
362 | if (INTEL_INFO(dev)->gen >= 8) { | |
363 | page_offset = offset_in_page(page_offset + sizeof(uint32_t)); | |
364 | ||
365 | if (page_offset == 0) { | |
366 | kunmap_atomic(vaddr); | |
033908ae | 367 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, |
edf4427b CW |
368 | (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); |
369 | } | |
370 | ||
371 | clflush_write32(vaddr + page_offset, upper_32_bits(delta)); | |
372 | } | |
373 | ||
374 | kunmap_atomic(vaddr); | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
54cf91dc CW |
379 | static int |
380 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
27173f1f | 381 | struct eb_vmas *eb, |
3e7a0322 | 382 | struct drm_i915_gem_relocation_entry *reloc) |
54cf91dc CW |
383 | { |
384 | struct drm_device *dev = obj->base.dev; | |
385 | struct drm_gem_object *target_obj; | |
149c8407 | 386 | struct drm_i915_gem_object *target_i915_obj; |
27173f1f | 387 | struct i915_vma *target_vma; |
d9ceb957 | 388 | uint64_t target_offset; |
8b78f0e5 | 389 | int ret; |
54cf91dc | 390 | |
67731b87 | 391 | /* we've already hold a reference to all valid objects */ |
27173f1f BW |
392 | target_vma = eb_get_vma(eb, reloc->target_handle); |
393 | if (unlikely(target_vma == NULL)) | |
54cf91dc | 394 | return -ENOENT; |
27173f1f BW |
395 | target_i915_obj = target_vma->obj; |
396 | target_obj = &target_vma->obj->base; | |
54cf91dc | 397 | |
5ce09725 | 398 | target_offset = target_vma->node.start; |
54cf91dc | 399 | |
e844b990 EA |
400 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
401 | * pipe_control writes because the gpu doesn't properly redirect them | |
402 | * through the ppgtt for non_secure batchbuffers. */ | |
403 | if (unlikely(IS_GEN6(dev) && | |
0875546c | 404 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) { |
fe14d5f4 | 405 | ret = i915_vma_bind(target_vma, target_i915_obj->cache_level, |
0875546c | 406 | PIN_GLOBAL); |
fe14d5f4 TU |
407 | if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!")) |
408 | return ret; | |
409 | } | |
e844b990 | 410 | |
54cf91dc | 411 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 412 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 413 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
414 | "obj %p target %d offset %d " |
415 | "read %08x write %08x", | |
416 | obj, reloc->target_handle, | |
417 | (int) reloc->offset, | |
418 | reloc->read_domains, | |
419 | reloc->write_domain); | |
8b78f0e5 | 420 | return -EINVAL; |
54cf91dc | 421 | } |
4ca4a250 DV |
422 | if (unlikely((reloc->write_domain | reloc->read_domains) |
423 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 424 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
425 | "obj %p target %d offset %d " |
426 | "read %08x write %08x", | |
427 | obj, reloc->target_handle, | |
428 | (int) reloc->offset, | |
429 | reloc->read_domains, | |
430 | reloc->write_domain); | |
8b78f0e5 | 431 | return -EINVAL; |
54cf91dc | 432 | } |
54cf91dc CW |
433 | |
434 | target_obj->pending_read_domains |= reloc->read_domains; | |
435 | target_obj->pending_write_domain |= reloc->write_domain; | |
436 | ||
437 | /* If the relocation already has the right value in it, no | |
438 | * more work needs to be done. | |
439 | */ | |
440 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 441 | return 0; |
54cf91dc CW |
442 | |
443 | /* Check that the relocation address is valid... */ | |
3c94ceee BW |
444 | if (unlikely(reloc->offset > |
445 | obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) { | |
ff240199 | 446 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
447 | "obj %p target %d offset %d size %d.\n", |
448 | obj, reloc->target_handle, | |
449 | (int) reloc->offset, | |
450 | (int) obj->base.size); | |
8b78f0e5 | 451 | return -EINVAL; |
54cf91dc | 452 | } |
b8f7ab17 | 453 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 454 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
455 | "obj %p target %d offset %d.\n", |
456 | obj, reloc->target_handle, | |
457 | (int) reloc->offset); | |
8b78f0e5 | 458 | return -EINVAL; |
54cf91dc CW |
459 | } |
460 | ||
dabdfe02 | 461 | /* We can't wait for rendering with pagefaults disabled */ |
32d82067 | 462 | if (obj->active && pagefault_disabled()) |
dabdfe02 CW |
463 | return -EFAULT; |
464 | ||
5032d871 | 465 | if (use_cpu_reloc(obj)) |
d9ceb957 | 466 | ret = relocate_entry_cpu(obj, reloc, target_offset); |
edf4427b | 467 | else if (obj->map_and_fenceable) |
d9ceb957 | 468 | ret = relocate_entry_gtt(obj, reloc, target_offset); |
edf4427b CW |
469 | else if (cpu_has_clflush) |
470 | ret = relocate_entry_clflush(obj, reloc, target_offset); | |
471 | else { | |
472 | WARN_ONCE(1, "Impossible case in relocation handling\n"); | |
473 | ret = -ENODEV; | |
474 | } | |
54cf91dc | 475 | |
d4d36014 DV |
476 | if (ret) |
477 | return ret; | |
478 | ||
54cf91dc CW |
479 | /* and update the user's relocation entry */ |
480 | reloc->presumed_offset = target_offset; | |
481 | ||
67731b87 | 482 | return 0; |
54cf91dc CW |
483 | } |
484 | ||
485 | static int | |
27173f1f BW |
486 | i915_gem_execbuffer_relocate_vma(struct i915_vma *vma, |
487 | struct eb_vmas *eb) | |
54cf91dc | 488 | { |
1d83f442 CW |
489 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
490 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 491 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
27173f1f | 492 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
1d83f442 | 493 | int remain, ret; |
54cf91dc | 494 | |
2bb4629a | 495 | user_relocs = to_user_ptr(entry->relocs_ptr); |
54cf91dc | 496 | |
1d83f442 CW |
497 | remain = entry->relocation_count; |
498 | while (remain) { | |
499 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
500 | int count = remain; | |
501 | if (count > ARRAY_SIZE(stack_reloc)) | |
502 | count = ARRAY_SIZE(stack_reloc); | |
503 | remain -= count; | |
504 | ||
505 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
506 | return -EFAULT; |
507 | ||
1d83f442 CW |
508 | do { |
509 | u64 offset = r->presumed_offset; | |
54cf91dc | 510 | |
3e7a0322 | 511 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r); |
1d83f442 CW |
512 | if (ret) |
513 | return ret; | |
514 | ||
515 | if (r->presumed_offset != offset && | |
516 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
517 | &r->presumed_offset, | |
518 | sizeof(r->presumed_offset))) { | |
519 | return -EFAULT; | |
520 | } | |
521 | ||
522 | user_relocs++; | |
523 | r++; | |
524 | } while (--count); | |
54cf91dc CW |
525 | } |
526 | ||
527 | return 0; | |
1d83f442 | 528 | #undef N_RELOC |
54cf91dc CW |
529 | } |
530 | ||
531 | static int | |
27173f1f BW |
532 | i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma, |
533 | struct eb_vmas *eb, | |
534 | struct drm_i915_gem_relocation_entry *relocs) | |
54cf91dc | 535 | { |
27173f1f | 536 | const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
54cf91dc CW |
537 | int i, ret; |
538 | ||
539 | for (i = 0; i < entry->relocation_count; i++) { | |
3e7a0322 | 540 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]); |
54cf91dc CW |
541 | if (ret) |
542 | return ret; | |
543 | } | |
544 | ||
545 | return 0; | |
546 | } | |
547 | ||
548 | static int | |
17601cbc | 549 | i915_gem_execbuffer_relocate(struct eb_vmas *eb) |
54cf91dc | 550 | { |
27173f1f | 551 | struct i915_vma *vma; |
d4aeee77 CW |
552 | int ret = 0; |
553 | ||
554 | /* This is the fast path and we cannot handle a pagefault whilst | |
555 | * holding the struct mutex lest the user pass in the relocations | |
556 | * contained within a mmaped bo. For in such a case we, the page | |
557 | * fault handler would call i915_gem_fault() and we would try to | |
558 | * acquire the struct mutex again. Obviously this is bad and so | |
559 | * lockdep complains vehemently. | |
560 | */ | |
561 | pagefault_disable(); | |
27173f1f BW |
562 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
563 | ret = i915_gem_execbuffer_relocate_vma(vma, eb); | |
54cf91dc | 564 | if (ret) |
d4aeee77 | 565 | break; |
54cf91dc | 566 | } |
d4aeee77 | 567 | pagefault_enable(); |
54cf91dc | 568 | |
d4aeee77 | 569 | return ret; |
54cf91dc CW |
570 | } |
571 | ||
edf4427b CW |
572 | static bool only_mappable_for_reloc(unsigned int flags) |
573 | { | |
574 | return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) == | |
575 | __EXEC_OBJECT_NEEDS_MAP; | |
576 | } | |
577 | ||
1690e1eb | 578 | static int |
27173f1f | 579 | i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, |
a4872ba6 | 580 | struct intel_engine_cs *ring, |
27173f1f | 581 | bool *need_reloc) |
1690e1eb | 582 | { |
6f65e29a | 583 | struct drm_i915_gem_object *obj = vma->obj; |
27173f1f | 584 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
d23db88c | 585 | uint64_t flags; |
1690e1eb CW |
586 | int ret; |
587 | ||
0875546c | 588 | flags = PIN_USER; |
0229da32 DV |
589 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT) |
590 | flags |= PIN_GLOBAL; | |
591 | ||
edf4427b | 592 | if (!drm_mm_node_allocated(&vma->node)) { |
101b506a MT |
593 | /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset, |
594 | * limit address to the first 4GBs for unflagged objects. | |
595 | */ | |
596 | if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0) | |
597 | flags |= PIN_ZONE_4G; | |
edf4427b CW |
598 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) |
599 | flags |= PIN_GLOBAL | PIN_MAPPABLE; | |
edf4427b CW |
600 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) |
601 | flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; | |
506a8e87 CW |
602 | if (entry->flags & EXEC_OBJECT_PINNED) |
603 | flags |= entry->offset | PIN_OFFSET_FIXED; | |
101b506a MT |
604 | if ((flags & PIN_MAPPABLE) == 0) |
605 | flags |= PIN_HIGH; | |
edf4427b | 606 | } |
1ec9e26d DV |
607 | |
608 | ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags); | |
edf4427b CW |
609 | if ((ret == -ENOSPC || ret == -E2BIG) && |
610 | only_mappable_for_reloc(entry->flags)) | |
611 | ret = i915_gem_object_pin(obj, vma->vm, | |
612 | entry->alignment, | |
0229da32 | 613 | flags & ~PIN_MAPPABLE); |
1690e1eb CW |
614 | if (ret) |
615 | return ret; | |
616 | ||
7788a765 CW |
617 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
618 | ||
82b6b6d7 CW |
619 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
620 | ret = i915_gem_object_get_fence(obj); | |
621 | if (ret) | |
622 | return ret; | |
9a5a53b3 | 623 | |
82b6b6d7 CW |
624 | if (i915_gem_object_pin_fence(obj)) |
625 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; | |
1690e1eb CW |
626 | } |
627 | ||
27173f1f BW |
628 | if (entry->offset != vma->node.start) { |
629 | entry->offset = vma->node.start; | |
ed5982e6 DV |
630 | *need_reloc = true; |
631 | } | |
632 | ||
633 | if (entry->flags & EXEC_OBJECT_WRITE) { | |
634 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; | |
635 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; | |
636 | } | |
637 | ||
1690e1eb | 638 | return 0; |
7788a765 | 639 | } |
1690e1eb | 640 | |
d23db88c | 641 | static bool |
e6a84468 | 642 | need_reloc_mappable(struct i915_vma *vma) |
d23db88c CW |
643 | { |
644 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
d23db88c | 645 | |
e6a84468 CW |
646 | if (entry->relocation_count == 0) |
647 | return false; | |
648 | ||
649 | if (!i915_is_ggtt(vma->vm)) | |
650 | return false; | |
651 | ||
652 | /* See also use_cpu_reloc() */ | |
653 | if (HAS_LLC(vma->obj->base.dev)) | |
654 | return false; | |
655 | ||
656 | if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU) | |
657 | return false; | |
658 | ||
659 | return true; | |
660 | } | |
661 | ||
662 | static bool | |
663 | eb_vma_misplaced(struct i915_vma *vma) | |
664 | { | |
665 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
666 | struct drm_i915_gem_object *obj = vma->obj; | |
d23db88c | 667 | |
e6a84468 | 668 | WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && |
d23db88c CW |
669 | !i915_is_ggtt(vma->vm)); |
670 | ||
671 | if (entry->alignment && | |
672 | vma->node.start & (entry->alignment - 1)) | |
673 | return true; | |
674 | ||
506a8e87 CW |
675 | if (entry->flags & EXEC_OBJECT_PINNED && |
676 | vma->node.start != entry->offset) | |
677 | return true; | |
678 | ||
d23db88c CW |
679 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS && |
680 | vma->node.start < BATCH_OFFSET_BIAS) | |
681 | return true; | |
682 | ||
edf4427b CW |
683 | /* avoid costly ping-pong once a batch bo ended up non-mappable */ |
684 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable) | |
685 | return !only_mappable_for_reloc(entry->flags); | |
686 | ||
101b506a MT |
687 | if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 && |
688 | (vma->node.start + vma->node.size - 1) >> 32) | |
689 | return true; | |
690 | ||
d23db88c CW |
691 | return false; |
692 | } | |
693 | ||
54cf91dc | 694 | static int |
a4872ba6 | 695 | i915_gem_execbuffer_reserve(struct intel_engine_cs *ring, |
27173f1f | 696 | struct list_head *vmas, |
b1b38278 | 697 | struct intel_context *ctx, |
ed5982e6 | 698 | bool *need_relocs) |
54cf91dc | 699 | { |
432e58ed | 700 | struct drm_i915_gem_object *obj; |
27173f1f | 701 | struct i915_vma *vma; |
68c8c17f | 702 | struct i915_address_space *vm; |
27173f1f | 703 | struct list_head ordered_vmas; |
506a8e87 | 704 | struct list_head pinned_vmas; |
7788a765 CW |
705 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
706 | int retry; | |
6fe4f140 | 707 | |
227f782e CW |
708 | i915_gem_retire_requests_ring(ring); |
709 | ||
68c8c17f BW |
710 | vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm; |
711 | ||
27173f1f | 712 | INIT_LIST_HEAD(&ordered_vmas); |
506a8e87 | 713 | INIT_LIST_HEAD(&pinned_vmas); |
27173f1f | 714 | while (!list_empty(vmas)) { |
6fe4f140 CW |
715 | struct drm_i915_gem_exec_object2 *entry; |
716 | bool need_fence, need_mappable; | |
717 | ||
27173f1f BW |
718 | vma = list_first_entry(vmas, struct i915_vma, exec_list); |
719 | obj = vma->obj; | |
720 | entry = vma->exec_entry; | |
6fe4f140 | 721 | |
b1b38278 DW |
722 | if (ctx->flags & CONTEXT_NO_ZEROMAP) |
723 | entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
724 | ||
82b6b6d7 CW |
725 | if (!has_fenced_gpu_access) |
726 | entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; | |
6fe4f140 | 727 | need_fence = |
6fe4f140 CW |
728 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
729 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 730 | need_mappable = need_fence || need_reloc_mappable(vma); |
6fe4f140 | 731 | |
506a8e87 CW |
732 | if (entry->flags & EXEC_OBJECT_PINNED) |
733 | list_move_tail(&vma->exec_list, &pinned_vmas); | |
734 | else if (need_mappable) { | |
e6a84468 | 735 | entry->flags |= __EXEC_OBJECT_NEEDS_MAP; |
27173f1f | 736 | list_move(&vma->exec_list, &ordered_vmas); |
e6a84468 | 737 | } else |
27173f1f | 738 | list_move_tail(&vma->exec_list, &ordered_vmas); |
595dad76 | 739 | |
ed5982e6 | 740 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
595dad76 | 741 | obj->base.pending_write_domain = 0; |
6fe4f140 | 742 | } |
27173f1f | 743 | list_splice(&ordered_vmas, vmas); |
506a8e87 | 744 | list_splice(&pinned_vmas, vmas); |
54cf91dc CW |
745 | |
746 | /* Attempt to pin all of the buffers into the GTT. | |
747 | * This is done in 3 phases: | |
748 | * | |
749 | * 1a. Unbind all objects that do not match the GTT constraints for | |
750 | * the execbuffer (fenceable, mappable, alignment etc). | |
751 | * 1b. Increment pin count for already bound objects. | |
752 | * 2. Bind new objects. | |
753 | * 3. Decrement pin count. | |
754 | * | |
7788a765 | 755 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
756 | * room for the earlier objects *unless* we need to defragment. |
757 | */ | |
758 | retry = 0; | |
759 | do { | |
7788a765 | 760 | int ret = 0; |
54cf91dc CW |
761 | |
762 | /* Unbind any ill-fitting objects or pin. */ | |
27173f1f | 763 | list_for_each_entry(vma, vmas, exec_list) { |
27173f1f | 764 | if (!drm_mm_node_allocated(&vma->node)) |
54cf91dc CW |
765 | continue; |
766 | ||
e6a84468 | 767 | if (eb_vma_misplaced(vma)) |
27173f1f | 768 | ret = i915_vma_unbind(vma); |
54cf91dc | 769 | else |
27173f1f | 770 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
432e58ed | 771 | if (ret) |
54cf91dc | 772 | goto err; |
54cf91dc CW |
773 | } |
774 | ||
775 | /* Bind fresh objects */ | |
27173f1f BW |
776 | list_for_each_entry(vma, vmas, exec_list) { |
777 | if (drm_mm_node_allocated(&vma->node)) | |
1690e1eb | 778 | continue; |
54cf91dc | 779 | |
27173f1f | 780 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
7788a765 CW |
781 | if (ret) |
782 | goto err; | |
54cf91dc CW |
783 | } |
784 | ||
a415d355 | 785 | err: |
6c085a72 | 786 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
787 | return ret; |
788 | ||
a415d355 CW |
789 | /* Decrement pin count for bound objects */ |
790 | list_for_each_entry(vma, vmas, exec_list) | |
791 | i915_gem_execbuffer_unreserve_vma(vma); | |
792 | ||
68c8c17f | 793 | ret = i915_gem_evict_vm(vm, true); |
54cf91dc CW |
794 | if (ret) |
795 | return ret; | |
54cf91dc CW |
796 | } while (1); |
797 | } | |
798 | ||
799 | static int | |
800 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
ed5982e6 | 801 | struct drm_i915_gem_execbuffer2 *args, |
54cf91dc | 802 | struct drm_file *file, |
a4872ba6 | 803 | struct intel_engine_cs *ring, |
27173f1f | 804 | struct eb_vmas *eb, |
b1b38278 DW |
805 | struct drm_i915_gem_exec_object2 *exec, |
806 | struct intel_context *ctx) | |
54cf91dc CW |
807 | { |
808 | struct drm_i915_gem_relocation_entry *reloc; | |
27173f1f BW |
809 | struct i915_address_space *vm; |
810 | struct i915_vma *vma; | |
ed5982e6 | 811 | bool need_relocs; |
dd6864a4 | 812 | int *reloc_offset; |
54cf91dc | 813 | int i, total, ret; |
b205ca57 | 814 | unsigned count = args->buffer_count; |
54cf91dc | 815 | |
27173f1f BW |
816 | vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm; |
817 | ||
67731b87 | 818 | /* We may process another execbuffer during the unlock... */ |
27173f1f BW |
819 | while (!list_empty(&eb->vmas)) { |
820 | vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); | |
821 | list_del_init(&vma->exec_list); | |
a415d355 | 822 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 823 | drm_gem_object_unreference(&vma->obj->base); |
67731b87 CW |
824 | } |
825 | ||
54cf91dc CW |
826 | mutex_unlock(&dev->struct_mutex); |
827 | ||
828 | total = 0; | |
829 | for (i = 0; i < count; i++) | |
432e58ed | 830 | total += exec[i].relocation_count; |
54cf91dc | 831 | |
dd6864a4 | 832 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 833 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
834 | if (reloc == NULL || reloc_offset == NULL) { |
835 | drm_free_large(reloc); | |
836 | drm_free_large(reloc_offset); | |
54cf91dc CW |
837 | mutex_lock(&dev->struct_mutex); |
838 | return -ENOMEM; | |
839 | } | |
840 | ||
841 | total = 0; | |
842 | for (i = 0; i < count; i++) { | |
843 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
844 | u64 invalid_offset = (u64)-1; |
845 | int j; | |
54cf91dc | 846 | |
2bb4629a | 847 | user_relocs = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
848 | |
849 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 850 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
851 | ret = -EFAULT; |
852 | mutex_lock(&dev->struct_mutex); | |
853 | goto err; | |
854 | } | |
855 | ||
262b6d36 CW |
856 | /* As we do not update the known relocation offsets after |
857 | * relocating (due to the complexities in lock handling), | |
858 | * we need to mark them as invalid now so that we force the | |
859 | * relocation processing next time. Just in case the target | |
860 | * object is evicted and then rebound into its old | |
861 | * presumed_offset before the next execbuffer - if that | |
862 | * happened we would make the mistake of assuming that the | |
863 | * relocations were valid. | |
864 | */ | |
865 | for (j = 0; j < exec[i].relocation_count; j++) { | |
9aab8bff CW |
866 | if (__copy_to_user(&user_relocs[j].presumed_offset, |
867 | &invalid_offset, | |
868 | sizeof(invalid_offset))) { | |
262b6d36 CW |
869 | ret = -EFAULT; |
870 | mutex_lock(&dev->struct_mutex); | |
871 | goto err; | |
872 | } | |
873 | } | |
874 | ||
dd6864a4 | 875 | reloc_offset[i] = total; |
432e58ed | 876 | total += exec[i].relocation_count; |
54cf91dc CW |
877 | } |
878 | ||
879 | ret = i915_mutex_lock_interruptible(dev); | |
880 | if (ret) { | |
881 | mutex_lock(&dev->struct_mutex); | |
882 | goto err; | |
883 | } | |
884 | ||
67731b87 | 885 | /* reacquire the objects */ |
67731b87 | 886 | eb_reset(eb); |
27173f1f | 887 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
888 | if (ret) |
889 | goto err; | |
67731b87 | 890 | |
ed5982e6 | 891 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
b1b38278 | 892 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs); |
54cf91dc CW |
893 | if (ret) |
894 | goto err; | |
895 | ||
27173f1f BW |
896 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
897 | int offset = vma->exec_entry - exec; | |
898 | ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb, | |
899 | reloc + reloc_offset[offset]); | |
54cf91dc CW |
900 | if (ret) |
901 | goto err; | |
54cf91dc CW |
902 | } |
903 | ||
904 | /* Leave the user relocations as are, this is the painfully slow path, | |
905 | * and we want to avoid the complication of dropping the lock whilst | |
906 | * having buffers reserved in the aperture and so causing spurious | |
907 | * ENOSPC for random operations. | |
908 | */ | |
909 | ||
910 | err: | |
911 | drm_free_large(reloc); | |
dd6864a4 | 912 | drm_free_large(reloc_offset); |
54cf91dc CW |
913 | return ret; |
914 | } | |
915 | ||
54cf91dc | 916 | static int |
535fbe82 | 917 | i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req, |
27173f1f | 918 | struct list_head *vmas) |
54cf91dc | 919 | { |
535fbe82 | 920 | const unsigned other_rings = ~intel_ring_flag(req->ring); |
27173f1f | 921 | struct i915_vma *vma; |
6ac42f41 | 922 | uint32_t flush_domains = 0; |
000433b6 | 923 | bool flush_chipset = false; |
432e58ed | 924 | int ret; |
54cf91dc | 925 | |
27173f1f BW |
926 | list_for_each_entry(vma, vmas, exec_list) { |
927 | struct drm_i915_gem_object *obj = vma->obj; | |
03ade511 CW |
928 | |
929 | if (obj->active & other_rings) { | |
91af127f | 930 | ret = i915_gem_object_sync(obj, req->ring, &req); |
03ade511 CW |
931 | if (ret) |
932 | return ret; | |
933 | } | |
6ac42f41 DV |
934 | |
935 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
000433b6 | 936 | flush_chipset |= i915_gem_clflush_object(obj, false); |
6ac42f41 | 937 | |
6ac42f41 | 938 | flush_domains |= obj->base.write_domain; |
c59a333f CW |
939 | } |
940 | ||
000433b6 | 941 | if (flush_chipset) |
535fbe82 | 942 | i915_gem_chipset_flush(req->ring->dev); |
6ac42f41 DV |
943 | |
944 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
945 | wmb(); | |
946 | ||
09cf7c9a CW |
947 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
948 | * any residual writes from the previous batch. | |
949 | */ | |
2f20055d | 950 | return intel_ring_invalidate_all_caches(req); |
54cf91dc CW |
951 | } |
952 | ||
432e58ed CW |
953 | static bool |
954 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 955 | { |
ed5982e6 DV |
956 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
957 | return false; | |
958 | ||
2f5945bc CW |
959 | /* Kernel clipping was a DRI1 misfeature */ |
960 | if (exec->num_cliprects || exec->cliprects_ptr) | |
961 | return false; | |
962 | ||
963 | if (exec->DR4 == 0xffffffff) { | |
964 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
965 | exec->DR4 = 0; | |
966 | } | |
967 | if (exec->DR1 || exec->DR4) | |
968 | return false; | |
969 | ||
970 | if ((exec->batch_start_offset | exec->batch_len) & 0x7) | |
971 | return false; | |
972 | ||
973 | return true; | |
54cf91dc CW |
974 | } |
975 | ||
976 | static int | |
ad19f10b CW |
977 | validate_exec_list(struct drm_device *dev, |
978 | struct drm_i915_gem_exec_object2 *exec, | |
54cf91dc CW |
979 | int count) |
980 | { | |
b205ca57 DV |
981 | unsigned relocs_total = 0; |
982 | unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry); | |
ad19f10b CW |
983 | unsigned invalid_flags; |
984 | int i; | |
985 | ||
986 | invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; | |
987 | if (USES_FULL_PPGTT(dev)) | |
988 | invalid_flags |= EXEC_OBJECT_NEEDS_GTT; | |
54cf91dc CW |
989 | |
990 | for (i = 0; i < count; i++) { | |
2bb4629a | 991 | char __user *ptr = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
992 | int length; /* limited by fault_in_pages_readable() */ |
993 | ||
ad19f10b | 994 | if (exec[i].flags & invalid_flags) |
ed5982e6 DV |
995 | return -EINVAL; |
996 | ||
55a9785d CW |
997 | if (exec[i].alignment && !is_power_of_2(exec[i].alignment)) |
998 | return -EINVAL; | |
999 | ||
3118a4f6 KC |
1000 | /* First check for malicious input causing overflow in |
1001 | * the worst case where we need to allocate the entire | |
1002 | * relocation tree as a single array. | |
1003 | */ | |
1004 | if (exec[i].relocation_count > relocs_max - relocs_total) | |
54cf91dc | 1005 | return -EINVAL; |
3118a4f6 | 1006 | relocs_total += exec[i].relocation_count; |
54cf91dc CW |
1007 | |
1008 | length = exec[i].relocation_count * | |
1009 | sizeof(struct drm_i915_gem_relocation_entry); | |
30587535 KC |
1010 | /* |
1011 | * We must check that the entire relocation array is safe | |
1012 | * to read, but since we may need to update the presumed | |
1013 | * offsets during execution, check for full write access. | |
1014 | */ | |
54cf91dc CW |
1015 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
1016 | return -EFAULT; | |
1017 | ||
d330a953 | 1018 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
1019 | if (fault_in_multipages_readable(ptr, length)) |
1020 | return -EFAULT; | |
1021 | } | |
54cf91dc CW |
1022 | } |
1023 | ||
1024 | return 0; | |
1025 | } | |
1026 | ||
273497e5 | 1027 | static struct intel_context * |
d299cce7 | 1028 | i915_gem_validate_context(struct drm_device *dev, struct drm_file *file, |
a4872ba6 | 1029 | struct intel_engine_cs *ring, const u32 ctx_id) |
d299cce7 | 1030 | { |
273497e5 | 1031 | struct intel_context *ctx = NULL; |
d299cce7 MK |
1032 | struct i915_ctx_hang_stats *hs; |
1033 | ||
821d66dd | 1034 | if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE) |
7c9c4b8f DV |
1035 | return ERR_PTR(-EINVAL); |
1036 | ||
41bde553 | 1037 | ctx = i915_gem_context_get(file->driver_priv, ctx_id); |
72ad5c45 | 1038 | if (IS_ERR(ctx)) |
41bde553 | 1039 | return ctx; |
d299cce7 | 1040 | |
41bde553 | 1041 | hs = &ctx->hang_stats; |
d299cce7 MK |
1042 | if (hs->banned) { |
1043 | DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id); | |
41bde553 | 1044 | return ERR_PTR(-EIO); |
d299cce7 MK |
1045 | } |
1046 | ||
ec3e9963 | 1047 | if (i915.enable_execlists && !ctx->engine[ring->id].state) { |
e84fe803 | 1048 | int ret = intel_lr_context_deferred_alloc(ctx, ring); |
ec3e9963 OM |
1049 | if (ret) { |
1050 | DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret); | |
1051 | return ERR_PTR(ret); | |
1052 | } | |
1053 | } | |
1054 | ||
41bde553 | 1055 | return ctx; |
d299cce7 MK |
1056 | } |
1057 | ||
ba8b7ccb | 1058 | void |
27173f1f | 1059 | i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
8a8edb59 | 1060 | struct drm_i915_gem_request *req) |
432e58ed | 1061 | { |
8a8edb59 | 1062 | struct intel_engine_cs *ring = i915_gem_request_get_ring(req); |
27173f1f | 1063 | struct i915_vma *vma; |
432e58ed | 1064 | |
27173f1f | 1065 | list_for_each_entry(vma, vmas, exec_list) { |
82b6b6d7 | 1066 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
27173f1f | 1067 | struct drm_i915_gem_object *obj = vma->obj; |
69c2fc89 CW |
1068 | u32 old_read = obj->base.read_domains; |
1069 | u32 old_write = obj->base.write_domain; | |
db53a302 | 1070 | |
51bc1404 | 1071 | obj->dirty = 1; /* be paranoid */ |
432e58ed | 1072 | obj->base.write_domain = obj->base.pending_write_domain; |
ed5982e6 DV |
1073 | if (obj->base.write_domain == 0) |
1074 | obj->base.pending_read_domains |= obj->base.read_domains; | |
1075 | obj->base.read_domains = obj->base.pending_read_domains; | |
432e58ed | 1076 | |
b2af0376 | 1077 | i915_vma_move_to_active(vma, req); |
432e58ed | 1078 | if (obj->base.write_domain) { |
97b2a6a1 | 1079 | i915_gem_request_assign(&obj->last_write_req, req); |
f99d7069 | 1080 | |
77a0d1ca | 1081 | intel_fb_obj_invalidate(obj, ORIGIN_CS); |
c8725f3d CW |
1082 | |
1083 | /* update for the implicit flush after a batch */ | |
1084 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
432e58ed | 1085 | } |
82b6b6d7 | 1086 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
97b2a6a1 | 1087 | i915_gem_request_assign(&obj->last_fenced_req, req); |
82b6b6d7 CW |
1088 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { |
1089 | struct drm_i915_private *dev_priv = to_i915(ring->dev); | |
1090 | list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list, | |
1091 | &dev_priv->mm.fence_list); | |
1092 | } | |
1093 | } | |
432e58ed | 1094 | |
db53a302 | 1095 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
1096 | } |
1097 | } | |
1098 | ||
ba8b7ccb | 1099 | void |
adeca76d | 1100 | i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params) |
54cf91dc | 1101 | { |
cc889e0f | 1102 | /* Unconditionally force add_request to emit a full flush. */ |
adeca76d | 1103 | params->ring->gpu_caches_dirty = true; |
54cf91dc | 1104 | |
432e58ed | 1105 | /* Add a breadcrumb for the completion of the batch buffer */ |
fcfa423c | 1106 | __i915_add_request(params->request, params->batch_obj, true); |
432e58ed | 1107 | } |
54cf91dc | 1108 | |
ae662d31 EA |
1109 | static int |
1110 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
2f20055d | 1111 | struct drm_i915_gem_request *req) |
ae662d31 | 1112 | { |
2f20055d | 1113 | struct intel_engine_cs *ring = req->ring; |
50227e1c | 1114 | struct drm_i915_private *dev_priv = dev->dev_private; |
ae662d31 EA |
1115 | int ret, i; |
1116 | ||
9d662da8 DV |
1117 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) { |
1118 | DRM_DEBUG("sol reset is gen7/rcs only\n"); | |
1119 | return -EINVAL; | |
1120 | } | |
ae662d31 | 1121 | |
5fb9de1a | 1122 | ret = intel_ring_begin(req, 4 * 3); |
ae662d31 EA |
1123 | if (ret) |
1124 | return ret; | |
1125 | ||
1126 | for (i = 0; i < 4; i++) { | |
1127 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 1128 | intel_ring_emit_reg(ring, GEN7_SO_WRITE_OFFSET(i)); |
ae662d31 EA |
1129 | intel_ring_emit(ring, 0); |
1130 | } | |
1131 | ||
1132 | intel_ring_advance(ring); | |
1133 | ||
1134 | return 0; | |
1135 | } | |
1136 | ||
71745376 BV |
1137 | static struct drm_i915_gem_object* |
1138 | i915_gem_execbuffer_parse(struct intel_engine_cs *ring, | |
1139 | struct drm_i915_gem_exec_object2 *shadow_exec_entry, | |
1140 | struct eb_vmas *eb, | |
1141 | struct drm_i915_gem_object *batch_obj, | |
1142 | u32 batch_start_offset, | |
1143 | u32 batch_len, | |
17cabf57 | 1144 | bool is_master) |
71745376 | 1145 | { |
71745376 | 1146 | struct drm_i915_gem_object *shadow_batch_obj; |
17cabf57 | 1147 | struct i915_vma *vma; |
71745376 BV |
1148 | int ret; |
1149 | ||
06fbca71 | 1150 | shadow_batch_obj = i915_gem_batch_pool_get(&ring->batch_pool, |
17cabf57 | 1151 | PAGE_ALIGN(batch_len)); |
71745376 BV |
1152 | if (IS_ERR(shadow_batch_obj)) |
1153 | return shadow_batch_obj; | |
1154 | ||
1155 | ret = i915_parse_cmds(ring, | |
1156 | batch_obj, | |
1157 | shadow_batch_obj, | |
1158 | batch_start_offset, | |
1159 | batch_len, | |
1160 | is_master); | |
17cabf57 CW |
1161 | if (ret) |
1162 | goto err; | |
71745376 | 1163 | |
17cabf57 CW |
1164 | ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0); |
1165 | if (ret) | |
1166 | goto err; | |
71745376 | 1167 | |
de4e783a CW |
1168 | i915_gem_object_unpin_pages(shadow_batch_obj); |
1169 | ||
17cabf57 | 1170 | memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry)); |
71745376 | 1171 | |
17cabf57 CW |
1172 | vma = i915_gem_obj_to_ggtt(shadow_batch_obj); |
1173 | vma->exec_entry = shadow_exec_entry; | |
de4e783a | 1174 | vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN; |
17cabf57 CW |
1175 | drm_gem_object_reference(&shadow_batch_obj->base); |
1176 | list_add_tail(&vma->exec_list, &eb->vmas); | |
71745376 | 1177 | |
17cabf57 CW |
1178 | shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND; |
1179 | ||
1180 | return shadow_batch_obj; | |
71745376 | 1181 | |
17cabf57 | 1182 | err: |
de4e783a | 1183 | i915_gem_object_unpin_pages(shadow_batch_obj); |
17cabf57 CW |
1184 | if (ret == -EACCES) /* unhandled chained batch */ |
1185 | return batch_obj; | |
1186 | else | |
1187 | return ERR_PTR(ret); | |
71745376 | 1188 | } |
5c6c6003 | 1189 | |
a83014d3 | 1190 | int |
5f19e2bf | 1191 | i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, |
a83014d3 | 1192 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 1193 | struct list_head *vmas) |
78382593 | 1194 | { |
5f19e2bf JH |
1195 | struct drm_device *dev = params->dev; |
1196 | struct intel_engine_cs *ring = params->ring; | |
78382593 | 1197 | struct drm_i915_private *dev_priv = dev->dev_private; |
5f19e2bf | 1198 | u64 exec_start, exec_len; |
78382593 OM |
1199 | int instp_mode; |
1200 | u32 instp_mask; | |
2f5945bc | 1201 | int ret; |
78382593 | 1202 | |
535fbe82 | 1203 | ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas); |
78382593 | 1204 | if (ret) |
2f5945bc | 1205 | return ret; |
78382593 | 1206 | |
ba01cc93 | 1207 | ret = i915_switch_context(params->request); |
78382593 | 1208 | if (ret) |
2f5945bc | 1209 | return ret; |
78382593 | 1210 | |
5f19e2bf | 1211 | WARN(params->ctx->ppgtt && params->ctx->ppgtt->pd_dirty_rings & (1<<ring->id), |
9258811c | 1212 | "%s didn't clear reload\n", ring->name); |
563222a7 | 1213 | |
78382593 OM |
1214 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
1215 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
1216 | switch (instp_mode) { | |
1217 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
1218 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
1219 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
1220 | if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { | |
1221 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); | |
2f5945bc | 1222 | return -EINVAL; |
78382593 OM |
1223 | } |
1224 | ||
1225 | if (instp_mode != dev_priv->relative_constants_mode) { | |
1226 | if (INTEL_INFO(dev)->gen < 4) { | |
1227 | DRM_DEBUG("no rel constants on pre-gen4\n"); | |
2f5945bc | 1228 | return -EINVAL; |
78382593 OM |
1229 | } |
1230 | ||
1231 | if (INTEL_INFO(dev)->gen > 5 && | |
1232 | instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
1233 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
2f5945bc | 1234 | return -EINVAL; |
78382593 OM |
1235 | } |
1236 | ||
1237 | /* The HW changed the meaning on this bit on gen6 */ | |
1238 | if (INTEL_INFO(dev)->gen >= 6) | |
1239 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
1240 | } | |
1241 | break; | |
1242 | default: | |
1243 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
2f5945bc | 1244 | return -EINVAL; |
78382593 OM |
1245 | } |
1246 | ||
1247 | if (ring == &dev_priv->ring[RCS] && | |
2f5945bc | 1248 | instp_mode != dev_priv->relative_constants_mode) { |
5fb9de1a | 1249 | ret = intel_ring_begin(params->request, 4); |
78382593 | 1250 | if (ret) |
2f5945bc | 1251 | return ret; |
78382593 OM |
1252 | |
1253 | intel_ring_emit(ring, MI_NOOP); | |
1254 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 1255 | intel_ring_emit_reg(ring, INSTPM); |
78382593 OM |
1256 | intel_ring_emit(ring, instp_mask << 16 | instp_mode); |
1257 | intel_ring_advance(ring); | |
1258 | ||
1259 | dev_priv->relative_constants_mode = instp_mode; | |
1260 | } | |
1261 | ||
1262 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { | |
2f20055d | 1263 | ret = i915_reset_gen7_sol_offsets(dev, params->request); |
78382593 | 1264 | if (ret) |
2f5945bc | 1265 | return ret; |
78382593 OM |
1266 | } |
1267 | ||
5f19e2bf JH |
1268 | exec_len = args->batch_len; |
1269 | exec_start = params->batch_obj_vm_offset + | |
1270 | params->args_batch_start_offset; | |
1271 | ||
2f5945bc CW |
1272 | ret = ring->dispatch_execbuffer(params->request, |
1273 | exec_start, exec_len, | |
1274 | params->dispatch_flags); | |
1275 | if (ret) | |
1276 | return ret; | |
78382593 | 1277 | |
95c24161 | 1278 | trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); |
78382593 | 1279 | |
8a8edb59 | 1280 | i915_gem_execbuffer_move_to_active(vmas, params->request); |
adeca76d | 1281 | i915_gem_execbuffer_retire_commands(params); |
78382593 | 1282 | |
2f5945bc | 1283 | return 0; |
78382593 OM |
1284 | } |
1285 | ||
a8ebba75 ZY |
1286 | /** |
1287 | * Find one BSD ring to dispatch the corresponding BSD command. | |
1288 | * The Ring ID is returned. | |
1289 | */ | |
1290 | static int gen8_dispatch_bsd_ring(struct drm_device *dev, | |
1291 | struct drm_file *file) | |
1292 | { | |
1293 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1294 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1295 | ||
1296 | /* Check whether the file_priv is using one ring */ | |
1297 | if (file_priv->bsd_ring) | |
1298 | return file_priv->bsd_ring->id; | |
1299 | else { | |
1300 | /* If no, use the ping-pong mechanism to select one ring */ | |
1301 | int ring_id; | |
1302 | ||
1303 | mutex_lock(&dev->struct_mutex); | |
bdf1e7e3 | 1304 | if (dev_priv->mm.bsd_ring_dispatch_index == 0) { |
a8ebba75 | 1305 | ring_id = VCS; |
bdf1e7e3 | 1306 | dev_priv->mm.bsd_ring_dispatch_index = 1; |
a8ebba75 ZY |
1307 | } else { |
1308 | ring_id = VCS2; | |
bdf1e7e3 | 1309 | dev_priv->mm.bsd_ring_dispatch_index = 0; |
a8ebba75 ZY |
1310 | } |
1311 | file_priv->bsd_ring = &dev_priv->ring[ring_id]; | |
1312 | mutex_unlock(&dev->struct_mutex); | |
1313 | return ring_id; | |
1314 | } | |
1315 | } | |
1316 | ||
d23db88c CW |
1317 | static struct drm_i915_gem_object * |
1318 | eb_get_batch(struct eb_vmas *eb) | |
1319 | { | |
1320 | struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list); | |
1321 | ||
1322 | /* | |
1323 | * SNA is doing fancy tricks with compressing batch buffers, which leads | |
1324 | * to negative relocation deltas. Usually that works out ok since the | |
1325 | * relocate address is still positive, except when the batch is placed | |
1326 | * very low in the GTT. Ensure this doesn't happen. | |
1327 | * | |
1328 | * Note that actual hangs have only been observed on gen7, but for | |
1329 | * paranoia do it everywhere. | |
1330 | */ | |
506a8e87 CW |
1331 | if ((vma->exec_entry->flags & EXEC_OBJECT_PINNED) == 0) |
1332 | vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
d23db88c CW |
1333 | |
1334 | return vma->obj; | |
1335 | } | |
1336 | ||
54cf91dc CW |
1337 | static int |
1338 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
1339 | struct drm_file *file, | |
1340 | struct drm_i915_gem_execbuffer2 *args, | |
41bde553 | 1341 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc | 1342 | { |
50227e1c | 1343 | struct drm_i915_private *dev_priv = dev->dev_private; |
27173f1f | 1344 | struct eb_vmas *eb; |
54cf91dc | 1345 | struct drm_i915_gem_object *batch_obj; |
78a42377 | 1346 | struct drm_i915_gem_exec_object2 shadow_exec_entry; |
a4872ba6 | 1347 | struct intel_engine_cs *ring; |
273497e5 | 1348 | struct intel_context *ctx; |
41bde553 | 1349 | struct i915_address_space *vm; |
5f19e2bf JH |
1350 | struct i915_execbuffer_params params_master; /* XXX: will be removed later */ |
1351 | struct i915_execbuffer_params *params = ¶ms_master; | |
d299cce7 | 1352 | const u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
8e004efc | 1353 | u32 dispatch_flags; |
78382593 | 1354 | int ret; |
ed5982e6 | 1355 | bool need_relocs; |
54cf91dc | 1356 | |
ed5982e6 | 1357 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 1358 | return -EINVAL; |
432e58ed | 1359 | |
ad19f10b | 1360 | ret = validate_exec_list(dev, exec, args->buffer_count); |
54cf91dc CW |
1361 | if (ret) |
1362 | return ret; | |
1363 | ||
8e004efc | 1364 | dispatch_flags = 0; |
d7d4eedd CW |
1365 | if (args->flags & I915_EXEC_SECURE) { |
1366 | if (!file->is_master || !capable(CAP_SYS_ADMIN)) | |
1367 | return -EPERM; | |
1368 | ||
8e004efc | 1369 | dispatch_flags |= I915_DISPATCH_SECURE; |
d7d4eedd | 1370 | } |
b45305fc | 1371 | if (args->flags & I915_EXEC_IS_PINNED) |
8e004efc | 1372 | dispatch_flags |= I915_DISPATCH_PINNED; |
d7d4eedd | 1373 | |
b1a93306 | 1374 | if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) { |
ff240199 | 1375 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
1376 | (int)(args->flags & I915_EXEC_RING_MASK)); |
1377 | return -EINVAL; | |
1378 | } | |
ca01b12b | 1379 | |
8d360dff ZG |
1380 | if (((args->flags & I915_EXEC_RING_MASK) != I915_EXEC_BSD) && |
1381 | ((args->flags & I915_EXEC_BSD_MASK) != 0)) { | |
1382 | DRM_DEBUG("execbuf with non bsd ring but with invalid " | |
1383 | "bsd dispatch flags: %d\n", (int)(args->flags)); | |
1384 | return -EINVAL; | |
1385 | } | |
1386 | ||
ca01b12b BW |
1387 | if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT) |
1388 | ring = &dev_priv->ring[RCS]; | |
a8ebba75 ZY |
1389 | else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) { |
1390 | if (HAS_BSD2(dev)) { | |
1391 | int ring_id; | |
8d360dff ZG |
1392 | |
1393 | switch (args->flags & I915_EXEC_BSD_MASK) { | |
1394 | case I915_EXEC_BSD_DEFAULT: | |
1395 | ring_id = gen8_dispatch_bsd_ring(dev, file); | |
1396 | ring = &dev_priv->ring[ring_id]; | |
1397 | break; | |
1398 | case I915_EXEC_BSD_RING1: | |
1399 | ring = &dev_priv->ring[VCS]; | |
1400 | break; | |
1401 | case I915_EXEC_BSD_RING2: | |
1402 | ring = &dev_priv->ring[VCS2]; | |
1403 | break; | |
1404 | default: | |
1405 | DRM_DEBUG("execbuf with unknown bsd ring: %d\n", | |
1406 | (int)(args->flags & I915_EXEC_BSD_MASK)); | |
1407 | return -EINVAL; | |
1408 | } | |
a8ebba75 ZY |
1409 | } else |
1410 | ring = &dev_priv->ring[VCS]; | |
1411 | } else | |
ca01b12b BW |
1412 | ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1]; |
1413 | ||
a15817cf CW |
1414 | if (!intel_ring_initialized(ring)) { |
1415 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
1416 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
1417 | return -EINVAL; | |
1418 | } | |
54cf91dc CW |
1419 | |
1420 | if (args->buffer_count < 1) { | |
ff240199 | 1421 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1422 | return -EINVAL; |
1423 | } | |
54cf91dc | 1424 | |
a9ed33ca AJ |
1425 | if (args->flags & I915_EXEC_RESOURCE_STREAMER) { |
1426 | if (!HAS_RESOURCE_STREAMER(dev)) { | |
1427 | DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n"); | |
1428 | return -EINVAL; | |
1429 | } | |
1430 | if (ring->id != RCS) { | |
1431 | DRM_DEBUG("RS is not available on %s\n", | |
1432 | ring->name); | |
1433 | return -EINVAL; | |
1434 | } | |
1435 | ||
1436 | dispatch_flags |= I915_DISPATCH_RS; | |
1437 | } | |
1438 | ||
f65c9168 PZ |
1439 | intel_runtime_pm_get(dev_priv); |
1440 | ||
54cf91dc CW |
1441 | ret = i915_mutex_lock_interruptible(dev); |
1442 | if (ret) | |
1443 | goto pre_mutex_err; | |
1444 | ||
7c9c4b8f | 1445 | ctx = i915_gem_validate_context(dev, file, ring, ctx_id); |
72ad5c45 | 1446 | if (IS_ERR(ctx)) { |
d299cce7 | 1447 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 1448 | ret = PTR_ERR(ctx); |
d299cce7 | 1449 | goto pre_mutex_err; |
935f38d6 | 1450 | } |
41bde553 BW |
1451 | |
1452 | i915_gem_context_reference(ctx); | |
1453 | ||
ae6c4806 DV |
1454 | if (ctx->ppgtt) |
1455 | vm = &ctx->ppgtt->base; | |
1456 | else | |
7e0d96bc | 1457 | vm = &dev_priv->gtt.base; |
d299cce7 | 1458 | |
5f19e2bf JH |
1459 | memset(¶ms_master, 0x00, sizeof(params_master)); |
1460 | ||
17601cbc | 1461 | eb = eb_create(args); |
67731b87 | 1462 | if (eb == NULL) { |
935f38d6 | 1463 | i915_gem_context_unreference(ctx); |
67731b87 CW |
1464 | mutex_unlock(&dev->struct_mutex); |
1465 | ret = -ENOMEM; | |
1466 | goto pre_mutex_err; | |
1467 | } | |
1468 | ||
54cf91dc | 1469 | /* Look up object handles */ |
27173f1f | 1470 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
1471 | if (ret) |
1472 | goto err; | |
54cf91dc | 1473 | |
6fe4f140 | 1474 | /* take note of the batch buffer before we might reorder the lists */ |
d23db88c | 1475 | batch_obj = eb_get_batch(eb); |
6fe4f140 | 1476 | |
54cf91dc | 1477 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
ed5982e6 | 1478 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
b1b38278 | 1479 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs); |
54cf91dc CW |
1480 | if (ret) |
1481 | goto err; | |
1482 | ||
1483 | /* The objects are in their final locations, apply the relocations. */ | |
ed5982e6 | 1484 | if (need_relocs) |
17601cbc | 1485 | ret = i915_gem_execbuffer_relocate(eb); |
54cf91dc CW |
1486 | if (ret) { |
1487 | if (ret == -EFAULT) { | |
ed5982e6 | 1488 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring, |
b1b38278 | 1489 | eb, exec, ctx); |
54cf91dc CW |
1490 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1491 | } | |
1492 | if (ret) | |
1493 | goto err; | |
1494 | } | |
1495 | ||
1496 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1497 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1498 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1499 | ret = -EINVAL; |
1500 | goto err; | |
1501 | } | |
54cf91dc | 1502 | |
5f19e2bf | 1503 | params->args_batch_start_offset = args->batch_start_offset; |
743e78c1 | 1504 | if (i915_needs_cmd_parser(ring) && args->batch_len) { |
c7c7372e RP |
1505 | struct drm_i915_gem_object *parsed_batch_obj; |
1506 | ||
1507 | parsed_batch_obj = i915_gem_execbuffer_parse(ring, | |
71745376 BV |
1508 | &shadow_exec_entry, |
1509 | eb, | |
1510 | batch_obj, | |
1511 | args->batch_start_offset, | |
1512 | args->batch_len, | |
17cabf57 | 1513 | file->is_master); |
c7c7372e RP |
1514 | if (IS_ERR(parsed_batch_obj)) { |
1515 | ret = PTR_ERR(parsed_batch_obj); | |
78a42377 BV |
1516 | goto err; |
1517 | } | |
17cabf57 CW |
1518 | |
1519 | /* | |
c7c7372e RP |
1520 | * parsed_batch_obj == batch_obj means batch not fully parsed: |
1521 | * Accept, but don't promote to secure. | |
17cabf57 | 1522 | */ |
17cabf57 | 1523 | |
c7c7372e RP |
1524 | if (parsed_batch_obj != batch_obj) { |
1525 | /* | |
1526 | * Batch parsed and accepted: | |
1527 | * | |
1528 | * Set the DISPATCH_SECURE bit to remove the NON_SECURE | |
1529 | * bit from MI_BATCH_BUFFER_START commands issued in | |
1530 | * the dispatch_execbuffer implementations. We | |
1531 | * specifically don't want that set on batches the | |
1532 | * command parser has accepted. | |
1533 | */ | |
1534 | dispatch_flags |= I915_DISPATCH_SECURE; | |
5f19e2bf | 1535 | params->args_batch_start_offset = 0; |
c7c7372e RP |
1536 | batch_obj = parsed_batch_obj; |
1537 | } | |
351e3db2 BV |
1538 | } |
1539 | ||
78a42377 BV |
1540 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
1541 | ||
d7d4eedd CW |
1542 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1543 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
28cf5415 | 1544 | * hsw should have this fixed, but bdw mucks it up again. */ |
8e004efc | 1545 | if (dispatch_flags & I915_DISPATCH_SECURE) { |
da51a1e7 DV |
1546 | /* |
1547 | * So on first glance it looks freaky that we pin the batch here | |
1548 | * outside of the reservation loop. But: | |
1549 | * - The batch is already pinned into the relevant ppgtt, so we | |
1550 | * already have the backing storage fully allocated. | |
1551 | * - No other BO uses the global gtt (well contexts, but meh), | |
fd0753cf | 1552 | * so we don't really have issues with multiple objects not |
da51a1e7 DV |
1553 | * fitting due to fragmentation. |
1554 | * So this is actually safe. | |
1555 | */ | |
1556 | ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0); | |
1557 | if (ret) | |
1558 | goto err; | |
d7d4eedd | 1559 | |
5f19e2bf | 1560 | params->batch_obj_vm_offset = i915_gem_obj_ggtt_offset(batch_obj); |
da51a1e7 | 1561 | } else |
5f19e2bf | 1562 | params->batch_obj_vm_offset = i915_gem_obj_offset(batch_obj, vm); |
d7d4eedd | 1563 | |
0c8dac88 | 1564 | /* Allocate a request for this batch buffer nice and early. */ |
6a6ae79a | 1565 | ret = i915_gem_request_alloc(ring, ctx, ¶ms->request); |
0c8dac88 JH |
1566 | if (ret) |
1567 | goto err_batch_unpin; | |
1568 | ||
fcfa423c JH |
1569 | ret = i915_gem_request_add_to_client(params->request, file); |
1570 | if (ret) | |
1571 | goto err_batch_unpin; | |
1572 | ||
5f19e2bf JH |
1573 | /* |
1574 | * Save assorted stuff away to pass through to *_submission(). | |
1575 | * NB: This data should be 'persistent' and not local as it will | |
1576 | * kept around beyond the duration of the IOCTL once the GPU | |
1577 | * scheduler arrives. | |
1578 | */ | |
1579 | params->dev = dev; | |
1580 | params->file = file; | |
1581 | params->ring = ring; | |
1582 | params->dispatch_flags = dispatch_flags; | |
1583 | params->batch_obj = batch_obj; | |
1584 | params->ctx = ctx; | |
1585 | ||
1586 | ret = dev_priv->gt.execbuf_submit(params, args, &eb->vmas); | |
54cf91dc | 1587 | |
0c8dac88 | 1588 | err_batch_unpin: |
da51a1e7 DV |
1589 | /* |
1590 | * FIXME: We crucially rely upon the active tracking for the (ppgtt) | |
1591 | * batch vma for correctness. For less ugly and less fragility this | |
1592 | * needs to be adjusted to also track the ggtt batch vma properly as | |
1593 | * active. | |
1594 | */ | |
8e004efc | 1595 | if (dispatch_flags & I915_DISPATCH_SECURE) |
da51a1e7 | 1596 | i915_gem_object_ggtt_unpin(batch_obj); |
0c8dac88 | 1597 | |
54cf91dc | 1598 | err: |
41bde553 BW |
1599 | /* the request owns the ref now */ |
1600 | i915_gem_context_unreference(ctx); | |
67731b87 | 1601 | eb_destroy(eb); |
54cf91dc | 1602 | |
6a6ae79a JH |
1603 | /* |
1604 | * If the request was created but not successfully submitted then it | |
1605 | * must be freed again. If it was submitted then it is being tracked | |
1606 | * on the active request list and no clean up is required here. | |
1607 | */ | |
bccca494 | 1608 | if (ret && params->request) |
6a6ae79a | 1609 | i915_gem_request_cancel(params->request); |
6a6ae79a | 1610 | |
54cf91dc CW |
1611 | mutex_unlock(&dev->struct_mutex); |
1612 | ||
1613 | pre_mutex_err: | |
f65c9168 PZ |
1614 | /* intel_gpu_busy should also get a ref, so it will free when the device |
1615 | * is really idle. */ | |
1616 | intel_runtime_pm_put(dev_priv); | |
54cf91dc CW |
1617 | return ret; |
1618 | } | |
1619 | ||
1620 | /* | |
1621 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1622 | * list array and passes it to the real function. | |
1623 | */ | |
1624 | int | |
1625 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1626 | struct drm_file *file) | |
1627 | { | |
1628 | struct drm_i915_gem_execbuffer *args = data; | |
1629 | struct drm_i915_gem_execbuffer2 exec2; | |
1630 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1631 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1632 | int ret, i; | |
1633 | ||
54cf91dc | 1634 | if (args->buffer_count < 1) { |
ff240199 | 1635 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1636 | return -EINVAL; |
1637 | } | |
1638 | ||
1639 | /* Copy in the exec list from userland */ | |
1640 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1641 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1642 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1643 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1644 | args->buffer_count); |
1645 | drm_free_large(exec_list); | |
1646 | drm_free_large(exec2_list); | |
1647 | return -ENOMEM; | |
1648 | } | |
1649 | ret = copy_from_user(exec_list, | |
2bb4629a | 1650 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1651 | sizeof(*exec_list) * args->buffer_count); |
1652 | if (ret != 0) { | |
ff240199 | 1653 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1654 | args->buffer_count, ret); |
1655 | drm_free_large(exec_list); | |
1656 | drm_free_large(exec2_list); | |
1657 | return -EFAULT; | |
1658 | } | |
1659 | ||
1660 | for (i = 0; i < args->buffer_count; i++) { | |
1661 | exec2_list[i].handle = exec_list[i].handle; | |
1662 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1663 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1664 | exec2_list[i].alignment = exec_list[i].alignment; | |
1665 | exec2_list[i].offset = exec_list[i].offset; | |
1666 | if (INTEL_INFO(dev)->gen < 4) | |
1667 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1668 | else | |
1669 | exec2_list[i].flags = 0; | |
1670 | } | |
1671 | ||
1672 | exec2.buffers_ptr = args->buffers_ptr; | |
1673 | exec2.buffer_count = args->buffer_count; | |
1674 | exec2.batch_start_offset = args->batch_start_offset; | |
1675 | exec2.batch_len = args->batch_len; | |
1676 | exec2.DR1 = args->DR1; | |
1677 | exec2.DR4 = args->DR4; | |
1678 | exec2.num_cliprects = args->num_cliprects; | |
1679 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1680 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1681 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc | 1682 | |
41bde553 | 1683 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
54cf91dc | 1684 | if (!ret) { |
9aab8bff CW |
1685 | struct drm_i915_gem_exec_object __user *user_exec_list = |
1686 | to_user_ptr(args->buffers_ptr); | |
1687 | ||
54cf91dc | 1688 | /* Copy the new buffer offsets back to the user's exec list. */ |
9aab8bff CW |
1689 | for (i = 0; i < args->buffer_count; i++) { |
1690 | ret = __copy_to_user(&user_exec_list[i].offset, | |
1691 | &exec2_list[i].offset, | |
1692 | sizeof(user_exec_list[i].offset)); | |
1693 | if (ret) { | |
1694 | ret = -EFAULT; | |
1695 | DRM_DEBUG("failed to copy %d exec entries " | |
1696 | "back to user (%d)\n", | |
1697 | args->buffer_count, ret); | |
1698 | break; | |
1699 | } | |
54cf91dc CW |
1700 | } |
1701 | } | |
1702 | ||
1703 | drm_free_large(exec_list); | |
1704 | drm_free_large(exec2_list); | |
1705 | return ret; | |
1706 | } | |
1707 | ||
1708 | int | |
1709 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1710 | struct drm_file *file) | |
1711 | { | |
1712 | struct drm_i915_gem_execbuffer2 *args = data; | |
1713 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1714 | int ret; | |
1715 | ||
ed8cd3b2 XW |
1716 | if (args->buffer_count < 1 || |
1717 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1718 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1719 | return -EINVAL; |
1720 | } | |
1721 | ||
9cb34664 DV |
1722 | if (args->rsvd2 != 0) { |
1723 | DRM_DEBUG("dirty rvsd2 field\n"); | |
1724 | return -EINVAL; | |
1725 | } | |
1726 | ||
8408c282 | 1727 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
419fa72a | 1728 | GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
8408c282 CW |
1729 | if (exec2_list == NULL) |
1730 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1731 | args->buffer_count); | |
54cf91dc | 1732 | if (exec2_list == NULL) { |
ff240199 | 1733 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1734 | args->buffer_count); |
1735 | return -ENOMEM; | |
1736 | } | |
1737 | ret = copy_from_user(exec2_list, | |
2bb4629a | 1738 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1739 | sizeof(*exec2_list) * args->buffer_count); |
1740 | if (ret != 0) { | |
ff240199 | 1741 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1742 | args->buffer_count, ret); |
1743 | drm_free_large(exec2_list); | |
1744 | return -EFAULT; | |
1745 | } | |
1746 | ||
41bde553 | 1747 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
54cf91dc CW |
1748 | if (!ret) { |
1749 | /* Copy the new buffer offsets back to the user's exec list. */ | |
d593d992 | 1750 | struct drm_i915_gem_exec_object2 __user *user_exec_list = |
9aab8bff CW |
1751 | to_user_ptr(args->buffers_ptr); |
1752 | int i; | |
1753 | ||
1754 | for (i = 0; i < args->buffer_count; i++) { | |
1755 | ret = __copy_to_user(&user_exec_list[i].offset, | |
1756 | &exec2_list[i].offset, | |
1757 | sizeof(user_exec_list[i].offset)); | |
1758 | if (ret) { | |
1759 | ret = -EFAULT; | |
1760 | DRM_DEBUG("failed to copy %d exec entries " | |
1761 | "back to user\n", | |
1762 | args->buffer_count); | |
1763 | break; | |
1764 | } | |
54cf91dc CW |
1765 | } |
1766 | } | |
1767 | ||
1768 | drm_free_large(exec2_list); | |
1769 | return ret; | |
1770 | } |