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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
fca52a55 DV |
40 | /** |
41 | * DOC: interrupt handling | |
42 | * | |
43 | * These functions provide the basic support for enabling and disabling the | |
44 | * interrupt handling support. There's a lot more functionality in i915_irq.c | |
45 | * and related files, but that will be described in separate chapters. | |
46 | */ | |
47 | ||
e4ce95aa VS |
48 | static const u32 hpd_ilk[HPD_NUM_PINS] = { |
49 | [HPD_PORT_A] = DE_DP_A_HOTPLUG, | |
50 | }; | |
51 | ||
23bb4cb5 VS |
52 | static const u32 hpd_ivb[HPD_NUM_PINS] = { |
53 | [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB, | |
54 | }; | |
55 | ||
3a3b3c7d VS |
56 | static const u32 hpd_bdw[HPD_NUM_PINS] = { |
57 | [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG, | |
58 | }; | |
59 | ||
7c7e10db | 60 | static const u32 hpd_ibx[HPD_NUM_PINS] = { |
e5868a31 EE |
61 | [HPD_CRT] = SDE_CRT_HOTPLUG, |
62 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
63 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
64 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
65 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
66 | }; | |
67 | ||
7c7e10db | 68 | static const u32 hpd_cpt[HPD_NUM_PINS] = { |
e5868a31 | 69 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, |
73c352a2 | 70 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
71 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
72 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
73 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
74 | }; | |
75 | ||
26951caf | 76 | static const u32 hpd_spt[HPD_NUM_PINS] = { |
74c0b395 | 77 | [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT, |
26951caf XZ |
78 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
79 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
80 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, | |
81 | [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT | |
82 | }; | |
83 | ||
7c7e10db | 84 | static const u32 hpd_mask_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
85 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, |
86 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
87 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
88 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
89 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
90 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
91 | }; | |
92 | ||
7c7e10db | 93 | static const u32 hpd_status_g4x[HPD_NUM_PINS] = { |
e5868a31 EE |
94 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
95 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
96 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
97 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
98 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
99 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
100 | }; | |
101 | ||
4bca26d0 | 102 | static const u32 hpd_status_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
103 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
104 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
105 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
106 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
107 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
108 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
109 | }; | |
110 | ||
e0a20ad7 SS |
111 | /* BXT hpd list */ |
112 | static const u32 hpd_bxt[HPD_NUM_PINS] = { | |
7f3561be | 113 | [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA, |
e0a20ad7 SS |
114 | [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB, |
115 | [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC | |
116 | }; | |
117 | ||
5c502442 | 118 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 119 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
120 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
121 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
122 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
123 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
124 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
125 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
126 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
127 | } while (0) | |
128 | ||
f86f3fb0 | 129 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 130 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 131 | POSTING_READ(type##IMR); \ |
a9d356a6 | 132 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
133 | I915_WRITE(type##IIR, 0xffffffff); \ |
134 | POSTING_READ(type##IIR); \ | |
135 | I915_WRITE(type##IIR, 0xffffffff); \ | |
136 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
137 | } while (0) |
138 | ||
337ba017 PZ |
139 | /* |
140 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
141 | */ | |
b51a2842 VS |
142 | static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, u32 reg) |
143 | { | |
144 | u32 val = I915_READ(reg); | |
145 | ||
146 | if (val == 0) | |
147 | return; | |
148 | ||
149 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", | |
150 | reg, val); | |
151 | I915_WRITE(reg, 0xffffffff); | |
152 | POSTING_READ(reg); | |
153 | I915_WRITE(reg, 0xffffffff); | |
154 | POSTING_READ(reg); | |
155 | } | |
337ba017 | 156 | |
35079899 | 157 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
b51a2842 | 158 | gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \ |
35079899 | 159 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ |
7d1bd539 VS |
160 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
161 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
35079899 PZ |
162 | } while (0) |
163 | ||
164 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
b51a2842 | 165 | gen5_assert_iir_is_zero(dev_priv, type##IIR); \ |
35079899 | 166 | I915_WRITE(type##IER, (ier_val)); \ |
7d1bd539 VS |
167 | I915_WRITE(type##IMR, (imr_val)); \ |
168 | POSTING_READ(type##IMR); \ | |
35079899 PZ |
169 | } while (0) |
170 | ||
c9a9a268 ID |
171 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
172 | ||
0706f17c EE |
173 | /* For display hotplug interrupt */ |
174 | static inline void | |
175 | i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, | |
176 | uint32_t mask, | |
177 | uint32_t bits) | |
178 | { | |
179 | uint32_t val; | |
180 | ||
181 | assert_spin_locked(&dev_priv->irq_lock); | |
182 | WARN_ON(bits & ~mask); | |
183 | ||
184 | val = I915_READ(PORT_HOTPLUG_EN); | |
185 | val &= ~mask; | |
186 | val |= bits; | |
187 | I915_WRITE(PORT_HOTPLUG_EN, val); | |
188 | } | |
189 | ||
190 | /** | |
191 | * i915_hotplug_interrupt_update - update hotplug interrupt enable | |
192 | * @dev_priv: driver private | |
193 | * @mask: bits to update | |
194 | * @bits: bits to enable | |
195 | * NOTE: the HPD enable bits are modified both inside and outside | |
196 | * of an interrupt context. To avoid that read-modify-write cycles | |
197 | * interfer, these bits are protected by a spinlock. Since this | |
198 | * function is usually not called from a context where the lock is | |
199 | * held already, this function acquires the lock itself. A non-locking | |
200 | * version is also available. | |
201 | */ | |
202 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, | |
203 | uint32_t mask, | |
204 | uint32_t bits) | |
205 | { | |
206 | spin_lock_irq(&dev_priv->irq_lock); | |
207 | i915_hotplug_interrupt_update_locked(dev_priv, mask, bits); | |
208 | spin_unlock_irq(&dev_priv->irq_lock); | |
209 | } | |
210 | ||
d9dc34f1 VS |
211 | /** |
212 | * ilk_update_display_irq - update DEIMR | |
213 | * @dev_priv: driver private | |
214 | * @interrupt_mask: mask of interrupt bits to update | |
215 | * @enabled_irq_mask: mask of interrupt bits to enable | |
216 | */ | |
217 | static void ilk_update_display_irq(struct drm_i915_private *dev_priv, | |
218 | uint32_t interrupt_mask, | |
219 | uint32_t enabled_irq_mask) | |
036a4a7d | 220 | { |
d9dc34f1 VS |
221 | uint32_t new_val; |
222 | ||
4bc9d430 DV |
223 | assert_spin_locked(&dev_priv->irq_lock); |
224 | ||
d9dc34f1 VS |
225 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
226 | ||
9df7575f | 227 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 228 | return; |
c67a470b | 229 | |
d9dc34f1 VS |
230 | new_val = dev_priv->irq_mask; |
231 | new_val &= ~interrupt_mask; | |
232 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
233 | ||
234 | if (new_val != dev_priv->irq_mask) { | |
235 | dev_priv->irq_mask = new_val; | |
1ec14ad3 | 236 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
3143a2bf | 237 | POSTING_READ(DEIMR); |
036a4a7d ZW |
238 | } |
239 | } | |
240 | ||
47339cd9 | 241 | void |
d9dc34f1 | 242 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 243 | { |
d9dc34f1 VS |
244 | ilk_update_display_irq(dev_priv, mask, mask); |
245 | } | |
c67a470b | 246 | |
d9dc34f1 VS |
247 | void |
248 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) | |
249 | { | |
250 | ilk_update_display_irq(dev_priv, mask, 0); | |
036a4a7d ZW |
251 | } |
252 | ||
43eaea13 PZ |
253 | /** |
254 | * ilk_update_gt_irq - update GTIMR | |
255 | * @dev_priv: driver private | |
256 | * @interrupt_mask: mask of interrupt bits to update | |
257 | * @enabled_irq_mask: mask of interrupt bits to enable | |
258 | */ | |
259 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
260 | uint32_t interrupt_mask, | |
261 | uint32_t enabled_irq_mask) | |
262 | { | |
263 | assert_spin_locked(&dev_priv->irq_lock); | |
264 | ||
15a17aae DV |
265 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
266 | ||
9df7575f | 267 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 268 | return; |
c67a470b | 269 | |
43eaea13 PZ |
270 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
271 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
272 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
273 | POSTING_READ(GTIMR); | |
274 | } | |
275 | ||
480c8033 | 276 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
277 | { |
278 | ilk_update_gt_irq(dev_priv, mask, mask); | |
279 | } | |
280 | ||
480c8033 | 281 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
282 | { |
283 | ilk_update_gt_irq(dev_priv, mask, 0); | |
284 | } | |
285 | ||
b900b949 ID |
286 | static u32 gen6_pm_iir(struct drm_i915_private *dev_priv) |
287 | { | |
288 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; | |
289 | } | |
290 | ||
a72fbc3a ID |
291 | static u32 gen6_pm_imr(struct drm_i915_private *dev_priv) |
292 | { | |
293 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; | |
294 | } | |
295 | ||
b900b949 ID |
296 | static u32 gen6_pm_ier(struct drm_i915_private *dev_priv) |
297 | { | |
298 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; | |
299 | } | |
300 | ||
edbfdb45 PZ |
301 | /** |
302 | * snb_update_pm_irq - update GEN6_PMIMR | |
303 | * @dev_priv: driver private | |
304 | * @interrupt_mask: mask of interrupt bits to update | |
305 | * @enabled_irq_mask: mask of interrupt bits to enable | |
306 | */ | |
307 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
308 | uint32_t interrupt_mask, | |
309 | uint32_t enabled_irq_mask) | |
310 | { | |
605cd25b | 311 | uint32_t new_val; |
edbfdb45 | 312 | |
15a17aae DV |
313 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
314 | ||
edbfdb45 PZ |
315 | assert_spin_locked(&dev_priv->irq_lock); |
316 | ||
605cd25b | 317 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
318 | new_val &= ~interrupt_mask; |
319 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
320 | ||
605cd25b PZ |
321 | if (new_val != dev_priv->pm_irq_mask) { |
322 | dev_priv->pm_irq_mask = new_val; | |
a72fbc3a ID |
323 | I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask); |
324 | POSTING_READ(gen6_pm_imr(dev_priv)); | |
f52ecbcf | 325 | } |
edbfdb45 PZ |
326 | } |
327 | ||
480c8033 | 328 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
edbfdb45 | 329 | { |
9939fba2 ID |
330 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
331 | return; | |
332 | ||
edbfdb45 PZ |
333 | snb_update_pm_irq(dev_priv, mask, mask); |
334 | } | |
335 | ||
9939fba2 ID |
336 | static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv, |
337 | uint32_t mask) | |
edbfdb45 PZ |
338 | { |
339 | snb_update_pm_irq(dev_priv, mask, 0); | |
340 | } | |
341 | ||
9939fba2 ID |
342 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
343 | { | |
344 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
345 | return; | |
346 | ||
347 | __gen6_disable_pm_irq(dev_priv, mask); | |
348 | } | |
349 | ||
3cc134e3 ID |
350 | void gen6_reset_rps_interrupts(struct drm_device *dev) |
351 | { | |
352 | struct drm_i915_private *dev_priv = dev->dev_private; | |
353 | uint32_t reg = gen6_pm_iir(dev_priv); | |
354 | ||
355 | spin_lock_irq(&dev_priv->irq_lock); | |
356 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
357 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
358 | POSTING_READ(reg); | |
096fad9e | 359 | dev_priv->rps.pm_iir = 0; |
3cc134e3 ID |
360 | spin_unlock_irq(&dev_priv->irq_lock); |
361 | } | |
362 | ||
b900b949 ID |
363 | void gen6_enable_rps_interrupts(struct drm_device *dev) |
364 | { | |
365 | struct drm_i915_private *dev_priv = dev->dev_private; | |
366 | ||
367 | spin_lock_irq(&dev_priv->irq_lock); | |
78e68d36 | 368 | |
b900b949 | 369 | WARN_ON(dev_priv->rps.pm_iir); |
3cc134e3 | 370 | WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); |
d4d70aa5 | 371 | dev_priv->rps.interrupts_enabled = true; |
78e68d36 ID |
372 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) | |
373 | dev_priv->pm_rps_events); | |
b900b949 | 374 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
78e68d36 | 375 | |
b900b949 ID |
376 | spin_unlock_irq(&dev_priv->irq_lock); |
377 | } | |
378 | ||
59d02a1f ID |
379 | u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask) |
380 | { | |
381 | /* | |
f24eeb19 | 382 | * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer |
59d02a1f | 383 | * if GEN6_PM_UP_EI_EXPIRED is masked. |
f24eeb19 ID |
384 | * |
385 | * TODO: verify if this can be reproduced on VLV,CHV. | |
59d02a1f ID |
386 | */ |
387 | if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv)) | |
388 | mask &= ~GEN6_PM_RP_UP_EI_EXPIRED; | |
389 | ||
390 | if (INTEL_INFO(dev_priv)->gen >= 8) | |
391 | mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP; | |
392 | ||
393 | return mask; | |
394 | } | |
395 | ||
b900b949 ID |
396 | void gen6_disable_rps_interrupts(struct drm_device *dev) |
397 | { | |
398 | struct drm_i915_private *dev_priv = dev->dev_private; | |
399 | ||
d4d70aa5 ID |
400 | spin_lock_irq(&dev_priv->irq_lock); |
401 | dev_priv->rps.interrupts_enabled = false; | |
402 | spin_unlock_irq(&dev_priv->irq_lock); | |
403 | ||
404 | cancel_work_sync(&dev_priv->rps.work); | |
405 | ||
9939fba2 ID |
406 | spin_lock_irq(&dev_priv->irq_lock); |
407 | ||
59d02a1f | 408 | I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0)); |
9939fba2 ID |
409 | |
410 | __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
b900b949 ID |
411 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) & |
412 | ~dev_priv->pm_rps_events); | |
58072ccb ID |
413 | |
414 | spin_unlock_irq(&dev_priv->irq_lock); | |
415 | ||
416 | synchronize_irq(dev->irq); | |
b900b949 ID |
417 | } |
418 | ||
3a3b3c7d VS |
419 | /** |
420 | * bdw_update_port_irq - update DE port interrupt | |
421 | * @dev_priv: driver private | |
422 | * @interrupt_mask: mask of interrupt bits to update | |
423 | * @enabled_irq_mask: mask of interrupt bits to enable | |
424 | */ | |
425 | static void bdw_update_port_irq(struct drm_i915_private *dev_priv, | |
426 | uint32_t interrupt_mask, | |
427 | uint32_t enabled_irq_mask) | |
428 | { | |
429 | uint32_t new_val; | |
430 | uint32_t old_val; | |
431 | ||
432 | assert_spin_locked(&dev_priv->irq_lock); | |
433 | ||
434 | WARN_ON(enabled_irq_mask & ~interrupt_mask); | |
435 | ||
436 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
437 | return; | |
438 | ||
439 | old_val = I915_READ(GEN8_DE_PORT_IMR); | |
440 | ||
441 | new_val = old_val; | |
442 | new_val &= ~interrupt_mask; | |
443 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
444 | ||
445 | if (new_val != old_val) { | |
446 | I915_WRITE(GEN8_DE_PORT_IMR, new_val); | |
447 | POSTING_READ(GEN8_DE_PORT_IMR); | |
448 | } | |
449 | } | |
450 | ||
fee884ed DV |
451 | /** |
452 | * ibx_display_interrupt_update - update SDEIMR | |
453 | * @dev_priv: driver private | |
454 | * @interrupt_mask: mask of interrupt bits to update | |
455 | * @enabled_irq_mask: mask of interrupt bits to enable | |
456 | */ | |
47339cd9 DV |
457 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
458 | uint32_t interrupt_mask, | |
459 | uint32_t enabled_irq_mask) | |
fee884ed DV |
460 | { |
461 | uint32_t sdeimr = I915_READ(SDEIMR); | |
462 | sdeimr &= ~interrupt_mask; | |
463 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
464 | ||
15a17aae DV |
465 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
466 | ||
fee884ed DV |
467 | assert_spin_locked(&dev_priv->irq_lock); |
468 | ||
9df7575f | 469 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 470 | return; |
c67a470b | 471 | |
fee884ed DV |
472 | I915_WRITE(SDEIMR, sdeimr); |
473 | POSTING_READ(SDEIMR); | |
474 | } | |
8664281b | 475 | |
b5ea642a | 476 | static void |
755e9019 ID |
477 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
478 | u32 enable_mask, u32 status_mask) | |
7c463586 | 479 | { |
46c06a30 | 480 | u32 reg = PIPESTAT(pipe); |
755e9019 | 481 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 482 | |
b79480ba | 483 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 484 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 485 | |
04feced9 VS |
486 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
487 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
488 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
489 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
490 | return; |
491 | ||
492 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
493 | return; |
494 | ||
91d181dd ID |
495 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
496 | ||
46c06a30 | 497 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 498 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
499 | I915_WRITE(reg, pipestat); |
500 | POSTING_READ(reg); | |
7c463586 KP |
501 | } |
502 | ||
b5ea642a | 503 | static void |
755e9019 ID |
504 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
505 | u32 enable_mask, u32 status_mask) | |
7c463586 | 506 | { |
46c06a30 | 507 | u32 reg = PIPESTAT(pipe); |
755e9019 | 508 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 509 | |
b79480ba | 510 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 511 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 512 | |
04feced9 VS |
513 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
514 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
515 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
516 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
517 | return; |
518 | ||
755e9019 ID |
519 | if ((pipestat & enable_mask) == 0) |
520 | return; | |
521 | ||
91d181dd ID |
522 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
523 | ||
755e9019 | 524 | pipestat &= ~enable_mask; |
46c06a30 VS |
525 | I915_WRITE(reg, pipestat); |
526 | POSTING_READ(reg); | |
7c463586 KP |
527 | } |
528 | ||
10c59c51 ID |
529 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
530 | { | |
531 | u32 enable_mask = status_mask << 16; | |
532 | ||
533 | /* | |
724a6905 VS |
534 | * On pipe A we don't support the PSR interrupt yet, |
535 | * on pipe B and C the same bit MBZ. | |
10c59c51 ID |
536 | */ |
537 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
538 | return 0; | |
724a6905 VS |
539 | /* |
540 | * On pipe B and C we don't support the PSR interrupt yet, on pipe | |
541 | * A the same bit is for perf counters which we don't use either. | |
542 | */ | |
543 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) | |
544 | return 0; | |
10c59c51 ID |
545 | |
546 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
547 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
548 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
549 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
550 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
551 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
552 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
553 | ||
554 | return enable_mask; | |
555 | } | |
556 | ||
755e9019 ID |
557 | void |
558 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
559 | u32 status_mask) | |
560 | { | |
561 | u32 enable_mask; | |
562 | ||
10c59c51 ID |
563 | if (IS_VALLEYVIEW(dev_priv->dev)) |
564 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
565 | status_mask); | |
566 | else | |
567 | enable_mask = status_mask << 16; | |
755e9019 ID |
568 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
569 | } | |
570 | ||
571 | void | |
572 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
573 | u32 status_mask) | |
574 | { | |
575 | u32 enable_mask; | |
576 | ||
10c59c51 ID |
577 | if (IS_VALLEYVIEW(dev_priv->dev)) |
578 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
579 | status_mask); | |
580 | else | |
581 | enable_mask = status_mask << 16; | |
755e9019 ID |
582 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
583 | } | |
584 | ||
01c66889 | 585 | /** |
f49e38dd | 586 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
468f9d29 | 587 | * @dev: drm device |
01c66889 | 588 | */ |
f49e38dd | 589 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 590 | { |
2d1013dd | 591 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 | 592 | |
f49e38dd JN |
593 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
594 | return; | |
595 | ||
13321786 | 596 | spin_lock_irq(&dev_priv->irq_lock); |
01c66889 | 597 | |
755e9019 | 598 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
f898780b | 599 | if (INTEL_INFO(dev)->gen >= 4) |
3b6c42e8 | 600 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 601 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 | 602 | |
13321786 | 603 | spin_unlock_irq(&dev_priv->irq_lock); |
01c66889 ZY |
604 | } |
605 | ||
f75f3746 VS |
606 | /* |
607 | * This timing diagram depicts the video signal in and | |
608 | * around the vertical blanking period. | |
609 | * | |
610 | * Assumptions about the fictitious mode used in this example: | |
611 | * vblank_start >= 3 | |
612 | * vsync_start = vblank_start + 1 | |
613 | * vsync_end = vblank_start + 2 | |
614 | * vtotal = vblank_start + 3 | |
615 | * | |
616 | * start of vblank: | |
617 | * latch double buffered registers | |
618 | * increment frame counter (ctg+) | |
619 | * generate start of vblank interrupt (gen4+) | |
620 | * | | |
621 | * | frame start: | |
622 | * | generate frame start interrupt (aka. vblank interrupt) (gmch) | |
623 | * | may be shifted forward 1-3 extra lines via PIPECONF | |
624 | * | | | |
625 | * | | start of vsync: | |
626 | * | | generate vsync interrupt | |
627 | * | | | | |
628 | * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx | |
629 | * . \hs/ . \hs/ \hs/ \hs/ . \hs/ | |
630 | * ----va---> <-----------------vb--------------------> <--------va------------- | |
631 | * | | <----vs-----> | | |
632 | * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) | |
633 | * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) | |
634 | * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) | |
635 | * | | | | |
636 | * last visible pixel first visible pixel | |
637 | * | increment frame counter (gen3/4) | |
638 | * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) | |
639 | * | |
640 | * x = horizontal active | |
641 | * _ = horizontal blanking | |
642 | * hs = horizontal sync | |
643 | * va = vertical active | |
644 | * vb = vertical blanking | |
645 | * vs = vertical sync | |
646 | * vbs = vblank_start (number) | |
647 | * | |
648 | * Summary: | |
649 | * - most events happen at the start of horizontal sync | |
650 | * - frame start happens at the start of horizontal blank, 1-4 lines | |
651 | * (depending on PIPECONF settings) after the start of vblank | |
652 | * - gen3/4 pixel and frame counter are synchronized with the start | |
653 | * of horizontal active on the first line of vertical active | |
654 | */ | |
655 | ||
4cdb83ec VS |
656 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
657 | { | |
658 | /* Gen2 doesn't have a hardware frame counter */ | |
659 | return 0; | |
660 | } | |
661 | ||
42f52ef8 KP |
662 | /* Called from drm generic code, passed a 'crtc', which |
663 | * we use as a pipe index | |
664 | */ | |
f71d4af4 | 665 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 | 666 | { |
2d1013dd | 667 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a3e67a4 JB |
668 | unsigned long high_frame; |
669 | unsigned long low_frame; | |
0b2a8e09 | 670 | u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; |
f3a5c3f6 DV |
671 | struct intel_crtc *intel_crtc = |
672 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
fc467a22 | 673 | const struct drm_display_mode *mode = &intel_crtc->base.hwmode; |
0a3e67a4 | 674 | |
f3a5c3f6 DV |
675 | htotal = mode->crtc_htotal; |
676 | hsync_start = mode->crtc_hsync_start; | |
677 | vbl_start = mode->crtc_vblank_start; | |
678 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
679 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 | 680 | |
0b2a8e09 VS |
681 | /* Convert to pixel count */ |
682 | vbl_start *= htotal; | |
683 | ||
684 | /* Start of vblank event occurs at start of hsync */ | |
685 | vbl_start -= htotal - hsync_start; | |
686 | ||
9db4a9c7 JB |
687 | high_frame = PIPEFRAME(pipe); |
688 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 689 | |
0a3e67a4 JB |
690 | /* |
691 | * High & low register fields aren't synchronized, so make sure | |
692 | * we get a low value that's stable across two reads of the high | |
693 | * register. | |
694 | */ | |
695 | do { | |
5eddb70b | 696 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 697 | low = I915_READ(low_frame); |
5eddb70b | 698 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
699 | } while (high1 != high2); |
700 | ||
5eddb70b | 701 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 702 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 703 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
704 | |
705 | /* | |
706 | * The frame counter increments at beginning of active. | |
707 | * Cook up a vblank counter by also checking the pixel | |
708 | * counter against vblank start. | |
709 | */ | |
edc08d0a | 710 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
711 | } |
712 | ||
fd8f507c | 713 | static u32 g4x_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 | 714 | { |
2d1013dd | 715 | struct drm_i915_private *dev_priv = dev->dev_private; |
9880b7a5 | 716 | |
649636ef | 717 | return I915_READ(PIPE_FRMCOUNT_G4X(pipe)); |
9880b7a5 JB |
718 | } |
719 | ||
ad3543ed MK |
720 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
721 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
ad3543ed | 722 | |
a225f079 VS |
723 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
724 | { | |
725 | struct drm_device *dev = crtc->base.dev; | |
726 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fc467a22 | 727 | const struct drm_display_mode *mode = &crtc->base.hwmode; |
a225f079 | 728 | enum pipe pipe = crtc->pipe; |
80715b2f | 729 | int position, vtotal; |
a225f079 | 730 | |
80715b2f | 731 | vtotal = mode->crtc_vtotal; |
a225f079 VS |
732 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
733 | vtotal /= 2; | |
734 | ||
735 | if (IS_GEN2(dev)) | |
736 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; | |
737 | else | |
738 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; | |
739 | ||
41b578fb JB |
740 | /* |
741 | * On HSW, the DSL reg (0x70000) appears to return 0 if we | |
742 | * read it just before the start of vblank. So try it again | |
743 | * so we don't accidentally end up spanning a vblank frame | |
744 | * increment, causing the pipe_update_end() code to squak at us. | |
745 | * | |
746 | * The nature of this problem means we can't simply check the ISR | |
747 | * bit and return the vblank start value; nor can we use the scanline | |
748 | * debug register in the transcoder as it appears to have the same | |
749 | * problem. We may need to extend this to include other platforms, | |
750 | * but so far testing only shows the problem on HSW. | |
751 | */ | |
752 | if (IS_HASWELL(dev) && !position) { | |
753 | int i, temp; | |
754 | ||
755 | for (i = 0; i < 100; i++) { | |
756 | udelay(1); | |
757 | temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & | |
758 | DSL_LINEMASK_GEN3; | |
759 | if (temp != position) { | |
760 | position = temp; | |
761 | break; | |
762 | } | |
763 | } | |
764 | } | |
765 | ||
a225f079 | 766 | /* |
80715b2f VS |
767 | * See update_scanline_offset() for the details on the |
768 | * scanline_offset adjustment. | |
a225f079 | 769 | */ |
80715b2f | 770 | return (position + crtc->scanline_offset) % vtotal; |
a225f079 VS |
771 | } |
772 | ||
f71d4af4 | 773 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
abca9e45 | 774 | unsigned int flags, int *vpos, int *hpos, |
3bb403bf VS |
775 | ktime_t *stime, ktime_t *etime, |
776 | const struct drm_display_mode *mode) | |
0af7e4df | 777 | { |
c2baf4b7 VS |
778 | struct drm_i915_private *dev_priv = dev->dev_private; |
779 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
780 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3aa18df8 | 781 | int position; |
78e8fc6b | 782 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df MK |
783 | bool in_vbl = true; |
784 | int ret = 0; | |
ad3543ed | 785 | unsigned long irqflags; |
0af7e4df | 786 | |
fc467a22 | 787 | if (WARN_ON(!mode->crtc_clock)) { |
0af7e4df | 788 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 789 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
790 | return 0; |
791 | } | |
792 | ||
c2baf4b7 | 793 | htotal = mode->crtc_htotal; |
78e8fc6b | 794 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
795 | vtotal = mode->crtc_vtotal; |
796 | vbl_start = mode->crtc_vblank_start; | |
797 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 798 | |
d31faf65 VS |
799 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
800 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
801 | vbl_end /= 2; | |
802 | vtotal /= 2; | |
803 | } | |
804 | ||
c2baf4b7 VS |
805 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
806 | ||
ad3543ed MK |
807 | /* |
808 | * Lock uncore.lock, as we will do multiple timing critical raw | |
809 | * register reads, potentially with preemption disabled, so the | |
810 | * following code must not block on uncore.lock. | |
811 | */ | |
812 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 813 | |
ad3543ed MK |
814 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
815 | ||
816 | /* Get optional system timestamp before query. */ | |
817 | if (stime) | |
818 | *stime = ktime_get(); | |
819 | ||
7c06b08a | 820 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
821 | /* No obvious pixelcount register. Only query vertical |
822 | * scanout position from Display scan line register. | |
823 | */ | |
a225f079 | 824 | position = __intel_get_crtc_scanline(intel_crtc); |
0af7e4df MK |
825 | } else { |
826 | /* Have access to pixelcount since start of frame. | |
827 | * We can split this into vertical and horizontal | |
828 | * scanout position. | |
829 | */ | |
ad3543ed | 830 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 831 | |
3aa18df8 VS |
832 | /* convert to pixel counts */ |
833 | vbl_start *= htotal; | |
834 | vbl_end *= htotal; | |
835 | vtotal *= htotal; | |
78e8fc6b | 836 | |
7e78f1cb VS |
837 | /* |
838 | * In interlaced modes, the pixel counter counts all pixels, | |
839 | * so one field will have htotal more pixels. In order to avoid | |
840 | * the reported position from jumping backwards when the pixel | |
841 | * counter is beyond the length of the shorter field, just | |
842 | * clamp the position the length of the shorter field. This | |
843 | * matches how the scanline counter based position works since | |
844 | * the scanline counter doesn't count the two half lines. | |
845 | */ | |
846 | if (position >= vtotal) | |
847 | position = vtotal - 1; | |
848 | ||
78e8fc6b VS |
849 | /* |
850 | * Start of vblank interrupt is triggered at start of hsync, | |
851 | * just prior to the first active line of vblank. However we | |
852 | * consider lines to start at the leading edge of horizontal | |
853 | * active. So, should we get here before we've crossed into | |
854 | * the horizontal active of the first line in vblank, we would | |
855 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
856 | * always add htotal-hsync_start to the current pixel position. | |
857 | */ | |
858 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
859 | } |
860 | ||
ad3543ed MK |
861 | /* Get optional system timestamp after query. */ |
862 | if (etime) | |
863 | *etime = ktime_get(); | |
864 | ||
865 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
866 | ||
867 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
868 | ||
3aa18df8 VS |
869 | in_vbl = position >= vbl_start && position < vbl_end; |
870 | ||
871 | /* | |
872 | * While in vblank, position will be negative | |
873 | * counting up towards 0 at vbl_end. And outside | |
874 | * vblank, position will be positive counting | |
875 | * up since vbl_end. | |
876 | */ | |
877 | if (position >= vbl_start) | |
878 | position -= vbl_end; | |
879 | else | |
880 | position += vtotal - vbl_end; | |
0af7e4df | 881 | |
7c06b08a | 882 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
883 | *vpos = position; |
884 | *hpos = 0; | |
885 | } else { | |
886 | *vpos = position / htotal; | |
887 | *hpos = position - (*vpos * htotal); | |
888 | } | |
0af7e4df | 889 | |
0af7e4df MK |
890 | /* In vblank? */ |
891 | if (in_vbl) | |
3d3cbd84 | 892 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
0af7e4df MK |
893 | |
894 | return ret; | |
895 | } | |
896 | ||
a225f079 VS |
897 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
898 | { | |
899 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
900 | unsigned long irqflags; | |
901 | int position; | |
902 | ||
903 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
904 | position = __intel_get_crtc_scanline(crtc); | |
905 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
906 | ||
907 | return position; | |
908 | } | |
909 | ||
f71d4af4 | 910 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
911 | int *max_error, |
912 | struct timeval *vblank_time, | |
913 | unsigned flags) | |
914 | { | |
4041b853 | 915 | struct drm_crtc *crtc; |
0af7e4df | 916 | |
7eb552ae | 917 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 918 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
919 | return -EINVAL; |
920 | } | |
921 | ||
922 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
923 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
924 | if (crtc == NULL) { | |
925 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
926 | return -EINVAL; | |
927 | } | |
928 | ||
fc467a22 | 929 | if (!crtc->hwmode.crtc_clock) { |
4041b853 CW |
930 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); |
931 | return -EBUSY; | |
932 | } | |
0af7e4df MK |
933 | |
934 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
935 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
936 | vblank_time, flags, | |
fc467a22 | 937 | &crtc->hwmode); |
0af7e4df MK |
938 | } |
939 | ||
d0ecd7e2 | 940 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 | 941 | { |
2d1013dd | 942 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5b72e89 | 943 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 944 | u8 new_delay; |
9270388e | 945 | |
d0ecd7e2 | 946 | spin_lock(&mchdev_lock); |
f97108d1 | 947 | |
73edd18f DV |
948 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
949 | ||
20e4d407 | 950 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 951 | |
7648fa99 | 952 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
953 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
954 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
955 | max_avg = I915_READ(RCBMAXAVG); |
956 | min_avg = I915_READ(RCBMINAVG); | |
957 | ||
958 | /* Handle RCS change request from hw */ | |
b5b72e89 | 959 | if (busy_up > max_avg) { |
20e4d407 DV |
960 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
961 | new_delay = dev_priv->ips.cur_delay - 1; | |
962 | if (new_delay < dev_priv->ips.max_delay) | |
963 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 964 | } else if (busy_down < min_avg) { |
20e4d407 DV |
965 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
966 | new_delay = dev_priv->ips.cur_delay + 1; | |
967 | if (new_delay > dev_priv->ips.min_delay) | |
968 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
969 | } |
970 | ||
7648fa99 | 971 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 972 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 973 | |
d0ecd7e2 | 974 | spin_unlock(&mchdev_lock); |
9270388e | 975 | |
f97108d1 JB |
976 | return; |
977 | } | |
978 | ||
74cdb337 | 979 | static void notify_ring(struct intel_engine_cs *ring) |
549f7365 | 980 | { |
93b0a4e0 | 981 | if (!intel_ring_initialized(ring)) |
475553de CW |
982 | return; |
983 | ||
bcfcc8ba | 984 | trace_i915_gem_request_notify(ring); |
9862e600 | 985 | |
549f7365 | 986 | wake_up_all(&ring->irq_queue); |
549f7365 CW |
987 | } |
988 | ||
43cf3bf0 CW |
989 | static void vlv_c0_read(struct drm_i915_private *dev_priv, |
990 | struct intel_rps_ei *ei) | |
31685c25 | 991 | { |
43cf3bf0 CW |
992 | ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP); |
993 | ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT); | |
994 | ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT); | |
995 | } | |
31685c25 | 996 | |
43cf3bf0 CW |
997 | static bool vlv_c0_above(struct drm_i915_private *dev_priv, |
998 | const struct intel_rps_ei *old, | |
999 | const struct intel_rps_ei *now, | |
1000 | int threshold) | |
1001 | { | |
1002 | u64 time, c0; | |
7bad74d5 | 1003 | unsigned int mul = 100; |
31685c25 | 1004 | |
43cf3bf0 CW |
1005 | if (old->cz_clock == 0) |
1006 | return false; | |
31685c25 | 1007 | |
7bad74d5 VS |
1008 | if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH) |
1009 | mul <<= 8; | |
1010 | ||
43cf3bf0 | 1011 | time = now->cz_clock - old->cz_clock; |
7bad74d5 | 1012 | time *= threshold * dev_priv->czclk_freq; |
31685c25 | 1013 | |
43cf3bf0 CW |
1014 | /* Workload can be split between render + media, e.g. SwapBuffers |
1015 | * being blitted in X after being rendered in mesa. To account for | |
1016 | * this we need to combine both engines into our activity counter. | |
31685c25 | 1017 | */ |
43cf3bf0 CW |
1018 | c0 = now->render_c0 - old->render_c0; |
1019 | c0 += now->media_c0 - old->media_c0; | |
7bad74d5 | 1020 | c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC; |
31685c25 | 1021 | |
43cf3bf0 | 1022 | return c0 >= time; |
31685c25 D |
1023 | } |
1024 | ||
43cf3bf0 | 1025 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv) |
31685c25 | 1026 | { |
43cf3bf0 CW |
1027 | vlv_c0_read(dev_priv, &dev_priv->rps.down_ei); |
1028 | dev_priv->rps.up_ei = dev_priv->rps.down_ei; | |
43cf3bf0 | 1029 | } |
31685c25 | 1030 | |
43cf3bf0 CW |
1031 | static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) |
1032 | { | |
1033 | struct intel_rps_ei now; | |
1034 | u32 events = 0; | |
31685c25 | 1035 | |
6f4b12f8 | 1036 | if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0) |
43cf3bf0 | 1037 | return 0; |
31685c25 | 1038 | |
43cf3bf0 CW |
1039 | vlv_c0_read(dev_priv, &now); |
1040 | if (now.cz_clock == 0) | |
1041 | return 0; | |
31685c25 | 1042 | |
43cf3bf0 CW |
1043 | if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) { |
1044 | if (!vlv_c0_above(dev_priv, | |
1045 | &dev_priv->rps.down_ei, &now, | |
8fb55197 | 1046 | dev_priv->rps.down_threshold)) |
43cf3bf0 CW |
1047 | events |= GEN6_PM_RP_DOWN_THRESHOLD; |
1048 | dev_priv->rps.down_ei = now; | |
1049 | } | |
31685c25 | 1050 | |
43cf3bf0 CW |
1051 | if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { |
1052 | if (vlv_c0_above(dev_priv, | |
1053 | &dev_priv->rps.up_ei, &now, | |
8fb55197 | 1054 | dev_priv->rps.up_threshold)) |
43cf3bf0 CW |
1055 | events |= GEN6_PM_RP_UP_THRESHOLD; |
1056 | dev_priv->rps.up_ei = now; | |
31685c25 D |
1057 | } |
1058 | ||
43cf3bf0 | 1059 | return events; |
31685c25 D |
1060 | } |
1061 | ||
f5a4c67d CW |
1062 | static bool any_waiters(struct drm_i915_private *dev_priv) |
1063 | { | |
1064 | struct intel_engine_cs *ring; | |
1065 | int i; | |
1066 | ||
1067 | for_each_ring(ring, dev_priv, i) | |
1068 | if (ring->irq_refcount) | |
1069 | return true; | |
1070 | ||
1071 | return false; | |
1072 | } | |
1073 | ||
4912d041 | 1074 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1075 | { |
2d1013dd JN |
1076 | struct drm_i915_private *dev_priv = |
1077 | container_of(work, struct drm_i915_private, rps.work); | |
8d3afd7d CW |
1078 | bool client_boost; |
1079 | int new_delay, adj, min, max; | |
edbfdb45 | 1080 | u32 pm_iir; |
4912d041 | 1081 | |
59cdb63d | 1082 | spin_lock_irq(&dev_priv->irq_lock); |
d4d70aa5 ID |
1083 | /* Speed up work cancelation during disabling rps interrupts. */ |
1084 | if (!dev_priv->rps.interrupts_enabled) { | |
1085 | spin_unlock_irq(&dev_priv->irq_lock); | |
1086 | return; | |
1087 | } | |
c6a828d3 DV |
1088 | pm_iir = dev_priv->rps.pm_iir; |
1089 | dev_priv->rps.pm_iir = 0; | |
a72fbc3a ID |
1090 | /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ |
1091 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
8d3afd7d CW |
1092 | client_boost = dev_priv->rps.client_boost; |
1093 | dev_priv->rps.client_boost = false; | |
59cdb63d | 1094 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1095 | |
60611c13 | 1096 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1097 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
60611c13 | 1098 | |
8d3afd7d | 1099 | if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost) |
3b8d8d91 JB |
1100 | return; |
1101 | ||
4fc688ce | 1102 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1103 | |
43cf3bf0 CW |
1104 | pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); |
1105 | ||
dd75fdc8 | 1106 | adj = dev_priv->rps.last_adj; |
edcf284b | 1107 | new_delay = dev_priv->rps.cur_freq; |
8d3afd7d CW |
1108 | min = dev_priv->rps.min_freq_softlimit; |
1109 | max = dev_priv->rps.max_freq_softlimit; | |
1110 | ||
1111 | if (client_boost) { | |
1112 | new_delay = dev_priv->rps.max_freq_softlimit; | |
1113 | adj = 0; | |
1114 | } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { | |
dd75fdc8 CW |
1115 | if (adj > 0) |
1116 | adj *= 2; | |
edcf284b CW |
1117 | else /* CHV needs even encode values */ |
1118 | adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1; | |
7425034a VS |
1119 | /* |
1120 | * For better performance, jump directly | |
1121 | * to RPe if we're below it. | |
1122 | */ | |
edcf284b | 1123 | if (new_delay < dev_priv->rps.efficient_freq - adj) { |
b39fb297 | 1124 | new_delay = dev_priv->rps.efficient_freq; |
edcf284b CW |
1125 | adj = 0; |
1126 | } | |
f5a4c67d CW |
1127 | } else if (any_waiters(dev_priv)) { |
1128 | adj = 0; | |
dd75fdc8 | 1129 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1130 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1131 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1132 | else |
b39fb297 | 1133 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 CW |
1134 | adj = 0; |
1135 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1136 | if (adj < 0) | |
1137 | adj *= 2; | |
edcf284b CW |
1138 | else /* CHV needs even encode values */ |
1139 | adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1; | |
dd75fdc8 | 1140 | } else { /* unknown event */ |
edcf284b | 1141 | adj = 0; |
dd75fdc8 | 1142 | } |
3b8d8d91 | 1143 | |
edcf284b CW |
1144 | dev_priv->rps.last_adj = adj; |
1145 | ||
79249636 BW |
1146 | /* sysfs frequency interfaces may have snuck in while servicing the |
1147 | * interrupt | |
1148 | */ | |
edcf284b | 1149 | new_delay += adj; |
8d3afd7d | 1150 | new_delay = clamp_t(int, new_delay, min, max); |
27544369 | 1151 | |
ffe02b40 | 1152 | intel_set_rps(dev_priv->dev, new_delay); |
3b8d8d91 | 1153 | |
4fc688ce | 1154 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
1155 | } |
1156 | ||
e3689190 BW |
1157 | |
1158 | /** | |
1159 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1160 | * occurred. | |
1161 | * @work: workqueue struct | |
1162 | * | |
1163 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1164 | * this event, userspace should try to remap the bad rows since statistically | |
1165 | * it is likely the same row is more likely to go bad again. | |
1166 | */ | |
1167 | static void ivybridge_parity_work(struct work_struct *work) | |
1168 | { | |
2d1013dd JN |
1169 | struct drm_i915_private *dev_priv = |
1170 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1171 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1172 | char *parity_event[6]; |
e3689190 | 1173 | uint32_t misccpctl; |
35a85ac6 | 1174 | uint8_t slice = 0; |
e3689190 BW |
1175 | |
1176 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1177 | * In order to prevent a get/put style interface, acquire struct mutex | |
1178 | * any time we access those registers. | |
1179 | */ | |
1180 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1181 | ||
35a85ac6 BW |
1182 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1183 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1184 | goto out; | |
1185 | ||
e3689190 BW |
1186 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1187 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1188 | POSTING_READ(GEN7_MISCCPCTL); | |
1189 | ||
35a85ac6 BW |
1190 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
1191 | u32 reg; | |
e3689190 | 1192 | |
35a85ac6 BW |
1193 | slice--; |
1194 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
1195 | break; | |
e3689190 | 1196 | |
35a85ac6 | 1197 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1198 | |
35a85ac6 | 1199 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 1200 | |
35a85ac6 BW |
1201 | error_status = I915_READ(reg); |
1202 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1203 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1204 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1205 | ||
1206 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1207 | POSTING_READ(reg); | |
1208 | ||
1209 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1210 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1211 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1212 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1213 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1214 | parity_event[5] = NULL; | |
1215 | ||
5bdebb18 | 1216 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1217 | KOBJ_CHANGE, parity_event); |
e3689190 | 1218 | |
35a85ac6 BW |
1219 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1220 | slice, row, bank, subbank); | |
e3689190 | 1221 | |
35a85ac6 BW |
1222 | kfree(parity_event[4]); |
1223 | kfree(parity_event[3]); | |
1224 | kfree(parity_event[2]); | |
1225 | kfree(parity_event[1]); | |
1226 | } | |
e3689190 | 1227 | |
35a85ac6 | 1228 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1229 | |
35a85ac6 BW |
1230 | out: |
1231 | WARN_ON(dev_priv->l3_parity.which_slice); | |
4cb21832 | 1232 | spin_lock_irq(&dev_priv->irq_lock); |
480c8033 | 1233 | gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); |
4cb21832 | 1234 | spin_unlock_irq(&dev_priv->irq_lock); |
35a85ac6 BW |
1235 | |
1236 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1237 | } |
1238 | ||
35a85ac6 | 1239 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 | 1240 | { |
2d1013dd | 1241 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3689190 | 1242 | |
040d2baa | 1243 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1244 | return; |
1245 | ||
d0ecd7e2 | 1246 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1247 | gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1248 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1249 | |
35a85ac6 BW |
1250 | iir &= GT_PARITY_ERROR(dev); |
1251 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1252 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1253 | ||
1254 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1255 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1256 | ||
a4da4fa4 | 1257 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1258 | } |
1259 | ||
f1af8fc1 PZ |
1260 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1261 | struct drm_i915_private *dev_priv, | |
1262 | u32 gt_iir) | |
1263 | { | |
1264 | if (gt_iir & | |
1265 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
74cdb337 | 1266 | notify_ring(&dev_priv->ring[RCS]); |
f1af8fc1 | 1267 | if (gt_iir & ILK_BSD_USER_INTERRUPT) |
74cdb337 | 1268 | notify_ring(&dev_priv->ring[VCS]); |
f1af8fc1 PZ |
1269 | } |
1270 | ||
e7b4c6b1 DV |
1271 | static void snb_gt_irq_handler(struct drm_device *dev, |
1272 | struct drm_i915_private *dev_priv, | |
1273 | u32 gt_iir) | |
1274 | { | |
1275 | ||
cc609d5d BW |
1276 | if (gt_iir & |
1277 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
74cdb337 | 1278 | notify_ring(&dev_priv->ring[RCS]); |
cc609d5d | 1279 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
74cdb337 | 1280 | notify_ring(&dev_priv->ring[VCS]); |
cc609d5d | 1281 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
74cdb337 | 1282 | notify_ring(&dev_priv->ring[BCS]); |
e7b4c6b1 | 1283 | |
cc609d5d BW |
1284 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1285 | GT_BSD_CS_ERROR_INTERRUPT | | |
aaecdf61 DV |
1286 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) |
1287 | DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir); | |
e3689190 | 1288 | |
35a85ac6 BW |
1289 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1290 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1291 | } |
1292 | ||
74cdb337 | 1293 | static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv, |
abd58f01 BW |
1294 | u32 master_ctl) |
1295 | { | |
abd58f01 BW |
1296 | irqreturn_t ret = IRQ_NONE; |
1297 | ||
1298 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
74cdb337 | 1299 | u32 tmp = I915_READ_FW(GEN8_GT_IIR(0)); |
abd58f01 | 1300 | if (tmp) { |
cb0d205e | 1301 | I915_WRITE_FW(GEN8_GT_IIR(0), tmp); |
abd58f01 | 1302 | ret = IRQ_HANDLED; |
e981e7b1 | 1303 | |
74cdb337 CW |
1304 | if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT)) |
1305 | intel_lrc_irq_handler(&dev_priv->ring[RCS]); | |
1306 | if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT)) | |
1307 | notify_ring(&dev_priv->ring[RCS]); | |
1308 | ||
1309 | if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT)) | |
1310 | intel_lrc_irq_handler(&dev_priv->ring[BCS]); | |
1311 | if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT)) | |
1312 | notify_ring(&dev_priv->ring[BCS]); | |
abd58f01 BW |
1313 | } else |
1314 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1315 | } | |
1316 | ||
85f9b5f9 | 1317 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
74cdb337 | 1318 | u32 tmp = I915_READ_FW(GEN8_GT_IIR(1)); |
abd58f01 | 1319 | if (tmp) { |
cb0d205e | 1320 | I915_WRITE_FW(GEN8_GT_IIR(1), tmp); |
abd58f01 | 1321 | ret = IRQ_HANDLED; |
e981e7b1 | 1322 | |
74cdb337 CW |
1323 | if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT)) |
1324 | intel_lrc_irq_handler(&dev_priv->ring[VCS]); | |
1325 | if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT)) | |
1326 | notify_ring(&dev_priv->ring[VCS]); | |
abd58f01 | 1327 | |
74cdb337 CW |
1328 | if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT)) |
1329 | intel_lrc_irq_handler(&dev_priv->ring[VCS2]); | |
1330 | if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT)) | |
1331 | notify_ring(&dev_priv->ring[VCS2]); | |
0961021a | 1332 | } else |
abd58f01 | 1333 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); |
0961021a BW |
1334 | } |
1335 | ||
abd58f01 | 1336 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
74cdb337 | 1337 | u32 tmp = I915_READ_FW(GEN8_GT_IIR(3)); |
abd58f01 | 1338 | if (tmp) { |
74cdb337 | 1339 | I915_WRITE_FW(GEN8_GT_IIR(3), tmp); |
abd58f01 | 1340 | ret = IRQ_HANDLED; |
e981e7b1 | 1341 | |
74cdb337 CW |
1342 | if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT)) |
1343 | intel_lrc_irq_handler(&dev_priv->ring[VECS]); | |
1344 | if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT)) | |
1345 | notify_ring(&dev_priv->ring[VECS]); | |
abd58f01 BW |
1346 | } else |
1347 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1348 | } | |
1349 | ||
0961021a | 1350 | if (master_ctl & GEN8_GT_PM_IRQ) { |
74cdb337 | 1351 | u32 tmp = I915_READ_FW(GEN8_GT_IIR(2)); |
0961021a | 1352 | if (tmp & dev_priv->pm_rps_events) { |
cb0d205e CW |
1353 | I915_WRITE_FW(GEN8_GT_IIR(2), |
1354 | tmp & dev_priv->pm_rps_events); | |
38cc46d7 | 1355 | ret = IRQ_HANDLED; |
c9a9a268 | 1356 | gen6_rps_irq_handler(dev_priv, tmp); |
0961021a BW |
1357 | } else |
1358 | DRM_ERROR("The master control interrupt lied (PM)!\n"); | |
1359 | } | |
1360 | ||
abd58f01 BW |
1361 | return ret; |
1362 | } | |
1363 | ||
63c88d22 ID |
1364 | static bool bxt_port_hotplug_long_detect(enum port port, u32 val) |
1365 | { | |
1366 | switch (port) { | |
1367 | case PORT_A: | |
195baa06 | 1368 | return val & PORTA_HOTPLUG_LONG_DETECT; |
63c88d22 ID |
1369 | case PORT_B: |
1370 | return val & PORTB_HOTPLUG_LONG_DETECT; | |
1371 | case PORT_C: | |
1372 | return val & PORTC_HOTPLUG_LONG_DETECT; | |
63c88d22 ID |
1373 | default: |
1374 | return false; | |
1375 | } | |
1376 | } | |
1377 | ||
6dbf30ce VS |
1378 | static bool spt_port_hotplug2_long_detect(enum port port, u32 val) |
1379 | { | |
1380 | switch (port) { | |
1381 | case PORT_E: | |
1382 | return val & PORTE_HOTPLUG_LONG_DETECT; | |
1383 | default: | |
1384 | return false; | |
1385 | } | |
1386 | } | |
1387 | ||
74c0b395 VS |
1388 | static bool spt_port_hotplug_long_detect(enum port port, u32 val) |
1389 | { | |
1390 | switch (port) { | |
1391 | case PORT_A: | |
1392 | return val & PORTA_HOTPLUG_LONG_DETECT; | |
1393 | case PORT_B: | |
1394 | return val & PORTB_HOTPLUG_LONG_DETECT; | |
1395 | case PORT_C: | |
1396 | return val & PORTC_HOTPLUG_LONG_DETECT; | |
1397 | case PORT_D: | |
1398 | return val & PORTD_HOTPLUG_LONG_DETECT; | |
1399 | default: | |
1400 | return false; | |
1401 | } | |
1402 | } | |
1403 | ||
e4ce95aa VS |
1404 | static bool ilk_port_hotplug_long_detect(enum port port, u32 val) |
1405 | { | |
1406 | switch (port) { | |
1407 | case PORT_A: | |
1408 | return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT; | |
1409 | default: | |
1410 | return false; | |
1411 | } | |
1412 | } | |
1413 | ||
676574df | 1414 | static bool pch_port_hotplug_long_detect(enum port port, u32 val) |
13cf5504 DA |
1415 | { |
1416 | switch (port) { | |
13cf5504 | 1417 | case PORT_B: |
676574df | 1418 | return val & PORTB_HOTPLUG_LONG_DETECT; |
13cf5504 | 1419 | case PORT_C: |
676574df | 1420 | return val & PORTC_HOTPLUG_LONG_DETECT; |
13cf5504 | 1421 | case PORT_D: |
676574df JN |
1422 | return val & PORTD_HOTPLUG_LONG_DETECT; |
1423 | default: | |
1424 | return false; | |
13cf5504 DA |
1425 | } |
1426 | } | |
1427 | ||
676574df | 1428 | static bool i9xx_port_hotplug_long_detect(enum port port, u32 val) |
13cf5504 DA |
1429 | { |
1430 | switch (port) { | |
13cf5504 | 1431 | case PORT_B: |
676574df | 1432 | return val & PORTB_HOTPLUG_INT_LONG_PULSE; |
13cf5504 | 1433 | case PORT_C: |
676574df | 1434 | return val & PORTC_HOTPLUG_INT_LONG_PULSE; |
13cf5504 | 1435 | case PORT_D: |
676574df JN |
1436 | return val & PORTD_HOTPLUG_INT_LONG_PULSE; |
1437 | default: | |
1438 | return false; | |
13cf5504 DA |
1439 | } |
1440 | } | |
1441 | ||
42db67d6 VS |
1442 | /* |
1443 | * Get a bit mask of pins that have triggered, and which ones may be long. | |
1444 | * This can be called multiple times with the same masks to accumulate | |
1445 | * hotplug detection results from several registers. | |
1446 | * | |
1447 | * Note that the caller is expected to zero out the masks initially. | |
1448 | */ | |
fd63e2a9 | 1449 | static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask, |
8c841e57 | 1450 | u32 hotplug_trigger, u32 dig_hotplug_reg, |
fd63e2a9 ID |
1451 | const u32 hpd[HPD_NUM_PINS], |
1452 | bool long_pulse_detect(enum port port, u32 val)) | |
676574df | 1453 | { |
8c841e57 | 1454 | enum port port; |
676574df JN |
1455 | int i; |
1456 | ||
676574df | 1457 | for_each_hpd_pin(i) { |
8c841e57 JN |
1458 | if ((hpd[i] & hotplug_trigger) == 0) |
1459 | continue; | |
676574df | 1460 | |
8c841e57 JN |
1461 | *pin_mask |= BIT(i); |
1462 | ||
cc24fcdc ID |
1463 | if (!intel_hpd_pin_to_port(i, &port)) |
1464 | continue; | |
1465 | ||
fd63e2a9 | 1466 | if (long_pulse_detect(port, dig_hotplug_reg)) |
8c841e57 | 1467 | *long_mask |= BIT(i); |
676574df JN |
1468 | } |
1469 | ||
1470 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n", | |
1471 | hotplug_trigger, dig_hotplug_reg, *pin_mask); | |
1472 | ||
1473 | } | |
1474 | ||
515ac2bb DV |
1475 | static void gmbus_irq_handler(struct drm_device *dev) |
1476 | { | |
2d1013dd | 1477 | struct drm_i915_private *dev_priv = dev->dev_private; |
28c70f16 | 1478 | |
28c70f16 | 1479 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1480 | } |
1481 | ||
ce99c256 DV |
1482 | static void dp_aux_irq_handler(struct drm_device *dev) |
1483 | { | |
2d1013dd | 1484 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ee32fea | 1485 | |
9ee32fea | 1486 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1487 | } |
1488 | ||
8bf1e9f1 | 1489 | #if defined(CONFIG_DEBUG_FS) |
277de95e DV |
1490 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
1491 | uint32_t crc0, uint32_t crc1, | |
1492 | uint32_t crc2, uint32_t crc3, | |
1493 | uint32_t crc4) | |
8bf1e9f1 SH |
1494 | { |
1495 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1496 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1497 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1498 | int head, tail; |
b2c88f5b | 1499 | |
d538bbdf DL |
1500 | spin_lock(&pipe_crc->lock); |
1501 | ||
0c912c79 | 1502 | if (!pipe_crc->entries) { |
d538bbdf | 1503 | spin_unlock(&pipe_crc->lock); |
34273620 | 1504 | DRM_DEBUG_KMS("spurious interrupt\n"); |
0c912c79 DL |
1505 | return; |
1506 | } | |
1507 | ||
d538bbdf DL |
1508 | head = pipe_crc->head; |
1509 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1510 | |
1511 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1512 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1513 | DRM_ERROR("CRC buffer overflowing\n"); |
1514 | return; | |
1515 | } | |
1516 | ||
1517 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1518 | |
8bc5e955 | 1519 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
eba94eb9 DV |
1520 | entry->crc[0] = crc0; |
1521 | entry->crc[1] = crc1; | |
1522 | entry->crc[2] = crc2; | |
1523 | entry->crc[3] = crc3; | |
1524 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1525 | |
1526 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1527 | pipe_crc->head = head; |
1528 | ||
1529 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1530 | |
1531 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1532 | } |
277de95e DV |
1533 | #else |
1534 | static inline void | |
1535 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, | |
1536 | uint32_t crc0, uint32_t crc1, | |
1537 | uint32_t crc2, uint32_t crc3, | |
1538 | uint32_t crc4) {} | |
1539 | #endif | |
1540 | ||
eba94eb9 | 1541 | |
277de95e | 1542 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5a69b89f DV |
1543 | { |
1544 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1545 | ||
277de95e DV |
1546 | display_pipe_crc_irq_handler(dev, pipe, |
1547 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1548 | 0, 0, 0, 0); | |
5a69b89f DV |
1549 | } |
1550 | ||
277de95e | 1551 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
eba94eb9 DV |
1552 | { |
1553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1554 | ||
277de95e DV |
1555 | display_pipe_crc_irq_handler(dev, pipe, |
1556 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1557 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1558 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1559 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1560 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1561 | } |
5b3a856b | 1562 | |
277de95e | 1563 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5b3a856b DV |
1564 | { |
1565 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b5c5ed0 DV |
1566 | uint32_t res1, res2; |
1567 | ||
1568 | if (INTEL_INFO(dev)->gen >= 3) | |
1569 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); | |
1570 | else | |
1571 | res1 = 0; | |
1572 | ||
1573 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
1574 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); | |
1575 | else | |
1576 | res2 = 0; | |
5b3a856b | 1577 | |
277de95e DV |
1578 | display_pipe_crc_irq_handler(dev, pipe, |
1579 | I915_READ(PIPE_CRC_RES_RED(pipe)), | |
1580 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1581 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1582 | res1, res2); | |
5b3a856b | 1583 | } |
8bf1e9f1 | 1584 | |
1403c0d4 PZ |
1585 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1586 | * IMR bits until the work is done. Other interrupts can be processed without | |
1587 | * the work queue. */ | |
1588 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1589 | { |
a6706b45 | 1590 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1591 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1592 | gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
d4d70aa5 ID |
1593 | if (dev_priv->rps.interrupts_enabled) { |
1594 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; | |
1595 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
1596 | } | |
59cdb63d | 1597 | spin_unlock(&dev_priv->irq_lock); |
baf02a1f | 1598 | } |
baf02a1f | 1599 | |
c9a9a268 ID |
1600 | if (INTEL_INFO(dev_priv)->gen >= 8) |
1601 | return; | |
1602 | ||
1403c0d4 PZ |
1603 | if (HAS_VEBOX(dev_priv->dev)) { |
1604 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
74cdb337 | 1605 | notify_ring(&dev_priv->ring[VECS]); |
12638c57 | 1606 | |
aaecdf61 DV |
1607 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) |
1608 | DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); | |
12638c57 | 1609 | } |
baf02a1f BW |
1610 | } |
1611 | ||
8d7849db VS |
1612 | static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) |
1613 | { | |
8d7849db VS |
1614 | if (!drm_handle_vblank(dev, pipe)) |
1615 | return false; | |
1616 | ||
8d7849db VS |
1617 | return true; |
1618 | } | |
1619 | ||
c1874ed7 ID |
1620 | static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) |
1621 | { | |
1622 | struct drm_i915_private *dev_priv = dev->dev_private; | |
91d181dd | 1623 | u32 pipe_stats[I915_MAX_PIPES] = { }; |
c1874ed7 ID |
1624 | int pipe; |
1625 | ||
58ead0d7 | 1626 | spin_lock(&dev_priv->irq_lock); |
055e393f | 1627 | for_each_pipe(dev_priv, pipe) { |
91d181dd | 1628 | int reg; |
bbb5eebf | 1629 | u32 mask, iir_bit = 0; |
91d181dd | 1630 | |
bbb5eebf DV |
1631 | /* |
1632 | * PIPESTAT bits get signalled even when the interrupt is | |
1633 | * disabled with the mask bits, and some of the status bits do | |
1634 | * not generate interrupts at all (like the underrun bit). Hence | |
1635 | * we need to be careful that we only handle what we want to | |
1636 | * handle. | |
1637 | */ | |
0f239f4c DV |
1638 | |
1639 | /* fifo underruns are filterered in the underrun handler. */ | |
1640 | mask = PIPE_FIFO_UNDERRUN_STATUS; | |
bbb5eebf DV |
1641 | |
1642 | switch (pipe) { | |
1643 | case PIPE_A: | |
1644 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1645 | break; | |
1646 | case PIPE_B: | |
1647 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1648 | break; | |
3278f67f VS |
1649 | case PIPE_C: |
1650 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
1651 | break; | |
bbb5eebf DV |
1652 | } |
1653 | if (iir & iir_bit) | |
1654 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1655 | ||
1656 | if (!mask) | |
91d181dd ID |
1657 | continue; |
1658 | ||
1659 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1660 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1661 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1662 | |
1663 | /* | |
1664 | * Clear the PIPE*STAT regs before the IIR | |
1665 | */ | |
91d181dd ID |
1666 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1667 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1668 | I915_WRITE(reg, pipe_stats[pipe]); |
1669 | } | |
58ead0d7 | 1670 | spin_unlock(&dev_priv->irq_lock); |
c1874ed7 | 1671 | |
055e393f | 1672 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
1673 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
1674 | intel_pipe_handle_vblank(dev, pipe)) | |
1675 | intel_check_page_flip(dev, pipe); | |
c1874ed7 | 1676 | |
579a9b0e | 1677 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
c1874ed7 ID |
1678 | intel_prepare_page_flip(dev, pipe); |
1679 | intel_finish_page_flip(dev, pipe); | |
1680 | } | |
1681 | ||
1682 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
1683 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
1684 | ||
1f7247c0 DV |
1685 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
1686 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
c1874ed7 ID |
1687 | } |
1688 | ||
1689 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
1690 | gmbus_irq_handler(dev); | |
1691 | } | |
1692 | ||
16c6c56b VS |
1693 | static void i9xx_hpd_irq_handler(struct drm_device *dev) |
1694 | { | |
1695 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1696 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
42db67d6 | 1697 | u32 pin_mask = 0, long_mask = 0; |
16c6c56b | 1698 | |
0d2e4297 JN |
1699 | if (!hotplug_status) |
1700 | return; | |
16c6c56b | 1701 | |
0d2e4297 JN |
1702 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
1703 | /* | |
1704 | * Make sure hotplug status is cleared before we clear IIR, or else we | |
1705 | * may miss hotplug events. | |
1706 | */ | |
1707 | POSTING_READ(PORT_HOTPLUG_STAT); | |
16c6c56b | 1708 | |
0d2e4297 JN |
1709 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
1710 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; | |
16c6c56b | 1711 | |
58f2cf24 VS |
1712 | if (hotplug_trigger) { |
1713 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
1714 | hotplug_trigger, hpd_status_g4x, | |
1715 | i9xx_port_hotplug_long_detect); | |
1716 | ||
1717 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
1718 | } | |
369712e8 JN |
1719 | |
1720 | if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
1721 | dp_aux_irq_handler(dev); | |
0d2e4297 JN |
1722 | } else { |
1723 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
16c6c56b | 1724 | |
58f2cf24 VS |
1725 | if (hotplug_trigger) { |
1726 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
44cc6c08 | 1727 | hotplug_trigger, hpd_status_i915, |
58f2cf24 | 1728 | i9xx_port_hotplug_long_detect); |
58f2cf24 VS |
1729 | intel_hpd_irq_handler(dev, pin_mask, long_mask); |
1730 | } | |
3ff60f89 | 1731 | } |
16c6c56b VS |
1732 | } |
1733 | ||
ff1f525e | 1734 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe | 1735 | { |
45a83f84 | 1736 | struct drm_device *dev = arg; |
2d1013dd | 1737 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
1738 | u32 iir, gt_iir, pm_iir; |
1739 | irqreturn_t ret = IRQ_NONE; | |
7e231dbe | 1740 | |
2dd2a883 ID |
1741 | if (!intel_irqs_enabled(dev_priv)) |
1742 | return IRQ_NONE; | |
1743 | ||
7e231dbe | 1744 | while (true) { |
3ff60f89 OM |
1745 | /* Find, clear, then process each source of interrupt */ |
1746 | ||
7e231dbe | 1747 | gt_iir = I915_READ(GTIIR); |
3ff60f89 OM |
1748 | if (gt_iir) |
1749 | I915_WRITE(GTIIR, gt_iir); | |
1750 | ||
7e231dbe | 1751 | pm_iir = I915_READ(GEN6_PMIIR); |
3ff60f89 OM |
1752 | if (pm_iir) |
1753 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1754 | ||
1755 | iir = I915_READ(VLV_IIR); | |
1756 | if (iir) { | |
1757 | /* Consume port before clearing IIR or we'll miss events */ | |
1758 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
1759 | i9xx_hpd_irq_handler(dev); | |
1760 | I915_WRITE(VLV_IIR, iir); | |
1761 | } | |
7e231dbe JB |
1762 | |
1763 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1764 | goto out; | |
1765 | ||
1766 | ret = IRQ_HANDLED; | |
1767 | ||
3ff60f89 OM |
1768 | if (gt_iir) |
1769 | snb_gt_irq_handler(dev, dev_priv, gt_iir); | |
60611c13 | 1770 | if (pm_iir) |
d0ecd7e2 | 1771 | gen6_rps_irq_handler(dev_priv, pm_iir); |
3ff60f89 OM |
1772 | /* Call regardless, as some status bits might not be |
1773 | * signalled in iir */ | |
1774 | valleyview_pipestat_irq_handler(dev, iir); | |
7e231dbe JB |
1775 | } |
1776 | ||
1777 | out: | |
1778 | return ret; | |
1779 | } | |
1780 | ||
43f328d7 VS |
1781 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
1782 | { | |
45a83f84 | 1783 | struct drm_device *dev = arg; |
43f328d7 VS |
1784 | struct drm_i915_private *dev_priv = dev->dev_private; |
1785 | u32 master_ctl, iir; | |
1786 | irqreturn_t ret = IRQ_NONE; | |
43f328d7 | 1787 | |
2dd2a883 ID |
1788 | if (!intel_irqs_enabled(dev_priv)) |
1789 | return IRQ_NONE; | |
1790 | ||
8e5fd599 VS |
1791 | for (;;) { |
1792 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; | |
1793 | iir = I915_READ(VLV_IIR); | |
43f328d7 | 1794 | |
8e5fd599 VS |
1795 | if (master_ctl == 0 && iir == 0) |
1796 | break; | |
43f328d7 | 1797 | |
27b6c122 OM |
1798 | ret = IRQ_HANDLED; |
1799 | ||
8e5fd599 | 1800 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
43f328d7 | 1801 | |
27b6c122 | 1802 | /* Find, clear, then process each source of interrupt */ |
43f328d7 | 1803 | |
27b6c122 OM |
1804 | if (iir) { |
1805 | /* Consume port before clearing IIR or we'll miss events */ | |
1806 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
1807 | i9xx_hpd_irq_handler(dev); | |
1808 | I915_WRITE(VLV_IIR, iir); | |
1809 | } | |
43f328d7 | 1810 | |
74cdb337 | 1811 | gen8_gt_irq_handler(dev_priv, master_ctl); |
43f328d7 | 1812 | |
27b6c122 OM |
1813 | /* Call regardless, as some status bits might not be |
1814 | * signalled in iir */ | |
1815 | valleyview_pipestat_irq_handler(dev, iir); | |
43f328d7 | 1816 | |
8e5fd599 VS |
1817 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); |
1818 | POSTING_READ(GEN8_MASTER_IRQ); | |
8e5fd599 | 1819 | } |
3278f67f | 1820 | |
43f328d7 VS |
1821 | return ret; |
1822 | } | |
1823 | ||
40e56410 VS |
1824 | static void ibx_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger, |
1825 | const u32 hpd[HPD_NUM_PINS]) | |
1826 | { | |
1827 | struct drm_i915_private *dev_priv = to_i915(dev); | |
1828 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; | |
1829 | ||
1830 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
1831 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
1832 | ||
1833 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
1834 | dig_hotplug_reg, hpd, | |
1835 | pch_port_hotplug_long_detect); | |
1836 | ||
1837 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
1838 | } | |
1839 | ||
23e81d69 | 1840 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 | 1841 | { |
2d1013dd | 1842 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 1843 | int pipe; |
b543fb04 | 1844 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
13cf5504 | 1845 | |
40e56410 VS |
1846 | if (hotplug_trigger) |
1847 | ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); | |
91d131d2 | 1848 | |
cfc33bf7 VS |
1849 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1850 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1851 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1852 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1853 | port_name(port)); |
1854 | } | |
776ad806 | 1855 | |
ce99c256 DV |
1856 | if (pch_iir & SDE_AUX_MASK) |
1857 | dp_aux_irq_handler(dev); | |
1858 | ||
776ad806 | 1859 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1860 | gmbus_irq_handler(dev); |
776ad806 JB |
1861 | |
1862 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1863 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1864 | ||
1865 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1866 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1867 | ||
1868 | if (pch_iir & SDE_POISON) | |
1869 | DRM_ERROR("PCH poison interrupt\n"); | |
1870 | ||
9db4a9c7 | 1871 | if (pch_iir & SDE_FDI_MASK) |
055e393f | 1872 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
1873 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
1874 | pipe_name(pipe), | |
1875 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1876 | |
1877 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1878 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1879 | ||
1880 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1881 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1882 | ||
776ad806 | 1883 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
1f7247c0 | 1884 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
1885 | |
1886 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1f7247c0 | 1887 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
1888 | } |
1889 | ||
1890 | static void ivb_err_int_handler(struct drm_device *dev) | |
1891 | { | |
1892 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1893 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
5a69b89f | 1894 | enum pipe pipe; |
8664281b | 1895 | |
de032bf4 PZ |
1896 | if (err_int & ERR_INT_POISON) |
1897 | DRM_ERROR("Poison interrupt\n"); | |
1898 | ||
055e393f | 1899 | for_each_pipe(dev_priv, pipe) { |
1f7247c0 DV |
1900 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) |
1901 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
8bf1e9f1 | 1902 | |
5a69b89f DV |
1903 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
1904 | if (IS_IVYBRIDGE(dev)) | |
277de95e | 1905 | ivb_pipe_crc_irq_handler(dev, pipe); |
5a69b89f | 1906 | else |
277de95e | 1907 | hsw_pipe_crc_irq_handler(dev, pipe); |
5a69b89f DV |
1908 | } |
1909 | } | |
8bf1e9f1 | 1910 | |
8664281b PZ |
1911 | I915_WRITE(GEN7_ERR_INT, err_int); |
1912 | } | |
1913 | ||
1914 | static void cpt_serr_int_handler(struct drm_device *dev) | |
1915 | { | |
1916 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1917 | u32 serr_int = I915_READ(SERR_INT); | |
1918 | ||
de032bf4 PZ |
1919 | if (serr_int & SERR_INT_POISON) |
1920 | DRM_ERROR("PCH poison interrupt\n"); | |
1921 | ||
8664281b | 1922 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1f7247c0 | 1923 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
1924 | |
1925 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1f7247c0 | 1926 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
1927 | |
1928 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1f7247c0 | 1929 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); |
8664281b PZ |
1930 | |
1931 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
1932 | } |
1933 | ||
23e81d69 AJ |
1934 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
1935 | { | |
2d1013dd | 1936 | struct drm_i915_private *dev_priv = dev->dev_private; |
23e81d69 | 1937 | int pipe; |
6dbf30ce | 1938 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
13cf5504 | 1939 | |
40e56410 VS |
1940 | if (hotplug_trigger) |
1941 | ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); | |
91d131d2 | 1942 | |
cfc33bf7 VS |
1943 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
1944 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
1945 | SDE_AUDIO_POWER_SHIFT_CPT); | |
1946 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
1947 | port_name(port)); | |
1948 | } | |
23e81d69 AJ |
1949 | |
1950 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 1951 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
1952 | |
1953 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 1954 | gmbus_irq_handler(dev); |
23e81d69 AJ |
1955 | |
1956 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
1957 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
1958 | ||
1959 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
1960 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
1961 | ||
1962 | if (pch_iir & SDE_FDI_MASK_CPT) | |
055e393f | 1963 | for_each_pipe(dev_priv, pipe) |
23e81d69 AJ |
1964 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
1965 | pipe_name(pipe), | |
1966 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
1967 | |
1968 | if (pch_iir & SDE_ERROR_CPT) | |
1969 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
1970 | } |
1971 | ||
6dbf30ce VS |
1972 | static void spt_irq_handler(struct drm_device *dev, u32 pch_iir) |
1973 | { | |
1974 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1975 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & | |
1976 | ~SDE_PORTE_HOTPLUG_SPT; | |
1977 | u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT; | |
1978 | u32 pin_mask = 0, long_mask = 0; | |
1979 | ||
1980 | if (hotplug_trigger) { | |
1981 | u32 dig_hotplug_reg; | |
1982 | ||
1983 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
1984 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
1985 | ||
1986 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
1987 | dig_hotplug_reg, hpd_spt, | |
74c0b395 | 1988 | spt_port_hotplug_long_detect); |
6dbf30ce VS |
1989 | } |
1990 | ||
1991 | if (hotplug2_trigger) { | |
1992 | u32 dig_hotplug_reg; | |
1993 | ||
1994 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2); | |
1995 | I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg); | |
1996 | ||
1997 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger, | |
1998 | dig_hotplug_reg, hpd_spt, | |
1999 | spt_port_hotplug2_long_detect); | |
2000 | } | |
2001 | ||
2002 | if (pin_mask) | |
2003 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
2004 | ||
2005 | if (pch_iir & SDE_GMBUS_CPT) | |
2006 | gmbus_irq_handler(dev); | |
2007 | } | |
2008 | ||
40e56410 VS |
2009 | static void ilk_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger, |
2010 | const u32 hpd[HPD_NUM_PINS]) | |
2011 | { | |
2012 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2013 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; | |
2014 | ||
2015 | dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); | |
2016 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg); | |
2017 | ||
2018 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
2019 | dig_hotplug_reg, hpd, | |
2020 | ilk_port_hotplug_long_detect); | |
2021 | ||
2022 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
2023 | } | |
2024 | ||
c008bc6e PZ |
2025 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2026 | { | |
2027 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40da17c2 | 2028 | enum pipe pipe; |
e4ce95aa VS |
2029 | u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; |
2030 | ||
40e56410 VS |
2031 | if (hotplug_trigger) |
2032 | ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ilk); | |
c008bc6e PZ |
2033 | |
2034 | if (de_iir & DE_AUX_CHANNEL_A) | |
2035 | dp_aux_irq_handler(dev); | |
2036 | ||
2037 | if (de_iir & DE_GSE) | |
2038 | intel_opregion_asle_intr(dev); | |
2039 | ||
c008bc6e PZ |
2040 | if (de_iir & DE_POISON) |
2041 | DRM_ERROR("Poison interrupt\n"); | |
2042 | ||
055e393f | 2043 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2044 | if (de_iir & DE_PIPE_VBLANK(pipe) && |
2045 | intel_pipe_handle_vblank(dev, pipe)) | |
2046 | intel_check_page_flip(dev, pipe); | |
5b3a856b | 2047 | |
40da17c2 | 2048 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1f7247c0 | 2049 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
5b3a856b | 2050 | |
40da17c2 DV |
2051 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
2052 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
c008bc6e | 2053 | |
40da17c2 DV |
2054 | /* plane/pipes map 1:1 on ilk+ */ |
2055 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
2056 | intel_prepare_page_flip(dev, pipe); | |
2057 | intel_finish_page_flip_plane(dev, pipe); | |
2058 | } | |
c008bc6e PZ |
2059 | } |
2060 | ||
2061 | /* check event from PCH */ | |
2062 | if (de_iir & DE_PCH_EVENT) { | |
2063 | u32 pch_iir = I915_READ(SDEIIR); | |
2064 | ||
2065 | if (HAS_PCH_CPT(dev)) | |
2066 | cpt_irq_handler(dev, pch_iir); | |
2067 | else | |
2068 | ibx_irq_handler(dev, pch_iir); | |
2069 | ||
2070 | /* should clear PCH hotplug event before clear CPU irq */ | |
2071 | I915_WRITE(SDEIIR, pch_iir); | |
2072 | } | |
2073 | ||
2074 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
2075 | ironlake_rps_change_irq_handler(dev); | |
2076 | } | |
2077 | ||
9719fb98 PZ |
2078 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2079 | { | |
2080 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 2081 | enum pipe pipe; |
23bb4cb5 VS |
2082 | u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; |
2083 | ||
40e56410 VS |
2084 | if (hotplug_trigger) |
2085 | ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ivb); | |
9719fb98 PZ |
2086 | |
2087 | if (de_iir & DE_ERR_INT_IVB) | |
2088 | ivb_err_int_handler(dev); | |
2089 | ||
2090 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
2091 | dp_aux_irq_handler(dev); | |
2092 | ||
2093 | if (de_iir & DE_GSE_IVB) | |
2094 | intel_opregion_asle_intr(dev); | |
2095 | ||
055e393f | 2096 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2097 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && |
2098 | intel_pipe_handle_vblank(dev, pipe)) | |
2099 | intel_check_page_flip(dev, pipe); | |
40da17c2 DV |
2100 | |
2101 | /* plane/pipes map 1:1 on ilk+ */ | |
07d27e20 DL |
2102 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
2103 | intel_prepare_page_flip(dev, pipe); | |
2104 | intel_finish_page_flip_plane(dev, pipe); | |
9719fb98 PZ |
2105 | } |
2106 | } | |
2107 | ||
2108 | /* check event from PCH */ | |
2109 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
2110 | u32 pch_iir = I915_READ(SDEIIR); | |
2111 | ||
2112 | cpt_irq_handler(dev, pch_iir); | |
2113 | ||
2114 | /* clear PCH hotplug event before clear CPU irq */ | |
2115 | I915_WRITE(SDEIIR, pch_iir); | |
2116 | } | |
2117 | } | |
2118 | ||
72c90f62 OM |
2119 | /* |
2120 | * To handle irqs with the minimum potential races with fresh interrupts, we: | |
2121 | * 1 - Disable Master Interrupt Control. | |
2122 | * 2 - Find the source(s) of the interrupt. | |
2123 | * 3 - Clear the Interrupt Identity bits (IIR). | |
2124 | * 4 - Process the interrupt(s) that had bits set in the IIRs. | |
2125 | * 5 - Re-enable Master Interrupt Control. | |
2126 | */ | |
f1af8fc1 | 2127 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 | 2128 | { |
45a83f84 | 2129 | struct drm_device *dev = arg; |
2d1013dd | 2130 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1af8fc1 | 2131 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 2132 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 2133 | |
2dd2a883 ID |
2134 | if (!intel_irqs_enabled(dev_priv)) |
2135 | return IRQ_NONE; | |
2136 | ||
8664281b PZ |
2137 | /* We get interrupts on unclaimed registers, so check for this before we |
2138 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 2139 | intel_uncore_check_errors(dev); |
8664281b | 2140 | |
b1f14ad0 JB |
2141 | /* disable master interrupt before clearing iir */ |
2142 | de_ier = I915_READ(DEIER); | |
2143 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 2144 | POSTING_READ(DEIER); |
b1f14ad0 | 2145 | |
44498aea PZ |
2146 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
2147 | * interrupts will will be stored on its back queue, and then we'll be | |
2148 | * able to process them after we restore SDEIER (as soon as we restore | |
2149 | * it, we'll get an interrupt if SDEIIR still has something to process | |
2150 | * due to its back queue). */ | |
ab5c608b BW |
2151 | if (!HAS_PCH_NOP(dev)) { |
2152 | sde_ier = I915_READ(SDEIER); | |
2153 | I915_WRITE(SDEIER, 0); | |
2154 | POSTING_READ(SDEIER); | |
2155 | } | |
44498aea | 2156 | |
72c90f62 OM |
2157 | /* Find, clear, then process each source of interrupt */ |
2158 | ||
b1f14ad0 | 2159 | gt_iir = I915_READ(GTIIR); |
0e43406b | 2160 | if (gt_iir) { |
72c90f62 OM |
2161 | I915_WRITE(GTIIR, gt_iir); |
2162 | ret = IRQ_HANDLED; | |
d8fc8a47 | 2163 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 2164 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
2165 | else |
2166 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
b1f14ad0 JB |
2167 | } |
2168 | ||
0e43406b CW |
2169 | de_iir = I915_READ(DEIIR); |
2170 | if (de_iir) { | |
72c90f62 OM |
2171 | I915_WRITE(DEIIR, de_iir); |
2172 | ret = IRQ_HANDLED; | |
f1af8fc1 PZ |
2173 | if (INTEL_INFO(dev)->gen >= 7) |
2174 | ivb_display_irq_handler(dev, de_iir); | |
2175 | else | |
2176 | ilk_display_irq_handler(dev, de_iir); | |
b1f14ad0 JB |
2177 | } |
2178 | ||
f1af8fc1 PZ |
2179 | if (INTEL_INFO(dev)->gen >= 6) { |
2180 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
2181 | if (pm_iir) { | |
f1af8fc1 PZ |
2182 | I915_WRITE(GEN6_PMIIR, pm_iir); |
2183 | ret = IRQ_HANDLED; | |
72c90f62 | 2184 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 | 2185 | } |
0e43406b | 2186 | } |
b1f14ad0 | 2187 | |
b1f14ad0 JB |
2188 | I915_WRITE(DEIER, de_ier); |
2189 | POSTING_READ(DEIER); | |
ab5c608b BW |
2190 | if (!HAS_PCH_NOP(dev)) { |
2191 | I915_WRITE(SDEIER, sde_ier); | |
2192 | POSTING_READ(SDEIER); | |
2193 | } | |
b1f14ad0 JB |
2194 | |
2195 | return ret; | |
2196 | } | |
2197 | ||
40e56410 VS |
2198 | static void bxt_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger, |
2199 | const u32 hpd[HPD_NUM_PINS]) | |
d04a492d | 2200 | { |
cebd87a0 VS |
2201 | struct drm_i915_private *dev_priv = to_i915(dev); |
2202 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; | |
d04a492d | 2203 | |
a52bb15b VS |
2204 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
2205 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
d04a492d | 2206 | |
cebd87a0 | 2207 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, |
40e56410 | 2208 | dig_hotplug_reg, hpd, |
cebd87a0 | 2209 | bxt_port_hotplug_long_detect); |
40e56410 | 2210 | |
676574df | 2211 | intel_hpd_irq_handler(dev, pin_mask, long_mask); |
d04a492d SS |
2212 | } |
2213 | ||
abd58f01 BW |
2214 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
2215 | { | |
2216 | struct drm_device *dev = arg; | |
2217 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2218 | u32 master_ctl; | |
2219 | irqreturn_t ret = IRQ_NONE; | |
2220 | uint32_t tmp = 0; | |
c42664cc | 2221 | enum pipe pipe; |
88e04703 JB |
2222 | u32 aux_mask = GEN8_AUX_CHANNEL_A; |
2223 | ||
2dd2a883 ID |
2224 | if (!intel_irqs_enabled(dev_priv)) |
2225 | return IRQ_NONE; | |
2226 | ||
b4834a50 | 2227 | if (INTEL_INFO(dev_priv)->gen >= 9) |
88e04703 JB |
2228 | aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | |
2229 | GEN9_AUX_CHANNEL_D; | |
abd58f01 | 2230 | |
cb0d205e | 2231 | master_ctl = I915_READ_FW(GEN8_MASTER_IRQ); |
abd58f01 BW |
2232 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; |
2233 | if (!master_ctl) | |
2234 | return IRQ_NONE; | |
2235 | ||
cb0d205e | 2236 | I915_WRITE_FW(GEN8_MASTER_IRQ, 0); |
abd58f01 | 2237 | |
38cc46d7 OM |
2238 | /* Find, clear, then process each source of interrupt */ |
2239 | ||
74cdb337 | 2240 | ret = gen8_gt_irq_handler(dev_priv, master_ctl); |
abd58f01 BW |
2241 | |
2242 | if (master_ctl & GEN8_DE_MISC_IRQ) { | |
2243 | tmp = I915_READ(GEN8_DE_MISC_IIR); | |
abd58f01 BW |
2244 | if (tmp) { |
2245 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); | |
2246 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2247 | if (tmp & GEN8_DE_MISC_GSE) |
2248 | intel_opregion_asle_intr(dev); | |
2249 | else | |
2250 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
abd58f01 | 2251 | } |
38cc46d7 OM |
2252 | else |
2253 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
abd58f01 BW |
2254 | } |
2255 | ||
6d766f02 DV |
2256 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
2257 | tmp = I915_READ(GEN8_DE_PORT_IIR); | |
6d766f02 | 2258 | if (tmp) { |
d04a492d | 2259 | bool found = false; |
cebd87a0 VS |
2260 | u32 hotplug_trigger = 0; |
2261 | ||
2262 | if (IS_BROXTON(dev_priv)) | |
2263 | hotplug_trigger = tmp & BXT_DE_PORT_HOTPLUG_MASK; | |
2264 | else if (IS_BROADWELL(dev_priv)) | |
2265 | hotplug_trigger = tmp & GEN8_PORT_DP_A_HOTPLUG; | |
d04a492d | 2266 | |
6d766f02 DV |
2267 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); |
2268 | ret = IRQ_HANDLED; | |
88e04703 | 2269 | |
d04a492d | 2270 | if (tmp & aux_mask) { |
38cc46d7 | 2271 | dp_aux_irq_handler(dev); |
d04a492d SS |
2272 | found = true; |
2273 | } | |
2274 | ||
40e56410 VS |
2275 | if (hotplug_trigger) { |
2276 | if (IS_BROXTON(dev)) | |
2277 | bxt_hpd_irq_handler(dev, hotplug_trigger, hpd_bxt); | |
2278 | else | |
2279 | ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_bdw); | |
d04a492d SS |
2280 | found = true; |
2281 | } | |
2282 | ||
9e63743e SS |
2283 | if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) { |
2284 | gmbus_irq_handler(dev); | |
2285 | found = true; | |
2286 | } | |
2287 | ||
d04a492d | 2288 | if (!found) |
38cc46d7 | 2289 | DRM_ERROR("Unexpected DE Port interrupt\n"); |
6d766f02 | 2290 | } |
38cc46d7 OM |
2291 | else |
2292 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
6d766f02 DV |
2293 | } |
2294 | ||
055e393f | 2295 | for_each_pipe(dev_priv, pipe) { |
770de83d | 2296 | uint32_t pipe_iir, flip_done = 0, fault_errors = 0; |
abd58f01 | 2297 | |
c42664cc DV |
2298 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2299 | continue; | |
abd58f01 | 2300 | |
c42664cc | 2301 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
c42664cc DV |
2302 | if (pipe_iir) { |
2303 | ret = IRQ_HANDLED; | |
2304 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); | |
770de83d | 2305 | |
d6bbafa1 CW |
2306 | if (pipe_iir & GEN8_PIPE_VBLANK && |
2307 | intel_pipe_handle_vblank(dev, pipe)) | |
2308 | intel_check_page_flip(dev, pipe); | |
38cc46d7 | 2309 | |
b4834a50 | 2310 | if (INTEL_INFO(dev_priv)->gen >= 9) |
770de83d DL |
2311 | flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE; |
2312 | else | |
2313 | flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE; | |
2314 | ||
2315 | if (flip_done) { | |
38cc46d7 OM |
2316 | intel_prepare_page_flip(dev, pipe); |
2317 | intel_finish_page_flip_plane(dev, pipe); | |
2318 | } | |
2319 | ||
2320 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) | |
2321 | hsw_pipe_crc_irq_handler(dev, pipe); | |
2322 | ||
1f7247c0 DV |
2323 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) |
2324 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
2325 | pipe); | |
38cc46d7 | 2326 | |
770de83d | 2327 | |
b4834a50 | 2328 | if (INTEL_INFO(dev_priv)->gen >= 9) |
770de83d DL |
2329 | fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS; |
2330 | else | |
2331 | fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
2332 | ||
2333 | if (fault_errors) | |
38cc46d7 OM |
2334 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", |
2335 | pipe_name(pipe), | |
2336 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); | |
c42664cc | 2337 | } else |
abd58f01 BW |
2338 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
2339 | } | |
2340 | ||
266ea3d9 SS |
2341 | if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) && |
2342 | master_ctl & GEN8_DE_PCH_IRQ) { | |
92d03a80 DV |
2343 | /* |
2344 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2345 | * scheme also closed the SDE interrupt handling race we've seen | |
2346 | * on older pch-split platforms. But this needs testing. | |
2347 | */ | |
2348 | u32 pch_iir = I915_READ(SDEIIR); | |
92d03a80 DV |
2349 | if (pch_iir) { |
2350 | I915_WRITE(SDEIIR, pch_iir); | |
2351 | ret = IRQ_HANDLED; | |
6dbf30ce VS |
2352 | |
2353 | if (HAS_PCH_SPT(dev_priv)) | |
2354 | spt_irq_handler(dev, pch_iir); | |
2355 | else | |
2356 | cpt_irq_handler(dev, pch_iir); | |
38cc46d7 OM |
2357 | } else |
2358 | DRM_ERROR("The master control interrupt lied (SDE)!\n"); | |
2359 | ||
92d03a80 DV |
2360 | } |
2361 | ||
cb0d205e CW |
2362 | I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2363 | POSTING_READ_FW(GEN8_MASTER_IRQ); | |
abd58f01 BW |
2364 | |
2365 | return ret; | |
2366 | } | |
2367 | ||
17e1df07 DV |
2368 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
2369 | bool reset_completed) | |
2370 | { | |
a4872ba6 | 2371 | struct intel_engine_cs *ring; |
17e1df07 DV |
2372 | int i; |
2373 | ||
2374 | /* | |
2375 | * Notify all waiters for GPU completion events that reset state has | |
2376 | * been changed, and that they need to restart their wait after | |
2377 | * checking for potential errors (and bail out to drop locks if there is | |
2378 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2379 | */ | |
2380 | ||
2381 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
2382 | for_each_ring(ring, dev_priv, i) | |
2383 | wake_up_all(&ring->irq_queue); | |
2384 | ||
2385 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2386 | wake_up_all(&dev_priv->pending_flip_queue); | |
2387 | ||
2388 | /* | |
2389 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
2390 | * reset state is cleared. | |
2391 | */ | |
2392 | if (reset_completed) | |
2393 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
2394 | } | |
2395 | ||
8a905236 | 2396 | /** |
b8d24a06 | 2397 | * i915_reset_and_wakeup - do process context error handling work |
468f9d29 | 2398 | * @dev: drm device |
8a905236 JB |
2399 | * |
2400 | * Fire an error uevent so userspace can see that a hang or error | |
2401 | * was detected. | |
2402 | */ | |
b8d24a06 | 2403 | static void i915_reset_and_wakeup(struct drm_device *dev) |
8a905236 | 2404 | { |
b8d24a06 MK |
2405 | struct drm_i915_private *dev_priv = to_i915(dev); |
2406 | struct i915_gpu_error *error = &dev_priv->gpu_error; | |
cce723ed BW |
2407 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2408 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2409 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 2410 | int ret; |
8a905236 | 2411 | |
5bdebb18 | 2412 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2413 | |
7db0ba24 DV |
2414 | /* |
2415 | * Note that there's only one work item which does gpu resets, so we | |
2416 | * need not worry about concurrent gpu resets potentially incrementing | |
2417 | * error->reset_counter twice. We only need to take care of another | |
2418 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
2419 | * quick check for that is good enough: schedule_work ensures the | |
2420 | * correct ordering between hang detection and this work item, and since | |
2421 | * the reset in-progress bit is only ever set by code outside of this | |
2422 | * work we don't need to worry about any other races. | |
2423 | */ | |
2424 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 2425 | DRM_DEBUG_DRIVER("resetting chip\n"); |
5bdebb18 | 2426 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
7db0ba24 | 2427 | reset_event); |
1f83fee0 | 2428 | |
f454c694 ID |
2429 | /* |
2430 | * In most cases it's guaranteed that we get here with an RPM | |
2431 | * reference held, for example because there is a pending GPU | |
2432 | * request that won't finish until the reset is done. This | |
2433 | * isn't the case at least when we get here by doing a | |
2434 | * simulated reset via debugs, so get an RPM reference. | |
2435 | */ | |
2436 | intel_runtime_pm_get(dev_priv); | |
7514747d VS |
2437 | |
2438 | intel_prepare_reset(dev); | |
2439 | ||
17e1df07 DV |
2440 | /* |
2441 | * All state reset _must_ be completed before we update the | |
2442 | * reset counter, for otherwise waiters might miss the reset | |
2443 | * pending state and not properly drop locks, resulting in | |
2444 | * deadlocks with the reset work. | |
2445 | */ | |
f69061be DV |
2446 | ret = i915_reset(dev); |
2447 | ||
7514747d | 2448 | intel_finish_reset(dev); |
17e1df07 | 2449 | |
f454c694 ID |
2450 | intel_runtime_pm_put(dev_priv); |
2451 | ||
f69061be DV |
2452 | if (ret == 0) { |
2453 | /* | |
2454 | * After all the gem state is reset, increment the reset | |
2455 | * counter and wake up everyone waiting for the reset to | |
2456 | * complete. | |
2457 | * | |
2458 | * Since unlock operations are a one-sided barrier only, | |
2459 | * we need to insert a barrier here to order any seqno | |
2460 | * updates before | |
2461 | * the counter increment. | |
2462 | */ | |
4e857c58 | 2463 | smp_mb__before_atomic(); |
f69061be DV |
2464 | atomic_inc(&dev_priv->gpu_error.reset_counter); |
2465 | ||
5bdebb18 | 2466 | kobject_uevent_env(&dev->primary->kdev->kobj, |
f69061be | 2467 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2468 | } else { |
805de8f4 | 2469 | atomic_or(I915_WEDGED, &error->reset_counter); |
f316a42c | 2470 | } |
1f83fee0 | 2471 | |
17e1df07 DV |
2472 | /* |
2473 | * Note: The wake_up also serves as a memory barrier so that | |
2474 | * waiters see the update value of the reset counter atomic_t. | |
2475 | */ | |
2476 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2477 | } |
8a905236 JB |
2478 | } |
2479 | ||
35aed2e6 | 2480 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
2481 | { |
2482 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2483 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2484 | u32 eir = I915_READ(EIR); |
050ee91f | 2485 | int pipe, i; |
8a905236 | 2486 | |
35aed2e6 CW |
2487 | if (!eir) |
2488 | return; | |
8a905236 | 2489 | |
a70491cc | 2490 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2491 | |
bd9854f9 BW |
2492 | i915_get_extra_instdone(dev, instdone); |
2493 | ||
8a905236 JB |
2494 | if (IS_G4X(dev)) { |
2495 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2496 | u32 ipeir = I915_READ(IPEIR_I965); | |
2497 | ||
a70491cc JP |
2498 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2499 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2500 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2501 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2502 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2503 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2504 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2505 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2506 | } |
2507 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2508 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2509 | pr_err("page table error\n"); |
2510 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2511 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2512 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2513 | } |
2514 | } | |
2515 | ||
a6c45cf0 | 2516 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2517 | if (eir & I915_ERROR_PAGE_TABLE) { |
2518 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2519 | pr_err("page table error\n"); |
2520 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2521 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2522 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2523 | } |
2524 | } | |
2525 | ||
2526 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2527 | pr_err("memory refresh error:\n"); |
055e393f | 2528 | for_each_pipe(dev_priv, pipe) |
a70491cc | 2529 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2530 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2531 | /* pipestat has already been acked */ |
2532 | } | |
2533 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2534 | pr_err("instruction error\n"); |
2535 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2536 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2537 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2538 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2539 | u32 ipeir = I915_READ(IPEIR); |
2540 | ||
a70491cc JP |
2541 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2542 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2543 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2544 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2545 | POSTING_READ(IPEIR); |
8a905236 JB |
2546 | } else { |
2547 | u32 ipeir = I915_READ(IPEIR_I965); | |
2548 | ||
a70491cc JP |
2549 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2550 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2551 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2552 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2553 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2554 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2555 | } |
2556 | } | |
2557 | ||
2558 | I915_WRITE(EIR, eir); | |
3143a2bf | 2559 | POSTING_READ(EIR); |
8a905236 JB |
2560 | eir = I915_READ(EIR); |
2561 | if (eir) { | |
2562 | /* | |
2563 | * some errors might have become stuck, | |
2564 | * mask them. | |
2565 | */ | |
2566 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2567 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2568 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2569 | } | |
35aed2e6 CW |
2570 | } |
2571 | ||
2572 | /** | |
b8d24a06 | 2573 | * i915_handle_error - handle a gpu error |
35aed2e6 CW |
2574 | * @dev: drm device |
2575 | * | |
aafd8581 | 2576 | * Do some basic checking of register state at error time and |
35aed2e6 CW |
2577 | * dump it to the syslog. Also call i915_capture_error_state() to make |
2578 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2579 | * so userspace knows something bad happened (should trigger collection | |
2580 | * of a ring dump etc.). | |
2581 | */ | |
58174462 MK |
2582 | void i915_handle_error(struct drm_device *dev, bool wedged, |
2583 | const char *fmt, ...) | |
35aed2e6 CW |
2584 | { |
2585 | struct drm_i915_private *dev_priv = dev->dev_private; | |
58174462 MK |
2586 | va_list args; |
2587 | char error_msg[80]; | |
35aed2e6 | 2588 | |
58174462 MK |
2589 | va_start(args, fmt); |
2590 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2591 | va_end(args); | |
2592 | ||
2593 | i915_capture_error_state(dev, wedged, error_msg); | |
35aed2e6 | 2594 | i915_report_and_clear_eir(dev); |
8a905236 | 2595 | |
ba1234d1 | 2596 | if (wedged) { |
805de8f4 | 2597 | atomic_or(I915_RESET_IN_PROGRESS_FLAG, |
f69061be | 2598 | &dev_priv->gpu_error.reset_counter); |
ba1234d1 | 2599 | |
11ed50ec | 2600 | /* |
b8d24a06 MK |
2601 | * Wakeup waiting processes so that the reset function |
2602 | * i915_reset_and_wakeup doesn't deadlock trying to grab | |
2603 | * various locks. By bumping the reset counter first, the woken | |
17e1df07 DV |
2604 | * processes will see a reset in progress and back off, |
2605 | * releasing their locks and then wait for the reset completion. | |
2606 | * We must do this for _all_ gpu waiters that might hold locks | |
2607 | * that the reset work needs to acquire. | |
2608 | * | |
2609 | * Note: The wake_up serves as the required memory barrier to | |
2610 | * ensure that the waiters see the updated value of the reset | |
2611 | * counter atomic_t. | |
11ed50ec | 2612 | */ |
17e1df07 | 2613 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2614 | } |
2615 | ||
b8d24a06 | 2616 | i915_reset_and_wakeup(dev); |
8a905236 JB |
2617 | } |
2618 | ||
42f52ef8 KP |
2619 | /* Called from drm generic code, passed 'crtc' which |
2620 | * we use as a pipe index | |
2621 | */ | |
f71d4af4 | 2622 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2623 | { |
2d1013dd | 2624 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2625 | unsigned long irqflags; |
71e0ffa5 | 2626 | |
1ec14ad3 | 2627 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2628 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 | 2629 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2630 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
e9d21d7f | 2631 | else |
7c463586 | 2632 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2633 | PIPE_VBLANK_INTERRUPT_STATUS); |
1ec14ad3 | 2634 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2635 | |
0a3e67a4 JB |
2636 | return 0; |
2637 | } | |
2638 | ||
f71d4af4 | 2639 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2640 | { |
2d1013dd | 2641 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2642 | unsigned long irqflags; |
b518421f | 2643 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2644 | DE_PIPE_VBLANK(pipe); |
f796cf8f | 2645 | |
f796cf8f | 2646 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
b518421f | 2647 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2648 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2649 | ||
2650 | return 0; | |
2651 | } | |
2652 | ||
7e231dbe JB |
2653 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
2654 | { | |
2d1013dd | 2655 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2656 | unsigned long irqflags; |
7e231dbe | 2657 | |
7e231dbe | 2658 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
31acc7f5 | 2659 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2660 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2661 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2662 | ||
2663 | return 0; | |
2664 | } | |
2665 | ||
abd58f01 BW |
2666 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
2667 | { | |
2668 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2669 | unsigned long irqflags; | |
abd58f01 | 2670 | |
abd58f01 | 2671 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
7167d7c6 DV |
2672 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
2673 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2674 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2675 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2676 | return 0; | |
2677 | } | |
2678 | ||
42f52ef8 KP |
2679 | /* Called from drm generic code, passed 'crtc' which |
2680 | * we use as a pipe index | |
2681 | */ | |
f71d4af4 | 2682 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2683 | { |
2d1013dd | 2684 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2685 | unsigned long irqflags; |
0a3e67a4 | 2686 | |
1ec14ad3 | 2687 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2688 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 ID |
2689 | PIPE_VBLANK_INTERRUPT_STATUS | |
2690 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
f796cf8f JB |
2691 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2692 | } | |
2693 | ||
f71d4af4 | 2694 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2695 | { |
2d1013dd | 2696 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2697 | unsigned long irqflags; |
b518421f | 2698 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2699 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2700 | |
2701 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2702 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2703 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2704 | } | |
2705 | ||
7e231dbe JB |
2706 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
2707 | { | |
2d1013dd | 2708 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2709 | unsigned long irqflags; |
7e231dbe JB |
2710 | |
2711 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2712 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 | 2713 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2714 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2715 | } | |
2716 | ||
abd58f01 BW |
2717 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
2718 | { | |
2719 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2720 | unsigned long irqflags; | |
abd58f01 | 2721 | |
abd58f01 | 2722 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
7167d7c6 DV |
2723 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
2724 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2725 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2726 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2727 | } | |
2728 | ||
9107e9d2 | 2729 | static bool |
94f7bbe1 | 2730 | ring_idle(struct intel_engine_cs *ring, u32 seqno) |
9107e9d2 CW |
2731 | { |
2732 | return (list_empty(&ring->request_list) || | |
94f7bbe1 | 2733 | i915_seqno_passed(seqno, ring->last_submitted_seqno)); |
f65d9421 BG |
2734 | } |
2735 | ||
a028c4b0 DV |
2736 | static bool |
2737 | ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr) | |
2738 | { | |
2739 | if (INTEL_INFO(dev)->gen >= 8) { | |
a6cdb93a | 2740 | return (ipehr >> 23) == 0x1c; |
a028c4b0 DV |
2741 | } else { |
2742 | ipehr &= ~MI_SEMAPHORE_SYNC_MASK; | |
2743 | return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | | |
2744 | MI_SEMAPHORE_REGISTER); | |
2745 | } | |
2746 | } | |
2747 | ||
a4872ba6 | 2748 | static struct intel_engine_cs * |
a6cdb93a | 2749 | semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset) |
921d42ea DV |
2750 | { |
2751 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 2752 | struct intel_engine_cs *signaller; |
921d42ea DV |
2753 | int i; |
2754 | ||
2755 | if (INTEL_INFO(dev_priv->dev)->gen >= 8) { | |
a6cdb93a RV |
2756 | for_each_ring(signaller, dev_priv, i) { |
2757 | if (ring == signaller) | |
2758 | continue; | |
2759 | ||
2760 | if (offset == signaller->semaphore.signal_ggtt[ring->id]) | |
2761 | return signaller; | |
2762 | } | |
921d42ea DV |
2763 | } else { |
2764 | u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; | |
2765 | ||
2766 | for_each_ring(signaller, dev_priv, i) { | |
2767 | if(ring == signaller) | |
2768 | continue; | |
2769 | ||
ebc348b2 | 2770 | if (sync_bits == signaller->semaphore.mbox.wait[ring->id]) |
921d42ea DV |
2771 | return signaller; |
2772 | } | |
2773 | } | |
2774 | ||
a6cdb93a RV |
2775 | DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n", |
2776 | ring->id, ipehr, offset); | |
921d42ea DV |
2777 | |
2778 | return NULL; | |
2779 | } | |
2780 | ||
a4872ba6 OM |
2781 | static struct intel_engine_cs * |
2782 | semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno) | |
a24a11e6 CW |
2783 | { |
2784 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88fe429d | 2785 | u32 cmd, ipehr, head; |
a6cdb93a RV |
2786 | u64 offset = 0; |
2787 | int i, backwards; | |
a24a11e6 | 2788 | |
381e8ae3 TE |
2789 | /* |
2790 | * This function does not support execlist mode - any attempt to | |
2791 | * proceed further into this function will result in a kernel panic | |
2792 | * when dereferencing ring->buffer, which is not set up in execlist | |
2793 | * mode. | |
2794 | * | |
2795 | * The correct way of doing it would be to derive the currently | |
2796 | * executing ring buffer from the current context, which is derived | |
2797 | * from the currently running request. Unfortunately, to get the | |
2798 | * current request we would have to grab the struct_mutex before doing | |
2799 | * anything else, which would be ill-advised since some other thread | |
2800 | * might have grabbed it already and managed to hang itself, causing | |
2801 | * the hang checker to deadlock. | |
2802 | * | |
2803 | * Therefore, this function does not support execlist mode in its | |
2804 | * current form. Just return NULL and move on. | |
2805 | */ | |
2806 | if (ring->buffer == NULL) | |
2807 | return NULL; | |
2808 | ||
a24a11e6 | 2809 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); |
a028c4b0 | 2810 | if (!ipehr_is_semaphore_wait(ring->dev, ipehr)) |
6274f212 | 2811 | return NULL; |
a24a11e6 | 2812 | |
88fe429d DV |
2813 | /* |
2814 | * HEAD is likely pointing to the dword after the actual command, | |
2815 | * so scan backwards until we find the MBOX. But limit it to just 3 | |
a6cdb93a RV |
2816 | * or 4 dwords depending on the semaphore wait command size. |
2817 | * Note that we don't care about ACTHD here since that might | |
88fe429d DV |
2818 | * point at at batch, and semaphores are always emitted into the |
2819 | * ringbuffer itself. | |
a24a11e6 | 2820 | */ |
88fe429d | 2821 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
a6cdb93a | 2822 | backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4; |
88fe429d | 2823 | |
a6cdb93a | 2824 | for (i = backwards; i; --i) { |
88fe429d DV |
2825 | /* |
2826 | * Be paranoid and presume the hw has gone off into the wild - | |
2827 | * our ring is smaller than what the hardware (and hence | |
2828 | * HEAD_ADDR) allows. Also handles wrap-around. | |
2829 | */ | |
ee1b1e5e | 2830 | head &= ring->buffer->size - 1; |
88fe429d DV |
2831 | |
2832 | /* This here seems to blow up */ | |
ee1b1e5e | 2833 | cmd = ioread32(ring->buffer->virtual_start + head); |
a24a11e6 CW |
2834 | if (cmd == ipehr) |
2835 | break; | |
2836 | ||
88fe429d DV |
2837 | head -= 4; |
2838 | } | |
a24a11e6 | 2839 | |
88fe429d DV |
2840 | if (!i) |
2841 | return NULL; | |
a24a11e6 | 2842 | |
ee1b1e5e | 2843 | *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1; |
a6cdb93a RV |
2844 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2845 | offset = ioread32(ring->buffer->virtual_start + head + 12); | |
2846 | offset <<= 32; | |
2847 | offset = ioread32(ring->buffer->virtual_start + head + 8); | |
2848 | } | |
2849 | return semaphore_wait_to_signaller_ring(ring, ipehr, offset); | |
a24a11e6 CW |
2850 | } |
2851 | ||
a4872ba6 | 2852 | static int semaphore_passed(struct intel_engine_cs *ring) |
6274f212 CW |
2853 | { |
2854 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 2855 | struct intel_engine_cs *signaller; |
a0d036b0 | 2856 | u32 seqno; |
6274f212 | 2857 | |
4be17381 | 2858 | ring->hangcheck.deadlock++; |
6274f212 CW |
2859 | |
2860 | signaller = semaphore_waits_for(ring, &seqno); | |
4be17381 CW |
2861 | if (signaller == NULL) |
2862 | return -1; | |
2863 | ||
2864 | /* Prevent pathological recursion due to driver bugs */ | |
2865 | if (signaller->hangcheck.deadlock >= I915_NUM_RINGS) | |
6274f212 CW |
2866 | return -1; |
2867 | ||
4be17381 CW |
2868 | if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno)) |
2869 | return 1; | |
2870 | ||
a0d036b0 CW |
2871 | /* cursory check for an unkickable deadlock */ |
2872 | if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE && | |
2873 | semaphore_passed(signaller) < 0) | |
4be17381 CW |
2874 | return -1; |
2875 | ||
2876 | return 0; | |
6274f212 CW |
2877 | } |
2878 | ||
2879 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2880 | { | |
a4872ba6 | 2881 | struct intel_engine_cs *ring; |
6274f212 CW |
2882 | int i; |
2883 | ||
2884 | for_each_ring(ring, dev_priv, i) | |
4be17381 | 2885 | ring->hangcheck.deadlock = 0; |
6274f212 CW |
2886 | } |
2887 | ||
ad8beaea | 2888 | static enum intel_ring_hangcheck_action |
a4872ba6 | 2889 | ring_stuck(struct intel_engine_cs *ring, u64 acthd) |
1ec14ad3 CW |
2890 | { |
2891 | struct drm_device *dev = ring->dev; | |
2892 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2893 | u32 tmp; |
2894 | ||
f260fe7b MK |
2895 | if (acthd != ring->hangcheck.acthd) { |
2896 | if (acthd > ring->hangcheck.max_acthd) { | |
2897 | ring->hangcheck.max_acthd = acthd; | |
2898 | return HANGCHECK_ACTIVE; | |
2899 | } | |
2900 | ||
2901 | return HANGCHECK_ACTIVE_LOOP; | |
2902 | } | |
6274f212 | 2903 | |
9107e9d2 | 2904 | if (IS_GEN2(dev)) |
f2f4d82f | 2905 | return HANGCHECK_HUNG; |
9107e9d2 CW |
2906 | |
2907 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2908 | * If so we can simply poke the RB_WAIT bit | |
2909 | * and break the hang. This should work on | |
2910 | * all but the second generation chipsets. | |
2911 | */ | |
2912 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 | 2913 | if (tmp & RING_WAIT) { |
58174462 MK |
2914 | i915_handle_error(dev, false, |
2915 | "Kicking stuck wait on %s", | |
2916 | ring->name); | |
1ec14ad3 | 2917 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2918 | return HANGCHECK_KICK; |
6274f212 CW |
2919 | } |
2920 | ||
2921 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2922 | switch (semaphore_passed(ring)) { | |
2923 | default: | |
f2f4d82f | 2924 | return HANGCHECK_HUNG; |
6274f212 | 2925 | case 1: |
58174462 MK |
2926 | i915_handle_error(dev, false, |
2927 | "Kicking stuck semaphore on %s", | |
2928 | ring->name); | |
6274f212 | 2929 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2930 | return HANGCHECK_KICK; |
6274f212 | 2931 | case 0: |
f2f4d82f | 2932 | return HANGCHECK_WAIT; |
6274f212 | 2933 | } |
9107e9d2 | 2934 | } |
ed5cbb03 | 2935 | |
f2f4d82f | 2936 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
2937 | } |
2938 | ||
737b1506 | 2939 | /* |
f65d9421 | 2940 | * This is called when the chip hasn't reported back with completed |
05407ff8 MK |
2941 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2942 | * if there are no progress, hangcheck score for that ring is increased. | |
2943 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2944 | * we kick the ring. If we see no progress on three subsequent calls | |
2945 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 2946 | */ |
737b1506 | 2947 | static void i915_hangcheck_elapsed(struct work_struct *work) |
f65d9421 | 2948 | { |
737b1506 CW |
2949 | struct drm_i915_private *dev_priv = |
2950 | container_of(work, typeof(*dev_priv), | |
2951 | gpu_error.hangcheck_work.work); | |
2952 | struct drm_device *dev = dev_priv->dev; | |
a4872ba6 | 2953 | struct intel_engine_cs *ring; |
b4519513 | 2954 | int i; |
05407ff8 | 2955 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2956 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2957 | #define BUSY 1 | |
2958 | #define KICK 5 | |
2959 | #define HUNG 20 | |
893eead0 | 2960 | |
d330a953 | 2961 | if (!i915.enable_hangcheck) |
3e0dc6b0 BW |
2962 | return; |
2963 | ||
b4519513 | 2964 | for_each_ring(ring, dev_priv, i) { |
50877445 CW |
2965 | u64 acthd; |
2966 | u32 seqno; | |
9107e9d2 | 2967 | bool busy = true; |
05407ff8 | 2968 | |
6274f212 CW |
2969 | semaphore_clear_deadlocks(dev_priv); |
2970 | ||
05407ff8 MK |
2971 | seqno = ring->get_seqno(ring, false); |
2972 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2973 | |
9107e9d2 | 2974 | if (ring->hangcheck.seqno == seqno) { |
94f7bbe1 | 2975 | if (ring_idle(ring, seqno)) { |
da661464 MK |
2976 | ring->hangcheck.action = HANGCHECK_IDLE; |
2977 | ||
9107e9d2 CW |
2978 | if (waitqueue_active(&ring->irq_queue)) { |
2979 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 | 2980 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
f4adcd24 DV |
2981 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
2982 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2983 | ring->name); | |
2984 | else | |
2985 | DRM_INFO("Fake missed irq on %s\n", | |
2986 | ring->name); | |
094f9a54 CW |
2987 | wake_up_all(&ring->irq_queue); |
2988 | } | |
2989 | /* Safeguard against driver failure */ | |
2990 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
2991 | } else |
2992 | busy = false; | |
05407ff8 | 2993 | } else { |
6274f212 CW |
2994 | /* We always increment the hangcheck score |
2995 | * if the ring is busy and still processing | |
2996 | * the same request, so that no single request | |
2997 | * can run indefinitely (such as a chain of | |
2998 | * batches). The only time we do not increment | |
2999 | * the hangcheck score on this ring, if this | |
3000 | * ring is in a legitimate wait for another | |
3001 | * ring. In that case the waiting ring is a | |
3002 | * victim and we want to be sure we catch the | |
3003 | * right culprit. Then every time we do kick | |
3004 | * the ring, add a small increment to the | |
3005 | * score so that we can catch a batch that is | |
3006 | * being repeatedly kicked and so responsible | |
3007 | * for stalling the machine. | |
3008 | */ | |
ad8beaea MK |
3009 | ring->hangcheck.action = ring_stuck(ring, |
3010 | acthd); | |
3011 | ||
3012 | switch (ring->hangcheck.action) { | |
da661464 | 3013 | case HANGCHECK_IDLE: |
f2f4d82f | 3014 | case HANGCHECK_WAIT: |
f2f4d82f | 3015 | case HANGCHECK_ACTIVE: |
f260fe7b MK |
3016 | break; |
3017 | case HANGCHECK_ACTIVE_LOOP: | |
ea04cb31 | 3018 | ring->hangcheck.score += BUSY; |
6274f212 | 3019 | break; |
f2f4d82f | 3020 | case HANGCHECK_KICK: |
ea04cb31 | 3021 | ring->hangcheck.score += KICK; |
6274f212 | 3022 | break; |
f2f4d82f | 3023 | case HANGCHECK_HUNG: |
ea04cb31 | 3024 | ring->hangcheck.score += HUNG; |
6274f212 CW |
3025 | stuck[i] = true; |
3026 | break; | |
3027 | } | |
05407ff8 | 3028 | } |
9107e9d2 | 3029 | } else { |
da661464 MK |
3030 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
3031 | ||
9107e9d2 CW |
3032 | /* Gradually reduce the count so that we catch DoS |
3033 | * attempts across multiple batches. | |
3034 | */ | |
3035 | if (ring->hangcheck.score > 0) | |
3036 | ring->hangcheck.score--; | |
f260fe7b MK |
3037 | |
3038 | ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0; | |
d1e61e7f CW |
3039 | } |
3040 | ||
05407ff8 MK |
3041 | ring->hangcheck.seqno = seqno; |
3042 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 3043 | busy_count += busy; |
893eead0 | 3044 | } |
b9201c14 | 3045 | |
92cab734 | 3046 | for_each_ring(ring, dev_priv, i) { |
b6b0fac0 | 3047 | if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
b8d88d1d DV |
3048 | DRM_INFO("%s on %s\n", |
3049 | stuck[i] ? "stuck" : "no progress", | |
3050 | ring->name); | |
a43adf07 | 3051 | rings_hung++; |
92cab734 MK |
3052 | } |
3053 | } | |
3054 | ||
05407ff8 | 3055 | if (rings_hung) |
58174462 | 3056 | return i915_handle_error(dev, true, "Ring hung"); |
f65d9421 | 3057 | |
05407ff8 MK |
3058 | if (busy_count) |
3059 | /* Reset timer case chip hangs without another request | |
3060 | * being added */ | |
10cd45b6 MK |
3061 | i915_queue_hangcheck(dev); |
3062 | } | |
3063 | ||
3064 | void i915_queue_hangcheck(struct drm_device *dev) | |
3065 | { | |
737b1506 | 3066 | struct i915_gpu_error *e = &to_i915(dev)->gpu_error; |
672e7b7c | 3067 | |
d330a953 | 3068 | if (!i915.enable_hangcheck) |
10cd45b6 MK |
3069 | return; |
3070 | ||
737b1506 CW |
3071 | /* Don't continually defer the hangcheck so that it is always run at |
3072 | * least once after work has been scheduled on any ring. Otherwise, | |
3073 | * we will ignore a hung ring if a second ring is kept busy. | |
3074 | */ | |
3075 | ||
3076 | queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work, | |
3077 | round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
3078 | } |
3079 | ||
1c69eb42 | 3080 | static void ibx_irq_reset(struct drm_device *dev) |
91738a95 PZ |
3081 | { |
3082 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3083 | ||
3084 | if (HAS_PCH_NOP(dev)) | |
3085 | return; | |
3086 | ||
f86f3fb0 | 3087 | GEN5_IRQ_RESET(SDE); |
105b122e PZ |
3088 | |
3089 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) | |
3090 | I915_WRITE(SERR_INT, 0xffffffff); | |
622364b6 | 3091 | } |
105b122e | 3092 | |
622364b6 PZ |
3093 | /* |
3094 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
3095 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
3096 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
3097 | * only unmask them as needed with SDEIMR. | |
3098 | * | |
3099 | * This function needs to be called before interrupts are enabled. | |
3100 | */ | |
3101 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
3102 | { | |
3103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3104 | ||
3105 | if (HAS_PCH_NOP(dev)) | |
3106 | return; | |
3107 | ||
3108 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
3109 | I915_WRITE(SDEIER, 0xffffffff); |
3110 | POSTING_READ(SDEIER); | |
3111 | } | |
3112 | ||
7c4d664e | 3113 | static void gen5_gt_irq_reset(struct drm_device *dev) |
d18ea1b5 DV |
3114 | { |
3115 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3116 | ||
f86f3fb0 | 3117 | GEN5_IRQ_RESET(GT); |
a9d356a6 | 3118 | if (INTEL_INFO(dev)->gen >= 6) |
f86f3fb0 | 3119 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
3120 | } |
3121 | ||
1da177e4 LT |
3122 | /* drm_dma.h hooks |
3123 | */ | |
be30b29f | 3124 | static void ironlake_irq_reset(struct drm_device *dev) |
036a4a7d | 3125 | { |
2d1013dd | 3126 | struct drm_i915_private *dev_priv = dev->dev_private; |
036a4a7d | 3127 | |
0c841212 | 3128 | I915_WRITE(HWSTAM, 0xffffffff); |
bdfcdb63 | 3129 | |
f86f3fb0 | 3130 | GEN5_IRQ_RESET(DE); |
c6d954c1 PZ |
3131 | if (IS_GEN7(dev)) |
3132 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); | |
036a4a7d | 3133 | |
7c4d664e | 3134 | gen5_gt_irq_reset(dev); |
c650156a | 3135 | |
1c69eb42 | 3136 | ibx_irq_reset(dev); |
7d99163d | 3137 | } |
c650156a | 3138 | |
70591a41 VS |
3139 | static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) |
3140 | { | |
3141 | enum pipe pipe; | |
3142 | ||
0706f17c | 3143 | i915_hotplug_interrupt_update(dev_priv, 0xFFFFFFFF, 0); |
70591a41 VS |
3144 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
3145 | ||
3146 | for_each_pipe(dev_priv, pipe) | |
3147 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3148 | ||
3149 | GEN5_IRQ_RESET(VLV_); | |
3150 | } | |
3151 | ||
7e231dbe JB |
3152 | static void valleyview_irq_preinstall(struct drm_device *dev) |
3153 | { | |
2d1013dd | 3154 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 3155 | |
7e231dbe JB |
3156 | /* VLV magic */ |
3157 | I915_WRITE(VLV_IMR, 0); | |
3158 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
3159 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
3160 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
3161 | ||
7c4d664e | 3162 | gen5_gt_irq_reset(dev); |
7e231dbe | 3163 | |
7c4cde39 | 3164 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); |
7e231dbe | 3165 | |
70591a41 | 3166 | vlv_display_irq_reset(dev_priv); |
7e231dbe JB |
3167 | } |
3168 | ||
d6e3cca3 DV |
3169 | static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) |
3170 | { | |
3171 | GEN8_IRQ_RESET_NDX(GT, 0); | |
3172 | GEN8_IRQ_RESET_NDX(GT, 1); | |
3173 | GEN8_IRQ_RESET_NDX(GT, 2); | |
3174 | GEN8_IRQ_RESET_NDX(GT, 3); | |
3175 | } | |
3176 | ||
823f6b38 | 3177 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 BW |
3178 | { |
3179 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3180 | int pipe; | |
3181 | ||
abd58f01 BW |
3182 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
3183 | POSTING_READ(GEN8_MASTER_IRQ); | |
3184 | ||
d6e3cca3 | 3185 | gen8_gt_irq_reset(dev_priv); |
abd58f01 | 3186 | |
055e393f | 3187 | for_each_pipe(dev_priv, pipe) |
f458ebbc DV |
3188 | if (intel_display_power_is_enabled(dev_priv, |
3189 | POWER_DOMAIN_PIPE(pipe))) | |
813bde43 | 3190 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 3191 | |
f86f3fb0 PZ |
3192 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
3193 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
3194 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 3195 | |
266ea3d9 SS |
3196 | if (HAS_PCH_SPLIT(dev)) |
3197 | ibx_irq_reset(dev); | |
abd58f01 | 3198 | } |
09f2344d | 3199 | |
4c6c03be DL |
3200 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
3201 | unsigned int pipe_mask) | |
d49bdb0e | 3202 | { |
1180e206 | 3203 | uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; |
d49bdb0e | 3204 | |
13321786 | 3205 | spin_lock_irq(&dev_priv->irq_lock); |
d14c0343 DL |
3206 | if (pipe_mask & 1 << PIPE_A) |
3207 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A, | |
3208 | dev_priv->de_irq_mask[PIPE_A], | |
3209 | ~dev_priv->de_irq_mask[PIPE_A] | extra_ier); | |
4c6c03be DL |
3210 | if (pipe_mask & 1 << PIPE_B) |
3211 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, | |
3212 | dev_priv->de_irq_mask[PIPE_B], | |
3213 | ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); | |
3214 | if (pipe_mask & 1 << PIPE_C) | |
3215 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, | |
3216 | dev_priv->de_irq_mask[PIPE_C], | |
3217 | ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); | |
13321786 | 3218 | spin_unlock_irq(&dev_priv->irq_lock); |
d49bdb0e PZ |
3219 | } |
3220 | ||
43f328d7 VS |
3221 | static void cherryview_irq_preinstall(struct drm_device *dev) |
3222 | { | |
3223 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3224 | |
3225 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3226 | POSTING_READ(GEN8_MASTER_IRQ); | |
3227 | ||
d6e3cca3 | 3228 | gen8_gt_irq_reset(dev_priv); |
43f328d7 VS |
3229 | |
3230 | GEN5_IRQ_RESET(GEN8_PCU_); | |
3231 | ||
43f328d7 VS |
3232 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); |
3233 | ||
70591a41 | 3234 | vlv_display_irq_reset(dev_priv); |
43f328d7 VS |
3235 | } |
3236 | ||
87a02106 VS |
3237 | static u32 intel_hpd_enabled_irqs(struct drm_device *dev, |
3238 | const u32 hpd[HPD_NUM_PINS]) | |
3239 | { | |
3240 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3241 | struct intel_encoder *encoder; | |
3242 | u32 enabled_irqs = 0; | |
3243 | ||
3244 | for_each_intel_encoder(dev, encoder) | |
3245 | if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) | |
3246 | enabled_irqs |= hpd[encoder->hpd_pin]; | |
3247 | ||
3248 | return enabled_irqs; | |
3249 | } | |
3250 | ||
82a28bcf | 3251 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 | 3252 | { |
2d1013dd | 3253 | struct drm_i915_private *dev_priv = dev->dev_private; |
87a02106 | 3254 | u32 hotplug_irqs, hotplug, enabled_irqs; |
82a28bcf DV |
3255 | |
3256 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 3257 | hotplug_irqs = SDE_HOTPLUG_MASK; |
87a02106 | 3258 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ibx); |
82a28bcf | 3259 | } else { |
fee884ed | 3260 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
87a02106 | 3261 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_cpt); |
82a28bcf | 3262 | } |
7fe0b973 | 3263 | |
fee884ed | 3264 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
3265 | |
3266 | /* | |
3267 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
6dbf30ce VS |
3268 | * duration to 2ms (which is the minimum in the Display Port spec). |
3269 | * The pulse duration bits are reserved on LPT+. | |
82a28bcf | 3270 | */ |
7fe0b973 KP |
3271 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3272 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
3273 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
3274 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
3275 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
0b2eb33e VS |
3276 | /* |
3277 | * When CPU and PCH are on the same package, port A | |
3278 | * HPD must be enabled in both north and south. | |
3279 | */ | |
3280 | if (HAS_PCH_LPT_LP(dev)) | |
3281 | hotplug |= PORTA_HOTPLUG_ENABLE; | |
7fe0b973 | 3282 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
6dbf30ce | 3283 | } |
26951caf | 3284 | |
6dbf30ce VS |
3285 | static void spt_hpd_irq_setup(struct drm_device *dev) |
3286 | { | |
3287 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3288 | u32 hotplug_irqs, hotplug, enabled_irqs; | |
3289 | ||
3290 | hotplug_irqs = SDE_HOTPLUG_MASK_SPT; | |
3291 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_spt); | |
3292 | ||
3293 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); | |
3294 | ||
3295 | /* Enable digital hotplug on the PCH */ | |
3296 | hotplug = I915_READ(PCH_PORT_HOTPLUG); | |
3297 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE | | |
74c0b395 | 3298 | PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE; |
6dbf30ce VS |
3299 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
3300 | ||
3301 | hotplug = I915_READ(PCH_PORT_HOTPLUG2); | |
3302 | hotplug |= PORTE_HOTPLUG_ENABLE; | |
3303 | I915_WRITE(PCH_PORT_HOTPLUG2, hotplug); | |
7fe0b973 KP |
3304 | } |
3305 | ||
e4ce95aa VS |
3306 | static void ilk_hpd_irq_setup(struct drm_device *dev) |
3307 | { | |
3308 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3309 | u32 hotplug_irqs, hotplug, enabled_irqs; | |
3310 | ||
3a3b3c7d VS |
3311 | if (INTEL_INFO(dev)->gen >= 8) { |
3312 | hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG; | |
3313 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bdw); | |
3314 | ||
3315 | bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
3316 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
23bb4cb5 VS |
3317 | hotplug_irqs = DE_DP_A_HOTPLUG_IVB; |
3318 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ivb); | |
3a3b3c7d VS |
3319 | |
3320 | ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
23bb4cb5 VS |
3321 | } else { |
3322 | hotplug_irqs = DE_DP_A_HOTPLUG; | |
3323 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ilk); | |
e4ce95aa | 3324 | |
3a3b3c7d VS |
3325 | ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); |
3326 | } | |
e4ce95aa VS |
3327 | |
3328 | /* | |
3329 | * Enable digital hotplug on the CPU, and configure the DP short pulse | |
3330 | * duration to 2ms (which is the minimum in the Display Port spec) | |
23bb4cb5 | 3331 | * The pulse duration bits are reserved on HSW+. |
e4ce95aa VS |
3332 | */ |
3333 | hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); | |
3334 | hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK; | |
3335 | hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms; | |
3336 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug); | |
3337 | ||
3338 | ibx_hpd_irq_setup(dev); | |
3339 | } | |
3340 | ||
e0a20ad7 SS |
3341 | static void bxt_hpd_irq_setup(struct drm_device *dev) |
3342 | { | |
3343 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a52bb15b | 3344 | u32 hotplug_irqs, hotplug, enabled_irqs; |
e0a20ad7 | 3345 | |
a52bb15b VS |
3346 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bxt); |
3347 | hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK; | |
e0a20ad7 | 3348 | |
a52bb15b | 3349 | bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); |
e0a20ad7 | 3350 | |
a52bb15b VS |
3351 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3352 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE | | |
3353 | PORTA_HOTPLUG_ENABLE; | |
3354 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
e0a20ad7 SS |
3355 | } |
3356 | ||
d46da437 PZ |
3357 | static void ibx_irq_postinstall(struct drm_device *dev) |
3358 | { | |
2d1013dd | 3359 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3360 | u32 mask; |
e5868a31 | 3361 | |
692a04cf DV |
3362 | if (HAS_PCH_NOP(dev)) |
3363 | return; | |
3364 | ||
105b122e | 3365 | if (HAS_PCH_IBX(dev)) |
5c673b60 | 3366 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 3367 | else |
5c673b60 | 3368 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 3369 | |
b51a2842 | 3370 | gen5_assert_iir_is_zero(dev_priv, SDEIIR); |
d46da437 | 3371 | I915_WRITE(SDEIMR, ~mask); |
d46da437 PZ |
3372 | } |
3373 | ||
0a9a8c91 DV |
3374 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
3375 | { | |
3376 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3377 | u32 pm_irqs, gt_irqs; | |
3378 | ||
3379 | pm_irqs = gt_irqs = 0; | |
3380 | ||
3381 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 3382 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 3383 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
3384 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
3385 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
3386 | } |
3387 | ||
3388 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
3389 | if (IS_GEN5(dev)) { | |
3390 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
3391 | ILK_BSD_USER_INTERRUPT; | |
3392 | } else { | |
3393 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3394 | } | |
3395 | ||
35079899 | 3396 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 DV |
3397 | |
3398 | if (INTEL_INFO(dev)->gen >= 6) { | |
78e68d36 ID |
3399 | /* |
3400 | * RPS interrupts will get enabled/disabled on demand when RPS | |
3401 | * itself is enabled/disabled. | |
3402 | */ | |
0a9a8c91 DV |
3403 | if (HAS_VEBOX(dev)) |
3404 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
3405 | ||
605cd25b | 3406 | dev_priv->pm_irq_mask = 0xffffffff; |
35079899 | 3407 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); |
0a9a8c91 DV |
3408 | } |
3409 | } | |
3410 | ||
f71d4af4 | 3411 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3412 | { |
2d1013dd | 3413 | struct drm_i915_private *dev_priv = dev->dev_private; |
8e76f8dc PZ |
3414 | u32 display_mask, extra_mask; |
3415 | ||
3416 | if (INTEL_INFO(dev)->gen >= 7) { | |
3417 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
3418 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3419 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3420 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3421 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
23bb4cb5 VS |
3422 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB | |
3423 | DE_DP_A_HOTPLUG_IVB); | |
8e76f8dc PZ |
3424 | } else { |
3425 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3426 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3427 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3428 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3429 | DE_POISON); | |
e4ce95aa VS |
3430 | extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3431 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | | |
3432 | DE_DP_A_HOTPLUG); | |
8e76f8dc | 3433 | } |
036a4a7d | 3434 | |
1ec14ad3 | 3435 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3436 | |
0c841212 PZ |
3437 | I915_WRITE(HWSTAM, 0xeffe); |
3438 | ||
622364b6 PZ |
3439 | ibx_irq_pre_postinstall(dev); |
3440 | ||
35079899 | 3441 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3442 | |
0a9a8c91 | 3443 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3444 | |
d46da437 | 3445 | ibx_irq_postinstall(dev); |
7fe0b973 | 3446 | |
f97108d1 | 3447 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
3448 | /* Enable PCU event interrupts |
3449 | * | |
3450 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3451 | * setup is guaranteed to run in single-threaded context. But we |
3452 | * need it to make the assert_spin_locked happy. */ | |
d6207435 | 3453 | spin_lock_irq(&dev_priv->irq_lock); |
f97108d1 | 3454 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
d6207435 | 3455 | spin_unlock_irq(&dev_priv->irq_lock); |
f97108d1 JB |
3456 | } |
3457 | ||
036a4a7d ZW |
3458 | return 0; |
3459 | } | |
3460 | ||
f8b79e58 ID |
3461 | static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) |
3462 | { | |
3463 | u32 pipestat_mask; | |
3464 | u32 iir_mask; | |
120dda4f | 3465 | enum pipe pipe; |
f8b79e58 ID |
3466 | |
3467 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3468 | PIPE_FIFO_UNDERRUN_STATUS; | |
3469 | ||
120dda4f VS |
3470 | for_each_pipe(dev_priv, pipe) |
3471 | I915_WRITE(PIPESTAT(pipe), pipestat_mask); | |
f8b79e58 ID |
3472 | POSTING_READ(PIPESTAT(PIPE_A)); |
3473 | ||
3474 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3475 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3476 | ||
120dda4f VS |
3477 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3478 | for_each_pipe(dev_priv, pipe) | |
3479 | i915_enable_pipestat(dev_priv, pipe, pipestat_mask); | |
f8b79e58 ID |
3480 | |
3481 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3482 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3483 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
120dda4f VS |
3484 | if (IS_CHERRYVIEW(dev_priv)) |
3485 | iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
f8b79e58 ID |
3486 | dev_priv->irq_mask &= ~iir_mask; |
3487 | ||
3488 | I915_WRITE(VLV_IIR, iir_mask); | |
3489 | I915_WRITE(VLV_IIR, iir_mask); | |
f8b79e58 | 3490 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
76e41860 VS |
3491 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
3492 | POSTING_READ(VLV_IMR); | |
f8b79e58 ID |
3493 | } |
3494 | ||
3495 | static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) | |
3496 | { | |
3497 | u32 pipestat_mask; | |
3498 | u32 iir_mask; | |
120dda4f | 3499 | enum pipe pipe; |
f8b79e58 ID |
3500 | |
3501 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3502 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
6c7fba04 | 3503 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
120dda4f VS |
3504 | if (IS_CHERRYVIEW(dev_priv)) |
3505 | iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
f8b79e58 ID |
3506 | |
3507 | dev_priv->irq_mask |= iir_mask; | |
f8b79e58 | 3508 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
76e41860 | 3509 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
f8b79e58 ID |
3510 | I915_WRITE(VLV_IIR, iir_mask); |
3511 | I915_WRITE(VLV_IIR, iir_mask); | |
3512 | POSTING_READ(VLV_IIR); | |
3513 | ||
3514 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3515 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3516 | ||
120dda4f VS |
3517 | i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3518 | for_each_pipe(dev_priv, pipe) | |
3519 | i915_disable_pipestat(dev_priv, pipe, pipestat_mask); | |
f8b79e58 ID |
3520 | |
3521 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3522 | PIPE_FIFO_UNDERRUN_STATUS; | |
120dda4f VS |
3523 | |
3524 | for_each_pipe(dev_priv, pipe) | |
3525 | I915_WRITE(PIPESTAT(pipe), pipestat_mask); | |
f8b79e58 ID |
3526 | POSTING_READ(PIPESTAT(PIPE_A)); |
3527 | } | |
3528 | ||
3529 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) | |
3530 | { | |
3531 | assert_spin_locked(&dev_priv->irq_lock); | |
3532 | ||
3533 | if (dev_priv->display_irqs_enabled) | |
3534 | return; | |
3535 | ||
3536 | dev_priv->display_irqs_enabled = true; | |
3537 | ||
950eabaf | 3538 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3539 | valleyview_display_irqs_install(dev_priv); |
3540 | } | |
3541 | ||
3542 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3543 | { | |
3544 | assert_spin_locked(&dev_priv->irq_lock); | |
3545 | ||
3546 | if (!dev_priv->display_irqs_enabled) | |
3547 | return; | |
3548 | ||
3549 | dev_priv->display_irqs_enabled = false; | |
3550 | ||
950eabaf | 3551 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3552 | valleyview_display_irqs_uninstall(dev_priv); |
3553 | } | |
3554 | ||
0e6c9a9e | 3555 | static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) |
7e231dbe | 3556 | { |
f8b79e58 | 3557 | dev_priv->irq_mask = ~0; |
7e231dbe | 3558 | |
0706f17c | 3559 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
20afbda2 DV |
3560 | POSTING_READ(PORT_HOTPLUG_EN); |
3561 | ||
7e231dbe | 3562 | I915_WRITE(VLV_IIR, 0xffffffff); |
76e41860 VS |
3563 | I915_WRITE(VLV_IIR, 0xffffffff); |
3564 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3565 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3566 | POSTING_READ(VLV_IMR); | |
7e231dbe | 3567 | |
b79480ba DV |
3568 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3569 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3570 | spin_lock_irq(&dev_priv->irq_lock); |
f8b79e58 ID |
3571 | if (dev_priv->display_irqs_enabled) |
3572 | valleyview_display_irqs_install(dev_priv); | |
d6207435 | 3573 | spin_unlock_irq(&dev_priv->irq_lock); |
0e6c9a9e VS |
3574 | } |
3575 | ||
3576 | static int valleyview_irq_postinstall(struct drm_device *dev) | |
3577 | { | |
3578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3579 | ||
3580 | vlv_display_irq_postinstall(dev_priv); | |
7e231dbe | 3581 | |
0a9a8c91 | 3582 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
3583 | |
3584 | /* ack & enable invalid PTE error interrupts */ | |
3585 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
3586 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
3587 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
3588 | #endif | |
3589 | ||
3590 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
3591 | |
3592 | return 0; | |
3593 | } | |
3594 | ||
abd58f01 BW |
3595 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3596 | { | |
abd58f01 BW |
3597 | /* These are interrupts we'll toggle with the ring mask register */ |
3598 | uint32_t gt_interrupts[] = { | |
3599 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
73d477f6 | 3600 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
abd58f01 | 3601 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | |
73d477f6 OM |
3602 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT | |
3603 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
abd58f01 | 3604 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
73d477f6 OM |
3605 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
3606 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT | | |
3607 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
abd58f01 | 3608 | 0, |
73d477f6 OM |
3609 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3610 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
abd58f01 BW |
3611 | }; |
3612 | ||
0961021a | 3613 | dev_priv->pm_irq_mask = 0xffffffff; |
9a2d2d87 D |
3614 | GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); |
3615 | GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); | |
78e68d36 ID |
3616 | /* |
3617 | * RPS interrupts will get enabled/disabled on demand when RPS itself | |
3618 | * is enabled/disabled. | |
3619 | */ | |
3620 | GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0); | |
9a2d2d87 | 3621 | GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); |
abd58f01 BW |
3622 | } |
3623 | ||
3624 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3625 | { | |
770de83d DL |
3626 | uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; |
3627 | uint32_t de_pipe_enables; | |
3a3b3c7d VS |
3628 | u32 de_port_masked = GEN8_AUX_CHANNEL_A; |
3629 | u32 de_port_enables; | |
3630 | enum pipe pipe; | |
770de83d | 3631 | |
b4834a50 | 3632 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
770de83d DL |
3633 | de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | |
3634 | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
3a3b3c7d VS |
3635 | de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | |
3636 | GEN9_AUX_CHANNEL_D; | |
9e63743e | 3637 | if (IS_BROXTON(dev_priv)) |
3a3b3c7d VS |
3638 | de_port_masked |= BXT_DE_PORT_GMBUS; |
3639 | } else { | |
770de83d DL |
3640 | de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE | |
3641 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
3a3b3c7d | 3642 | } |
770de83d DL |
3643 | |
3644 | de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | | |
3645 | GEN8_PIPE_FIFO_UNDERRUN; | |
3646 | ||
3a3b3c7d | 3647 | de_port_enables = de_port_masked; |
a52bb15b VS |
3648 | if (IS_BROXTON(dev_priv)) |
3649 | de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; | |
3650 | else if (IS_BROADWELL(dev_priv)) | |
3a3b3c7d VS |
3651 | de_port_enables |= GEN8_PORT_DP_A_HOTPLUG; |
3652 | ||
13b3a0a7 DV |
3653 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3654 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3655 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3656 | |
055e393f | 3657 | for_each_pipe(dev_priv, pipe) |
f458ebbc | 3658 | if (intel_display_power_is_enabled(dev_priv, |
813bde43 PZ |
3659 | POWER_DOMAIN_PIPE(pipe))) |
3660 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3661 | dev_priv->de_irq_mask[pipe], | |
3662 | de_pipe_enables); | |
abd58f01 | 3663 | |
3a3b3c7d | 3664 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables); |
abd58f01 BW |
3665 | } |
3666 | ||
3667 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3668 | { | |
3669 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3670 | ||
266ea3d9 SS |
3671 | if (HAS_PCH_SPLIT(dev)) |
3672 | ibx_irq_pre_postinstall(dev); | |
622364b6 | 3673 | |
abd58f01 BW |
3674 | gen8_gt_irq_postinstall(dev_priv); |
3675 | gen8_de_irq_postinstall(dev_priv); | |
3676 | ||
266ea3d9 SS |
3677 | if (HAS_PCH_SPLIT(dev)) |
3678 | ibx_irq_postinstall(dev); | |
abd58f01 BW |
3679 | |
3680 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | |
3681 | POSTING_READ(GEN8_MASTER_IRQ); | |
3682 | ||
3683 | return 0; | |
3684 | } | |
3685 | ||
43f328d7 VS |
3686 | static int cherryview_irq_postinstall(struct drm_device *dev) |
3687 | { | |
3688 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 | 3689 | |
c2b66797 | 3690 | vlv_display_irq_postinstall(dev_priv); |
43f328d7 VS |
3691 | |
3692 | gen8_gt_irq_postinstall(dev_priv); | |
3693 | ||
3694 | I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE); | |
3695 | POSTING_READ(GEN8_MASTER_IRQ); | |
3696 | ||
3697 | return 0; | |
3698 | } | |
3699 | ||
abd58f01 BW |
3700 | static void gen8_irq_uninstall(struct drm_device *dev) |
3701 | { | |
3702 | struct drm_i915_private *dev_priv = dev->dev_private; | |
abd58f01 BW |
3703 | |
3704 | if (!dev_priv) | |
3705 | return; | |
3706 | ||
823f6b38 | 3707 | gen8_irq_reset(dev); |
abd58f01 BW |
3708 | } |
3709 | ||
8ea0be4f VS |
3710 | static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv) |
3711 | { | |
3712 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
3713 | * just to make the assert_spin_locked check happy. */ | |
3714 | spin_lock_irq(&dev_priv->irq_lock); | |
3715 | if (dev_priv->display_irqs_enabled) | |
3716 | valleyview_display_irqs_uninstall(dev_priv); | |
3717 | spin_unlock_irq(&dev_priv->irq_lock); | |
3718 | ||
3719 | vlv_display_irq_reset(dev_priv); | |
3720 | ||
c352d1ba | 3721 | dev_priv->irq_mask = ~0; |
8ea0be4f VS |
3722 | } |
3723 | ||
7e231dbe JB |
3724 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3725 | { | |
2d1013dd | 3726 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
3727 | |
3728 | if (!dev_priv) | |
3729 | return; | |
3730 | ||
843d0e7d ID |
3731 | I915_WRITE(VLV_MASTER_IER, 0); |
3732 | ||
893fce8e VS |
3733 | gen5_gt_irq_reset(dev); |
3734 | ||
7e231dbe | 3735 | I915_WRITE(HWSTAM, 0xffffffff); |
f8b79e58 | 3736 | |
8ea0be4f | 3737 | vlv_display_irq_uninstall(dev_priv); |
7e231dbe JB |
3738 | } |
3739 | ||
43f328d7 VS |
3740 | static void cherryview_irq_uninstall(struct drm_device *dev) |
3741 | { | |
3742 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3743 | |
3744 | if (!dev_priv) | |
3745 | return; | |
3746 | ||
3747 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3748 | POSTING_READ(GEN8_MASTER_IRQ); | |
3749 | ||
a2c30fba | 3750 | gen8_gt_irq_reset(dev_priv); |
43f328d7 | 3751 | |
a2c30fba | 3752 | GEN5_IRQ_RESET(GEN8_PCU_); |
43f328d7 | 3753 | |
c2b66797 | 3754 | vlv_display_irq_uninstall(dev_priv); |
43f328d7 VS |
3755 | } |
3756 | ||
f71d4af4 | 3757 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3758 | { |
2d1013dd | 3759 | struct drm_i915_private *dev_priv = dev->dev_private; |
4697995b JB |
3760 | |
3761 | if (!dev_priv) | |
3762 | return; | |
3763 | ||
be30b29f | 3764 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3765 | } |
3766 | ||
a266c7d5 | 3767 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3768 | { |
2d1013dd | 3769 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 3770 | int pipe; |
91e3738e | 3771 | |
055e393f | 3772 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 | 3773 | I915_WRITE(PIPESTAT(pipe), 0); |
a266c7d5 CW |
3774 | I915_WRITE16(IMR, 0xffff); |
3775 | I915_WRITE16(IER, 0x0); | |
3776 | POSTING_READ16(IER); | |
c2798b19 CW |
3777 | } |
3778 | ||
3779 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3780 | { | |
2d1013dd | 3781 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 | 3782 | |
c2798b19 CW |
3783 | I915_WRITE16(EMR, |
3784 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3785 | ||
3786 | /* Unmask the interrupts that we always want on. */ | |
3787 | dev_priv->irq_mask = | |
3788 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3789 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3790 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
37ef01ab | 3791 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
c2798b19 CW |
3792 | I915_WRITE16(IMR, dev_priv->irq_mask); |
3793 | ||
3794 | I915_WRITE16(IER, | |
3795 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3796 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
c2798b19 CW |
3797 | I915_USER_INTERRUPT); |
3798 | POSTING_READ16(IER); | |
3799 | ||
379ef82d DV |
3800 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3801 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3802 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3803 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3804 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3805 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3806 | |
c2798b19 CW |
3807 | return 0; |
3808 | } | |
3809 | ||
90a72f87 VS |
3810 | /* |
3811 | * Returns true when a page flip has completed. | |
3812 | */ | |
3813 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
1f1c2e24 | 3814 | int plane, int pipe, u32 iir) |
90a72f87 | 3815 | { |
2d1013dd | 3816 | struct drm_i915_private *dev_priv = dev->dev_private; |
1f1c2e24 | 3817 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 | 3818 | |
8d7849db | 3819 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3820 | return false; |
3821 | ||
3822 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 3823 | goto check_page_flip; |
90a72f87 | 3824 | |
90a72f87 VS |
3825 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
3826 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3827 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3828 | * the flip is completed (no longer pending). Since this doesn't raise | |
3829 | * an interrupt per se, we watch for the change at vblank. | |
3830 | */ | |
3831 | if (I915_READ16(ISR) & flip_pending) | |
d6bbafa1 | 3832 | goto check_page_flip; |
90a72f87 | 3833 | |
7d47559e | 3834 | intel_prepare_page_flip(dev, plane); |
90a72f87 | 3835 | intel_finish_page_flip(dev, pipe); |
90a72f87 | 3836 | return true; |
d6bbafa1 CW |
3837 | |
3838 | check_page_flip: | |
3839 | intel_check_page_flip(dev, pipe); | |
3840 | return false; | |
90a72f87 VS |
3841 | } |
3842 | ||
ff1f525e | 3843 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 | 3844 | { |
45a83f84 | 3845 | struct drm_device *dev = arg; |
2d1013dd | 3846 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3847 | u16 iir, new_iir; |
3848 | u32 pipe_stats[2]; | |
c2798b19 CW |
3849 | int pipe; |
3850 | u16 flip_mask = | |
3851 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3852 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
3853 | ||
2dd2a883 ID |
3854 | if (!intel_irqs_enabled(dev_priv)) |
3855 | return IRQ_NONE; | |
3856 | ||
c2798b19 CW |
3857 | iir = I915_READ16(IIR); |
3858 | if (iir == 0) | |
3859 | return IRQ_NONE; | |
3860 | ||
3861 | while (iir & ~flip_mask) { | |
3862 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3863 | * have been cleared after the pipestat interrupt was received. | |
3864 | * It doesn't set the bit in iir again, but it still produces | |
3865 | * interrupts (for non-MSI). | |
3866 | */ | |
222c7f51 | 3867 | spin_lock(&dev_priv->irq_lock); |
c2798b19 | 3868 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3869 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
c2798b19 | 3870 | |
055e393f | 3871 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3872 | int reg = PIPESTAT(pipe); |
3873 | pipe_stats[pipe] = I915_READ(reg); | |
3874 | ||
3875 | /* | |
3876 | * Clear the PIPE*STAT regs before the IIR | |
3877 | */ | |
2d9d2b0b | 3878 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 3879 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 | 3880 | } |
222c7f51 | 3881 | spin_unlock(&dev_priv->irq_lock); |
c2798b19 CW |
3882 | |
3883 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3884 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3885 | ||
c2798b19 | 3886 | if (iir & I915_USER_INTERRUPT) |
74cdb337 | 3887 | notify_ring(&dev_priv->ring[RCS]); |
c2798b19 | 3888 | |
055e393f | 3889 | for_each_pipe(dev_priv, pipe) { |
1f1c2e24 | 3890 | int plane = pipe; |
3a77c4c4 | 3891 | if (HAS_FBC(dev)) |
1f1c2e24 VS |
3892 | plane = !plane; |
3893 | ||
4356d586 | 3894 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
1f1c2e24 VS |
3895 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
3896 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3897 | |
4356d586 | 3898 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
277de95e | 3899 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 3900 | |
1f7247c0 DV |
3901 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3902 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3903 | pipe); | |
4356d586 | 3904 | } |
c2798b19 CW |
3905 | |
3906 | iir = new_iir; | |
3907 | } | |
3908 | ||
3909 | return IRQ_HANDLED; | |
3910 | } | |
3911 | ||
3912 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3913 | { | |
2d1013dd | 3914 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3915 | int pipe; |
3916 | ||
055e393f | 3917 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3918 | /* Clear enable bits; then clear status bits */ |
3919 | I915_WRITE(PIPESTAT(pipe), 0); | |
3920 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3921 | } | |
3922 | I915_WRITE16(IMR, 0xffff); | |
3923 | I915_WRITE16(IER, 0x0); | |
3924 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3925 | } | |
3926 | ||
a266c7d5 CW |
3927 | static void i915_irq_preinstall(struct drm_device * dev) |
3928 | { | |
2d1013dd | 3929 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3930 | int pipe; |
3931 | ||
a266c7d5 | 3932 | if (I915_HAS_HOTPLUG(dev)) { |
0706f17c | 3933 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
a266c7d5 CW |
3934 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
3935 | } | |
3936 | ||
00d98ebd | 3937 | I915_WRITE16(HWSTAM, 0xeffe); |
055e393f | 3938 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
3939 | I915_WRITE(PIPESTAT(pipe), 0); |
3940 | I915_WRITE(IMR, 0xffffffff); | |
3941 | I915_WRITE(IER, 0x0); | |
3942 | POSTING_READ(IER); | |
3943 | } | |
3944 | ||
3945 | static int i915_irq_postinstall(struct drm_device *dev) | |
3946 | { | |
2d1013dd | 3947 | struct drm_i915_private *dev_priv = dev->dev_private; |
38bde180 | 3948 | u32 enable_mask; |
a266c7d5 | 3949 | |
38bde180 CW |
3950 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3951 | ||
3952 | /* Unmask the interrupts that we always want on. */ | |
3953 | dev_priv->irq_mask = | |
3954 | ~(I915_ASLE_INTERRUPT | | |
3955 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3956 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3957 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
37ef01ab | 3958 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
38bde180 CW |
3959 | |
3960 | enable_mask = | |
3961 | I915_ASLE_INTERRUPT | | |
3962 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3963 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
38bde180 CW |
3964 | I915_USER_INTERRUPT; |
3965 | ||
a266c7d5 | 3966 | if (I915_HAS_HOTPLUG(dev)) { |
0706f17c | 3967 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
20afbda2 DV |
3968 | POSTING_READ(PORT_HOTPLUG_EN); |
3969 | ||
a266c7d5 CW |
3970 | /* Enable in IER... */ |
3971 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3972 | /* and unmask in IMR */ | |
3973 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3974 | } | |
3975 | ||
a266c7d5 CW |
3976 | I915_WRITE(IMR, dev_priv->irq_mask); |
3977 | I915_WRITE(IER, enable_mask); | |
3978 | POSTING_READ(IER); | |
3979 | ||
f49e38dd | 3980 | i915_enable_asle_pipestat(dev); |
20afbda2 | 3981 | |
379ef82d DV |
3982 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3983 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3984 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3985 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3986 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3987 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3988 | |
20afbda2 DV |
3989 | return 0; |
3990 | } | |
3991 | ||
90a72f87 VS |
3992 | /* |
3993 | * Returns true when a page flip has completed. | |
3994 | */ | |
3995 | static bool i915_handle_vblank(struct drm_device *dev, | |
3996 | int plane, int pipe, u32 iir) | |
3997 | { | |
2d1013dd | 3998 | struct drm_i915_private *dev_priv = dev->dev_private; |
90a72f87 VS |
3999 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
4000 | ||
8d7849db | 4001 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
4002 | return false; |
4003 | ||
4004 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 4005 | goto check_page_flip; |
90a72f87 | 4006 | |
90a72f87 VS |
4007 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
4008 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
4009 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
4010 | * the flip is completed (no longer pending). Since this doesn't raise | |
4011 | * an interrupt per se, we watch for the change at vblank. | |
4012 | */ | |
4013 | if (I915_READ(ISR) & flip_pending) | |
d6bbafa1 | 4014 | goto check_page_flip; |
90a72f87 | 4015 | |
7d47559e | 4016 | intel_prepare_page_flip(dev, plane); |
90a72f87 | 4017 | intel_finish_page_flip(dev, pipe); |
90a72f87 | 4018 | return true; |
d6bbafa1 CW |
4019 | |
4020 | check_page_flip: | |
4021 | intel_check_page_flip(dev, pipe); | |
4022 | return false; | |
90a72f87 VS |
4023 | } |
4024 | ||
ff1f525e | 4025 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 | 4026 | { |
45a83f84 | 4027 | struct drm_device *dev = arg; |
2d1013dd | 4028 | struct drm_i915_private *dev_priv = dev->dev_private; |
8291ee90 | 4029 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
38bde180 CW |
4030 | u32 flip_mask = |
4031 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4032 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 4033 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 4034 | |
2dd2a883 ID |
4035 | if (!intel_irqs_enabled(dev_priv)) |
4036 | return IRQ_NONE; | |
4037 | ||
a266c7d5 | 4038 | iir = I915_READ(IIR); |
38bde180 CW |
4039 | do { |
4040 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 4041 | bool blc_event = false; |
a266c7d5 CW |
4042 | |
4043 | /* Can't rely on pipestat interrupt bit in iir as it might | |
4044 | * have been cleared after the pipestat interrupt was received. | |
4045 | * It doesn't set the bit in iir again, but it still produces | |
4046 | * interrupts (for non-MSI). | |
4047 | */ | |
222c7f51 | 4048 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4049 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 4050 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 4051 | |
055e393f | 4052 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
4053 | int reg = PIPESTAT(pipe); |
4054 | pipe_stats[pipe] = I915_READ(reg); | |
4055 | ||
38bde180 | 4056 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 4057 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 4058 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 4059 | irq_received = true; |
a266c7d5 CW |
4060 | } |
4061 | } | |
222c7f51 | 4062 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4063 | |
4064 | if (!irq_received) | |
4065 | break; | |
4066 | ||
a266c7d5 | 4067 | /* Consume port. Then clear IIR or we'll miss events */ |
16c6c56b VS |
4068 | if (I915_HAS_HOTPLUG(dev) && |
4069 | iir & I915_DISPLAY_PORT_INTERRUPT) | |
4070 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 4071 | |
38bde180 | 4072 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4073 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4074 | ||
a266c7d5 | 4075 | if (iir & I915_USER_INTERRUPT) |
74cdb337 | 4076 | notify_ring(&dev_priv->ring[RCS]); |
a266c7d5 | 4077 | |
055e393f | 4078 | for_each_pipe(dev_priv, pipe) { |
38bde180 | 4079 | int plane = pipe; |
3a77c4c4 | 4080 | if (HAS_FBC(dev)) |
38bde180 | 4081 | plane = !plane; |
90a72f87 | 4082 | |
8291ee90 | 4083 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
4084 | i915_handle_vblank(dev, plane, pipe, iir)) |
4085 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
4086 | |
4087 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4088 | blc_event = true; | |
4356d586 DV |
4089 | |
4090 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 4091 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 4092 | |
1f7247c0 DV |
4093 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4094 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
4095 | pipe); | |
a266c7d5 CW |
4096 | } |
4097 | ||
a266c7d5 CW |
4098 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
4099 | intel_opregion_asle_intr(dev); | |
4100 | ||
4101 | /* With MSI, interrupts are only generated when iir | |
4102 | * transitions from zero to nonzero. If another bit got | |
4103 | * set while we were handling the existing iir bits, then | |
4104 | * we would never get another interrupt. | |
4105 | * | |
4106 | * This is fine on non-MSI as well, as if we hit this path | |
4107 | * we avoid exiting the interrupt handler only to generate | |
4108 | * another one. | |
4109 | * | |
4110 | * Note that for MSI this could cause a stray interrupt report | |
4111 | * if an interrupt landed in the time between writing IIR and | |
4112 | * the posting read. This should be rare enough to never | |
4113 | * trigger the 99% of 100,000 interrupts test for disabling | |
4114 | * stray interrupts. | |
4115 | */ | |
38bde180 | 4116 | ret = IRQ_HANDLED; |
a266c7d5 | 4117 | iir = new_iir; |
38bde180 | 4118 | } while (iir & ~flip_mask); |
a266c7d5 CW |
4119 | |
4120 | return ret; | |
4121 | } | |
4122 | ||
4123 | static void i915_irq_uninstall(struct drm_device * dev) | |
4124 | { | |
2d1013dd | 4125 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4126 | int pipe; |
4127 | ||
a266c7d5 | 4128 | if (I915_HAS_HOTPLUG(dev)) { |
0706f17c | 4129 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
a266c7d5 CW |
4130 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
4131 | } | |
4132 | ||
00d98ebd | 4133 | I915_WRITE16(HWSTAM, 0xffff); |
055e393f | 4134 | for_each_pipe(dev_priv, pipe) { |
55b39755 | 4135 | /* Clear enable bits; then clear status bits */ |
a266c7d5 | 4136 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
4137 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
4138 | } | |
a266c7d5 CW |
4139 | I915_WRITE(IMR, 0xffffffff); |
4140 | I915_WRITE(IER, 0x0); | |
4141 | ||
a266c7d5 CW |
4142 | I915_WRITE(IIR, I915_READ(IIR)); |
4143 | } | |
4144 | ||
4145 | static void i965_irq_preinstall(struct drm_device * dev) | |
4146 | { | |
2d1013dd | 4147 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4148 | int pipe; |
4149 | ||
0706f17c | 4150 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
adca4730 | 4151 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
a266c7d5 CW |
4152 | |
4153 | I915_WRITE(HWSTAM, 0xeffe); | |
055e393f | 4154 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4155 | I915_WRITE(PIPESTAT(pipe), 0); |
4156 | I915_WRITE(IMR, 0xffffffff); | |
4157 | I915_WRITE(IER, 0x0); | |
4158 | POSTING_READ(IER); | |
4159 | } | |
4160 | ||
4161 | static int i965_irq_postinstall(struct drm_device *dev) | |
4162 | { | |
2d1013dd | 4163 | struct drm_i915_private *dev_priv = dev->dev_private; |
bbba0a97 | 4164 | u32 enable_mask; |
a266c7d5 CW |
4165 | u32 error_mask; |
4166 | ||
a266c7d5 | 4167 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 4168 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 4169 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
4170 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
4171 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4172 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4173 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
4174 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
4175 | ||
4176 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
4177 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
4178 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
4179 | enable_mask |= I915_USER_INTERRUPT; |
4180 | ||
4181 | if (IS_G4X(dev)) | |
4182 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 4183 | |
b79480ba DV |
4184 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4185 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 4186 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
4187 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
4188 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
4189 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4190 | spin_unlock_irq(&dev_priv->irq_lock); |
a266c7d5 | 4191 | |
a266c7d5 CW |
4192 | /* |
4193 | * Enable some error detection, note the instruction error mask | |
4194 | * bit is reserved, so we leave it masked. | |
4195 | */ | |
4196 | if (IS_G4X(dev)) { | |
4197 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
4198 | GM45_ERROR_MEM_PRIV | | |
4199 | GM45_ERROR_CP_PRIV | | |
4200 | I915_ERROR_MEMORY_REFRESH); | |
4201 | } else { | |
4202 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
4203 | I915_ERROR_MEMORY_REFRESH); | |
4204 | } | |
4205 | I915_WRITE(EMR, error_mask); | |
4206 | ||
4207 | I915_WRITE(IMR, dev_priv->irq_mask); | |
4208 | I915_WRITE(IER, enable_mask); | |
4209 | POSTING_READ(IER); | |
4210 | ||
0706f17c | 4211 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
20afbda2 DV |
4212 | POSTING_READ(PORT_HOTPLUG_EN); |
4213 | ||
f49e38dd | 4214 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
4215 | |
4216 | return 0; | |
4217 | } | |
4218 | ||
bac56d5b | 4219 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 | 4220 | { |
2d1013dd | 4221 | struct drm_i915_private *dev_priv = dev->dev_private; |
20afbda2 DV |
4222 | u32 hotplug_en; |
4223 | ||
b5ea2d56 DV |
4224 | assert_spin_locked(&dev_priv->irq_lock); |
4225 | ||
778eb334 VS |
4226 | /* Note HDMI and DP share hotplug bits */ |
4227 | /* enable bits are the same for all generations */ | |
0706f17c | 4228 | hotplug_en = intel_hpd_enabled_irqs(dev, hpd_mask_i915); |
778eb334 VS |
4229 | /* Programming the CRT detection parameters tends |
4230 | to generate a spurious hotplug event about three | |
4231 | seconds later. So just do it once. | |
4232 | */ | |
4233 | if (IS_G4X(dev)) | |
4234 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
778eb334 VS |
4235 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
4236 | ||
4237 | /* Ignore TV since it's buggy */ | |
0706f17c EE |
4238 | i915_hotplug_interrupt_update_locked(dev_priv, |
4239 | (HOTPLUG_INT_EN_MASK | |
4240 | | CRT_HOTPLUG_VOLTAGE_COMPARE_MASK), | |
4241 | hotplug_en); | |
a266c7d5 CW |
4242 | } |
4243 | ||
ff1f525e | 4244 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 | 4245 | { |
45a83f84 | 4246 | struct drm_device *dev = arg; |
2d1013dd | 4247 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4248 | u32 iir, new_iir; |
4249 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 4250 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
4251 | u32 flip_mask = |
4252 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4253 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 4254 | |
2dd2a883 ID |
4255 | if (!intel_irqs_enabled(dev_priv)) |
4256 | return IRQ_NONE; | |
4257 | ||
a266c7d5 CW |
4258 | iir = I915_READ(IIR); |
4259 | ||
a266c7d5 | 4260 | for (;;) { |
501e01d7 | 4261 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
4262 | bool blc_event = false; |
4263 | ||
a266c7d5 CW |
4264 | /* Can't rely on pipestat interrupt bit in iir as it might |
4265 | * have been cleared after the pipestat interrupt was received. | |
4266 | * It doesn't set the bit in iir again, but it still produces | |
4267 | * interrupts (for non-MSI). | |
4268 | */ | |
222c7f51 | 4269 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4270 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 4271 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 4272 | |
055e393f | 4273 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
4274 | int reg = PIPESTAT(pipe); |
4275 | pipe_stats[pipe] = I915_READ(reg); | |
4276 | ||
4277 | /* | |
4278 | * Clear the PIPE*STAT regs before the IIR | |
4279 | */ | |
4280 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 4281 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 4282 | irq_received = true; |
a266c7d5 CW |
4283 | } |
4284 | } | |
222c7f51 | 4285 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4286 | |
4287 | if (!irq_received) | |
4288 | break; | |
4289 | ||
4290 | ret = IRQ_HANDLED; | |
4291 | ||
4292 | /* Consume port. Then clear IIR or we'll miss events */ | |
16c6c56b VS |
4293 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
4294 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 4295 | |
21ad8330 | 4296 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4297 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4298 | ||
a266c7d5 | 4299 | if (iir & I915_USER_INTERRUPT) |
74cdb337 | 4300 | notify_ring(&dev_priv->ring[RCS]); |
a266c7d5 | 4301 | if (iir & I915_BSD_USER_INTERRUPT) |
74cdb337 | 4302 | notify_ring(&dev_priv->ring[VCS]); |
a266c7d5 | 4303 | |
055e393f | 4304 | for_each_pipe(dev_priv, pipe) { |
2c8ba29f | 4305 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
4306 | i915_handle_vblank(dev, pipe, pipe, iir)) |
4307 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
4308 | |
4309 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4310 | blc_event = true; | |
4356d586 DV |
4311 | |
4312 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 4313 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 | 4314 | |
1f7247c0 DV |
4315 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4316 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
2d9d2b0b | 4317 | } |
a266c7d5 CW |
4318 | |
4319 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
4320 | intel_opregion_asle_intr(dev); | |
4321 | ||
515ac2bb DV |
4322 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
4323 | gmbus_irq_handler(dev); | |
4324 | ||
a266c7d5 CW |
4325 | /* With MSI, interrupts are only generated when iir |
4326 | * transitions from zero to nonzero. If another bit got | |
4327 | * set while we were handling the existing iir bits, then | |
4328 | * we would never get another interrupt. | |
4329 | * | |
4330 | * This is fine on non-MSI as well, as if we hit this path | |
4331 | * we avoid exiting the interrupt handler only to generate | |
4332 | * another one. | |
4333 | * | |
4334 | * Note that for MSI this could cause a stray interrupt report | |
4335 | * if an interrupt landed in the time between writing IIR and | |
4336 | * the posting read. This should be rare enough to never | |
4337 | * trigger the 99% of 100,000 interrupts test for disabling | |
4338 | * stray interrupts. | |
4339 | */ | |
4340 | iir = new_iir; | |
4341 | } | |
4342 | ||
4343 | return ret; | |
4344 | } | |
4345 | ||
4346 | static void i965_irq_uninstall(struct drm_device * dev) | |
4347 | { | |
2d1013dd | 4348 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4349 | int pipe; |
4350 | ||
4351 | if (!dev_priv) | |
4352 | return; | |
4353 | ||
0706f17c | 4354 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
adca4730 | 4355 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
a266c7d5 CW |
4356 | |
4357 | I915_WRITE(HWSTAM, 0xffffffff); | |
055e393f | 4358 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4359 | I915_WRITE(PIPESTAT(pipe), 0); |
4360 | I915_WRITE(IMR, 0xffffffff); | |
4361 | I915_WRITE(IER, 0x0); | |
4362 | ||
055e393f | 4363 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4364 | I915_WRITE(PIPESTAT(pipe), |
4365 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
4366 | I915_WRITE(IIR, I915_READ(IIR)); | |
4367 | } | |
4368 | ||
fca52a55 DV |
4369 | /** |
4370 | * intel_irq_init - initializes irq support | |
4371 | * @dev_priv: i915 device instance | |
4372 | * | |
4373 | * This function initializes all the irq support including work items, timers | |
4374 | * and all the vtables. It does not setup the interrupt itself though. | |
4375 | */ | |
b963291c | 4376 | void intel_irq_init(struct drm_i915_private *dev_priv) |
f71d4af4 | 4377 | { |
b963291c | 4378 | struct drm_device *dev = dev_priv->dev; |
8b2e326d | 4379 | |
77913b39 JN |
4380 | intel_hpd_init_work(dev_priv); |
4381 | ||
c6a828d3 | 4382 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 4383 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 4384 | |
a6706b45 | 4385 | /* Let's track the enabled rps events */ |
b963291c | 4386 | if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
6c65a587 | 4387 | /* WaGsvRC0ResidencyMethod:vlv */ |
6f4b12f8 | 4388 | dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED; |
31685c25 D |
4389 | else |
4390 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
a6706b45 | 4391 | |
737b1506 CW |
4392 | INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work, |
4393 | i915_hangcheck_elapsed); | |
61bac78e | 4394 | |
97a19a24 | 4395 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 4396 | |
b963291c | 4397 | if (IS_GEN2(dev_priv)) { |
4cdb83ec VS |
4398 | dev->max_vblank_count = 0; |
4399 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
b963291c | 4400 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
f71d4af4 | 4401 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
fd8f507c | 4402 | dev->driver->get_vblank_counter = g4x_get_vblank_counter; |
391f75e2 VS |
4403 | } else { |
4404 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4405 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4406 | } |
4407 | ||
21da2700 VS |
4408 | /* |
4409 | * Opt out of the vblank disable timer on everything except gen2. | |
4410 | * Gen2 doesn't have a hardware frame counter and so depends on | |
4411 | * vblank interrupts to produce sane vblank seuquence numbers. | |
4412 | */ | |
b963291c | 4413 | if (!IS_GEN2(dev_priv)) |
21da2700 VS |
4414 | dev->vblank_disable_immediate = true; |
4415 | ||
f3a5c3f6 DV |
4416 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
4417 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; | |
f71d4af4 | 4418 | |
b963291c | 4419 | if (IS_CHERRYVIEW(dev_priv)) { |
43f328d7 VS |
4420 | dev->driver->irq_handler = cherryview_irq_handler; |
4421 | dev->driver->irq_preinstall = cherryview_irq_preinstall; | |
4422 | dev->driver->irq_postinstall = cherryview_irq_postinstall; | |
4423 | dev->driver->irq_uninstall = cherryview_irq_uninstall; | |
4424 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4425 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
4426 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
b963291c | 4427 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
4428 | dev->driver->irq_handler = valleyview_irq_handler; |
4429 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4430 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4431 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
4432 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4433 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 4434 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
b963291c | 4435 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
abd58f01 | 4436 | dev->driver->irq_handler = gen8_irq_handler; |
723761b8 | 4437 | dev->driver->irq_preinstall = gen8_irq_reset; |
abd58f01 BW |
4438 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
4439 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4440 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4441 | dev->driver->disable_vblank = gen8_disable_vblank; | |
6dbf30ce | 4442 | if (IS_BROXTON(dev)) |
e0a20ad7 | 4443 | dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; |
6dbf30ce VS |
4444 | else if (HAS_PCH_SPT(dev)) |
4445 | dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup; | |
4446 | else | |
3a3b3c7d | 4447 | dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; |
f71d4af4 JB |
4448 | } else if (HAS_PCH_SPLIT(dev)) { |
4449 | dev->driver->irq_handler = ironlake_irq_handler; | |
723761b8 | 4450 | dev->driver->irq_preinstall = ironlake_irq_reset; |
f71d4af4 JB |
4451 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
4452 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4453 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4454 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
23bb4cb5 | 4455 | dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; |
f71d4af4 | 4456 | } else { |
b963291c | 4457 | if (INTEL_INFO(dev_priv)->gen == 2) { |
c2798b19 CW |
4458 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
4459 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4460 | dev->driver->irq_handler = i8xx_irq_handler; | |
4461 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
b963291c | 4462 | } else if (INTEL_INFO(dev_priv)->gen == 3) { |
a266c7d5 CW |
4463 | dev->driver->irq_preinstall = i915_irq_preinstall; |
4464 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4465 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4466 | dev->driver->irq_handler = i915_irq_handler; | |
c2798b19 | 4467 | } else { |
a266c7d5 CW |
4468 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4469 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4470 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4471 | dev->driver->irq_handler = i965_irq_handler; | |
c2798b19 | 4472 | } |
778eb334 VS |
4473 | if (I915_HAS_HOTPLUG(dev_priv)) |
4474 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
f71d4af4 JB |
4475 | dev->driver->enable_vblank = i915_enable_vblank; |
4476 | dev->driver->disable_vblank = i915_disable_vblank; | |
4477 | } | |
4478 | } | |
20afbda2 | 4479 | |
fca52a55 DV |
4480 | /** |
4481 | * intel_irq_install - enables the hardware interrupt | |
4482 | * @dev_priv: i915 device instance | |
4483 | * | |
4484 | * This function enables the hardware interrupt handling, but leaves the hotplug | |
4485 | * handling still disabled. It is called after intel_irq_init(). | |
4486 | * | |
4487 | * In the driver load and resume code we need working interrupts in a few places | |
4488 | * but don't want to deal with the hassle of concurrent probe and hotplug | |
4489 | * workers. Hence the split into this two-stage approach. | |
4490 | */ | |
2aeb7d3a DV |
4491 | int intel_irq_install(struct drm_i915_private *dev_priv) |
4492 | { | |
4493 | /* | |
4494 | * We enable some interrupt sources in our postinstall hooks, so mark | |
4495 | * interrupts as enabled _before_ actually enabling them to avoid | |
4496 | * special cases in our ordering checks. | |
4497 | */ | |
4498 | dev_priv->pm.irqs_enabled = true; | |
4499 | ||
4500 | return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq); | |
4501 | } | |
4502 | ||
fca52a55 DV |
4503 | /** |
4504 | * intel_irq_uninstall - finilizes all irq handling | |
4505 | * @dev_priv: i915 device instance | |
4506 | * | |
4507 | * This stops interrupt and hotplug handling and unregisters and frees all | |
4508 | * resources acquired in the init functions. | |
4509 | */ | |
2aeb7d3a DV |
4510 | void intel_irq_uninstall(struct drm_i915_private *dev_priv) |
4511 | { | |
4512 | drm_irq_uninstall(dev_priv->dev); | |
4513 | intel_hpd_cancel_work(dev_priv); | |
4514 | dev_priv->pm.irqs_enabled = false; | |
4515 | } | |
4516 | ||
fca52a55 DV |
4517 | /** |
4518 | * intel_runtime_pm_disable_interrupts - runtime interrupt disabling | |
4519 | * @dev_priv: i915 device instance | |
4520 | * | |
4521 | * This function is used to disable interrupts at runtime, both in the runtime | |
4522 | * pm and the system suspend/resume code. | |
4523 | */ | |
b963291c | 4524 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4525 | { |
b963291c | 4526 | dev_priv->dev->driver->irq_uninstall(dev_priv->dev); |
2aeb7d3a | 4527 | dev_priv->pm.irqs_enabled = false; |
2dd2a883 | 4528 | synchronize_irq(dev_priv->dev->irq); |
c67a470b PZ |
4529 | } |
4530 | ||
fca52a55 DV |
4531 | /** |
4532 | * intel_runtime_pm_enable_interrupts - runtime interrupt enabling | |
4533 | * @dev_priv: i915 device instance | |
4534 | * | |
4535 | * This function is used to enable interrupts at runtime, both in the runtime | |
4536 | * pm and the system suspend/resume code. | |
4537 | */ | |
b963291c | 4538 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4539 | { |
2aeb7d3a | 4540 | dev_priv->pm.irqs_enabled = true; |
b963291c DV |
4541 | dev_priv->dev->driver->irq_preinstall(dev_priv->dev); |
4542 | dev_priv->dev->driver->irq_postinstall(dev_priv->dev); | |
c67a470b | 4543 | } |